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raw | patch | inline | side by side (parent: f25b10c)
author | Lokesh Vutla <lokeshvutla@ti.com> | |
Wed, 11 Nov 2020 15:09:27 +0000 (20:39 +0530) | ||
committer | Lokesh Vutla <lokeshvutla@ti.com> | |
Thu, 12 Nov 2020 07:39:14 +0000 (13:09 +0530) |
Update the sysfw data that corresponds to v2020.08b. Also fix the TI
link in Copyright headers.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
link in Copyright headers.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
index f3446b6b364a5a1347a94ad4942eb37c5c7735ce..3e91ec7d0868bf5bb5efbd1068baea31336e0443 100644 (file)
extern struct ti_sci_clocks_info j7200_clocks_info[];
-#endif /* __J7200_CLOCKS_INFO_H */
+#endif /* __J7200_CLOCKS_INFO_H */
\ No newline at end of file
index 60e988208dc13d0c32734c0bb220acd765f875fd..a6074131c7ef734d31c4559441159c92b33163ca 100644 (file)
[1] = {1, "J7200_DEV_MCU_ADC1"},
[2] = {2, "J7200_DEV_ATL0"},
[3] = {3, "J7200_DEV_COMPUTE_CLUSTER0"},
- [4] = {4, "J7200_DEV_A72SS0"},
+ [4] = {4, "J7200_DEV_A72SS0_CORE0"},
[5] = {5, "J7200_DEV_COMPUTE_CLUSTER0_CFG_WRAP"},
[6] = {6, "J7200_DEV_COMPUTE_CLUSTER0_CLEC"},
[7] = {7, "J7200_DEV_COMPUTE_CLUSTER0_CORE_CORE"},
[157] = {197, "J7200_DEV_WKUP_I2C0"},
[158] = {199, "J7200_DEV_NAVSS0"},
[159] = {201, "J7200_DEV_NAVSS0_CPTS_0"},
- [160] = {202, "J7200_DEV_A72SS0_CORE0"},
- [161] = {203, "J7200_DEV_A72SS0_CORE1"},
+ [160] = {202, "J7200_DEV_A72SS0_CORE0_0"},
+ [161] = {203, "J7200_DEV_A72SS0_CORE0_1"},
[162] = {206, "J7200_DEV_NAVSS0_DTI_0"},
[163] = {207, "J7200_DEV_NAVSS0_MODSS_INTA_0"},
[164] = {208, "J7200_DEV_NAVSS0_MODSS_INTA_1"},
index 215cb2e1ebc60e48c2ee66a0e38d77d7445617a1..581cbcedd58853e8cbdfa6effd3b9d86efc47ce6 100644 (file)
#include <socinfo.h>
struct ti_sci_host_info j7200_host_info[] = {
- [0] = {0, "DMSC", "Secure", "Device Management and Security Control"},
- [1] = {3, "MCU_0_R5_0", "Non Secure", "Cortex R5 context 0 on MCU island"},
- [2] = {4, "MCU_0_R5_1", "Secure", "Cortex R5 context 1 on MCU island(Boot)"},
- [3] = {5, "MCU_0_R5_2", "Non Secure", "Cortex R5 context 2 on MCU island"},
- [4] = {6, "MCU_0_R5_3", "Secure", "Cortex R5 context 3 on MCU island"},
- [5] = {10, "A72_0", "Secure", "Cortex A72 context 0 on Main island"},
- [6] = {11, "A72_1", "Secure", "Cortex A72 context 1 on Main island"},
- [7] = {12, "A72_2", "Non Secure", "Cortex A72 context 2 on Main island"},
- [8] = {13, "A72_3", "Non Secure", "Cortex A72 context 3 on Main island"},
- [9] = {14, "A72_4", "Non Secure", "Cortex A72 context 4 on Main island"},
- [10] = {35, "MAIN_0_R5_0", "Non Secure", "Cortex R5_0 context 0 on Main island"},
- [11] = {36, "MAIN_0_R5_1", "Secure", "Cortex R5_0 context 1 on Main island"},
- [12] = {37, "MAIN_0_R5_2", "Non Secure", "Cortex R5_0 context 2 on Main island"},
- [13] = {38, "MAIN_0_R5_3", "Secure", "Cortex R5_0 context 3 on MCU island"},
+ [0] = {0, "DMSC", "Secure", "Security Controller"},
+ [1] = {254, "DM", "Non Secure", "Device Management"},
+ [2] = {3, "MCU_0_R5_0", "Non Secure", "Cortex R5 context 0 on MCU island"},
+ [3] = {4, "MCU_0_R5_1", "Secure", "Cortex R5 context 1 on MCU island(Boot)"},
+ [4] = {5, "MCU_0_R5_2", "Non Secure", "Cortex R5 context 2 on MCU island"},
+ [5] = {6, "MCU_0_R5_3", "Secure", "Cortex R5 context 3 on MCU island"},
+ [6] = {10, "A72_0", "Secure", "Cortex A72 context 0 on Main island"},
+ [7] = {11, "A72_1", "Secure", "Cortex A72 context 1 on Main island"},
+ [8] = {12, "A72_2", "Non Secure", "Cortex A72 context 2 on Main island"},
+ [9] = {13, "A72_3", "Non Secure", "Cortex A72 context 3 on Main island"},
+ [10] = {14, "A72_4", "Non Secure", "Cortex A72 context 4 on Main island"},
+ [11] = {35, "MAIN_0_R5_0", "Non Secure", "Cortex R5_0 context 0 on Main island"},
+ [12] = {36, "MAIN_0_R5_1", "Secure", "Cortex R5_0 context 1 on Main island"},
+ [13] = {37, "MAIN_0_R5_2", "Non Secure", "Cortex R5_0 context 2 on Main island"},
+ [14] = {38, "MAIN_0_R5_3", "Secure", "Cortex R5_0 context 3 on MCU island"},
+ [15] = {250, "DM2DMSC", "Secure", "DM to DMSC communication"},
+ [16] = {251, "DMSC2DM", "Non Secure", "DMSC to DM communication"},
};
index 1e6a6f03eb05d788808303732ced6815a0b57fe6..0b58ec4a94329e5ad93a051fa91d9ff64879fb47 100644 (file)
#define __J7200_HOST_INFO_H
#define J7200_HOST_ID_DMSC 0
+#define J7200_HOST_ID_DM 254
#define J7200_HOST_ID_MCU_0_R5_0 3
#define J7200_HOST_ID_MCU_0_R5_1 4
#define J7200_HOST_ID_MCU_0_R5_2 5
#define J7200_HOST_ID_MAIN_0_R5_1 36
#define J7200_HOST_ID_MAIN_0_R5_2 37
#define J7200_HOST_ID_MAIN_0_R5_3 38
+#define J7200_HOST_ID_DM2DMSC 250
+#define J7200_HOST_ID_DMSC2DM 251
-#define J7200_MAX_HOST_IDS 14
+#define J7200_MAX_HOST_IDS 17
extern struct ti_sci_host_info j7200_host_info[];
index 799c8a036268028339eca9038f5b9115d6b37150..c09b4ef9b86d639441bedca7259b8ce09c724e09 100644 (file)
#include <socinfo.h>
struct ti_sci_processors_info j7200_processors_info[] = {
- [0] = {202, 2, 0x20, "A72SS0_CORE0"},
- [1] = {203, 0, 0x21, "A72SS0_CORE1"},
+ [0] = {202, 2, 0x20, "A72SS0_CORE0_0"},
+ [1] = {203, 0, 0x21, "A72SS0_CORE0_1"},
[2] = {250, 0, 0x01, "MCU_R5FSS0_CORE0"},
[3] = {251, 0, 0x02, "MCU_R5FSS0_CORE1"},
[4] = {245, 0, 0x06, "R5FSS0_CORE0"},
index 820bdaf835c2332441b983bcf721370ad778a968..9b5f78fb04befac94b9de767ae604e30f17cc1e4 100644 (file)
#include <socinfo.h>
struct ti_sci_sec_proxy_info j7200_main_sp_info[] = {
- [0] = {0, "read", 2, "A72_0", "notify"},
- [1] = {1, "read", 30, "A72_0", "response"},
- [2] = {2, "write", 10, "A72_0", "high_priority"},
- [3] = {3, "write", 20, "A72_0", "low_priority"},
- [4] = {4, "write", 2, "A72_0", "notify_resp"},
- [5] = {5, "read", 2, "A72_1", "notify"},
- [6] = {6, "read", 30, "A72_1", "response"},
- [7] = {7, "write", 10, "A72_1", "high_priority"},
- [8] = {8, "write", 20, "A72_1", "low_priority"},
- [9] = {9, "write", 2, "A72_1", "notify_resp"},
- [10] = {10, "read", 2, "A72_2", "notify"},
- [11] = {11, "read", 22, "A72_2", "response"},
- [12] = {12, "write", 2, "A72_2", "high_priority"},
- [13] = {13, "write", 20, "A72_2", "low_priority"},
- [14] = {14, "write", 2, "A72_2", "notify_resp"},
- [15] = {15, "read", 2, "A72_3", "notify"},
- [16] = {16, "read", 7, "A72_3", "response"},
- [17] = {17, "write", 2, "A72_3", "high_priority"},
- [18] = {18, "write", 5, "A72_3", "low_priority"},
- [19] = {19, "write", 2, "A72_3", "notify_resp"},
- [20] = {20, "read", 2, "A72_4", "notify"},
- [21] = {21, "read", 7, "A72_4", "response"},
- [22] = {22, "write", 2, "A72_4", "high_priority"},
- [23] = {23, "write", 5, "A72_4", "low_priority"},
- [24] = {24, "write", 2, "A72_4", "notify_resp"},
- [25] = {25, "read", 2, "MAIN_0_R5_0", "notify"},
- [26] = {26, "read", 7, "MAIN_0_R5_0", "response"},
- [27] = {27, "write", 2, "MAIN_0_R5_0", "high_priority"},
- [28] = {28, "write", 5, "MAIN_0_R5_0", "low_priority"},
- [29] = {29, "write", 2, "MAIN_0_R5_0", "notify_resp"},
- [30] = {30, "read", 2, "MAIN_0_R5_1", "notify"},
- [31] = {31, "read", 7, "MAIN_0_R5_1", "response"},
- [32] = {32, "write", 2, "MAIN_0_R5_1", "high_priority"},
- [33] = {33, "write", 5, "MAIN_0_R5_1", "low_priority"},
- [34] = {34, "write", 2, "MAIN_0_R5_1", "notify_resp"},
- [35] = {35, "read", 1, "MAIN_0_R5_2", "notify"},
- [36] = {36, "read", 2, "MAIN_0_R5_2", "response"},
- [37] = {37, "write", 1, "MAIN_0_R5_2", "high_priority"},
- [38] = {38, "write", 1, "MAIN_0_R5_2", "low_priority"},
- [39] = {39, "write", 1, "MAIN_0_R5_2", "notify_resp"},
- [40] = {40, "read", 1, "MAIN_0_R5_3", "notify"},
- [41] = {41, "read", 2, "MAIN_0_R5_3", "response"},
- [42] = {42, "write", 1, "MAIN_0_R5_3", "high_priority"},
- [43] = {43, "write", 1, "MAIN_0_R5_3", "low_priority"},
- [44] = {44, "write", 1, "MAIN_0_R5_3", "notify_resp"},
+ [0] = {148, "read", 9, "DM", "nonsec_high_priority_rx"},
+ [1] = {147, "read", 36, "DM", "nonsec_low_priority_rx"},
+ [2] = {146, "read", 9, "DM", "nonsec_notify_resp_rx"},
+ [3] = {145, "write", 2, "DM", "nonsec_A72_2_notify_tx"},
+ [4] = {144, "write", 22, "DM", "nonsec_A72_2_response_tx"},
+ [5] = {143, "write", 2, "DM", "nonsec_A72_3_notify_tx"},
+ [6] = {142, "write", 7, "DM", "nonsec_A72_3_response_tx"},
+ [7] = {141, "write", 2, "DM", "nonsec_A72_4_notify_tx"},
+ [8] = {140, "write", 7, "DM", "nonsec_A72_4_response_tx"},
+ [9] = {139, "write", 2, "DM", "nonsec_MAIN_0_R5_0_notify_tx"},
+ [10] = {138, "write", 7, "DM", "nonsec_MAIN_0_R5_0_response_tx"},
+ [11] = {137, "write", 1, "DM", "nonsec_MAIN_0_R5_2_notify_tx"},
+ [12] = {136, "write", 2, "DM", "nonsec_MAIN_0_R5_2_response_tx"},
+ [13] = {0, "read", 2, "A72_0", "notify"},
+ [14] = {1, "read", 30, "A72_0", "response"},
+ [15] = {2, "write", 10, "A72_0", "high_priority"},
+ [16] = {3, "write", 20, "A72_0", "low_priority"},
+ [17] = {4, "write", 2, "A72_0", "notify_resp"},
+ [18] = {5, "read", 2, "A72_1", "notify"},
+ [19] = {6, "read", 30, "A72_1", "response"},
+ [20] = {7, "write", 10, "A72_1", "high_priority"},
+ [21] = {8, "write", 20, "A72_1", "low_priority"},
+ [22] = {9, "write", 2, "A72_1", "notify_resp"},
+ [23] = {10, "read", 2, "A72_2", "notify"},
+ [24] = {11, "read", 22, "A72_2", "response"},
+ [25] = {12, "write", 2, "A72_2", "high_priority"},
+ [26] = {13, "write", 20, "A72_2", "low_priority"},
+ [27] = {14, "write", 2, "A72_2", "notify_resp"},
+ [28] = {15, "read", 2, "A72_3", "notify"},
+ [29] = {16, "read", 7, "A72_3", "response"},
+ [30] = {17, "write", 2, "A72_3", "high_priority"},
+ [31] = {18, "write", 5, "A72_3", "low_priority"},
+ [32] = {19, "write", 2, "A72_3", "notify_resp"},
+ [33] = {20, "read", 2, "A72_4", "notify"},
+ [34] = {21, "read", 7, "A72_4", "response"},
+ [35] = {22, "write", 2, "A72_4", "high_priority"},
+ [36] = {23, "write", 5, "A72_4", "low_priority"},
+ [37] = {24, "write", 2, "A72_4", "notify_resp"},
+ [38] = {25, "read", 2, "MAIN_0_R5_0", "notify"},
+ [39] = {26, "read", 7, "MAIN_0_R5_0", "response"},
+ [40] = {27, "write", 2, "MAIN_0_R5_0", "high_priority"},
+ [41] = {28, "write", 5, "MAIN_0_R5_0", "low_priority"},
+ [42] = {29, "write", 2, "MAIN_0_R5_0", "notify_resp"},
+ [43] = {30, "read", 2, "MAIN_0_R5_1", "notify"},
+ [44] = {31, "read", 7, "MAIN_0_R5_1", "response"},
+ [45] = {32, "write", 2, "MAIN_0_R5_1", "high_priority"},
+ [46] = {33, "write", 5, "MAIN_0_R5_1", "low_priority"},
+ [47] = {34, "write", 2, "MAIN_0_R5_1", "notify_resp"},
+ [48] = {35, "read", 1, "MAIN_0_R5_2", "notify"},
+ [49] = {36, "read", 2, "MAIN_0_R5_2", "response"},
+ [50] = {37, "write", 1, "MAIN_0_R5_2", "high_priority"},
+ [51] = {38, "write", 1, "MAIN_0_R5_2", "low_priority"},
+ [52] = {39, "write", 1, "MAIN_0_R5_2", "notify_resp"},
+ [53] = {40, "read", 1, "MAIN_0_R5_3", "notify"},
+ [54] = {41, "read", 2, "MAIN_0_R5_3", "response"},
+ [55] = {42, "write", 1, "MAIN_0_R5_3", "high_priority"},
+ [56] = {43, "write", 1, "MAIN_0_R5_3", "low_priority"},
+ [57] = {44, "write", 1, "MAIN_0_R5_3", "notify_resp"},
};
struct ti_sci_sec_proxy_info j7200_mcu_sp_info[] = {
- [0] = {0, "read", 2, "MCU_0_R5_0", "notify"},
- [1] = {1, "read", 20, "MCU_0_R5_0", "response"},
- [2] = {2, "write", 10, "MCU_0_R5_0", "high_priority"},
- [3] = {3, "write", 10, "MCU_0_R5_0", "low_priority"},
- [4] = {4, "write", 2, "MCU_0_R5_0", "notify_resp"},
- [5] = {5, "read", 2, "MCU_0_R5_1", "notify"},
- [6] = {6, "read", 20, "MCU_0_R5_1", "response"},
- [7] = {7, "write", 10, "MCU_0_R5_1", "high_priority"},
- [8] = {8, "write", 10, "MCU_0_R5_1", "low_priority"},
- [9] = {9, "write", 2, "MCU_0_R5_1", "notify_resp"},
- [10] = {10, "read", 1, "MCU_0_R5_2", "notify"},
- [11] = {11, "read", 2, "MCU_0_R5_2", "response"},
- [12] = {12, "write", 1, "MCU_0_R5_2", "high_priority"},
- [13] = {13, "write", 1, "MCU_0_R5_2", "low_priority"},
- [14] = {14, "write", 1, "MCU_0_R5_2", "notify_resp"},
- [15] = {15, "read", 1, "MCU_0_R5_3", "notify"},
- [16] = {16, "read", 2, "MCU_0_R5_3", "response"},
- [17] = {17, "write", 1, "MCU_0_R5_3", "high_priority"},
- [18] = {18, "write", 1, "MCU_0_R5_3", "low_priority"},
- [19] = {19, "write", 1, "MCU_0_R5_3", "notify_resp"},
+ [0] = {80, "read", 13, "DM", "nonsec_high_priority_rx"},
+ [1] = {79, "read", 13, "DM", "nonsec_low_priority_rx"},
+ [2] = {78, "read", 5, "DM", "nonsec_notify_resp_rx"},
+ [3] = {77, "write", 2, "DM", "nonsec_MCU_0_R5_0_notify_tx"},
+ [4] = {76, "write", 20, "DM", "nonsec_MCU_0_R5_0_response_tx"},
+ [5] = {75, "write", 1, "DM", "nonsec_MCU_0_R5_2_notify_tx"},
+ [6] = {74, "write", 2, "DM", "nonsec_MCU_0_R5_2_response_tx"},
+ [7] = {73, "write", 2, "DM", "nonsec_DMSC2DM_notify_tx"},
+ [8] = {72, "write", 4, "DM", "nonsec_DMSC2DM_response_tx"},
+ [9] = {0, "read", 2, "MCU_0_R5_0", "notify"},
+ [10] = {1, "read", 20, "MCU_0_R5_0", "response"},
+ [11] = {2, "write", 10, "MCU_0_R5_0", "high_priority"},
+ [12] = {3, "write", 10, "MCU_0_R5_0", "low_priority"},
+ [13] = {4, "write", 2, "MCU_0_R5_0", "notify_resp"},
+ [14] = {5, "read", 2, "MCU_0_R5_1", "notify"},
+ [15] = {6, "read", 20, "MCU_0_R5_1", "response"},
+ [16] = {7, "write", 10, "MCU_0_R5_1", "high_priority"},
+ [17] = {8, "write", 10, "MCU_0_R5_1", "low_priority"},
+ [18] = {9, "write", 2, "MCU_0_R5_1", "notify_resp"},
+ [19] = {10, "read", 1, "MCU_0_R5_2", "notify"},
+ [20] = {11, "read", 2, "MCU_0_R5_2", "response"},
+ [21] = {12, "write", 1, "MCU_0_R5_2", "high_priority"},
+ [22] = {13, "write", 1, "MCU_0_R5_2", "low_priority"},
+ [23] = {14, "write", 1, "MCU_0_R5_2", "notify_resp"},
+ [24] = {15, "read", 1, "MCU_0_R5_3", "notify"},
+ [25] = {16, "read", 2, "MCU_0_R5_3", "response"},
+ [26] = {17, "write", 1, "MCU_0_R5_3", "high_priority"},
+ [27] = {18, "write", 1, "MCU_0_R5_3", "low_priority"},
+ [28] = {19, "write", 1, "MCU_0_R5_3", "notify_resp"},
+ [29] = {20, "read", 2, "DM2DMSC", "notify"},
+ [30] = {21, "read", 4, "DM2DMSC", "response"},
+ [31] = {22, "write", 2, "DM2DMSC", "high_priority"},
+ [32] = {23, "write", 2, "DM2DMSC", "low_priority"},
+ [33] = {24, "write", 2, "DM2DMSC", "notify_resp"},
+ [34] = {25, "read", 2, "DMSC2DM", "notify"},
+ [35] = {26, "read", 4, "DMSC2DM", "response"},
+ [36] = {27, "write", 2, "DMSC2DM", "high_priority"},
+ [37] = {28, "write", 2, "DMSC2DM", "low_priority"},
+ [38] = {29, "write", 2, "DMSC2DM", "notify_resp"},
};
index ef232cec04ecc67198456bbff112d8f726a575ad..23e5835b2cb80a8537ffb6ead226fc3752c69995 100644 (file)
#ifndef __J7200_SEC_PROXY_INFO_H
#define __J7200_SEC_PROXY_INFO_H
-#define J7200_MAIN_SEC_PROXY_THREADS 45
-#define J7200_MCU_SEC_PROXY_THREADS 20
+#define J7200_MAIN_SEC_PROXY_THREADS 58
+#define J7200_MCU_SEC_PROXY_THREADS 39
extern struct ti_sci_sec_proxy_info j7200_main_sp_info[];
extern struct ti_sci_sec_proxy_info j7200_mcu_sp_info[];