soc: j721e: Add host id information

Host Id information of J721e devices.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/Makefile b/Makefile
index 00849a6070fe7f7ce5b75dc53637a389d4c5e618..5e57df006b0dde4e5e9f8f79bd909b2e3a05f09f 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -69,12 +69,16 @@ COMMONSOURCES=\
 AM65XSOURCES =\
              soc/am65x/am65x_host_info.c
 
 AM65XSOURCES =\
              soc/am65x/am65x_host_info.c
 

+J721ESOURCES =\
+             soc/j721e/j721e_host_info.c
+

 COMMONOBJECTS= $(COMMONSOURCES:.c=.o)
 AM65XOBJECTS=  $(AM65XSOURCES:.c=.o)
 COMMONOBJECTS= $(COMMONSOURCES:.c=.o)
 AM65XOBJECTS=  $(AM65XSOURCES:.c=.o)

+J721EOBJECTS=  $(J721ESOURCES:.c=.o)

 
 

-ALLSOURCES=    $(COMMONSOURCES) $(AM65XSOURCES)
+ALLSOURCES=    $(COMMONSOURCES) $(AM65XSOURCES) $(J721ESOURCES)

 
 

-ALLOBJECTS=    $(COMMONOBJECTS) $(AM65XOBJECTS)
+ALLOBJECTS=    $(COMMONOBJECTS) $(AM65XOBJECTS) $(J721EOBJECTS)

 
 #
 # Pretty print
 
 #
 # Pretty print

diff --git a/common/socinfo.c b/common/socinfo.c
index a7bd37945269a9f9969d4f7b96f601d1ca340ed3..94b2610947116eb6ade7b32e5241b81d62c009a9 100644 (file)
--- a/common/socinfo.c
+++ b/common/socinfo.c
@@ -38,6 +38,7 @@
 #include <string.h>
 #include <sec_proxy.h>
 #include <soc/am65x/am65x_host_info.h>
 #include <string.h>
 #include <sec_proxy.h>
 #include <soc/am65x/am65x_host_info.h>

+#include <soc/j721e/j721e_host_info.h>

 
 /* Assuming these addresses and definitions stay common across K3 devices */
 #define CTRLMMR_WKUP_JTAG_DEVICE_ID    0x43000018
 
 /* Assuming these addresses and definitions stay common across K3 devices */
 #define CTRLMMR_WKUP_JTAG_DEVICE_ID    0x43000018


@@ -85,6 +86,14 @@ static void am654_init(void)
        sci_info->num_hosts = AM65X_MAX_HOST_IDS;
 }
 
        sci_info->num_hosts = AM65X_MAX_HOST_IDS;
 }
 

+static void j721e_init(void)
+{
+       struct ti_sci_info *sci_info = &soc_info.sci_info;
+
+       sci_info->host_info = j721e_host_info;
+       sci_info->num_hosts = J721E_MAX_HOST_IDS;
+}
+

 int soc_init(void)
 {
        memset(&soc_info, 0, sizeof(soc_info));
 int soc_init(void)
 {
        memset(&soc_info, 0, sizeof(soc_info));


@@ -113,6 +122,8 @@ int soc_init(void)
 
        if (soc_info.soc == AM654)
                am654_init();
 
        if (soc_info.soc == AM654)
                am654_init();

+       else if (soc_info.soc == J721E)
+               j721e_init();

 
        /* ToDo: Add error if sec_proxy_init/sci_init is failed */
        if(!k3_sec_proxy_init())
 
        /* ToDo: Add error if sec_proxy_init/sci_init is failed */
        if(!k3_sec_proxy_init())

diff --git a/include/soc/j721e/j721e_host_info.h b/include/soc/j721e/j721e_host_info.h
new file mode 100644 (file)
index 0000000..e6b3306
--- /dev/null
+++ b/include/soc/j721e/j721e_host_info.h
@@ -0,0 +1,71 @@
+/*
+ * SoC Host Info
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __J721E_HOST_INFO
+#define __J721E_HOST_INFO
+
+#include <stdio.h>
+#include <stdint.h>
+
+#define J721E_HOST_ID_DMSC   0
+#define J721E_HOST_ID_MCU_0_R5_0   3
+#define J721E_HOST_ID_MCU_0_R5_1   4
+#define J721E_HOST_ID_MCU_0_R5_2   5
+#define J721E_HOST_ID_MCU_0_R5_3   6
+#define J721E_HOST_ID_A72_0   10
+#define J721E_HOST_ID_A72_1   11
+#define J721E_HOST_ID_A72_2   12
+#define J721E_HOST_ID_A72_3   13
+#define J721E_HOST_ID_A72_4   14
+#define J721E_HOST_ID_C7X_0   20
+#define J721E_HOST_ID_C7X_1   21
+#define J721E_HOST_ID_C6X_0_0   25
+#define J721E_HOST_ID_C6X_0_1   26
+#define J721E_HOST_ID_C6X_1_0   27
+#define J721E_HOST_ID_C6X_1_1   28
+#define J721E_HOST_ID_GPU_0   30
+#define J721E_HOST_ID_MAIN_0_R5_0   35
+#define J721E_HOST_ID_MAIN_0_R5_1   36
+#define J721E_HOST_ID_MAIN_0_R5_2   37
+#define J721E_HOST_ID_MAIN_0_R5_3   38
+#define J721E_HOST_ID_MAIN_1_R5_0   40
+#define J721E_HOST_ID_MAIN_1_R5_1   41
+#define J721E_HOST_ID_MAIN_1_R5_2   42
+#define J721E_HOST_ID_MAIN_1_R5_3   43
+#define J721E_HOST_ID_ICSSG_0   50
+
+#define J721E_MAX_HOST_IDS     26
+
+extern struct ti_sci_host_info j721e_host_info[];
+#endif
\ No newline at end of file

diff --git a/soc/j721e/j721e_host_info.c b/soc/j721e/j721e_host_info.c
new file mode 100644 (file)
index 0000000..15303f4
--- /dev/null
+++ b/soc/j721e/j721e_host_info.c
@@ -0,0 +1,65 @@
+/*
+ * SoC Host Info
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <tisci.h>
+#include <socinfo.h>
+
+struct ti_sci_host_info j721e_host_info[] = {
+       [0] = {0, "DMSC", "Secure", "Device Management and Security Control"},
+       [1] = {3, "MCU_0_R5_0", "Non Secure", "Cortex R5 context 0 on MCU island"},
+       [2] = {4, "MCU_0_R5_1", "Secure", "Cortex R5 context 1 on MCU island(Boot)"},
+       [3] = {5, "MCU_0_R5_2", "Non Secure", "Cortex R5 context 2 on MCU island"},
+       [4] = {6, "MCU_0_R5_3", "Secure", "Cortex R5 context 3 on MCU island"},
+       [5] = {10, "A72_0", "Secure", "Cortex A72 context 0 on Main island"},
+       [6] = {11, "A72_1", "Secure", "Cortex A72 context 1 on Main island"},
+       [7] = {12, "A72_2", "Non Secure", "Cortex A72 context 2 on Main island"},
+       [8] = {13, "A72_3", "Non Secure", "Cortex A72 context 3 on Main island"},
+       [9] = {14, "A72_4", "Non Secure", "Cortex A72 context 4 on Main island"},
+       [10] = {20, "C7X_0", "Secure", "C7x Context 0 on Main island"},
+       [11] = {21, "C7X_1", "Non Secure", "C7x context 1 on Main island"},
+       [12] = {25, "C6X_0_0", "Secure", "C6x_0 Context 0 on Main island"},
+       [13] = {26, "C6X_0_1", "Non Secure", "C6x_0 context 1 on Main island"},
+       [14] = {27, "C6X_1_0", "Secure", "C6x_1 Context 0 on Main island"},
+       [15] = {28, "C6X_1_1", "Non Secure", "C6x_1 context 1 on Main island"},
+       [16] = {30, "GPU_0", "Non Secure", "RGX context 0 on Main island"},
+       [17] = {35, "MAIN_0_R5_0", "Non Secure", "Cortex R5_0 context 0 on Main island"},
+       [18] = {36, "MAIN_0_R5_1", "Secure", "Cortex R5_0 context 1 on Main island"},
+       [19] = {37, "MAIN_0_R5_2", "Non Secure", "Cortex R5_0 context 2 on Main island"},
+       [20] = {38, "MAIN_0_R5_3", "Secure", "Cortex R5_0 context 3 on MCU island"},
+       [21] = {40, "MAIN_1_R5_0", "Non Secure", "Cortex R5_1 context 0 on Main island"},
+       [22] = {41, "MAIN_1_R5_1", "Secure", "Cortex R5_1 context 1 on Main island"},
+       [23] = {42, "MAIN_1_R5_2", "Non Secure", "Cortex R5_1 context 2 on Main island"},
+       [24] = {43, "MAIN_1_R5_3", "Secure", "Cortex R5_1 context 3 on MCU island"},
+       [25] = {50, "ICSSG_0", "Non Secure", "ICSSG context 0 on Main island"},
+};