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raw | patch | inline | side by side (parent: b4c5d8c)
raw | patch | inline | side by side (parent: b4c5d8c)
author | Bryan Brattlof <bb@ti.com> | |
Tue, 1 Feb 2022 22:06:43 +0000 (16:06 -0600) | ||
committer | Bryan Brattlof <bb@ti.com> | |
Fri, 18 Mar 2022 14:00:14 +0000 (09:00 -0500) |
Provide the information for the clock IDs that identify incoming and
outgoing clocks from devices identified via device IDs in am62x SoC.
Signed-off-by: Bryan Brattlof <bb@ti.com>
outgoing clocks from devices identified via device IDs in am62x SoC.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Makefile | patch | blob | history | |
common/socinfo.c | patch | blob | history | |
soc/am62x/am62x_clocks_info.c | [new file with mode: 0644] | patch | blob |
soc/am62x/am62x_clocks_info.h | [new file with mode: 0644] | patch | blob |
diff --git a/Makefile b/Makefile
index af46cd393fa3249e995874b2999181932035bb35..7f4e31376ab70cd3b53d14e56e4a6ce7b49758d8 100644 (file)
--- a/Makefile
+++ b/Makefile
soc/am64x/am64x_rm_info.c
AM62XSOURCES =\
- soc/am62x/am62x_devices_info.c
+ soc/am62x/am62x_devices_info.c \
+ soc/am62x/am62x_clocks_info.c
COMMONOBJECTS= $(COMMONSOURCES:.c=.o)
AM65XOBJECTS= $(AM65XSOURCES:.c=.o)
diff --git a/common/socinfo.c b/common/socinfo.c
index 877678e413b5497606fca62f6d7b731ec377daf6..c6505194a367e7cc7610c4c301232982c748b6c4 100644 (file)
--- a/common/socinfo.c
+++ b/common/socinfo.c
#include <soc/am64x/am64x_clocks_info.h>
#include <soc/am64x/am64x_rm_info.h>
#include <soc/am62x/am62x_devices_info.h>
+#include <soc/am62x/am62x_clocks_info.h>
/* Assuming these addresses and definitions stay common across K3 devices */
#define CTRLMMR_WKUP_JTAG_DEVICE_ID 0x43000018
sci_info->devices_info = am62x_devices_info;
sci_info->num_devices = AM62X_MAX_DEVICES;
+ sci_info->clocks_info = am62x_clocks_info;
+ sci_info->num_clocks = AM62X_MAX_CLOCKS;
soc_info.host_id = 13;
soc_info.sec_proxy = &k3_lite_sec_proxy_base;
}
diff --git a/soc/am62x/am62x_clocks_info.c b/soc/am62x/am62x_clocks_info.c
--- /dev/null
@@ -0,0 +1,897 @@
+/*
+ * AM62X Clocks Info
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <tisci.h>
+#include <socinfo.h>
+
+struct ti_sci_clocks_info am62x_clocks_info[] = {
+ [0] = {166, 2, "DEV_A53SS0_A53_DIVH_CLK4_OBSCLK_OUT_CLK", "Output clock"},
+ [1] = {166, 3, "DEV_A53SS0_COREPAC_ARM_CLK_CLK", "Input clock"},
+ [2] = {166, 5, "DEV_A53SS0_PLL_CTRL_CLK", "Input clock"},
+ [3] = {135, 0, "DEV_A53SS0_CORE_0_A53_CORE0_ARM_CLK_CLK", "Input clock"},
+ [4] = {136, 0, "DEV_A53SS0_CORE_1_A53_CORE1_ARM_CLK_CLK", "Input clock"},
+ [5] = {137, 0, "DEV_A53SS0_CORE_2_A53_CORE2_ARM_CLK_CLK", "Input clock"},
+ [6] = {138, 0, "DEV_A53SS0_CORE_3_A53_CORE3_ARM_CLK_CLK", "Input clock"},
+ [7] = {172, 0, "DEV_A53_RS_BW_LIMITER0_CLK_CLK", "Input clock"},
+ [8] = {173, 0, "DEV_A53_WS_BW_LIMITER1_CLK_CLK", "Input clock"},
+ [9] = {157, 0, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN", "Input muxed clock"},
+ [10] = {157, 1, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [11] = {157, 2, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [12] = {157, 3, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [13] = {157, 4, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [14] = {157, 5, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [15] = {157, 6, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [16] = {157, 7, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [17] = {157, 8, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [18] = {157, 9, "DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT", "Output clock"},
+ [19] = {157, 10, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN", "Input muxed clock"},
+ [20] = {157, 11, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [21] = {157, 12, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [22] = {157, 13, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [23] = {157, 14, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [24] = {157, 15, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [25] = {157, 16, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [26] = {157, 17, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [27] = {157, 18, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [28] = {157, 19, "DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT", "Output clock"},
+ [29] = {157, 20, "DEV_BOARD0_CLKOUT0_IN", "Input muxed clock"},
+ [30] = {157, 21, "DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5", "Parent input clock option to DEV_BOARD0_CLKOUT0_IN"},
+ [31] = {157, 22, "DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10", "Parent input clock option to DEV_BOARD0_CLKOUT0_IN"},
+ [32] = {157, 23, "DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Output clock"},
+ [33] = {157, 24, "DEV_BOARD0_DDR0_CK0_IN", "Input clock"},
+ [34] = {157, 25, "DEV_BOARD0_DDR0_CK0_N_IN", "Input clock"},
+ [35] = {157, 27, "DEV_BOARD0_DDR0_CK0_OUT", "Output clock"},
+ [36] = {157, 33, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"},
+ [37] = {157, 34, "DEV_BOARD0_GPMC0_CLKLB_IN", "Input clock"},
+ [38] = {157, 35, "DEV_BOARD0_GPMC0_CLKLB_OUT", "Output clock"},
+ [39] = {157, 36, "DEV_BOARD0_GPMC0_CLK_IN", "Input clock"},
+ [40] = {157, 37, "DEV_BOARD0_GPMC0_FCLK_MUX_IN", "Input muxed clock"},
+ [41] = {157, 38, "DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_BOARD0_GPMC0_FCLK_MUX_IN"},
+ [42] = {157, 39, "DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK", "Parent input clock option to DEV_BOARD0_GPMC0_FCLK_MUX_IN"},
+ [43] = {157, 40, "DEV_BOARD0_I2C0_SCL_IN", "Input clock"},
+ [44] = {157, 41, "DEV_BOARD0_I2C0_SCL_OUT", "Output clock"},
+ [45] = {157, 42, "DEV_BOARD0_I2C1_SCL_IN", "Input clock"},
+ [46] = {157, 43, "DEV_BOARD0_I2C1_SCL_OUT", "Output clock"},
+ [47] = {157, 44, "DEV_BOARD0_I2C2_SCL_IN", "Input clock"},
+ [48] = {157, 45, "DEV_BOARD0_I2C2_SCL_OUT", "Output clock"},
+ [49] = {157, 46, "DEV_BOARD0_I2C3_SCL_IN", "Input clock"},
+ [50] = {157, 47, "DEV_BOARD0_I2C3_SCL_OUT", "Output clock"},
+ [51] = {157, 49, "DEV_BOARD0_MCASP0_ACLKR_IN", "Input clock"},
+ [52] = {157, 50, "DEV_BOARD0_MCASP0_ACLKR_OUT", "Output clock"},
+ [53] = {157, 51, "DEV_BOARD0_MCASP0_ACLKX_IN", "Input clock"},
+ [54] = {157, 52, "DEV_BOARD0_MCASP0_ACLKX_OUT", "Output clock"},
+ [55] = {157, 53, "DEV_BOARD0_MCASP0_AFSR_IN", "Input clock"},
+ [56] = {157, 54, "DEV_BOARD0_MCASP0_AFSX_IN", "Input clock"},
+ [57] = {157, 55, "DEV_BOARD0_MCASP1_ACLKR_IN", "Input clock"},
+ [58] = {157, 56, "DEV_BOARD0_MCASP1_ACLKR_OUT", "Output clock"},
+ [59] = {157, 57, "DEV_BOARD0_MCASP1_ACLKX_IN", "Input clock"},
+ [60] = {157, 58, "DEV_BOARD0_MCASP1_ACLKX_OUT", "Output clock"},
+ [61] = {157, 59, "DEV_BOARD0_MCASP1_AFSR_IN", "Input clock"},
+ [62] = {157, 60, "DEV_BOARD0_MCASP1_AFSX_IN", "Input clock"},
+ [63] = {157, 61, "DEV_BOARD0_MCASP2_ACLKR_IN", "Input clock"},
+ [64] = {157, 62, "DEV_BOARD0_MCASP2_ACLKR_OUT", "Output clock"},
+ [65] = {157, 63, "DEV_BOARD0_MCASP2_ACLKX_IN", "Input clock"},
+ [66] = {157, 64, "DEV_BOARD0_MCASP2_ACLKX_OUT", "Output clock"},
+ [67] = {157, 65, "DEV_BOARD0_MCASP2_AFSR_IN", "Input clock"},
+ [68] = {157, 66, "DEV_BOARD0_MCASP2_AFSX_IN", "Input clock"},
+ [69] = {157, 67, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"},
+ [70] = {157, 68, "DEV_BOARD0_MCU_I2C0_SCL_IN", "Input clock"},
+ [71] = {157, 69, "DEV_BOARD0_MCU_I2C0_SCL_OUT", "Output clock"},
+ [72] = {157, 70, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"},
+ [73] = {157, 71, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
+ [74] = {157, 72, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
+ [75] = {157, 73, "DEV_BOARD0_MCU_SPI0_CLK_IN", "Input clock"},
+ [76] = {157, 75, "DEV_BOARD0_MCU_SPI1_CLK_IN", "Input clock"},
+ [77] = {157, 77, "DEV_BOARD0_MCU_SYSCLKOUT0_IN", "Input clock"},
+ [78] = {157, 78, "DEV_BOARD0_MCU_TIMER_IO0_IN", "Input clock"},
+ [79] = {157, 79, "DEV_BOARD0_MCU_TIMER_IO1_IN", "Input clock"},
+ [80] = {157, 80, "DEV_BOARD0_MCU_TIMER_IO2_IN", "Input clock"},
+ [81] = {157, 81, "DEV_BOARD0_MCU_TIMER_IO3_IN", "Input clock"},
+ [82] = {157, 82, "DEV_BOARD0_MDIO0_MDC_IN", "Input clock"},
+ [83] = {157, 83, "DEV_BOARD0_MMC0_CLKLB_IN", "Input clock"},
+ [84] = {157, 84, "DEV_BOARD0_MMC0_CLKLB_OUT", "Output clock"},
+ [85] = {157, 86, "DEV_BOARD0_MMC0_CLK_OUT", "Output clock"},
+ [86] = {157, 87, "DEV_BOARD0_MMC1_CLKLB_IN", "Input clock"},
+ [87] = {157, 88, "DEV_BOARD0_MMC1_CLKLB_OUT", "Output clock"},
+ [88] = {157, 89, "DEV_BOARD0_MMC1_CLK_IN", "Input clock"},
+ [89] = {157, 90, "DEV_BOARD0_MMC1_CLK_OUT", "Output clock"},
+ [90] = {157, 91, "DEV_BOARD0_MMC2_CLKLB_IN", "Input clock"},
+ [91] = {157, 92, "DEV_BOARD0_MMC2_CLKLB_OUT", "Output clock"},
+ [92] = {157, 93, "DEV_BOARD0_MMC2_CLK_IN", "Input clock"},
+ [93] = {157, 94, "DEV_BOARD0_MMC2_CLK_OUT", "Output clock"},
+ [94] = {157, 95, "DEV_BOARD0_OBSCLK0_IN", "Input clock"},
+ [95] = {157, 96, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [96] = {157, 97, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [97] = {157, 98, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [98] = {157, 99, "DEV_BOARD0_OBSCLK0_IN_PARENT_SAM62_A53_512KB_WRAP_MAIN_0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSCLK_OUT_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [99] = {157, 100, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [100] = {157, 101, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [101] = {157, 102, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [102] = {157, 103, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [103] = {157, 104, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [104] = {157, 105, "DEV_BOARD0_OBSCLK0_IN_PARENT_MAIN_OBSCLK0_MUX_SEL_DIV_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [105] = {157, 106, "DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [106] = {157, 107, "DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [107] = {157, 108, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [108] = {157, 109, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [109] = {157, 110, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [110] = {157, 111, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [111] = {157, 112, "DEV_BOARD0_OBSCLK0_IN_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [112] = {157, 113, "DEV_BOARD0_OBSCLK0_IN_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [113] = {157, 128, "DEV_BOARD0_OSPI0_DQS_OUT", "Output clock"},
+ [114] = {157, 129, "DEV_BOARD0_OSPI0_LBCLKO_IN", "Input clock"},
+ [115] = {157, 130, "DEV_BOARD0_OSPI0_LBCLKO_OUT", "Output clock"},
+ [116] = {157, 131, "DEV_BOARD0_RGMII1_RXC_OUT", "Output clock"},
+ [117] = {157, 132, "DEV_BOARD0_RGMII1_TXC_IN", "Input clock"},
+ [118] = {157, 133, "DEV_BOARD0_RGMII1_TXC_OUT", "Output clock"},
+ [119] = {157, 134, "DEV_BOARD0_RGMII2_RXC_OUT", "Output clock"},
+ [120] = {157, 135, "DEV_BOARD0_RGMII2_TXC_IN", "Input clock"},
+ [121] = {157, 136, "DEV_BOARD0_RGMII2_TXC_OUT", "Output clock"},
+ [122] = {157, 137, "DEV_BOARD0_RMII1_REF_CLK_OUT", "Output clock"},
+ [123] = {157, 138, "DEV_BOARD0_RMII2_REF_CLK_OUT", "Output clock"},
+ [124] = {157, 139, "DEV_BOARD0_SPI0_CLK_IN", "Input clock"},
+ [125] = {157, 141, "DEV_BOARD0_SPI1_CLK_IN", "Input clock"},
+ [126] = {157, 143, "DEV_BOARD0_SPI2_CLK_IN", "Input clock"},
+ [127] = {157, 145, "DEV_BOARD0_SYSCLKOUT0_IN", "Input clock"},
+ [128] = {157, 146, "DEV_BOARD0_TCK_OUT", "Output clock"},
+ [129] = {157, 147, "DEV_BOARD0_TIMER_IO0_IN", "Input clock"},
+ [130] = {157, 148, "DEV_BOARD0_TIMER_IO1_IN", "Input clock"},
+ [131] = {157, 149, "DEV_BOARD0_TIMER_IO2_IN", "Input clock"},
+ [132] = {157, 150, "DEV_BOARD0_TIMER_IO3_IN", "Input clock"},
+ [133] = {157, 151, "DEV_BOARD0_TIMER_IO4_IN", "Input clock"},
+ [134] = {157, 152, "DEV_BOARD0_TIMER_IO5_IN", "Input clock"},
+ [135] = {157, 153, "DEV_BOARD0_TIMER_IO6_IN", "Input clock"},
+ [136] = {157, 154, "DEV_BOARD0_TIMER_IO7_IN", "Input clock"},
+ [137] = {157, 155, "DEV_BOARD0_TRC_CLK_IN", "Input clock"},
+ [138] = {157, 156, "DEV_BOARD0_VOUT0_EXTPCLKIN_OUT", "Output clock"},
+ [139] = {157, 157, "DEV_BOARD0_VOUT0_PCLK_IN", "Input clock"},
+ [140] = {157, 158, "DEV_BOARD0_WKUP_CLKOUT0_IN", "Input muxed clock"},
+ [141] = {157, 159, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"},
+ [142] = {157, 160, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_LFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"},
+ [143] = {157, 161, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"},
+ [144] = {157, 162, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"},
+ [145] = {157, 163, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT9_CLK", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"},
+ [146] = {157, 164, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"},
+ [147] = {157, 165, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"},
+ [148] = {157, 166, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"},
+ [149] = {193, 0, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK", "Input muxed clock"},
+ [150] = {193, 1, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK"},
+ [151] = {193, 2, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK"},
+ [152] = {193, 3, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_DIV_CLKOUT", "Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK"},
+ [153] = {193, 4, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT", "Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK"},
+ [154] = {1, 0, "DEV_CMP_EVENT_INTROUTER0_INTR_CLK", "Input clock"},
+ [155] = {13, 0, "DEV_CPSW0_CPPI_CLK_CLK", "Input clock"},
+ [156] = {13, 1, "DEV_CPSW0_CPTS_GENF0", "Output clock"},
+ [157] = {13, 2, "DEV_CPSW0_CPTS_GENF1", "Output clock"},
+ [158] = {13, 3, "DEV_CPSW0_CPTS_RFT_CLK", "Input muxed clock"},
+ [159] = {13, 4, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+ [160] = {13, 5, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+ [161] = {13, 6, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+ [162] = {13, 8, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+ [163] = {13, 9, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+ [164] = {13, 10, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+ [165] = {13, 11, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+ [166] = {13, 13, "DEV_CPSW0_GMII1_MR_CLK", "Input clock"},
+ [167] = {13, 14, "DEV_CPSW0_GMII1_MT_CLK", "Input clock"},
+ [168] = {13, 15, "DEV_CPSW0_GMII2_MR_CLK", "Input clock"},
+ [169] = {13, 16, "DEV_CPSW0_GMII2_MT_CLK", "Input clock"},
+ [170] = {13, 17, "DEV_CPSW0_GMII_RFT_CLK", "Input clock"},
+ [171] = {13, 18, "DEV_CPSW0_MDIO_MDCLK_O", "Output clock"},
+ [172] = {13, 19, "DEV_CPSW0_RGMII1_RXC_I", "Input clock"},
+ [173] = {13, 20, "DEV_CPSW0_RGMII1_TXC_I", "Input clock"},
+ [174] = {13, 21, "DEV_CPSW0_RGMII1_TXC_O", "Output clock"},
+ [175] = {13, 22, "DEV_CPSW0_RGMII2_RXC_I", "Input clock"},
+ [176] = {13, 23, "DEV_CPSW0_RGMII2_TXC_I", "Input clock"},
+ [177] = {13, 24, "DEV_CPSW0_RGMII2_TXC_O", "Output clock"},
+ [178] = {13, 25, "DEV_CPSW0_RGMII_MHZ_250_CLK", "Input clock"},
+ [179] = {13, 26, "DEV_CPSW0_RGMII_MHZ_50_CLK", "Input clock"},
+ [180] = {13, 27, "DEV_CPSW0_RGMII_MHZ_5_CLK", "Input clock"},
+ [181] = {13, 28, "DEV_CPSW0_RMII1_MHZ_50_CLK", "Input clock"},
+ [182] = {13, 29, "DEV_CPSW0_RMII2_MHZ_50_CLK", "Input clock"},
+ [183] = {14, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"},
+ [184] = {181, 0, "DEV_CPT2_AGGR1_VCLK_CLK", "Input clock"},
+ [185] = {182, 0, "DEV_CSI_RX_IF0_MAIN_CLK_CLK", "Input clock"},
+ [186] = {182, 2, "DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK", "Input clock"},
+ [187] = {182, 3, "DEV_CSI_RX_IF0_VBUS_CLK_CLK", "Input clock"},
+ [188] = {182, 4, "DEV_CSI_RX_IF0_VP_CLK_CLK", "Input clock"},
+ [189] = {2, 0, "DEV_DBGSUSPENDROUTER0_INTR_CLK", "Input clock"},
+ [190] = {16, 0, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"},
+ [191] = {16, 1, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"},
+ [192] = {16, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"},
+ [193] = {16, 3, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"},
+ [194] = {16, 4, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"},
+ [195] = {16, 5, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"},
+ [196] = {16, 6, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"},
+ [197] = {16, 7, "DEV_DCC0_DCC_CLKSRC7_CLK", "Input clock"},
+ [198] = {16, 8, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"},
+ [199] = {16, 9, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"},
+ [200] = {16, 10, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"},
+ [201] = {16, 11, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"},
+ [202] = {16, 12, "DEV_DCC0_VBUS_CLK", "Input clock"},
+ [203] = {17, 0, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"},
+ [204] = {17, 1, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"},
+ [205] = {17, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"},
+ [206] = {17, 3, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"},
+ [207] = {17, 4, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"},
+ [208] = {17, 5, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"},
+ [209] = {17, 6, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"},
+ [210] = {17, 7, "DEV_DCC1_DCC_CLKSRC7_CLK", "Input clock"},
+ [211] = {17, 8, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"},
+ [212] = {17, 9, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"},
+ [213] = {17, 10, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"},
+ [214] = {17, 11, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"},
+ [215] = {17, 12, "DEV_DCC1_VBUS_CLK", "Input clock"},
+ [216] = {18, 0, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"},
+ [217] = {18, 1, "DEV_DCC2_DCC_CLKSRC1_CLK", "Input clock"},
+ [218] = {18, 2, "DEV_DCC2_DCC_CLKSRC2_CLK", "Input clock"},
+ [219] = {18, 3, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"},
+ [220] = {18, 4, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"},
+ [221] = {18, 5, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"},
+ [222] = {18, 6, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"},
+ [223] = {18, 7, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"},
+ [224] = {18, 8, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"},
+ [225] = {18, 9, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"},
+ [226] = {18, 10, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"},
+ [227] = {18, 11, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"},
+ [228] = {18, 12, "DEV_DCC2_VBUS_CLK", "Input clock"},
+ [229] = {19, 0, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"},
+ [230] = {19, 1, "DEV_DCC3_DCC_CLKSRC1_CLK", "Input clock"},
+ [231] = {19, 3, "DEV_DCC3_DCC_CLKSRC3_CLK", "Input clock"},
+ [232] = {19, 4, "DEV_DCC3_DCC_CLKSRC4_CLK", "Input clock"},
+ [233] = {19, 5, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"},
+ [234] = {19, 6, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"},
+ [235] = {19, 7, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"},
+ [236] = {19, 8, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"},
+ [237] = {19, 9, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"},
+ [238] = {19, 10, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"},
+ [239] = {19, 11, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"},
+ [240] = {19, 12, "DEV_DCC3_VBUS_CLK", "Input clock"},
+ [241] = {20, 0, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input clock"},
+ [242] = {20, 1, "DEV_DCC4_DCC_CLKSRC1_CLK", "Input clock"},
+ [243] = {20, 2, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"},
+ [244] = {20, 3, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"},
+ [245] = {20, 4, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"},
+ [246] = {20, 5, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"},
+ [247] = {20, 6, "DEV_DCC4_DCC_CLKSRC6_CLK", "Input clock"},
+ [248] = {20, 7, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"},
+ [249] = {20, 8, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"},
+ [250] = {20, 9, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"},
+ [251] = {20, 10, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"},
+ [252] = {20, 11, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"},
+ [253] = {20, 12, "DEV_DCC4_VBUS_CLK", "Input clock"},
+ [254] = {21, 0, "DEV_DCC5_DCC_CLKSRC0_CLK", "Input clock"},
+ [255] = {21, 1, "DEV_DCC5_DCC_CLKSRC1_CLK", "Input clock"},
+ [256] = {21, 2, "DEV_DCC5_DCC_CLKSRC2_CLK", "Input clock"},
+ [257] = {21, 3, "DEV_DCC5_DCC_CLKSRC3_CLK", "Input clock"},
+ [258] = {21, 4, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"},
+ [259] = {21, 5, "DEV_DCC5_DCC_CLKSRC5_CLK", "Input clock"},
+ [260] = {21, 6, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"},
+ [261] = {21, 7, "DEV_DCC5_DCC_CLKSRC7_CLK", "Input clock"},
+ [262] = {21, 8, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"},
+ [263] = {21, 9, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"},
+ [264] = {21, 10, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"},
+ [265] = {21, 11, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"},
+ [266] = {21, 12, "DEV_DCC5_VBUS_CLK", "Input clock"},
+ [267] = {183, 0, "DEV_DCC6_DCC_CLKSRC0_CLK", "Input clock"},
+ [268] = {183, 1, "DEV_DCC6_DCC_CLKSRC1_CLK", "Input clock"},
+ [269] = {183, 2, "DEV_DCC6_DCC_CLKSRC2_CLK", "Input clock"},
+ [270] = {183, 3, "DEV_DCC6_DCC_CLKSRC3_CLK", "Input clock"},
+ [271] = {183, 4, "DEV_DCC6_DCC_CLKSRC4_CLK", "Input clock"},
+ [272] = {183, 5, "DEV_DCC6_DCC_CLKSRC5_CLK", "Input clock"},
+ [273] = {183, 6, "DEV_DCC6_DCC_CLKSRC6_CLK", "Input clock"},
+ [274] = {183, 7, "DEV_DCC6_DCC_CLKSRC7_CLK", "Input clock"},
+ [275] = {183, 8, "DEV_DCC6_DCC_INPUT00_CLK", "Input clock"},
+ [276] = {183, 9, "DEV_DCC6_DCC_INPUT01_CLK", "Input clock"},
+ [277] = {183, 10, "DEV_DCC6_DCC_INPUT02_CLK", "Input clock"},
+ [278] = {183, 11, "DEV_DCC6_DCC_INPUT10_CLK", "Input clock"},
+ [279] = {183, 12, "DEV_DCC6_VBUS_CLK", "Input clock"},
+ [280] = {85, 0, "DEV_DDPA0_DDPA_CLK", "Input clock"},
+ [281] = {170, 0, "DEV_DDR16SS0_DDRSS_DDR_PLL_CLK", "Input clock"},
+ [282] = {170, 1, "DEV_DDR16SS0_DDRSS_TCK", "Input clock"},
+ [283] = {170, 2, "DEV_DDR16SS0_PLL_CTRL_CLK", "Input clock"},
+ [284] = {171, 0, "DEV_DEBUGSS0_CFG_CLK", "Input clock"},
+ [285] = {171, 1, "DEV_DEBUGSS0_DBG_CLK", "Input clock"},
+ [286] = {171, 2, "DEV_DEBUGSS0_SYS_CLK", "Input clock"},
+ [287] = {24, 0, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"},
+ [288] = {24, 1, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"},
+ [289] = {24, 2, "DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK", "Output clock"},
+ [290] = {24, 20, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"},
+ [291] = {24, 22, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"},
+ [292] = {26, 0, "DEV_DMASS0_BCDMA_0_CLK", "Input clock"},
+ [293] = {27, 0, "DEV_DMASS0_CBASS_0_CLK", "Input clock"},
+ [294] = {28, 0, "DEV_DMASS0_INTAGGR_0_CLK", "Input clock"},
+ [295] = {29, 0, "DEV_DMASS0_IPCSS_0_CLK", "Input clock"},
+ [296] = {30, 0, "DEV_DMASS0_PKTDMA_0_CLK", "Input clock"},
+ [297] = {33, 0, "DEV_DMASS0_RINGACC_0_CLK", "Input clock"},
+ [298] = {185, 2, "DEV_DPHY_RX0_IO_RX_CL_L_M", "Input clock"},
+ [299] = {185, 2, "DEV_DPHY_RX0_IO_RX_CL_L_M", "Output clock"},
+ [300] = {185, 3, "DEV_DPHY_RX0_IO_RX_CL_L_P", "Input clock"},
+ [301] = {185, 3, "DEV_DPHY_RX0_IO_RX_CL_L_P", "Output clock"},
+ [302] = {185, 4, "DEV_DPHY_RX0_JTAG_TCK", "Input clock"},
+ [303] = {185, 5, "DEV_DPHY_RX0_MAIN_CLK_CLK", "Input clock"},
+ [304] = {185, 7, "DEV_DPHY_RX0_PPI_RX_BYTE_CLK", "Output clock"},
+ [305] = {186, 0, "DEV_DSS0_DPI_0_IN_CLK", "Input clock"},
+ [306] = {186, 2, "DEV_DSS0_DPI_1_IN_CLK", "Input muxed clock"},
+ [307] = {186, 3, "DEV_DSS0_DPI_1_IN_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI_1_IN_CLK"},
+ [308] = {186, 4, "DEV_DSS0_DPI_1_IN_CLK_PARENT_BOARD_0_VOUT0_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI_1_IN_CLK"},
+ [309] = {186, 5, "DEV_DSS0_DPI_1_OUT_CLK", "Output clock"},
+ [310] = {186, 6, "DEV_DSS0_DSS_FUNC_CLK", "Input clock"},
+ [311] = {51, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"},
+ [312] = {52, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"},
+ [313] = {53, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"},
+ [314] = {54, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"},
+ [315] = {86, 0, "DEV_EPWM0_VBUSP_CLK", "Input clock"},
+ [316] = {87, 0, "DEV_EPWM1_VBUSP_CLK", "Input clock"},
+ [317] = {88, 0, "DEV_EPWM2_VBUSP_CLK", "Input clock"},
+ [318] = {59, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"},
+ [319] = {60, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"},
+ [320] = {62, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"},
+ [321] = {63, 0, "DEV_ESM0_CLK", "Input clock"},
+ [322] = {74, 0, "DEV_FSS0_FSAS_0_GCLK", "Input clock"},
+ [323] = {75, 0, "DEV_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"},
+ [324] = {75, 1, "DEV_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"},
+ [325] = {75, 2, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"},
+ [326] = {75, 3, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_ICLK_CLK"},
+ [327] = {75, 4, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_ICLK_CLK"},
+ [328] = {75, 5, "DEV_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"},
+ [329] = {75, 6, "DEV_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"},
+ [330] = {75, 7, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK", "Input muxed clock"},
+ [331] = {75, 8, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_RCLK_CLK"},
+ [332] = {75, 9, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_RCLK_CLK"},
+ [333] = {76, 0, "DEV_GICSS0_VCLK_CLK", "Input clock"},
+ [334] = {77, 0, "DEV_GPIO0_MMR_CLK", "Input clock"},
+ [335] = {78, 0, "DEV_GPIO1_MMR_CLK", "Input clock"},
+ [336] = {80, 0, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"},
+ [337] = {80, 1, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
+ [338] = {80, 2, "DEV_GPMC0_FUNC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
+ [339] = {80, 3, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"},
+ [340] = {80, 4, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"},
+ [341] = {80, 5, "DEV_GPMC0_VBUSM_CLK", "Input clock"},
+ [342] = {187, 0, "DEV_GPU0_GPU_CLK", "Input clock"},
+ [343] = {174, 0, "DEV_GPU_RS_BW_LIMITER2_CLK_CLK", "Input clock"},
+ [344] = {175, 0, "DEV_GPU_WS_BW_LIMITER3_CLK_CLK", "Input clock"},
+ [345] = {102, 0, "DEV_I2C0_CLK", "Input clock"},
+ [346] = {102, 1, "DEV_I2C0_PISCL", "Input clock"},
+ [347] = {102, 2, "DEV_I2C0_PISYS_CLK", "Input clock"},
+ [348] = {102, 3, "DEV_I2C0_PORSCL", "Output clock"},
+ [349] = {103, 0, "DEV_I2C1_CLK", "Input clock"},
+ [350] = {103, 1, "DEV_I2C1_PISCL", "Input clock"},
+ [351] = {103, 2, "DEV_I2C1_PISYS_CLK", "Input clock"},
+ [352] = {103, 3, "DEV_I2C1_PORSCL", "Output clock"},
+ [353] = {104, 0, "DEV_I2C2_CLK", "Input clock"},
+ [354] = {104, 1, "DEV_I2C2_PISCL", "Input clock"},
+ [355] = {104, 2, "DEV_I2C2_PISYS_CLK", "Input clock"},
+ [356] = {104, 3, "DEV_I2C2_PORSCL", "Output clock"},
+ [357] = {105, 0, "DEV_I2C3_CLK", "Input clock"},
+ [358] = {105, 1, "DEV_I2C3_PISCL", "Input clock"},
+ [359] = {105, 2, "DEV_I2C3_PISYS_CLK", "Input clock"},
+ [360] = {105, 3, "DEV_I2C3_PORSCL", "Output clock"},
+ [361] = {81, 0, "DEV_ICSSM0_CORE_CLK", "Input muxed clock"},
+ [362] = {81, 1, "DEV_ICSSM0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_ICSSM0_CORE_CLK"},
+ [363] = {81, 2, "DEV_ICSSM0_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK", "Parent input clock option to DEV_ICSSM0_CORE_CLK"},
+ [364] = {81, 3, "DEV_ICSSM0_IEP_CLK", "Input muxed clock"},
+ [365] = {81, 4, "DEV_ICSSM0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_ICSSM0_IEP_CLK"},
+ [366] = {81, 5, "DEV_ICSSM0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_ICSSM0_IEP_CLK"},
+ [367] = {81, 6, "DEV_ICSSM0_IEP_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_ICSSM0_IEP_CLK"},
+ [368] = {81, 8, "DEV_ICSSM0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ICSSM0_IEP_CLK"},
+ [369] = {81, 9, "DEV_ICSSM0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ICSSM0_IEP_CLK"},
+ [370] = {81, 10, "DEV_ICSSM0_IEP_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_ICSSM0_IEP_CLK"},
+ [371] = {81, 11, "DEV_ICSSM0_IEP_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_ICSSM0_IEP_CLK"},
+ [372] = {81, 13, "DEV_ICSSM0_UCLK_CLK", "Input clock"},
+ [373] = {81, 14, "DEV_ICSSM0_VCLK_CLK", "Input clock"},
+ [374] = {83, 1, "DEV_LED0_VBUS_CLK", "Input clock"},
+ [375] = {3, 0, "DEV_MAIN_GPIOMUX_INTROUTER0_INTR_CLK", "Input clock"},
+ [376] = {98, 1, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [377] = {98, 2, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+ [378] = {98, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+ [379] = {98, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+ [380] = {98, 5, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+ [381] = {98, 6, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"},
+ [382] = {190, 0, "DEV_MCASP0_AUX_CLK", "Input muxed clock"},
+ [383] = {190, 1, "DEV_MCASP0_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+ [384] = {190, 2, "DEV_MCASP0_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+ [385] = {190, 3, "DEV_MCASP0_MCASP_ACLKR_PIN", "Input clock"},
+ [386] = {190, 4, "DEV_MCASP0_MCASP_ACLKR_POUT", "Output clock"},
+ [387] = {190, 5, "DEV_MCASP0_MCASP_ACLKX_PIN", "Input clock"},
+ [388] = {190, 6, "DEV_MCASP0_MCASP_ACLKX_POUT", "Output clock"},
+ [389] = {190, 7, "DEV_MCASP0_MCASP_AFSR_POUT", "Output clock"},
+ [390] = {190, 8, "DEV_MCASP0_MCASP_AFSX_POUT", "Output clock"},
+ [391] = {190, 9, "DEV_MCASP0_MCASP_AHCLKR_PIN", "Input muxed clock"},
+ [392] = {190, 10, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+ [393] = {190, 11, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+ [394] = {190, 12, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+ [395] = {190, 13, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+ [396] = {190, 14, "DEV_MCASP0_MCASP_AHCLKR_POUT", "Output clock"},
+ [397] = {190, 15, "DEV_MCASP0_MCASP_AHCLKX_PIN", "Input muxed clock"},
+ [398] = {190, 16, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+ [399] = {190, 17, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+ [400] = {190, 18, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+ [401] = {190, 19, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+ [402] = {190, 20, "DEV_MCASP0_MCASP_AHCLKX_POUT", "Output clock"},
+ [403] = {190, 21, "DEV_MCASP0_VBUSP_CLK", "Input clock"},
+ [404] = {191, 0, "DEV_MCASP1_AUX_CLK", "Input muxed clock"},
+ [405] = {191, 1, "DEV_MCASP1_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+ [406] = {191, 2, "DEV_MCASP1_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+ [407] = {191, 3, "DEV_MCASP1_MCASP_ACLKR_PIN", "Input clock"},
+ [408] = {191, 4, "DEV_MCASP1_MCASP_ACLKR_POUT", "Output clock"},
+ [409] = {191, 5, "DEV_MCASP1_MCASP_ACLKX_PIN", "Input clock"},
+ [410] = {191, 6, "DEV_MCASP1_MCASP_ACLKX_POUT", "Output clock"},
+ [411] = {191, 7, "DEV_MCASP1_MCASP_AFSR_POUT", "Output clock"},
+ [412] = {191, 8, "DEV_MCASP1_MCASP_AFSX_POUT", "Output clock"},
+ [413] = {191, 9, "DEV_MCASP1_MCASP_AHCLKR_PIN", "Input muxed clock"},
+ [414] = {191, 10, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+ [415] = {191, 11, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+ [416] = {191, 12, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+ [417] = {191, 13, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+ [418] = {191, 14, "DEV_MCASP1_MCASP_AHCLKR_POUT", "Output clock"},
+ [419] = {191, 15, "DEV_MCASP1_MCASP_AHCLKX_PIN", "Input muxed clock"},
+ [420] = {191, 16, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+ [421] = {191, 17, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+ [422] = {191, 18, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+ [423] = {191, 19, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+ [424] = {191, 20, "DEV_MCASP1_MCASP_AHCLKX_POUT", "Output clock"},
+ [425] = {191, 21, "DEV_MCASP1_VBUSP_CLK", "Input clock"},
+ [426] = {192, 0, "DEV_MCASP2_AUX_CLK", "Input muxed clock"},
+ [427] = {192, 1, "DEV_MCASP2_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+ [428] = {192, 2, "DEV_MCASP2_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+ [429] = {192, 3, "DEV_MCASP2_MCASP_ACLKR_PIN", "Input clock"},
+ [430] = {192, 4, "DEV_MCASP2_MCASP_ACLKR_POUT", "Output clock"},
+ [431] = {192, 5, "DEV_MCASP2_MCASP_ACLKX_PIN", "Input clock"},
+ [432] = {192, 6, "DEV_MCASP2_MCASP_ACLKX_POUT", "Output clock"},
+ [433] = {192, 7, "DEV_MCASP2_MCASP_AFSR_POUT", "Output clock"},
+ [434] = {192, 8, "DEV_MCASP2_MCASP_AFSX_POUT", "Output clock"},
+ [435] = {192, 9, "DEV_MCASP2_MCASP_AHCLKR_PIN", "Input muxed clock"},
+ [436] = {192, 10, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+ [437] = {192, 11, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+ [438] = {192, 12, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+ [439] = {192, 13, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+ [440] = {192, 14, "DEV_MCASP2_MCASP_AHCLKR_POUT", "Output clock"},
+ [441] = {192, 15, "DEV_MCASP2_MCASP_AHCLKX_PIN", "Input muxed clock"},
+ [442] = {192, 16, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+ [443] = {192, 17, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+ [444] = {192, 18, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+ [445] = {192, 19, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+ [446] = {192, 20, "DEV_MCASP2_MCASP_AHCLKX_POUT", "Output clock"},
+ [447] = {192, 21, "DEV_MCASP2_VBUSP_CLK", "Input clock"},
+ [448] = {116, 0, "DEV_MCRC64_0_CLK", "Input clock"},
+ [449] = {141, 0, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"},
+ [450] = {141, 1, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"},
+ [451] = {141, 2, "DEV_MCSPI0_VBUSP_CLK", "Input clock"},
+ [452] = {142, 0, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"},
+ [453] = {142, 1, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"},
+ [454] = {142, 2, "DEV_MCSPI1_VBUSP_CLK", "Input clock"},
+ [455] = {143, 0, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"},
+ [456] = {143, 1, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"},
+ [457] = {143, 2, "DEV_MCSPI2_VBUSP_CLK", "Input clock"},
+ [458] = {23, 0, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"},
+ [459] = {23, 1, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"},
+ [460] = {23, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"},
+ [461] = {23, 3, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"},
+ [462] = {23, 4, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"},
+ [463] = {23, 5, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"},
+ [464] = {23, 6, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"},
+ [465] = {23, 7, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"},
+ [466] = {23, 8, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"},
+ [467] = {23, 9, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"},
+ [468] = {23, 10, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"},
+ [469] = {23, 11, "DEV_MCU_DCC0_DCC_INPUT10_CLK", "Input clock"},
+ [470] = {23, 12, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"},
+ [471] = {79, 0, "DEV_MCU_GPIO0_MMR_CLK", "Input muxed clock"},
+ [472] = {79, 1, "DEV_MCU_GPIO0_MMR_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_GPIO0_MMR_CLK"},
+ [473] = {79, 2, "DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_GPIO0_MMR_CLK"},
+ [474] = {79, 3, "DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_GPIO0_MMR_CLK"},
+ [475] = {79, 4, "DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_GPIO0_MMR_CLK"},
+ [476] = {106, 0, "DEV_MCU_I2C0_CLK", "Input clock"},
+ [477] = {106, 1, "DEV_MCU_I2C0_PISCL", "Input clock"},
+ [478] = {106, 2, "DEV_MCU_I2C0_PISYS_CLK", "Input clock"},
+ [479] = {106, 3, "DEV_MCU_I2C0_PORSCL", "Output clock"},
+ [480] = {8, 0, "DEV_MCU_M4FSS0_CBASS_0_CLK", "Input clock"},
+ [481] = {9, 0, "DEV_MCU_M4FSS0_CORE0_DAP_CLK", "Input clock"},
+ [482] = {9, 1, "DEV_MCU_M4FSS0_CORE0_VBUS_CLK", "Input muxed clock"},
+ [483] = {9, 2, "DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_M4FSS0_CORE0_VBUS_CLK"},
+ [484] = {9, 3, "DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_M4FSS0_CORE0_VBUS_CLK"},
+ [485] = {188, 1, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [486] = {188, 2, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
+ [487] = {188, 3, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
+ [488] = {188, 4, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
+ [489] = {188, 5, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
+ [490] = {188, 6, "DEV_MCU_MCAN0_MCANSS_HCLK_CLK", "Input clock"},
+ [491] = {189, 1, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [492] = {189, 2, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
+ [493] = {189, 3, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
+ [494] = {189, 4, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
+ [495] = {189, 5, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
+ [496] = {189, 6, "DEV_MCU_MCAN1_MCANSS_HCLK_CLK", "Input clock"},
+ [497] = {100, 0, "DEV_MCU_MCRC64_0_CLK", "Input clock"},
+ [498] = {147, 0, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"},
+ [499] = {147, 1, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"},
+ [500] = {147, 2, "DEV_MCU_MCSPI0_VBUSP_CLK", "Input clock"},
+ [501] = {148, 0, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"},
+ [502] = {148, 1, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"},
+ [503] = {148, 2, "DEV_MCU_MCSPI1_VBUSP_CLK", "Input clock"},
+ [504] = {180, 3, "DEV_MCU_MCU_16FF0_PLL_CTRL_MCU_CLK24_CLK", "Input clock"},
+ [505] = {131, 0, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"},
+ [506] = {131, 1, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
+ [507] = {131, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
+ [508] = {131, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
+ [509] = {131, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_MCU_WWDTCLK_SEL_DIV_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
+ [510] = {131, 5, "DEV_MCU_RTI0_VBUSP_CLK", "Input clock"},
+ [511] = {35, 0, "DEV_MCU_TIMER0_TIMER_HCLK_CLK", "Input clock"},
+ [512] = {35, 1, "DEV_MCU_TIMER0_TIMER_PWM", "Output clock"},
+ [513] = {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"},
+ [514] = {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+ [515] = {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+ [516] = {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+ [517] = {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+ [518] = {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+ [519] = {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+ [520] = {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+ [521] = {35, 10, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT0_DIV_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+ [522] = {48, 0, "DEV_MCU_TIMER1_TIMER_HCLK_CLK", "Input clock"},
+ [523] = {48, 1, "DEV_MCU_TIMER1_TIMER_PWM", "Output clock"},
+ [524] = {48, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"},
+ [525] = {48, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
+ [526] = {48, 4, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
+ [527] = {48, 5, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
+ [528] = {48, 6, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
+ [529] = {48, 7, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
+ [530] = {48, 8, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
+ [531] = {48, 9, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
+ [532] = {48, 10, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT1_DIV_CLKOUT", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
+ [533] = {49, 0, "DEV_MCU_TIMER2_TIMER_HCLK_CLK", "Input clock"},
+ [534] = {49, 1, "DEV_MCU_TIMER2_TIMER_PWM", "Output clock"},
+ [535] = {49, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"},
+ [536] = {49, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+ [537] = {49, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+ [538] = {49, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+ [539] = {49, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+ [540] = {49, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+ [541] = {49, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+ [542] = {49, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+ [543] = {49, 10, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT2_DIV_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+ [544] = {50, 0, "DEV_MCU_TIMER3_TIMER_HCLK_CLK", "Input clock"},
+ [545] = {50, 1, "DEV_MCU_TIMER3_TIMER_PWM", "Output clock"},
+ [546] = {50, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"},
+ [547] = {50, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
+ [548] = {50, 4, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
+ [549] = {50, 5, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
+ [550] = {50, 6, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
+ [551] = {50, 7, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
+ [552] = {50, 8, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
+ [553] = {50, 9, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
+ [554] = {50, 10, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT3_DIV_CLKOUT", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
+ [555] = {149, 0, "DEV_MCU_UART0_FCLK_CLK", "Input clock"},
+ [556] = {149, 3, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"},
+ [557] = {57, 0, "DEV_MMCSD0_EMMCSDSS_IO_CLK_I", "Input muxed clock"},
+ [558] = {57, 1, "DEV_MMCSD0_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC0_CLKLB_OUT", "Parent input clock option to DEV_MMCSD0_EMMCSDSS_IO_CLK_I"},
+ [559] = {57, 2, "DEV_MMCSD0_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC0_CLK_OUT", "Parent input clock option to DEV_MMCSD0_EMMCSDSS_IO_CLK_I"},
+ [560] = {57, 3, "DEV_MMCSD0_EMMCSDSS_IO_CLK_O", "Output clock"},
+ [561] = {57, 5, "DEV_MMCSD0_EMMCSDSS_VBUS_CLK", "Input clock"},
+ [562] = {57, 6, "DEV_MMCSD0_EMMCSDSS_XIN_CLK", "Input muxed clock"},
+ [563] = {57, 7, "DEV_MMCSD0_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSDSS_XIN_CLK"},
+ [564] = {57, 8, "DEV_MMCSD0_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSDSS_XIN_CLK"},
+ [565] = {58, 0, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I", "Input muxed clock"},
+ [566] = {58, 1, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLKLB_OUT", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_IO_CLK_I"},
+ [567] = {58, 2, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLK_OUT", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_IO_CLK_I"},
+ [568] = {58, 3, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O", "Output clock"},
+ [569] = {58, 5, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"},
+ [570] = {58, 6, "DEV_MMCSD1_EMMCSDSS_XIN_CLK", "Input muxed clock"},
+ [571] = {58, 7, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
+ [572] = {58, 8, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
+ [573] = {184, 0, "DEV_MMCSD2_EMMCSDSS_IO_CLK_I", "Input muxed clock"},
+ [574] = {184, 1, "DEV_MMCSD2_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC2_CLKLB_OUT", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_IO_CLK_I"},
+ [575] = {184, 2, "DEV_MMCSD2_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC2_CLK_OUT", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_IO_CLK_I"},
+ [576] = {184, 3, "DEV_MMCSD2_EMMCSDSS_IO_CLK_O", "Output clock"},
+ [577] = {184, 5, "DEV_MMCSD2_EMMCSDSS_VBUS_CLK", "Input clock"},
+ [578] = {184, 6, "DEV_MMCSD2_EMMCSDSS_XIN_CLK", "Input muxed clock"},
+ [579] = {184, 7, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"},
+ [580] = {184, 8, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"},
+ [581] = {163, 7, "DEV_PBIST0_CLK8_CLK", "Input clock"},
+ [582] = {163, 9, "DEV_PBIST0_TCLK_CLK", "Input clock"},
+ [583] = {164, 7, "DEV_PBIST1_CLK8_CLK", "Input clock"},
+ [584] = {164, 9, "DEV_PBIST1_TCLK_CLK", "Input clock"},
+ [585] = {168, 0, "DEV_PSC0_FW_0_CLK", "Input clock"},
+ [586] = {169, 0, "DEV_PSC0_PSC_0_CLK", "Input clock"},
+ [587] = {169, 1, "DEV_PSC0_PSC_0_SLOW_CLK", "Input clock"},
+ [588] = {121, 0, "DEV_R5FSS0_CORE0_CPU_CLK", "Input muxed clock"},
+ [589] = {121, 1, "DEV_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_R5FSS0_CORE0_CPU_CLK"},
+ [590] = {121, 2, "DEV_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_R5FSS0_CORE0_CPU_CLK"},
+ [591] = {121, 3, "DEV_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"},
+ [592] = {125, 0, "DEV_RTI0_RTI_CLK", "Input muxed clock"},
+ [593] = {125, 1, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+ [594] = {125, 2, "DEV_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+ [595] = {125, 3, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+ [596] = {125, 4, "DEV_RTI0_RTI_CLK_PARENT_MAIN_WWDTCLKN_SEL_OUT0_DIV_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+ [597] = {125, 5, "DEV_RTI0_VBUSP_CLK", "Input clock"},
+ [598] = {126, 0, "DEV_RTI1_RTI_CLK", "Input muxed clock"},
+ [599] = {126, 1, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+ [600] = {126, 2, "DEV_RTI1_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+ [601] = {126, 3, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+ [602] = {126, 4, "DEV_RTI1_RTI_CLK_PARENT_MAIN_WWDTCLKN_SEL_OUT1_DIV_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+ [603] = {126, 5, "DEV_RTI1_VBUSP_CLK", "Input clock"},
+ [604] = {130, 0, "DEV_RTI15_RTI_CLK", "Input muxed clock"},
+ [605] = {130, 1, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+ [606] = {130, 2, "DEV_RTI15_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+ [607] = {130, 3, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+ [608] = {130, 4, "DEV_RTI15_RTI_CLK_PARENT_MAIN_WWDTCLKN_SEL_OUT4_DIV_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+ [609] = {130, 5, "DEV_RTI15_VBUSP_CLK", "Input clock"},
+ [610] = {127, 0, "DEV_RTI2_RTI_CLK", "Input muxed clock"},
+ [611] = {127, 1, "DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI2_RTI_CLK"},
+ [612] = {127, 2, "DEV_RTI2_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI2_RTI_CLK"},
+ [613] = {127, 3, "DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI2_RTI_CLK"},
+ [614] = {127, 4, "DEV_RTI2_RTI_CLK_PARENT_MAIN_WWDTCLKN_SEL_OUT2_DIV_CLKOUT", "Parent input clock option to DEV_RTI2_RTI_CLK"},
+ [615] = {127, 5, "DEV_RTI2_VBUSP_CLK", "Input clock"},
+ [616] = {128, 0, "DEV_RTI3_RTI_CLK", "Input muxed clock"},
+ [617] = {128, 1, "DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI3_RTI_CLK"},
+ [618] = {128, 2, "DEV_RTI3_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI3_RTI_CLK"},
+ [619] = {128, 3, "DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI3_RTI_CLK"},
+ [620] = {128, 4, "DEV_RTI3_RTI_CLK_PARENT_MAIN_WWDTCLKN_SEL_OUT3_DIV_CLKOUT", "Parent input clock option to DEV_RTI3_RTI_CLK"},
+ [621] = {128, 5, "DEV_RTI3_VBUSP_CLK", "Input clock"},
+ [622] = {66, 0, "DEV_SA3_SS0_DMSS_ECCAGGR_0_X1_CLK", "Input clock"},
+ [623] = {67, 0, "DEV_SA3_SS0_INTAGGR_0_X1_CLK", "Input clock"},
+ [624] = {68, 0, "DEV_SA3_SS0_PKTDMA_0_X1_CLK", "Input clock"},
+ [625] = {69, 0, "DEV_SA3_SS0_RINGACC_0_X1_CLK", "Input clock"},
+ [626] = {70, 0, "DEV_SA3_SS0_SA_UL_0_PKA_IN_CLK", "Input clock"},
+ [627] = {70, 1, "DEV_SA3_SS0_SA_UL_0_X1_CLK", "Input clock"},
+ [628] = {70, 2, "DEV_SA3_SS0_SA_UL_0_X2_CLK", "Input clock"},
+ [629] = {150, 0, "DEV_SPINLOCK0_VCLK_CLK", "Input clock"},
+ [630] = {15, 0, "DEV_STM0_ATB_CLK", "Input clock"},
+ [631] = {15, 1, "DEV_STM0_CORE_CLK", "Input clock"},
+ [632] = {15, 2, "DEV_STM0_VBUSP_CLK", "Input clock"},
+ [633] = {36, 0, "DEV_TIMER0_TIMER_HCLK_CLK", "Input clock"},
+ [634] = {36, 1, "DEV_TIMER0_TIMER_PWM", "Output clock"},
+ [635] = {36, 2, "DEV_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"},
+ [636] = {36, 3, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [637] = {36, 4, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [638] = {36, 5, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [639] = {36, 6, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [640] = {36, 7, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [641] = {36, 8, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [642] = {36, 10, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [643] = {36, 11, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [644] = {36, 12, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [645] = {36, 13, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [646] = {36, 14, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [647] = {37, 0, "DEV_TIMER1_TIMER_HCLK_CLK", "Input clock"},
+ [648] = {37, 1, "DEV_TIMER1_TIMER_PWM", "Output clock"},
+ [649] = {37, 2, "DEV_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"},
+ [650] = {37, 3, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
+ [651] = {37, 4, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
+ [652] = {37, 5, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
+ [653] = {37, 6, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
+ [654] = {37, 7, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
+ [655] = {37, 8, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
+ [656] = {37, 10, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
+ [657] = {37, 11, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
+ [658] = {37, 12, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
+ [659] = {37, 13, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
+ [660] = {37, 14, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
+ [661] = {38, 0, "DEV_TIMER2_TIMER_HCLK_CLK", "Input clock"},
+ [662] = {38, 1, "DEV_TIMER2_TIMER_PWM", "Output clock"},
+ [663] = {38, 2, "DEV_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"},
+ [664] = {38, 3, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [665] = {38, 4, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [666] = {38, 5, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [667] = {38, 6, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [668] = {38, 7, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [669] = {38, 8, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [670] = {38, 10, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [671] = {38, 11, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [672] = {38, 12, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [673] = {38, 13, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [674] = {38, 14, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [675] = {39, 0, "DEV_TIMER3_TIMER_HCLK_CLK", "Input clock"},
+ [676] = {39, 1, "DEV_TIMER3_TIMER_PWM", "Output clock"},
+ [677] = {39, 2, "DEV_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"},
+ [678] = {39, 3, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
+ [679] = {39, 4, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
+ [680] = {39, 5, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
+ [681] = {39, 6, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
+ [682] = {39, 7, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
+ [683] = {39, 8, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
+ [684] = {39, 10, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
+ [685] = {39, 11, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
+ [686] = {39, 12, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
+ [687] = {39, 13, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
+ [688] = {39, 14, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
+ [689] = {40, 0, "DEV_TIMER4_TIMER_HCLK_CLK", "Input clock"},
+ [690] = {40, 1, "DEV_TIMER4_TIMER_PWM", "Output clock"},
+ [691] = {40, 2, "DEV_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"},
+ [692] = {40, 3, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [693] = {40, 4, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [694] = {40, 5, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [695] = {40, 6, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [696] = {40, 7, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [697] = {40, 8, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [698] = {40, 10, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [699] = {40, 11, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [700] = {40, 12, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [701] = {40, 13, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [702] = {40, 14, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [703] = {41, 0, "DEV_TIMER5_TIMER_HCLK_CLK", "Input clock"},
+ [704] = {41, 1, "DEV_TIMER5_TIMER_PWM", "Output clock"},
+ [705] = {41, 2, "DEV_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"},
+ [706] = {41, 3, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
+ [707] = {41, 4, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
+ [708] = {41, 5, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
+ [709] = {41, 6, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
+ [710] = {41, 7, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
+ [711] = {41, 8, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
+ [712] = {41, 10, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
+ [713] = {41, 11, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
+ [714] = {41, 12, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
+ [715] = {41, 13, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
+ [716] = {41, 14, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
+ [717] = {42, 0, "DEV_TIMER6_TIMER_HCLK_CLK", "Input clock"},
+ [718] = {42, 1, "DEV_TIMER6_TIMER_PWM", "Output clock"},
+ [719] = {42, 2, "DEV_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"},
+ [720] = {42, 3, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [721] = {42, 4, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [722] = {42, 5, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [723] = {42, 6, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [724] = {42, 7, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [725] = {42, 8, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [726] = {42, 10, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [727] = {42, 11, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [728] = {42, 12, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [729] = {42, 13, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [730] = {42, 14, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [731] = {43, 0, "DEV_TIMER7_TIMER_HCLK_CLK", "Input clock"},
+ [732] = {43, 1, "DEV_TIMER7_TIMER_PWM", "Output clock"},
+ [733] = {43, 2, "DEV_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"},
+ [734] = {43, 3, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
+ [735] = {43, 4, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
+ [736] = {43, 5, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
+ [737] = {43, 6, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
+ [738] = {43, 7, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
+ [739] = {43, 8, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
+ [740] = {43, 10, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
+ [741] = {43, 11, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
+ [742] = {43, 12, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
+ [743] = {43, 13, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
+ [744] = {43, 14, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
+ [745] = {6, 0, "DEV_TIMESYNC_EVENT_ROUTER0_INTR_CLK", "Input clock"},
+ [746] = {146, 0, "DEV_UART0_FCLK_CLK", "Input muxed clock"},
+ [747] = {146, 1, "DEV_UART0_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT0", "Parent input clock option to DEV_UART0_FCLK_CLK"},
+ [748] = {146, 2, "DEV_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART0_FCLK_CLK"},
+ [749] = {146, 5, "DEV_UART0_VBUSP_CLK", "Input clock"},
+ [750] = {152, 0, "DEV_UART1_FCLK_CLK", "Input muxed clock"},
+ [751] = {152, 1, "DEV_UART1_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT1", "Parent input clock option to DEV_UART1_FCLK_CLK"},
+ [752] = {152, 2, "DEV_UART1_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART1_FCLK_CLK"},
+ [753] = {152, 5, "DEV_UART1_VBUSP_CLK", "Input clock"},
+ [754] = {153, 0, "DEV_UART2_FCLK_CLK", "Input muxed clock"},
+ [755] = {153, 1, "DEV_UART2_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT2", "Parent input clock option to DEV_UART2_FCLK_CLK"},
+ [756] = {153, 2, "DEV_UART2_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART2_FCLK_CLK"},
+ [757] = {153, 5, "DEV_UART2_VBUSP_CLK", "Input clock"},
+ [758] = {154, 0, "DEV_UART3_FCLK_CLK", "Input muxed clock"},
+ [759] = {154, 1, "DEV_UART3_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT3", "Parent input clock option to DEV_UART3_FCLK_CLK"},
+ [760] = {154, 2, "DEV_UART3_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART3_FCLK_CLK"},
+ [761] = {154, 5, "DEV_UART3_VBUSP_CLK", "Input clock"},
+ [762] = {155, 0, "DEV_UART4_FCLK_CLK", "Input muxed clock"},
+ [763] = {155, 1, "DEV_UART4_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT4", "Parent input clock option to DEV_UART4_FCLK_CLK"},
+ [764] = {155, 2, "DEV_UART4_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART4_FCLK_CLK"},
+ [765] = {155, 5, "DEV_UART4_VBUSP_CLK", "Input clock"},
+ [766] = {156, 0, "DEV_UART5_FCLK_CLK", "Input muxed clock"},
+ [767] = {156, 1, "DEV_UART5_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT5", "Parent input clock option to DEV_UART5_FCLK_CLK"},
+ [768] = {156, 2, "DEV_UART5_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART5_FCLK_CLK"},
+ [769] = {156, 5, "DEV_UART5_VBUSP_CLK", "Input clock"},
+ [770] = {158, 0, "DEV_UART6_FCLK_CLK", "Input muxed clock"},
+ [771] = {158, 1, "DEV_UART6_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT6", "Parent input clock option to DEV_UART6_FCLK_CLK"},
+ [772] = {158, 2, "DEV_UART6_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART6_FCLK_CLK"},
+ [773] = {158, 5, "DEV_UART6_VBUSP_CLK", "Input clock"},
+ [774] = {161, 0, "DEV_USB0_BUS_CLK", "Input clock"},
+ [775] = {161, 1, "DEV_USB0_CFG_CLK", "Input clock"},
+ [776] = {161, 2, "DEV_USB0_USB2_APB_PCLK_CLK", "Input clock"},
+ [777] = {161, 3, "DEV_USB0_USB2_REFCLOCK_CLK", "Input muxed clock"},
+ [778] = {161, 4, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"},
+ [779] = {161, 5, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"},
+ [780] = {161, 10, "DEV_USB0_USB2_TAP_TCK", "Input clock"},
+ [781] = {162, 0, "DEV_USB1_BUS_CLK", "Input clock"},
+ [782] = {162, 1, "DEV_USB1_CFG_CLK", "Input clock"},
+ [783] = {162, 2, "DEV_USB1_USB2_APB_PCLK_CLK", "Input clock"},
+ [784] = {162, 3, "DEV_USB1_USB2_REFCLOCK_CLK", "Input muxed clock"},
+ [785] = {162, 4, "DEV_USB1_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK"},
+ [786] = {162, 5, "DEV_USB1_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK"},
+ [787] = {162, 10, "DEV_USB1_USB2_TAP_TCK", "Input clock"},
+ [788] = {176, 0, "DEV_WKUP_DEEPSLEEP_SOURCES0_CLK_12M_RC_CLK", "Input clock"},
+ [789] = {64, 0, "DEV_WKUP_ESM0_CLK", "Input clock"},
+ [790] = {61, 0, "DEV_WKUP_GTC0_GTC_CLK", "Input muxed clock"},
+ [791] = {61, 1, "DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"},
+ [792] = {61, 2, "DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"},
+ [793] = {61, 3, "DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"},
+ [794] = {61, 5, "DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"},
+ [795] = {61, 6, "DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"},
+ [796] = {61, 7, "DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"},
+ [797] = {61, 8, "DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"},
+ [798] = {61, 9, "DEV_WKUP_GTC0_VBUSP_CLK", "Input muxed clock"},
+ [799] = {61, 10, "DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_GTC0_VBUSP_CLK"},
+ [800] = {61, 11, "DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_GTC0_VBUSP_CLK"},
+ [801] = {107, 0, "DEV_WKUP_I2C0_CLK", "Input muxed clock"},
+ [802] = {107, 1, "DEV_WKUP_I2C0_CLK_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_I2C0_CLK"},
+ [803] = {107, 2, "DEV_WKUP_I2C0_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_I2C0_CLK"},
+ [804] = {107, 3, "DEV_WKUP_I2C0_PISCL", "Input clock"},
+ [805] = {107, 4, "DEV_WKUP_I2C0_PISYS_CLK", "Input clock"},
+ [806] = {107, 5, "DEV_WKUP_I2C0_PORSCL", "Output clock"},
+ [807] = {5, 0, "DEV_WKUP_MCU_GPIOMUX_INTROUTER0_INTR_CLK", "Input clock"},
+ [808] = {165, 7, "DEV_WKUP_PBIST0_CLK8_CLK", "Input clock"},
+ [809] = {140, 0, "DEV_WKUP_PSC0_CLK", "Input clock"},
+ [810] = {140, 1, "DEV_WKUP_PSC0_SLOW_CLK", "Input clock"},
+ [811] = {117, 0, "DEV_WKUP_RTCSS0_ANA_OSC32K_CLK", "Input muxed clock"},
+ [812] = {117, 1, "DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_WKUP_RTCSS0_ANA_OSC32K_CLK"},
+ [813] = {117, 2, "DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_RTC_CLK_SEL_DIV_CLKOUT", "Parent input clock option to DEV_WKUP_RTCSS0_ANA_OSC32K_CLK"},
+ [814] = {117, 6, "DEV_WKUP_RTCSS0_VCLK_CLK", "Input muxed clock"},
+ [815] = {117, 7, "DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_RTCSS0_VCLK_CLK"},
+ [816] = {117, 8, "DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_RTCSS0_VCLK_CLK"},
+ [817] = {132, 0, "DEV_WKUP_RTI0_RTI_CLK", "Input muxed clock"},
+ [818] = {132, 1, "DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_RTI0_RTI_CLK"},
+ [819] = {132, 2, "DEV_WKUP_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_WKUP_RTI0_RTI_CLK"},
+ [820] = {132, 3, "DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_WKUP_RTI0_RTI_CLK"},
+ [821] = {132, 4, "DEV_WKUP_RTI0_RTI_CLK_PARENT_WKUP_WWDTCLK_SEL_DIV_CLKOUT", "Parent input clock option to DEV_WKUP_RTI0_RTI_CLK"},
+ [822] = {132, 5, "DEV_WKUP_RTI0_VBUSP_CLK", "Input muxed clock"},
+ [823] = {132, 6, "DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_RTI0_VBUSP_CLK"},
+ [824] = {132, 7, "DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_RTI0_VBUSP_CLK"},
+ [825] = {110, 0, "DEV_WKUP_TIMER0_TIMER_HCLK_CLK", "Input muxed clock"},
+ [826] = {110, 1, "DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_HCLK_CLK"},
+ [827] = {110, 2, "DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_HCLK_CLK"},
+ [828] = {110, 4, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"},
+ [829] = {110, 5, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"},
+ [830] = {110, 6, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_WKUP_CLKSEL_OUT04", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"},
+ [831] = {110, 7, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"},
+ [832] = {110, 8, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"},
+ [833] = {110, 9, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"},
+ [834] = {110, 10, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"},
+ [835] = {110, 11, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"},
+ [836] = {110, 12, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_WKUP_TIMERCLKN_SEL_OUT0_DIV_CLKOUT", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"},
+ [837] = {111, 0, "DEV_WKUP_TIMER1_TIMER_HCLK_CLK", "Input muxed clock"},
+ [838] = {111, 1, "DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_HCLK_CLK"},
+ [839] = {111, 2, "DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_HCLK_CLK"},
+ [840] = {111, 4, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"},
+ [841] = {111, 5, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"},
+ [842] = {111, 6, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_WKUP_CLKSEL_OUT04", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"},
+ [843] = {111, 7, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"},
+ [844] = {111, 8, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"},
+ [845] = {111, 9, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"},
+ [846] = {111, 10, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"},
+ [847] = {111, 11, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"},
+ [848] = {111, 12, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_WKUP_TIMERCLKN_SEL_OUT1_DIV_CLKOUT", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"},
+ [849] = {114, 0, "DEV_WKUP_UART0_FCLK_CLK", "Input clock"},
+ [850] = {114, 3, "DEV_WKUP_UART0_VBUSP_CLK", "Input muxed clock"},
+ [851] = {114, 4, "DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_UART0_VBUSP_CLK"},
+ [852] = {114, 5, "DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_UART0_VBUSP_CLK"},
+ [853] = {95, 0, "DEV_WKUP_VTM0_FIX_REF2_CLK", "Input clock"},
+ [854] = {95, 1, "DEV_WKUP_VTM0_FIX_REF_CLK", "Input clock"},
+ [855] = {95, 2, "DEV_WKUP_VTM0_VBUSP_CLK", "Input muxed clock"},
+ [856] = {95, 3, "DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_VTM0_VBUSP_CLK"},
+ [857] = {95, 4, "DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_VTM0_VBUSP_CLK"},
+};
diff --git a/soc/am62x/am62x_clocks_info.h b/soc/am62x/am62x_clocks_info.h
--- /dev/null
@@ -0,0 +1,42 @@
+/*
+ * AM62X Clocks Info
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __AM62X_CLOCKS_INFO_H
+#define __AM62X_CLOCKS_INFO_H
+
+#define AM62X_MAX_CLOCKS 858
+
+extern struct ti_sci_clocks_info am62x_clocks_info[];
+
+#endif /* __AM62X_CLOCKS_INFO_H */
\ No newline at end of file