soc: j721e: Add the missing clock ids for each device
authorLokesh Vutla <lokeshvutla@ti.com>
Tue, 14 Apr 2020 05:44:32 +0000 (11:14 +0530)
committerLokesh Vutla <lokeshvutla@ti.com>
Tue, 14 Apr 2020 05:45:36 +0000 (11:15 +0530)
First clock for each device is missed by auto generation. Add the first
clock id and update the clock names to latest sysfw documentation.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
soc/j721e/j721e_clocks_info.c
soc/j721e/j721e_clocks_info.h

index b41b791abab665d06de5b9f3662cb35983589f13..f5da88e067ad8ed0869e3ec1bd81c9846203b956 100644 (file)
 #include <socinfo.h>
 
 struct ti_sci_clocks_info j721e_clocks_info[] = {
-       [0] = {202, 1, "DEV_A72SS0_CORE0_MSMC_CLK", "Input clock"},
-       [1] = {202, 2, "DEV_A72SS0_CORE0_ARM_CLK_CLK", "Input clock"},
-       [2] = {139, 1, "DEV_AASRC0_VBUSP_CLK", "Input clock"},
-       [3] = {139, 2, "DEV_AASRC0_RX0_SYNC_0", "Input muxed clock"},
-       [4] = {139, 3, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [5] = {139, 4, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [6] = {139, 5, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [7] = {139, 6, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [8] = {139, 7, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [9] = {139, 8, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [10] = {139, 9, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [11] = {139, 10, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [12] = {139, 11, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [13] = {139, 12, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [14] = {139, 13, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [15] = {139, 14, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [16] = {139, 15, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [17] = {139, 16, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [18] = {139, 17, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [19] = {139, 18, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [20] = {139, 19, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [21] = {139, 20, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [22] = {139, 21, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [23] = {139, 22, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [24] = {139, 23, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [25] = {139, 24, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [26] = {139, 25, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [27] = {139, 26, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [28] = {139, 27, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [29] = {139, 28, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [30] = {139, 29, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [31] = {139, 30, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [32] = {139, 31, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [33] = {139, 32, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [34] = {139, 33, "DEV_AASRC0_RX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [35] = {139, 34, "DEV_AASRC0_RX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [36] = {139, 35, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [37] = {139, 36, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [38] = {139, 37, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [39] = {139, 38, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
-       [40] = {139, 39, "DEV_AASRC0_RX1_SYNC_0", "Input muxed clock"},
-       [41] = {139, 40, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [42] = {139, 41, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [43] = {139, 42, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [44] = {139, 43, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [45] = {139, 44, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [46] = {139, 45, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [47] = {139, 46, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [48] = {139, 47, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [49] = {139, 48, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [50] = {139, 49, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [51] = {139, 50, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [52] = {139, 51, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [53] = {139, 52, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [54] = {139, 53, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [55] = {139, 54, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [56] = {139, 55, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [57] = {139, 56, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [58] = {139, 57, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [59] = {139, 58, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [60] = {139, 59, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [61] = {139, 60, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [62] = {139, 61, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [63] = {139, 62, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [64] = {139, 63, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [65] = {139, 64, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [66] = {139, 65, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [67] = {139, 66, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [68] = {139, 67, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [69] = {139, 68, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [70] = {139, 69, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [71] = {139, 70, "DEV_AASRC0_RX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [72] = {139, 71, "DEV_AASRC0_RX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [73] = {139, 72, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [74] = {139, 73, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [75] = {139, 74, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [76] = {139, 75, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
-       [77] = {139, 76, "DEV_AASRC0_RX2_SYNC_0", "Input muxed clock"},
-       [78] = {139, 77, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [79] = {139, 78, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [80] = {139, 79, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [81] = {139, 80, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [82] = {139, 81, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [83] = {139, 82, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [84] = {139, 83, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [85] = {139, 84, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [86] = {139, 85, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [87] = {139, 86, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [88] = {139, 87, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [89] = {139, 88, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [90] = {139, 89, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [91] = {139, 90, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [92] = {139, 91, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [93] = {139, 92, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [94] = {139, 93, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [95] = {139, 94, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [96] = {139, 95, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [97] = {139, 96, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [98] = {139, 97, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [99] = {139, 98, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [100] = {139, 99, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [101] = {139, 100, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [102] = {139, 101, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [103] = {139, 102, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [104] = {139, 103, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [105] = {139, 104, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [106] = {139, 105, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [107] = {139, 106, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [108] = {139, 107, "DEV_AASRC0_RX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [109] = {139, 108, "DEV_AASRC0_RX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [110] = {139, 109, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [111] = {139, 110, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [112] = {139, 111, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [113] = {139, 112, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
-       [114] = {139, 113, "DEV_AASRC0_RX3_SYNC_0", "Input muxed clock"},
-       [115] = {139, 114, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [116] = {139, 115, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [117] = {139, 116, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [118] = {139, 117, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [119] = {139, 118, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [120] = {139, 119, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [121] = {139, 120, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [122] = {139, 121, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [123] = {139, 122, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [124] = {139, 123, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [125] = {139, 124, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [126] = {139, 125, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [127] = {139, 126, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [128] = {139, 127, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [129] = {139, 128, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [130] = {139, 129, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [131] = {139, 130, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [132] = {139, 131, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [133] = {139, 132, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [134] = {139, 133, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [135] = {139, 134, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [136] = {139, 135, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [137] = {139, 136, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [138] = {139, 137, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [139] = {139, 138, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [140] = {139, 139, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [141] = {139, 140, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [142] = {139, 141, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [143] = {139, 142, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [144] = {139, 143, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [145] = {139, 144, "DEV_AASRC0_RX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [146] = {139, 145, "DEV_AASRC0_RX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [147] = {139, 146, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [148] = {139, 147, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [149] = {139, 148, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [150] = {139, 149, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
-       [151] = {139, 150, "DEV_AASRC0_TX0_SYNC_0", "Input muxed clock"},
-       [152] = {139, 151, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [153] = {139, 152, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [154] = {139, 153, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [155] = {139, 154, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [156] = {139, 155, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [157] = {139, 156, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [158] = {139, 157, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [159] = {139, 158, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [160] = {139, 159, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [161] = {139, 160, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [162] = {139, 161, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [163] = {139, 162, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [164] = {139, 163, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [165] = {139, 164, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [166] = {139, 165, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [167] = {139, 166, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [168] = {139, 167, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [169] = {139, 168, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [170] = {139, 169, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [171] = {139, 170, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [172] = {139, 171, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [173] = {139, 172, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [174] = {139, 173, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [175] = {139, 174, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [176] = {139, 175, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [177] = {139, 176, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [178] = {139, 177, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [179] = {139, 178, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [180] = {139, 179, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [181] = {139, 180, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [182] = {139, 181, "DEV_AASRC0_TX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [183] = {139, 182, "DEV_AASRC0_TX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [184] = {139, 183, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [185] = {139, 184, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [186] = {139, 185, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [187] = {139, 186, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
-       [188] = {139, 187, "DEV_AASRC0_TX1_SYNC_0", "Input muxed clock"},
-       [189] = {139, 188, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [190] = {139, 189, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [191] = {139, 190, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [192] = {139, 191, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [193] = {139, 192, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [194] = {139, 193, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [195] = {139, 194, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [196] = {139, 195, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [197] = {139, 196, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [198] = {139, 197, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [199] = {139, 198, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [200] = {139, 199, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [201] = {139, 200, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [202] = {139, 201, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [203] = {139, 202, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [204] = {139, 203, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [205] = {139, 204, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [206] = {139, 205, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [207] = {139, 206, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [208] = {139, 207, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [209] = {139, 208, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [210] = {139, 209, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [211] = {139, 210, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [212] = {139, 211, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [213] = {139, 212, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [214] = {139, 213, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [215] = {139, 214, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [216] = {139, 215, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [217] = {139, 216, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [218] = {139, 217, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [219] = {139, 218, "DEV_AASRC0_TX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [220] = {139, 219, "DEV_AASRC0_TX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [221] = {139, 220, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [222] = {139, 221, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [223] = {139, 222, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [224] = {139, 223, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
-       [225] = {139, 224, "DEV_AASRC0_TX2_SYNC_0", "Input muxed clock"},
-       [226] = {139, 225, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [227] = {139, 226, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [228] = {139, 227, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [229] = {139, 228, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [230] = {139, 229, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [231] = {139, 230, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [232] = {139, 231, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [233] = {139, 232, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [234] = {139, 233, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [235] = {139, 234, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [236] = {139, 235, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [237] = {139, 236, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [238] = {139, 237, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [239] = {139, 238, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [240] = {139, 239, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [241] = {139, 240, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [242] = {139, 241, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [243] = {139, 242, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [244] = {139, 243, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [245] = {139, 244, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [246] = {139, 245, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [247] = {139, 246, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [248] = {139, 247, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [249] = {139, 248, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [250] = {139, 249, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [251] = {139, 250, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [252] = {139, 251, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [253] = {139, 252, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [254] = {139, 253, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [255] = {139, 254, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [256] = {139, 255, "DEV_AASRC0_TX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [257] = {139, 256, "DEV_AASRC0_TX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [258] = {139, 257, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [259] = {139, 258, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [260] = {139, 259, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [261] = {139, 260, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
-       [262] = {139, 261, "DEV_AASRC0_TX3_SYNC_0", "Input muxed clock"},
-       [263] = {139, 262, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [264] = {139, 263, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [265] = {139, 264, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [266] = {139, 265, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [267] = {139, 266, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [268] = {139, 267, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [269] = {139, 268, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [270] = {139, 269, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [271] = {139, 270, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [272] = {139, 271, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [273] = {139, 272, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [274] = {139, 273, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [275] = {139, 274, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [276] = {139, 275, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [277] = {139, 276, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [278] = {139, 277, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [279] = {139, 278, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [280] = {139, 279, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [281] = {139, 280, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [282] = {139, 281, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [283] = {139, 282, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [284] = {139, 283, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [285] = {139, 284, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [286] = {139, 285, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [287] = {139, 286, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [288] = {139, 287, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [289] = {139, 288, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [290] = {139, 289, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [291] = {139, 290, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [292] = {139, 291, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [293] = {139, 292, "DEV_AASRC0_TX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [294] = {139, 293, "DEV_AASRC0_TX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [295] = {139, 294, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [296] = {139, 295, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [297] = {139, 296, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [298] = {139, 297, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
-       [299] = {2, 1, "DEV_ATL0_ATL_CLK", "Input muxed clock"},
-       [300] = {2, 2, "DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT1_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
-       [301] = {2, 3, "DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
-       [302] = {2, 4, "DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT1_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
-       [303] = {2, 5, "DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
-       [304] = {2, 6, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"},
-       [305] = {2, 7, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"},
-       [306] = {2, 8, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1", "Output clock"},
-       [307] = {2, 9, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_0", "Output clock"},
-       [308] = {2, 10, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3", "Output clock"},
-       [309] = {2, 11, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2", "Output clock"},
-       [310] = {157, 2, "DEV_BOARD0_SPI1_CLK_IN", "Input clock"},
-       [311] = {157, 4, "DEV_BOARD0_SPI2_CLK_IN", "Input clock"},
-       [312] = {157, 6, "DEV_BOARD0_SPI3_CLK_IN", "Input clock"},
-       [313] = {157, 8, "DEV_BOARD0_SPI5_CLK_IN", "Input clock"},
-       [314] = {157, 10, "DEV_BOARD0_SPI6_CLK_IN", "Input clock"},
-       [315] = {157, 12, "DEV_BOARD0_SPI7_CLK_IN", "Input clock"},
-       [316] = {157, 14, "DEV_BOARD0_MCU_SPI0_CLK_IN", "Input clock"},
-       [317] = {157, 16, "DEV_BOARD0_MCU_SPI1_CLK_IN", "Input clock"},
-       [318] = {157, 18, "DEV_BOARD0_MCU_OSPI0_CLK_IN", "Input clock"},
-       [319] = {157, 19, "DEV_BOARD0_MCU_OSPI0_LBCLKO_IN", "Input clock"},
-       [320] = {157, 20, "DEV_BOARD0_MCU_OSPI0_DQS_OUT", "Output clock"},
-       [321] = {157, 21, "DEV_BOARD0_MCU_OSPI1_CLK_IN", "Input clock"},
-       [322] = {157, 22, "DEV_BOARD0_MCU_OSPI1_LBCLKO_IN", "Input clock"},
-       [323] = {157, 23, "DEV_BOARD0_MCU_OSPI1_DQS_OUT", "Output clock"},
-       [324] = {157, 25, "DEV_BOARD0_I2C0_SCL_OUT", "Output clock"},
-       [325] = {157, 27, "DEV_BOARD0_I2C1_SCL_OUT", "Output clock"},
-       [326] = {157, 29, "DEV_BOARD0_I2C2_SCL_OUT", "Output clock"},
-       [327] = {157, 31, "DEV_BOARD0_I2C3_SCL_OUT", "Output clock"},
-       [328] = {157, 33, "DEV_BOARD0_I2C4_SCL_OUT", "Output clock"},
-       [329] = {157, 35, "DEV_BOARD0_I2C5_SCL_OUT", "Output clock"},
-       [330] = {157, 37, "DEV_BOARD0_I2C6_SCL_OUT", "Output clock"},
-       [331] = {157, 38, "DEV_BOARD0_MCU_I2C0_SCL_IN", "Input clock"},
-       [332] = {157, 39, "DEV_BOARD0_MCU_I2C0_SCL_OUT", "Output clock"},
-       [333] = {157, 41, "DEV_BOARD0_MCU_I2C1_SCL_OUT", "Output clock"},
-       [334] = {157, 42, "DEV_BOARD0_WKUP_I2C0_SCL_IN", "Input clock"},
-       [335] = {157, 43, "DEV_BOARD0_WKUP_I2C0_SCL_OUT", "Output clock"},
-       [336] = {157, 44, "DEV_BOARD0_I3C0_SCL_IN", "Input clock"},
-       [337] = {157, 45, "DEV_BOARD0_I3C0_SCL_OUT", "Output clock"},
-       [338] = {157, 46, "DEV_BOARD0_MCU_I3C0_SCL_IN", "Input clock"},
-       [339] = {157, 47, "DEV_BOARD0_MCU_I3C0_SCL_OUT", "Output clock"},
-       [340] = {157, 48, "DEV_BOARD0_MCU_I3C1_SCL_IN", "Input clock"},
-       [341] = {157, 49, "DEV_BOARD0_MCU_I3C1_SCL_OUT", "Output clock"},
-       [342] = {157, 50, "DEV_BOARD0_MCU_HYPERBUS0_CK_IN", "Input clock"},
-       [343] = {157, 51, "DEV_BOARD0_MCU_HYPERBUS0_CKN_IN", "Input clock"},
-       [344] = {157, 52, "DEV_BOARD0_DSI_TXCLKP_IN", "Input clock"},
-       [345] = {157, 53, "DEV_BOARD0_DSI_TXCLKN_IN", "Input clock"},
-       [346] = {157, 54, "DEV_BOARD0_PRG0_MDIO0_MDC_IN", "Input clock"},
-       [347] = {157, 55, "DEV_BOARD0_PRG0_RGMII1_TXC_IN", "Input clock"},
-       [348] = {157, 56, "DEV_BOARD0_PRG0_RGMII1_TXC_OUT", "Output clock"},
-       [349] = {157, 57, "DEV_BOARD0_PRG0_RGMII1_RXC_OUT", "Output clock"},
-       [350] = {157, 58, "DEV_BOARD0_PRG0_RGMII2_TXC_IN", "Input clock"},
-       [351] = {157, 59, "DEV_BOARD0_PRG0_RGMII2_TXC_OUT", "Output clock"},
-       [352] = {157, 60, "DEV_BOARD0_PRG0_RGMII2_RXC_OUT", "Output clock"},
-       [353] = {157, 61, "DEV_BOARD0_PRG1_MDIO0_MDC_IN", "Input clock"},
-       [354] = {157, 62, "DEV_BOARD0_PRG1_RGMII1_TXC_IN", "Input clock"},
-       [355] = {157, 63, "DEV_BOARD0_PRG1_RGMII1_TXC_OUT", "Output clock"},
-       [356] = {157, 64, "DEV_BOARD0_PRG1_RGMII1_RXC_OUT", "Output clock"},
-       [357] = {157, 65, "DEV_BOARD0_PRG1_RGMII2_TXC_IN", "Input clock"},
-       [358] = {157, 66, "DEV_BOARD0_PRG1_RGMII2_TXC_OUT", "Output clock"},
-       [359] = {157, 67, "DEV_BOARD0_PRG1_RGMII2_RXC_OUT", "Output clock"},
-       [360] = {157, 68, "DEV_BOARD0_MDIO0_MDC_IN", "Input clock"},
-       [361] = {157, 70, "DEV_BOARD0_RGMII3_RXC_OUT", "Output clock"},
-       [362] = {157, 72, "DEV_BOARD0_RGMII4_RXC_OUT", "Output clock"},
-       [363] = {157, 74, "DEV_BOARD0_RGMII5_RXC_OUT", "Output clock"},
-       [364] = {157, 76, "DEV_BOARD0_RGMII6_RXC_OUT", "Output clock"},
-       [365] = {157, 78, "DEV_BOARD0_RGMII7_RXC_OUT", "Output clock"},
-       [366] = {157, 80, "DEV_BOARD0_RGMII8_RXC_OUT", "Output clock"},
-       [367] = {157, 81, "DEV_BOARD0_RMII_REF_CLK_OUT", "Output clock"},
-       [368] = {157, 82, "DEV_BOARD0_CPTS0_RFT_CLK_OUT", "Output clock"},
-       [369] = {157, 83, "DEV_BOARD0_MCU_MDIO0_MDC_IN", "Input clock"},
-       [370] = {157, 84, "DEV_BOARD0_MCU_RGMII1_TXC_IN", "Input clock"},
-       [371] = {157, 85, "DEV_BOARD0_MCU_RGMII1_TXC_OUT", "Output clock"},
-       [372] = {157, 86, "DEV_BOARD0_MCU_RGMII1_RXC_OUT", "Output clock"},
-       [373] = {157, 87, "DEV_BOARD0_MCU_RMII1_REF_CLK_OUT", "Output clock"},
-       [374] = {157, 88, "DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT", "Output clock"},
-       [375] = {157, 89, "DEV_BOARD0_UFS0_REF_CLK_IN", "Input clock"},
-       [376] = {157, 91, "DEV_BOARD0_DDR0_CK0_IN", "Input clock"},
-       [377] = {157, 92, "DEV_BOARD0_DDR0_CK0_N_IN", "Input clock"},
-       [378] = {157, 99, "DEV_BOARD0_MMC0_CLK_IN", "Input clock"},
-       [379] = {157, 100, "DEV_BOARD0_MMC1_CLK_IN", "Input clock"},
-       [380] = {157, 101, "DEV_BOARD0_MMC2_CLK_IN", "Input clock"},
-       [381] = {157, 102, "DEV_BOARD0_GPMC0_CLK_IN", "Input clock"},
-       [382] = {157, 103, "DEV_BOARD0_GPMC0_CLK_OUT", "Output clock"},
-       [383] = {157, 104, "DEV_BOARD0_GPMC0_FCLK_MUX_IN", "Input clock"},
-       [384] = {157, 105, "DEV_BOARD0_MLB0_MLBCLK_OUT", "Output clock"},
-       [385] = {157, 106, "DEV_BOARD0_MLB0_MLBCP_OUT", "Output clock"},
-       [386] = {157, 108, "DEV_BOARD0_VPFE0_PCLK_OUT", "Output clock"},
-       [387] = {157, 109, "DEV_BOARD0_VOUT1_PCLK_IN", "Input clock"},
-       [388] = {157, 110, "DEV_BOARD0_VOUT1_EXTPCLKIN_OUT", "Output clock"},
-       [389] = {157, 111, "DEV_BOARD0_VOUT2_PCLK_IN", "Input clock"},
-       [390] = {157, 112, "DEV_BOARD0_VOUT2_EXTPCLKIN_OUT", "Output clock"},
-       [391] = {157, 113, "DEV_BOARD0_OBSCLK0_IN", "Input clock"},
-       [392] = {157, 114, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [393] = {157, 115, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [394] = {157, 116, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [395] = {157, 117, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [396] = {157, 118, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [397] = {157, 119, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_5_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [398] = {157, 120, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [399] = {157, 126, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [400] = {157, 127, "DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [401] = {157, 128, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [402] = {157, 129, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [403] = {157, 130, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [404] = {157, 131, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [405] = {157, 132, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [406] = {157, 133, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [407] = {157, 137, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [408] = {157, 138, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_24_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [409] = {157, 139, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [410] = {157, 140, "DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [411] = {157, 141, "DEV_BOARD0_OBSCLK0_IN_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [412] = {157, 142, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [413] = {157, 143, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [414] = {157, 144, "DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [415] = {157, 145, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
-       [416] = {157, 146, "DEV_BOARD0_OBSCLK1_IN", "Input muxed clock"},
-       [417] = {157, 147, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_7_HSDIVOUT0_CLK3", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
-       [418] = {157, 148, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK7", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
-       [419] = {157, 149, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_13_HSDIVOUT0_CLK3", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
-       [420] = {157, 152, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"},
-       [421] = {157, 153, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
-       [422] = {157, 154, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
-       [423] = {157, 169, "DEV_BOARD0_SYSCLKOUT0_IN", "Input clock"},
-       [424] = {157, 170, "DEV_BOARD0_MCU_SYSCLKOUT0_IN", "Input clock"},
-       [425] = {157, 171, "DEV_BOARD0_TRC_CLK_IN", "Input clock"},
-       [426] = {157, 172, "DEV_BOARD0_CLKOUT_IN", "Input muxed clock"},
-       [427] = {157, 173, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"},
-       [428] = {157, 174, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"},
-       [429] = {157, 175, "DEV_BOARD0_MCU_CLKOUT0_IN", "Input muxed clock"},
-       [430] = {157, 176, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK4", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"},
-       [431] = {157, 177, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK9", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"},
-       [432] = {157, 178, "DEV_BOARD0_LED_CLK_OUT", "Output clock"},
-       [433] = {157, 179, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"},
-       [434] = {157, 180, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"},
-       [435] = {157, 181, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"},
-       [436] = {157, 182, "DEV_BOARD0_TCK_OUT", "Output clock"},
-       [437] = {157, 185, "DEV_BOARD0_PCIE_REFCLK0P_OUT", "Output clock"},
-       [438] = {157, 186, "DEV_BOARD0_PCIE_REFCLK0N_OUT", "Output clock"},
-       [439] = {157, 191, "DEV_BOARD0_PCIE_REFCLK1P_OUT", "Output clock"},
-       [440] = {157, 192, "DEV_BOARD0_PCIE_REFCLK1N_OUT", "Output clock"},
-       [441] = {157, 197, "DEV_BOARD0_PCIE_REFCLK2P_OUT", "Output clock"},
-       [442] = {157, 198, "DEV_BOARD0_PCIE_REFCLK2N_OUT", "Output clock"},
-       [443] = {157, 201, "DEV_BOARD0_PCIE_REFCLK3P_OUT", "Output clock"},
-       [444] = {157, 202, "DEV_BOARD0_PCIE_REFCLK3N_OUT", "Output clock"},
-       [445] = {157, 217, "DEV_BOARD0_MCASP0_ACLKR_IN", "Input clock"},
-       [446] = {157, 218, "DEV_BOARD0_MCASP0_ACLKR_OUT", "Output clock"},
-       [447] = {157, 219, "DEV_BOARD0_MCASP0_AFSR_OUT", "Output clock"},
-       [448] = {157, 220, "DEV_BOARD0_MCASP0_ACLKX_IN", "Input clock"},
-       [449] = {157, 221, "DEV_BOARD0_MCASP0_ACLKX_OUT", "Output clock"},
-       [450] = {157, 222, "DEV_BOARD0_MCASP0_AFSX_OUT", "Output clock"},
-       [451] = {157, 223, "DEV_BOARD0_MCASP1_ACLKR_IN", "Input clock"},
-       [452] = {157, 224, "DEV_BOARD0_MCASP1_ACLKR_OUT", "Output clock"},
-       [453] = {157, 225, "DEV_BOARD0_MCASP1_AFSR_OUT", "Output clock"},
-       [454] = {157, 226, "DEV_BOARD0_MCASP1_ACLKX_IN", "Input clock"},
-       [455] = {157, 227, "DEV_BOARD0_MCASP1_ACLKX_OUT", "Output clock"},
-       [456] = {157, 228, "DEV_BOARD0_MCASP1_AFSX_OUT", "Output clock"},
-       [457] = {157, 229, "DEV_BOARD0_MCASP2_ACLKR_IN", "Input clock"},
-       [458] = {157, 230, "DEV_BOARD0_MCASP2_ACLKR_OUT", "Output clock"},
-       [459] = {157, 231, "DEV_BOARD0_MCASP2_AFSR_OUT", "Output clock"},
-       [460] = {157, 232, "DEV_BOARD0_MCASP2_ACLKX_IN", "Input clock"},
-       [461] = {157, 233, "DEV_BOARD0_MCASP2_ACLKX_OUT", "Output clock"},
-       [462] = {157, 234, "DEV_BOARD0_MCASP2_AFSX_OUT", "Output clock"},
-       [463] = {157, 235, "DEV_BOARD0_MCASP3_ACLKR_IN", "Input clock"},
-       [464] = {157, 236, "DEV_BOARD0_MCASP3_ACLKR_OUT", "Output clock"},
-       [465] = {157, 237, "DEV_BOARD0_MCASP3_AFSR_OUT", "Output clock"},
-       [466] = {157, 238, "DEV_BOARD0_MCASP3_ACLKX_IN", "Input clock"},
-       [467] = {157, 239, "DEV_BOARD0_MCASP3_ACLKX_OUT", "Output clock"},
-       [468] = {157, 240, "DEV_BOARD0_MCASP3_AFSX_OUT", "Output clock"},
-       [469] = {157, 241, "DEV_BOARD0_MCASP4_ACLKR_IN", "Input clock"},
-       [470] = {157, 242, "DEV_BOARD0_MCASP4_ACLKR_OUT", "Output clock"},
-       [471] = {157, 243, "DEV_BOARD0_MCASP4_AFSR_OUT", "Output clock"},
-       [472] = {157, 244, "DEV_BOARD0_MCASP4_ACLKX_IN", "Input clock"},
-       [473] = {157, 245, "DEV_BOARD0_MCASP4_ACLKX_OUT", "Output clock"},
-       [474] = {157, 246, "DEV_BOARD0_MCASP4_AFSX_OUT", "Output clock"},
-       [475] = {157, 247, "DEV_BOARD0_MCASP5_ACLKR_IN", "Input clock"},
-       [476] = {157, 248, "DEV_BOARD0_MCASP5_ACLKR_OUT", "Output clock"},
-       [477] = {157, 249, "DEV_BOARD0_MCASP5_AFSR_OUT", "Output clock"},
-       [478] = {157, 250, "DEV_BOARD0_MCASP5_ACLKX_IN", "Input clock"},
-       [479] = {157, 251, "DEV_BOARD0_MCASP5_ACLKX_OUT", "Output clock"},
-       [480] = {157, 252, "DEV_BOARD0_MCASP5_AFSX_OUT", "Output clock"},
-       [481] = {157, 253, "DEV_BOARD0_MCASP6_ACLKR_IN", "Input clock"},
-       [482] = {157, 254, "DEV_BOARD0_MCASP6_ACLKR_OUT", "Output clock"},
-       [483] = {157, 255, "DEV_BOARD0_MCASP6_AFSR_OUT", "Output clock"},
-       [484] = {157, 256, "DEV_BOARD0_MCASP6_ACLKX_IN", "Input clock"},
-       [485] = {157, 257, "DEV_BOARD0_MCASP6_ACLKX_OUT", "Output clock"},
-       [486] = {157, 258, "DEV_BOARD0_MCASP6_AFSX_OUT", "Output clock"},
-       [487] = {157, 259, "DEV_BOARD0_MCASP7_ACLKR_IN", "Input clock"},
-       [488] = {157, 260, "DEV_BOARD0_MCASP7_ACLKR_OUT", "Output clock"},
-       [489] = {157, 261, "DEV_BOARD0_MCASP7_AFSR_OUT", "Output clock"},
-       [490] = {157, 262, "DEV_BOARD0_MCASP7_ACLKX_IN", "Input clock"},
-       [491] = {157, 263, "DEV_BOARD0_MCASP7_ACLKX_OUT", "Output clock"},
-       [492] = {157, 264, "DEV_BOARD0_MCASP7_AFSX_OUT", "Output clock"},
-       [493] = {157, 265, "DEV_BOARD0_MCASP8_ACLKR_IN", "Input clock"},
-       [494] = {157, 267, "DEV_BOARD0_MCASP8_ACLKR_OUT", "Output clock"},
-       [495] = {157, 268, "DEV_BOARD0_MCASP8_AFSR_OUT", "Output clock"},
-       [496] = {157, 269, "DEV_BOARD0_MCASP8_ACLKX_IN", "Input clock"},
-       [497] = {157, 270, "DEV_BOARD0_MCASP8_ACLKX_OUT", "Output clock"},
-       [498] = {157, 271, "DEV_BOARD0_MCASP8_AFSX_OUT", "Output clock"},
-       [499] = {157, 272, "DEV_BOARD0_MCASP9_ACLKR_IN", "Input clock"},
-       [500] = {157, 273, "DEV_BOARD0_MCASP9_ACLKR_OUT", "Output clock"},
-       [501] = {157, 274, "DEV_BOARD0_MCASP9_AFSR_OUT", "Output clock"},
-       [502] = {157, 275, "DEV_BOARD0_MCASP9_ACLKX_IN", "Input clock"},
-       [503] = {157, 276, "DEV_BOARD0_MCASP9_ACLKX_OUT", "Output clock"},
-       [504] = {157, 278, "DEV_BOARD0_MCASP9_AFSX_OUT", "Output clock"},
-       [505] = {157, 279, "DEV_BOARD0_MCASP10_ACLKR_IN", "Input clock"},
-       [506] = {157, 280, "DEV_BOARD0_MCASP10_ACLKR_OUT", "Output clock"},
-       [507] = {157, 281, "DEV_BOARD0_MCASP10_AFSR_OUT", "Output clock"},
-       [508] = {157, 282, "DEV_BOARD0_MCASP10_ACLKX_IN", "Input clock"},
-       [509] = {157, 283, "DEV_BOARD0_MCASP10_ACLKX_OUT", "Output clock"},
-       [510] = {157, 284, "DEV_BOARD0_MCASP10_AFSX_OUT", "Output clock"},
-       [511] = {157, 285, "DEV_BOARD0_MCASP11_ACLKR_IN", "Input clock"},
-       [512] = {157, 286, "DEV_BOARD0_MCASP11_ACLKR_OUT", "Output clock"},
-       [513] = {157, 287, "DEV_BOARD0_MCASP11_AFSR_OUT", "Output clock"},
-       [514] = {157, 288, "DEV_BOARD0_MCASP11_ACLKX_IN", "Input clock"},
-       [515] = {157, 289, "DEV_BOARD0_MCASP11_ACLKX_OUT", "Output clock"},
-       [516] = {157, 290, "DEV_BOARD0_MCASP11_AFSX_OUT", "Output clock"},
-       [517] = {157, 300, "DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT", "Output clock"},
-       [518] = {157, 301, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN", "Input muxed clock"},
-       [519] = {157, 302, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [520] = {157, 303, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [521] = {157, 304, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [522] = {157, 305, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [523] = {157, 306, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [524] = {157, 307, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [525] = {157, 308, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [526] = {157, 309, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [527] = {157, 310, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [528] = {157, 311, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [529] = {157, 312, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [530] = {157, 313, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [531] = {157, 314, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [532] = {157, 315, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [533] = {157, 316, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [534] = {157, 317, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [535] = {157, 318, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [536] = {157, 319, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [537] = {157, 320, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [538] = {157, 321, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [539] = {157, 322, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [540] = {157, 323, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [541] = {157, 324, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [542] = {157, 325, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [543] = {157, 326, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [544] = {157, 327, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [545] = {157, 328, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [546] = {157, 329, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [547] = {157, 330, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [548] = {157, 331, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [549] = {157, 334, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
-       [550] = {157, 335, "DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT", "Output clock"},
-       [551] = {157, 336, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN", "Input muxed clock"},
-       [552] = {157, 337, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [553] = {157, 338, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [554] = {157, 339, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [555] = {157, 340, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [556] = {157, 341, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [557] = {157, 342, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [558] = {157, 343, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [559] = {157, 344, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [560] = {157, 345, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [561] = {157, 346, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [562] = {157, 347, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [563] = {157, 348, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [564] = {157, 349, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [565] = {157, 350, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [566] = {157, 351, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [567] = {157, 352, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [568] = {157, 353, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [569] = {157, 354, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [570] = {157, 355, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [571] = {157, 356, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [572] = {157, 357, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [573] = {157, 358, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [574] = {157, 359, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [575] = {157, 360, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [576] = {157, 361, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [577] = {157, 362, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [578] = {157, 363, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [579] = {157, 364, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [580] = {157, 365, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [581] = {157, 366, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [582] = {157, 369, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
-       [583] = {157, 370, "DEV_BOARD0_AUDIO_EXT_REFCLK2_OUT", "Output clock"},
-       [584] = {157, 371, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN", "Input muxed clock"},
-       [585] = {157, 372, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [586] = {157, 373, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [587] = {157, 374, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [588] = {157, 375, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [589] = {157, 376, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [590] = {157, 377, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [591] = {157, 378, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [592] = {157, 379, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [593] = {157, 380, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [594] = {157, 381, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [595] = {157, 382, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [596] = {157, 383, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [597] = {157, 384, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [598] = {157, 385, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [599] = {157, 386, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [600] = {157, 387, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [601] = {157, 388, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [602] = {157, 389, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [603] = {157, 390, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [604] = {157, 391, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [605] = {157, 392, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [606] = {157, 393, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [607] = {157, 394, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [608] = {157, 395, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [609] = {157, 396, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [610] = {157, 397, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [611] = {157, 398, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [612] = {157, 399, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [613] = {157, 400, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [614] = {157, 401, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [615] = {157, 404, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
-       [616] = {157, 405, "DEV_BOARD0_AUDIO_EXT_REFCLK3_OUT", "Output clock"},
-       [617] = {157, 406, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN", "Input muxed clock"},
-       [618] = {157, 407, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [619] = {157, 408, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [620] = {157, 409, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [621] = {157, 410, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [622] = {157, 411, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [623] = {157, 412, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [624] = {157, 413, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [625] = {157, 414, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [626] = {157, 415, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [627] = {157, 416, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [628] = {157, 417, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [629] = {157, 418, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [630] = {157, 419, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [631] = {157, 420, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [632] = {157, 421, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [633] = {157, 422, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [634] = {157, 423, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [635] = {157, 424, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [636] = {157, 425, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [637] = {157, 426, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [638] = {157, 427, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [639] = {157, 428, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [640] = {157, 429, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [641] = {157, 430, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [642] = {157, 431, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [643] = {157, 432, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [644] = {157, 433, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [645] = {157, 434, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [646] = {157, 435, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [647] = {157, 436, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [648] = {157, 439, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK3_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
-       [649] = {142, 1, "DEV_C66SS0_CORE0_GEM_CLK2_OUT_CLK", "Output clock"},
-       [650] = {142, 4, "DEV_C66SS0_CORE0_GEM_PBIST_ROM_CLK", "Output clock"},
-       [651] = {143, 1, "DEV_C66SS1_CORE0_GEM_CLK2_OUT_CLK", "Output clock"},
-       [652] = {143, 4, "DEV_C66SS1_CORE0_GEM_PBIST_ROM_CLK", "Output clock"},
-       [653] = {15, 1, "DEV_C71SS0_PLL_CTRL_CLK", "Input clock"},
-       [654] = {16, 1, "DEV_C71SS0_MMA_MMA_CLK", "Input clock"},
-       [655] = {6, 1, "DEV_COMPUTE_CLUSTER0_CLEC_CLK1_CLK", "Input clock"},
-       [656] = {7, 1, "DEV_COMPUTE_CLUSTER0_CORE_CORE_CLK1_CLK", "Input clock"},
-       [657] = {8, 1, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_DDRSS_DDR_PLL_CLK", "Input clock"},
-       [658] = {9, 1, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK2_CLK_CLK", "Input clock"},
-       [659] = {17, 1, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK4_CLK_CLK", "Input clock"},
-       [660] = {17, 2, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK2_CLK_CLK", "Input clock"},
-       [661] = {19, 1, "DEV_CPSW0_SERDES6_TXFCLK", "Input clock"},
-       [662] = {19, 2, "DEV_CPSW0_SERDES8_TXMCLK", "Input clock"},
-       [663] = {19, 3, "DEV_CPSW0_GMII2_MR_CLK", "Input clock"},
-       [664] = {19, 4, "DEV_CPSW0_SERDES2_TXFCLK", "Input clock"},
-       [665] = {19, 5, "DEV_CPSW0_SERDES4_RXCLK", "Input clock"},
-       [666] = {19, 6, "DEV_CPSW0_SERDES7_TXMCLK", "Input clock"},
-       [667] = {19, 7, "DEV_CPSW0_SERDES7_RXCLK", "Input clock"},
-       [668] = {19, 8, "DEV_CPSW0_SERDES6_REFCLK", "Input clock"},
-       [669] = {19, 9, "DEV_CPSW0_SERDES5_TXFCLK", "Input clock"},
-       [670] = {19, 10, "DEV_CPSW0_SERDES5_RXCLK", "Input clock"},
-       [671] = {19, 11, "DEV_CPSW0_GMII4_MT_CLK", "Input clock"},
-       [672] = {19, 12, "DEV_CPSW0_SERDES3_TXFCLK", "Input clock"},
-       [673] = {19, 13, "DEV_CPSW0_SERDES2_REFCLK", "Input clock"},
-       [674] = {19, 14, "DEV_CPSW0_SERDES4_RXFCLK", "Input clock"},
-       [675] = {19, 15, "DEV_CPSW0_SERDES6_RXFCLK", "Input clock"},
-       [676] = {19, 16, "DEV_CPSW0_CPTS_RFT_CLK", "Input muxed clock"},
-       [677] = {19, 17, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
-       [678] = {19, 18, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
-       [679] = {19, 19, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
-       [680] = {19, 20, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
-       [681] = {19, 21, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
-       [682] = {19, 22, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
-       [683] = {19, 23, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
-       [684] = {19, 24, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
-       [685] = {19, 25, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
-       [686] = {19, 26, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
-       [687] = {19, 27, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
-       [688] = {19, 28, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
-       [689] = {19, 29, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
-       [690] = {19, 30, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
-       [691] = {19, 31, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
-       [692] = {19, 32, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
-       [693] = {19, 33, "DEV_CPSW0_SERDES5_RXFCLK", "Input clock"},
-       [694] = {19, 34, "DEV_CPSW0_SERDES5_TXMCLK", "Input clock"},
-       [695] = {19, 35, "DEV_CPSW0_GMII5_MT_CLK", "Input clock"},
-       [696] = {19, 36, "DEV_CPSW0_SERDES2_RXCLK", "Input clock"},
-       [697] = {19, 37, "DEV_CPSW0_SERDES8_RXFCLK", "Input clock"},
-       [698] = {19, 38, "DEV_CPSW0_SERDES1_RXFCLK", "Input clock"},
-       [699] = {19, 39, "DEV_CPSW0_SERDES8_RXCLK", "Input clock"},
-       [700] = {19, 40, "DEV_CPSW0_GMII_RFT_CLK", "Input clock"},
-       [701] = {19, 41, "DEV_CPSW0_SERDES3_REFCLK", "Input clock"},
-       [702] = {19, 42, "DEV_CPSW0_RGMII_MHZ_250_CLK", "Input clock"},
-       [703] = {19, 43, "DEV_CPSW0_SERDES7_REFCLK", "Input clock"},
-       [704] = {19, 44, "DEV_CPSW0_GMII6_MT_CLK", "Input clock"},
-       [705] = {19, 45, "DEV_CPSW0_SERDES6_TXMCLK", "Input clock"},
-       [706] = {19, 46, "DEV_CPSW0_RMII_MHZ_50_CLK", "Input clock"},
-       [707] = {19, 47, "DEV_CPSW0_GMII4_MR_CLK", "Input clock"},
-       [708] = {19, 48, "DEV_CPSW0_SERDES2_TXMCLK", "Input clock"},
-       [709] = {19, 49, "DEV_CPSW0_RGMII_MHZ_50_CLK", "Input clock"},
-       [710] = {19, 50, "DEV_CPSW0_SERDES4_TXMCLK", "Input clock"},
-       [711] = {19, 51, "DEV_CPSW0_SERDES3_RXFCLK", "Input clock"},
-       [712] = {19, 52, "DEV_CPSW0_GMII8_MT_CLK", "Input clock"},
-       [713] = {19, 53, "DEV_CPSW0_SERDES7_TXFCLK", "Input clock"},
-       [714] = {19, 54, "DEV_CPSW0_GMII7_MT_CLK", "Input clock"},
-       [715] = {19, 55, "DEV_CPSW0_GMII7_MR_CLK", "Input clock"},
-       [716] = {19, 56, "DEV_CPSW0_SERDES6_RXCLK", "Input clock"},
-       [717] = {19, 57, "DEV_CPSW0_SERDES3_RXCLK", "Input clock"},
-       [718] = {19, 58, "DEV_CPSW0_SERDES4_REFCLK", "Input clock"},
-       [719] = {19, 59, "DEV_CPSW0_SERDES1_RXCLK", "Input clock"},
-       [720] = {19, 60, "DEV_CPSW0_SERDES1_TXFCLK", "Input clock"},
-       [721] = {19, 61, "DEV_CPSW0_GMII6_MR_CLK", "Input clock"},
-       [722] = {19, 62, "DEV_CPSW0_SERDES1_REFCLK", "Input clock"},
-       [723] = {19, 63, "DEV_CPSW0_RGMII_MHZ_5_CLK", "Input clock"},
-       [724] = {19, 64, "DEV_CPSW0_SERDES5_REFCLK", "Input clock"},
-       [725] = {19, 65, "DEV_CPSW0_GMII2_MT_CLK", "Input clock"},
-       [726] = {19, 66, "DEV_CPSW0_SERDES8_TXFCLK", "Input clock"},
-       [727] = {19, 67, "DEV_CPSW0_GMII8_MR_CLK", "Input clock"},
-       [728] = {19, 68, "DEV_CPSW0_GMII1_MR_CLK", "Input clock"},
-       [729] = {19, 69, "DEV_CPSW0_SERDES8_REFCLK", "Input clock"},
-       [730] = {19, 70, "DEV_CPSW0_SERDES3_TXMCLK", "Input clock"},
-       [731] = {19, 71, "DEV_CPSW0_GMII3_MR_CLK", "Input clock"},
-       [732] = {19, 72, "DEV_CPSW0_SERDES1_TXMCLK", "Input clock"},
-       [733] = {19, 73, "DEV_CPSW0_SERDES7_RXFCLK", "Input clock"},
-       [734] = {19, 74, "DEV_CPSW0_GMII5_MR_CLK", "Input clock"},
-       [735] = {19, 75, "DEV_CPSW0_GMII1_MT_CLK", "Input clock"},
-       [736] = {19, 76, "DEV_CPSW0_SERDES2_RXFCLK", "Input clock"},
-       [737] = {19, 77, "DEV_CPSW0_SERDES4_TXFCLK", "Input clock"},
-       [738] = {19, 78, "DEV_CPSW0_SERDES3_TXCLK", "Output clock"},
-       [739] = {19, 79, "DEV_CPSW0_CPTS_GENF0_0", "Output clock"},
-       [740] = {19, 80, "DEV_CPSW0_SERDES5_TXCLK", "Output clock"},
-       [741] = {19, 81, "DEV_CPSW0_SERDES6_TXCLK", "Output clock"},
-       [742] = {19, 82, "DEV_CPSW0_SERDES8_TXCLK", "Output clock"},
-       [743] = {19, 83, "DEV_CPSW0_SERDES1_TXCLK", "Output clock"},
-       [744] = {19, 84, "DEV_CPSW0_SERDES4_TXCLK", "Output clock"},
-       [745] = {19, 85, "DEV_CPSW0_SERDES2_TXCLK", "Output clock"},
-       [746] = {19, 86, "DEV_CPSW0_SERDES7_TXCLK", "Output clock"},
-       [747] = {19, 87, "DEV_CPSW0_MDIO_MDCLK_O_0", "Output clock"},
-       [748] = {19, 89, "DEV_CPSW0_CPPI_CLK_CLK", "Input clock"},
-       [749] = {26, 1, "DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK", "Input clock"},
-       [750] = {26, 2, "DEV_CSI_RX_IF0_MAIN_CLK_CLK", "Input clock"},
-       [751] = {26, 3, "DEV_CSI_RX_IF0_VP_CLK_CLK", "Input clock"},
-       [752] = {27, 1, "DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK", "Input clock"},
-       [753] = {27, 2, "DEV_CSI_RX_IF1_MAIN_CLK_CLK", "Input clock"},
-       [754] = {27, 3, "DEV_CSI_RX_IF1_VP_CLK_CLK", "Input clock"},
-       [755] = {28, 1, "DEV_CSI_TX_IF0_DPHY_TXBYTECLKHS_CL_CLK", "Input clock"},
-       [756] = {28, 2, "DEV_CSI_TX_IF0_VBUS_CLK_CLK", "Input clock"},
-       [757] = {28, 3, "DEV_CSI_TX_IF0_MAIN_CLK_CLK", "Input clock"},
-       [758] = {30, 1, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"},
-       [759] = {30, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"},
-       [760] = {30, 3, "DEV_DCC0_DCC_CLKSRC7_CLK", "Input clock"},
-       [761] = {30, 4, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"},
-       [762] = {30, 5, "DEV_DCC0_VBUS_CLK", "Input clock"},
-       [763] = {30, 6, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"},
-       [764] = {30, 7, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"},
-       [765] = {30, 8, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"},
-       [766] = {30, 9, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"},
-       [767] = {30, 10, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"},
-       [768] = {30, 11, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"},
-       [769] = {30, 12, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"},
-       [770] = {31, 1, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"},
-       [771] = {31, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"},
-       [772] = {31, 3, "DEV_DCC1_DCC_CLKSRC7_CLK", "Input clock"},
-       [773] = {31, 4, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"},
-       [774] = {31, 5, "DEV_DCC1_VBUS_CLK", "Input clock"},
-       [775] = {31, 6, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"},
-       [776] = {31, 7, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"},
-       [777] = {31, 8, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"},
-       [778] = {31, 9, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"},
-       [779] = {31, 10, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"},
-       [780] = {31, 11, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"},
-       [781] = {31, 12, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"},
-       [782] = {41, 1, "DEV_DCC10_DCC_INPUT01_CLK", "Input clock"},
-       [783] = {41, 2, "DEV_DCC10_DCC_CLKSRC2_CLK", "Input clock"},
-       [784] = {41, 3, "DEV_DCC10_DCC_CLKSRC7_CLK", "Input clock"},
-       [785] = {41, 4, "DEV_DCC10_DCC_CLKSRC0_CLK", "Input clock"},
-       [786] = {41, 5, "DEV_DCC10_VBUS_CLK", "Input clock"},
-       [787] = {41, 6, "DEV_DCC10_DCC_CLKSRC4_CLK", "Input clock"},
-       [788] = {41, 7, "DEV_DCC10_DCC_CLKSRC1_CLK", "Input clock"},
-       [789] = {41, 8, "DEV_DCC10_DCC_CLKSRC3_CLK", "Input clock"},
-       [790] = {41, 9, "DEV_DCC10_DCC_INPUT00_CLK", "Input clock"},
-       [791] = {41, 10, "DEV_DCC10_DCC_CLKSRC5_CLK", "Input clock"},
-       [792] = {41, 11, "DEV_DCC10_DCC_CLKSRC6_CLK", "Input clock"},
-       [793] = {41, 12, "DEV_DCC10_DCC_INPUT02_CLK", "Input clock"},
-       [794] = {42, 1, "DEV_DCC11_DCC_INPUT01_CLK", "Input clock"},
-       [795] = {42, 2, "DEV_DCC11_DCC_CLKSRC2_CLK", "Input clock"},
-       [796] = {42, 3, "DEV_DCC11_DCC_CLKSRC7_CLK", "Input clock"},
-       [797] = {42, 4, "DEV_DCC11_DCC_CLKSRC0_CLK", "Input clock"},
-       [798] = {42, 5, "DEV_DCC11_VBUS_CLK", "Input clock"},
-       [799] = {42, 6, "DEV_DCC11_DCC_CLKSRC4_CLK", "Input clock"},
-       [800] = {42, 7, "DEV_DCC11_DCC_CLKSRC1_CLK", "Input clock"},
-       [801] = {42, 8, "DEV_DCC11_DCC_CLKSRC3_CLK", "Input clock"},
-       [802] = {42, 9, "DEV_DCC11_DCC_INPUT00_CLK", "Input clock"},
-       [803] = {42, 10, "DEV_DCC11_DCC_CLKSRC5_CLK", "Input clock"},
-       [804] = {42, 11, "DEV_DCC11_DCC_CLKSRC6_CLK", "Input clock"},
-       [805] = {42, 12, "DEV_DCC11_DCC_INPUT02_CLK", "Input clock"},
-       [806] = {43, 1, "DEV_DCC12_DCC_INPUT01_CLK", "Input clock"},
-       [807] = {43, 2, "DEV_DCC12_DCC_CLKSRC2_CLK", "Input clock"},
-       [808] = {43, 3, "DEV_DCC12_DCC_CLKSRC7_CLK", "Input clock"},
-       [809] = {43, 4, "DEV_DCC12_DCC_CLKSRC0_CLK", "Input clock"},
-       [810] = {43, 5, "DEV_DCC12_VBUS_CLK", "Input clock"},
-       [811] = {43, 6, "DEV_DCC12_DCC_CLKSRC4_CLK", "Input clock"},
-       [812] = {43, 7, "DEV_DCC12_DCC_CLKSRC1_CLK", "Input clock"},
-       [813] = {43, 8, "DEV_DCC12_DCC_CLKSRC3_CLK", "Input clock"},
-       [814] = {43, 9, "DEV_DCC12_DCC_INPUT00_CLK", "Input clock"},
-       [815] = {43, 10, "DEV_DCC12_DCC_CLKSRC5_CLK", "Input clock"},
-       [816] = {43, 11, "DEV_DCC12_DCC_CLKSRC6_CLK", "Input clock"},
-       [817] = {43, 12, "DEV_DCC12_DCC_INPUT02_CLK", "Input clock"},
-       [818] = {32, 1, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"},
-       [819] = {32, 2, "DEV_DCC2_DCC_CLKSRC2_CLK", "Input clock"},
-       [820] = {32, 3, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"},
-       [821] = {32, 4, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"},
-       [822] = {32, 5, "DEV_DCC2_VBUS_CLK", "Input clock"},
-       [823] = {32, 6, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"},
-       [824] = {32, 7, "DEV_DCC2_DCC_CLKSRC1_CLK", "Input clock"},
-       [825] = {32, 8, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"},
-       [826] = {32, 9, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"},
-       [827] = {32, 10, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"},
-       [828] = {32, 11, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"},
-       [829] = {32, 12, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"},
-       [830] = {33, 1, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"},
-       [831] = {33, 2, "DEV_DCC3_DCC_CLKSRC2_CLK", "Input clock"},
-       [832] = {33, 3, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"},
-       [833] = {33, 4, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"},
-       [834] = {33, 5, "DEV_DCC3_VBUS_CLK", "Input clock"},
-       [835] = {33, 6, "DEV_DCC3_DCC_CLKSRC4_CLK", "Input clock"},
-       [836] = {33, 7, "DEV_DCC3_DCC_CLKSRC1_CLK", "Input clock"},
-       [837] = {33, 8, "DEV_DCC3_DCC_CLKSRC3_CLK", "Input clock"},
-       [838] = {33, 9, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"},
-       [839] = {33, 10, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"},
-       [840] = {33, 11, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"},
-       [841] = {33, 12, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"},
-       [842] = {34, 1, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"},
-       [843] = {34, 2, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"},
-       [844] = {34, 3, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"},
-       [845] = {34, 4, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input clock"},
-       [846] = {34, 5, "DEV_DCC4_VBUS_CLK", "Input clock"},
-       [847] = {34, 6, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"},
-       [848] = {34, 7, "DEV_DCC4_DCC_CLKSRC1_CLK", "Input clock"},
-       [849] = {34, 8, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"},
-       [850] = {34, 9, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"},
-       [851] = {34, 10, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"},
-       [852] = {34, 11, "DEV_DCC4_DCC_CLKSRC6_CLK", "Input clock"},
-       [853] = {34, 12, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"},
-       [854] = {36, 1, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"},
-       [855] = {36, 2, "DEV_DCC5_DCC_CLKSRC2_CLK", "Input clock"},
-       [856] = {36, 3, "DEV_DCC5_DCC_CLKSRC7_CLK", "Input clock"},
-       [857] = {36, 4, "DEV_DCC5_DCC_CLKSRC0_CLK", "Input clock"},
-       [858] = {36, 5, "DEV_DCC5_VBUS_CLK", "Input clock"},
-       [859] = {36, 6, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"},
-       [860] = {36, 7, "DEV_DCC5_DCC_CLKSRC1_CLK", "Input clock"},
-       [861] = {36, 8, "DEV_DCC5_DCC_CLKSRC3_CLK", "Input clock"},
-       [862] = {36, 9, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"},
-       [863] = {36, 10, "DEV_DCC5_DCC_CLKSRC5_CLK", "Input clock"},
-       [864] = {36, 11, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"},
-       [865] = {36, 12, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"},
-       [866] = {37, 1, "DEV_DCC6_DCC_INPUT01_CLK", "Input clock"},
-       [867] = {37, 2, "DEV_DCC6_DCC_CLKSRC2_CLK", "Input clock"},
-       [868] = {37, 3, "DEV_DCC6_DCC_CLKSRC7_CLK", "Input clock"},
-       [869] = {37, 4, "DEV_DCC6_DCC_CLKSRC0_CLK", "Input clock"},
-       [870] = {37, 5, "DEV_DCC6_VBUS_CLK", "Input clock"},
-       [871] = {37, 6, "DEV_DCC6_DCC_CLKSRC4_CLK", "Input clock"},
-       [872] = {37, 7, "DEV_DCC6_DCC_CLKSRC1_CLK", "Input clock"},
-       [873] = {37, 8, "DEV_DCC6_DCC_CLKSRC3_CLK", "Input clock"},
-       [874] = {37, 9, "DEV_DCC6_DCC_INPUT00_CLK", "Input clock"},
-       [875] = {37, 10, "DEV_DCC6_DCC_CLKSRC5_CLK", "Input clock"},
-       [876] = {37, 11, "DEV_DCC6_DCC_CLKSRC6_CLK", "Input clock"},
-       [877] = {37, 12, "DEV_DCC6_DCC_INPUT02_CLK", "Input clock"},
-       [878] = {38, 1, "DEV_DCC7_DCC_INPUT01_CLK", "Input clock"},
-       [879] = {38, 2, "DEV_DCC7_DCC_CLKSRC2_CLK", "Input clock"},
-       [880] = {38, 3, "DEV_DCC7_DCC_CLKSRC7_CLK", "Input clock"},
-       [881] = {38, 4, "DEV_DCC7_DCC_CLKSRC0_CLK", "Input clock"},
-       [882] = {38, 5, "DEV_DCC7_VBUS_CLK", "Input clock"},
-       [883] = {38, 6, "DEV_DCC7_DCC_CLKSRC4_CLK", "Input clock"},
-       [884] = {38, 7, "DEV_DCC7_DCC_CLKSRC1_CLK", "Input clock"},
-       [885] = {38, 8, "DEV_DCC7_DCC_CLKSRC3_CLK", "Input clock"},
-       [886] = {38, 9, "DEV_DCC7_DCC_INPUT00_CLK", "Input clock"},
-       [887] = {38, 10, "DEV_DCC7_DCC_CLKSRC5_CLK", "Input clock"},
-       [888] = {38, 11, "DEV_DCC7_DCC_CLKSRC6_CLK", "Input clock"},
-       [889] = {38, 12, "DEV_DCC7_DCC_INPUT02_CLK", "Input clock"},
-       [890] = {39, 1, "DEV_DCC8_DCC_INPUT01_CLK", "Input clock"},
-       [891] = {39, 2, "DEV_DCC8_DCC_CLKSRC2_CLK", "Input clock"},
-       [892] = {39, 3, "DEV_DCC8_DCC_CLKSRC7_CLK", "Input clock"},
-       [893] = {39, 4, "DEV_DCC8_DCC_CLKSRC0_CLK", "Input clock"},
-       [894] = {39, 5, "DEV_DCC8_VBUS_CLK", "Input clock"},
-       [895] = {39, 6, "DEV_DCC8_DCC_CLKSRC4_CLK", "Input clock"},
-       [896] = {39, 7, "DEV_DCC8_DCC_CLKSRC1_CLK", "Input clock"},
-       [897] = {39, 8, "DEV_DCC8_DCC_CLKSRC3_CLK", "Input clock"},
-       [898] = {39, 9, "DEV_DCC8_DCC_INPUT00_CLK", "Input clock"},
-       [899] = {39, 10, "DEV_DCC8_DCC_CLKSRC5_CLK", "Input clock"},
-       [900] = {39, 11, "DEV_DCC8_DCC_CLKSRC6_CLK", "Input clock"},
-       [901] = {39, 12, "DEV_DCC8_DCC_INPUT02_CLK", "Input clock"},
-       [902] = {40, 1, "DEV_DCC9_DCC_INPUT01_CLK", "Input clock"},
-       [903] = {40, 2, "DEV_DCC9_DCC_CLKSRC2_CLK", "Input clock"},
-       [904] = {40, 3, "DEV_DCC9_DCC_CLKSRC7_CLK", "Input clock"},
-       [905] = {40, 4, "DEV_DCC9_DCC_CLKSRC0_CLK", "Input clock"},
-       [906] = {40, 5, "DEV_DCC9_VBUS_CLK", "Input clock"},
-       [907] = {40, 6, "DEV_DCC9_DCC_CLKSRC4_CLK", "Input clock"},
-       [908] = {40, 7, "DEV_DCC9_DCC_CLKSRC1_CLK", "Input clock"},
-       [909] = {40, 8, "DEV_DCC9_DCC_CLKSRC3_CLK", "Input clock"},
-       [910] = {40, 9, "DEV_DCC9_DCC_INPUT00_CLK", "Input clock"},
-       [911] = {40, 10, "DEV_DCC9_DCC_CLKSRC5_CLK", "Input clock"},
-       [912] = {40, 11, "DEV_DCC9_DCC_CLKSRC6_CLK", "Input clock"},
-       [913] = {40, 12, "DEV_DCC9_DCC_INPUT02_CLK", "Input clock"},
-       [914] = {47, 1, "DEV_DDR0_PLL_CTRL_CLK", "Input clock"},
-       [915] = {47, 2, "DEV_DDR0_DDRSS_DDR_PLL_CLK", "Input clock"},
-       [916] = {47, 3, "DEV_DDR0_DDRSS_CFG_CLK", "Input clock"},
-       [917] = {47, 4, "DEV_DDR0_DDRSS_IO_CK_N_0", "Output clock"},
-       [918] = {47, 5, "DEV_DDR0_DDRSS_IO_CK_0", "Output clock"},
-       [919] = {304, 9, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"},
-       [920] = {304, 25, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"},
-       [921] = {304, 32, "DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK_0", "Output clock"},
-       [922] = {304, 35, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"},
-       [923] = {147, 1, "DEV_DPHY_RX0_PPI_RX_BYTE_CLK", "Output clock"},
-       [924] = {148, 1, "DEV_DPHY_RX1_PPI_RX_BYTE_CLK", "Output clock"},
-       [925] = {296, 1, "DEV_DPHY_TX0_PSM_CLK", "Input clock"},
-       [926] = {296, 2, "DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK", "Input clock"},
-       [927] = {296, 3, "DEV_DPHY_TX0_DPHY_REF_CLK", "Input muxed clock"},
-       [928] = {296, 4, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
-       [929] = {296, 5, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
-       [930] = {296, 6, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
-       [931] = {296, 7, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
-       [932] = {296, 8, "DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK", "Output clock"},
-       [933] = {296, 9, "DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK", "Output clock"},
-       [934] = {296, 10, "DEV_DPHY_TX0_CK_P_0", "Output clock"},
-       [935] = {296, 11, "DEV_DPHY_TX0_CK_M_0", "Output clock"},
-       [936] = {296, 12, "DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK", "Output clock"},
-       [937] = {152, 1, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK", "Input muxed clock"},
-       [938] = {152, 2, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"},
-       [939] = {152, 3, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"},
-       [940] = {152, 4, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK", "Input muxed clock"},
-       [941] = {152, 5, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
-       [942] = {152, 6, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
-       [943] = {152, 7, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
-       [944] = {152, 8, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
-       [945] = {152, 9, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK", "Input muxed clock"},
-       [946] = {152, 10, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"},
-       [947] = {152, 11, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"},
-       [948] = {152, 12, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"},
-       [949] = {152, 13, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK", "Input muxed clock"},
-       [950] = {152, 14, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
-       [951] = {152, 15, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
-       [952] = {152, 16, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
-       [953] = {152, 17, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
-       [954] = {152, 18, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
-       [955] = {152, 23, "DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK", "Output clock"},
-       [956] = {152, 24, "DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK", "Output clock"},
-       [957] = {152, 25, "DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK", "Output clock"},
-       [958] = {152, 27, "DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK", "Output clock"},
-       [959] = {152, 29, "DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK", "Output clock"},
-       [960] = {152, 31, "DEV_DSS0_DPI0_EXT_CLKSEL", "Input muxed clock"},
-       [961] = {152, 32, "DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL"},
-       [962] = {152, 33, "DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_BOARD_0_VOUT1_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL"},
-       [963] = {152, 34, "DEV_DSS0_DPI1_EXT_CLKSEL", "Input muxed clock"},
-       [964] = {152, 35, "DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL"},
-       [965] = {152, 36, "DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_BOARD_0_VOUT2_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL"},
-       [966] = {150, 1, "DEV_DSS_DSI0_DPI_0_CLK", "Input clock"},
-       [967] = {150, 2, "DEV_DSS_DSI0_PLL_CTRL_CLK", "Input clock"},
-       [968] = {150, 3, "DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK", "Input clock"},
-       [969] = {150, 4, "DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK", "Input clock"},
-       [970] = {150, 5, "DEV_DSS_DSI0_SYS_CLK", "Input clock"},
-       [971] = {151, 1, "DEV_DSS_EDP0_DPI_2_CLK", "Input clock"},
-       [972] = {151, 2, "DEV_DSS_EDP0_PHY_LN2_TXFCLK", "Input clock"},
-       [973] = {151, 3, "DEV_DSS_EDP0_PHY_LN0_RXCLK", "Input clock"},
-       [974] = {151, 4, "DEV_DSS_EDP0_PHY_LN2_TXMCLK", "Input clock"},
-       [975] = {151, 5, "DEV_DSS_EDP0_PHY_LN0_RXFCLK", "Input clock"},
-       [976] = {151, 6, "DEV_DSS_EDP0_PHY_LN0_REFCLK", "Input clock"},
-       [977] = {151, 7, "DEV_DSS_EDP0_PHY_LN1_RXCLK", "Input clock"},
-       [978] = {151, 8, "DEV_DSS_EDP0_PHY_LN2_RXFCLK", "Input clock"},
-       [979] = {151, 9, "DEV_DSS_EDP0_DPI_4_CLK", "Input clock"},
-       [980] = {151, 10, "DEV_DSS_EDP0_DPI_2_2X_CLK", "Input clock"},
-       [981] = {151, 11, "DEV_DSS_EDP0_PHY_LN0_TXFCLK", "Input clock"},
-       [982] = {151, 12, "DEV_DSS_EDP0_PHY_LN2_RXCLK", "Input clock"},
-       [983] = {151, 13, "DEV_DSS_EDP0_PHY_LN2_REFCLK", "Input clock"},
-       [984] = {151, 14, "DEV_DSS_EDP0_PHY_LN3_REFCLK", "Input clock"},
-       [985] = {151, 15, "DEV_DSS_EDP0_DPI_5_CLK", "Input clock"},
-       [986] = {151, 16, "DEV_DSS_EDP0_PHY_LN3_RXCLK", "Input clock"},
-       [987] = {151, 17, "DEV_DSS_EDP0_PHY_LN1_REFCLK", "Input clock"},
-       [988] = {151, 18, "DEV_DSS_EDP0_AIF_I2S_CLK", "Input clock"},
-       [989] = {151, 19, "DEV_DSS_EDP0_PHY_LN3_TXFCLK", "Input clock"},
-       [990] = {151, 20, "DEV_DSS_EDP0_DPI_3_CLK", "Input clock"},
-       [991] = {151, 21, "DEV_DSS_EDP0_PHY_LN1_RXFCLK", "Input clock"},
-       [992] = {151, 22, "DEV_DSS_EDP0_PHY_LN1_TXMCLK", "Input clock"},
-       [993] = {151, 23, "DEV_DSS_EDP0_PLL_CTRL_CLK", "Input clock"},
-       [994] = {151, 24, "DEV_DSS_EDP0_PHY_LN3_TXMCLK", "Input clock"},
-       [995] = {151, 25, "DEV_DSS_EDP0_PHY_LN3_RXFCLK", "Input clock"},
-       [996] = {151, 26, "DEV_DSS_EDP0_PHY_LN0_TXMCLK", "Input clock"},
-       [997] = {151, 27, "DEV_DSS_EDP0_PHY_LN2_TXCLK", "Output clock"},
-       [998] = {151, 28, "DEV_DSS_EDP0_PHY_LN3_TXCLK", "Output clock"},
-       [999] = {151, 29, "DEV_DSS_EDP0_PHY_LN0_TXCLK", "Output clock"},
-       [1000] = {151, 30, "DEV_DSS_EDP0_PHY_LN1_TXCLK", "Output clock"},
-       [1001] = {151, 36, "DEV_DSS_EDP0_DPTX_MOD_CLK", "Input clock"},
-       [1002] = {115, 1, "DEV_GPMC0_VBUSP_CLK", "Input clock"},
-       [1003] = {115, 2, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"},
-       [1004] = {115, 3, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
-       [1005] = {115, 4, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
-       [1006] = {115, 5, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK3", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
-       [1007] = {115, 6, "DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
-       [1008] = {115, 7, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"},
-       [1009] = {61, 1, "DEV_GTC0_GTC_CLK", "Input muxed clock"},
-       [1010] = {61, 2, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
-       [1011] = {61, 3, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
-       [1012] = {61, 4, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
-       [1013] = {61, 5, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
-       [1014] = {61, 6, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
-       [1015] = {61, 7, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
-       [1016] = {61, 8, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
-       [1017] = {61, 9, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
-       [1018] = {61, 10, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
-       [1019] = {61, 11, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
-       [1020] = {61, 12, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
-       [1021] = {61, 13, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
-       [1022] = {61, 14, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
-       [1023] = {61, 15, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
-       [1024] = {61, 16, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
-       [1025] = {61, 17, "DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
-       [1026] = {187, 1, "DEV_I2C0_PISCL_0", "Input clock"},
-       [1027] = {187, 2, "DEV_I2C0_CLK", "Input clock"},
-       [1028] = {188, 1, "DEV_I2C1_PISCL_0", "Input clock"},
-       [1029] = {188, 2, "DEV_I2C1_CLK", "Input clock"},
-       [1030] = {189, 1, "DEV_I2C2_PISCL_0", "Input clock"},
-       [1031] = {189, 2, "DEV_I2C2_CLK", "Input clock"},
-       [1032] = {190, 1, "DEV_I2C3_PISCL_0", "Input clock"},
-       [1033] = {190, 2, "DEV_I2C3_CLK", "Input clock"},
-       [1034] = {191, 1, "DEV_I2C4_PISCL_0", "Input clock"},
-       [1035] = {191, 2, "DEV_I2C4_CLK", "Input clock"},
-       [1036] = {192, 1, "DEV_I2C5_PISCL_0", "Input clock"},
-       [1037] = {192, 2, "DEV_I2C5_CLK", "Input clock"},
-       [1038] = {193, 1, "DEV_I2C6_PISCL_0", "Input clock"},
-       [1039] = {193, 2, "DEV_I2C6_CLK", "Input clock"},
-       [1040] = {116, 1, "DEV_I3C0_I3C_SCL_DI", "Input clock"},
-       [1041] = {116, 2, "DEV_I3C0_I3C_SCLK_CLK", "Input clock"},
-       [1042] = {116, 3, "DEV_I3C0_I3C_SCL_DO_0", "Output clock"},
-       [1043] = {127, 1, "DEV_LED0_VBUS_CLK", "Input clock"},
-       [1044] = {156, 1, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"},
-       [1045] = {156, 2, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
-       [1046] = {156, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
-       [1047] = {156, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
-       [1048] = {156, 5, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
-       [1049] = {158, 1, "DEV_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"},
-       [1050] = {158, 2, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
-       [1051] = {158, 3, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
-       [1052] = {158, 4, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
-       [1053] = {158, 5, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
-       [1054] = {168, 1, "DEV_MCAN10_MCANSS_CCLK_CLK", "Input muxed clock"},
-       [1055] = {168, 2, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
-       [1056] = {168, 3, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
-       [1057] = {168, 4, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
-       [1058] = {168, 5, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
-       [1059] = {169, 1, "DEV_MCAN11_MCANSS_CCLK_CLK", "Input muxed clock"},
-       [1060] = {169, 2, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
-       [1061] = {169, 3, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
-       [1062] = {169, 4, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
-       [1063] = {169, 5, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
-       [1064] = {170, 1, "DEV_MCAN12_MCANSS_CCLK_CLK", "Input muxed clock"},
-       [1065] = {170, 2, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
-       [1066] = {170, 3, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
-       [1067] = {170, 4, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
-       [1068] = {170, 5, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
-       [1069] = {171, 1, "DEV_MCAN13_MCANSS_CCLK_CLK", "Input muxed clock"},
-       [1070] = {171, 2, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
-       [1071] = {171, 3, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
-       [1072] = {171, 4, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
-       [1073] = {171, 5, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
-       [1074] = {160, 1, "DEV_MCAN2_MCANSS_CCLK_CLK", "Input muxed clock"},
-       [1075] = {160, 2, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
-       [1076] = {160, 3, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
-       [1077] = {160, 4, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
-       [1078] = {160, 5, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
-       [1079] = {161, 1, "DEV_MCAN3_MCANSS_CCLK_CLK", "Input muxed clock"},
-       [1080] = {161, 2, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
-       [1081] = {161, 3, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
-       [1082] = {161, 4, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
-       [1083] = {161, 5, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
-       [1084] = {162, 1, "DEV_MCAN4_MCANSS_CCLK_CLK", "Input muxed clock"},
-       [1085] = {162, 2, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
-       [1086] = {162, 3, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
-       [1087] = {162, 4, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
-       [1088] = {162, 5, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
-       [1089] = {163, 1, "DEV_MCAN5_MCANSS_CCLK_CLK", "Input muxed clock"},
-       [1090] = {163, 2, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
-       [1091] = {163, 3, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
-       [1092] = {163, 4, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
-       [1093] = {163, 5, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
-       [1094] = {164, 1, "DEV_MCAN6_MCANSS_CCLK_CLK", "Input muxed clock"},
-       [1095] = {164, 2, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
-       [1096] = {164, 3, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
-       [1097] = {164, 4, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
-       [1098] = {164, 5, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
-       [1099] = {165, 1, "DEV_MCAN7_MCANSS_CCLK_CLK", "Input muxed clock"},
-       [1100] = {165, 2, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
-       [1101] = {165, 3, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
-       [1102] = {165, 4, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
-       [1103] = {165, 5, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
-       [1104] = {166, 1, "DEV_MCAN8_MCANSS_CCLK_CLK", "Input muxed clock"},
-       [1105] = {166, 2, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
-       [1106] = {166, 3, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
-       [1107] = {166, 4, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
-       [1108] = {166, 5, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
-       [1109] = {167, 1, "DEV_MCAN9_MCANSS_CCLK_CLK", "Input muxed clock"},
-       [1110] = {167, 2, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
-       [1111] = {167, 3, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
-       [1112] = {167, 4, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
-       [1113] = {167, 5, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
-       [1114] = {174, 1, "DEV_MCASP0_AUX_CLK", "Input muxed clock"},
-       [1115] = {174, 2, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
-       [1116] = {174, 3, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
-       [1117] = {174, 4, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
-       [1118] = {174, 6, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
-       [1119] = {174, 7, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
-       [1120] = {174, 8, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
-       [1121] = {174, 9, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
-       [1122] = {174, 10, "DEV_MCASP0_MCASP_ACLKX_POUT_0", "Output clock"},
-       [1123] = {174, 11, "DEV_MCASP0_MCASP_ACLKX_PIN_0", "Input clock"},
-       [1124] = {174, 12, "DEV_MCASP0_MCASP_ACLKR_POUT_0", "Output clock"},
-       [1125] = {174, 13, "DEV_MCASP0_MCASP_ACLKR_PIN_0", "Input clock"},
-       [1126] = {174, 14, "DEV_MCASP0_MCASP_AHCLKX_POUT_0", "Output clock"},
-       [1127] = {174, 15, "DEV_MCASP0_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
-       [1128] = {174, 16, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
-       [1129] = {174, 17, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
-       [1130] = {174, 18, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
-       [1131] = {174, 19, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
-       [1132] = {174, 20, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
-       [1133] = {174, 21, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
-       [1134] = {174, 22, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
-       [1135] = {174, 23, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
-       [1136] = {174, 24, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
-       [1137] = {174, 25, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
-       [1138] = {174, 26, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
-       [1139] = {174, 27, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
-       [1140] = {174, 28, "DEV_MCASP0_MCASP_AHCLKR_POUT_0", "Output clock"},
-       [1141] = {174, 29, "DEV_MCASP0_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
-       [1142] = {174, 30, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
-       [1143] = {174, 31, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
-       [1144] = {174, 32, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
-       [1145] = {174, 33, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
-       [1146] = {174, 34, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
-       [1147] = {174, 35, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
-       [1148] = {174, 36, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
-       [1149] = {174, 37, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
-       [1150] = {174, 38, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
-       [1151] = {174, 39, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
-       [1152] = {174, 40, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
-       [1153] = {174, 41, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
-       [1154] = {175, 1, "DEV_MCASP1_AUX_CLK", "Input muxed clock"},
-       [1155] = {175, 2, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
-       [1156] = {175, 3, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
-       [1157] = {175, 4, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
-       [1158] = {175, 6, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
-       [1159] = {175, 7, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
-       [1160] = {175, 8, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
-       [1161] = {175, 9, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
-       [1162] = {175, 10, "DEV_MCASP1_MCASP_ACLKX_POUT_0", "Output clock"},
-       [1163] = {175, 11, "DEV_MCASP1_MCASP_ACLKX_PIN_0", "Input clock"},
-       [1164] = {175, 12, "DEV_MCASP1_MCASP_ACLKR_POUT_0", "Output clock"},
-       [1165] = {175, 13, "DEV_MCASP1_MCASP_ACLKR_PIN_0", "Input clock"},
-       [1166] = {175, 14, "DEV_MCASP1_MCASP_AHCLKX_POUT_0", "Output clock"},
-       [1167] = {175, 15, "DEV_MCASP1_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
-       [1168] = {175, 16, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
-       [1169] = {175, 17, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
-       [1170] = {175, 18, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
-       [1171] = {175, 19, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
-       [1172] = {175, 20, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
-       [1173] = {175, 21, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
-       [1174] = {175, 22, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
-       [1175] = {175, 23, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
-       [1176] = {175, 24, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
-       [1177] = {175, 25, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
-       [1178] = {175, 26, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
-       [1179] = {175, 27, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
-       [1180] = {175, 28, "DEV_MCASP1_MCASP_AHCLKR_POUT_0", "Output clock"},
-       [1181] = {175, 29, "DEV_MCASP1_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
-       [1182] = {175, 30, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
-       [1183] = {175, 31, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
-       [1184] = {175, 32, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
-       [1185] = {175, 33, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
-       [1186] = {175, 34, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
-       [1187] = {175, 35, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
-       [1188] = {175, 36, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
-       [1189] = {175, 37, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
-       [1190] = {175, 38, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
-       [1191] = {175, 39, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
-       [1192] = {175, 40, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
-       [1193] = {175, 41, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
-       [1194] = {184, 1, "DEV_MCASP10_AUX_CLK", "Input muxed clock"},
-       [1195] = {184, 2, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
-       [1196] = {184, 3, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
-       [1197] = {184, 4, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
-       [1198] = {184, 6, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
-       [1199] = {184, 7, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
-       [1200] = {184, 8, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
-       [1201] = {184, 9, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
-       [1202] = {184, 10, "DEV_MCASP10_MCASP_ACLKX_POUT_0", "Output clock"},
-       [1203] = {184, 11, "DEV_MCASP10_MCASP_ACLKX_PIN_0", "Input clock"},
-       [1204] = {184, 12, "DEV_MCASP10_MCASP_ACLKR_POUT_0", "Output clock"},
-       [1205] = {184, 13, "DEV_MCASP10_MCASP_ACLKR_PIN_0", "Input clock"},
-       [1206] = {184, 14, "DEV_MCASP10_MCASP_AHCLKX_POUT_0", "Output clock"},
-       [1207] = {184, 15, "DEV_MCASP10_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
-       [1208] = {184, 16, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
-       [1209] = {184, 17, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
-       [1210] = {184, 18, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
-       [1211] = {184, 19, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
-       [1212] = {184, 20, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
-       [1213] = {184, 21, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
-       [1214] = {184, 22, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
-       [1215] = {184, 23, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
-       [1216] = {184, 24, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
-       [1217] = {184, 25, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
-       [1218] = {184, 26, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
-       [1219] = {184, 27, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
-       [1220] = {184, 28, "DEV_MCASP10_MCASP_AHCLKR_POUT_0", "Output clock"},
-       [1221] = {184, 29, "DEV_MCASP10_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
-       [1222] = {184, 30, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
-       [1223] = {184, 31, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
-       [1224] = {184, 32, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
-       [1225] = {184, 33, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
-       [1226] = {184, 34, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
-       [1227] = {184, 35, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
-       [1228] = {184, 36, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
-       [1229] = {184, 37, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
-       [1230] = {184, 38, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
-       [1231] = {184, 39, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
-       [1232] = {184, 40, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
-       [1233] = {184, 41, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
-       [1234] = {185, 1, "DEV_MCASP11_AUX_CLK", "Input muxed clock"},
-       [1235] = {185, 2, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
-       [1236] = {185, 3, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
-       [1237] = {185, 4, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
-       [1238] = {185, 6, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
-       [1239] = {185, 7, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
-       [1240] = {185, 8, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
-       [1241] = {185, 9, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
-       [1242] = {185, 10, "DEV_MCASP11_MCASP_ACLKX_POUT_0", "Output clock"},
-       [1243] = {185, 11, "DEV_MCASP11_MCASP_ACLKX_PIN_0", "Input clock"},
-       [1244] = {185, 12, "DEV_MCASP11_MCASP_ACLKR_POUT_0", "Output clock"},
-       [1245] = {185, 13, "DEV_MCASP11_MCASP_ACLKR_PIN_0", "Input clock"},
-       [1246] = {185, 14, "DEV_MCASP11_MCASP_AHCLKX_POUT_0", "Output clock"},
-       [1247] = {185, 15, "DEV_MCASP11_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
-       [1248] = {185, 16, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
-       [1249] = {185, 17, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
-       [1250] = {185, 18, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
-       [1251] = {185, 19, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
-       [1252] = {185, 20, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
-       [1253] = {185, 21, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
-       [1254] = {185, 22, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
-       [1255] = {185, 23, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
-       [1256] = {185, 24, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
-       [1257] = {185, 25, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
-       [1258] = {185, 26, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
-       [1259] = {185, 27, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
-       [1260] = {185, 28, "DEV_MCASP11_MCASP_AHCLKR_POUT_0", "Output clock"},
-       [1261] = {185, 29, "DEV_MCASP11_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
-       [1262] = {185, 30, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
-       [1263] = {185, 31, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
-       [1264] = {185, 32, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
-       [1265] = {185, 33, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
-       [1266] = {185, 34, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
-       [1267] = {185, 35, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
-       [1268] = {185, 36, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
-       [1269] = {185, 37, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
-       [1270] = {185, 38, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
-       [1271] = {185, 39, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
-       [1272] = {185, 40, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
-       [1273] = {185, 41, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
-       [1274] = {176, 1, "DEV_MCASP2_AUX_CLK", "Input muxed clock"},
-       [1275] = {176, 2, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
-       [1276] = {176, 3, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
-       [1277] = {176, 4, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
-       [1278] = {176, 6, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
-       [1279] = {176, 7, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
-       [1280] = {176, 8, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
-       [1281] = {176, 9, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
-       [1282] = {176, 10, "DEV_MCASP2_MCASP_ACLKX_POUT_0", "Output clock"},
-       [1283] = {176, 11, "DEV_MCASP2_MCASP_ACLKX_PIN_0", "Input clock"},
-       [1284] = {176, 12, "DEV_MCASP2_MCASP_ACLKR_POUT_0", "Output clock"},
-       [1285] = {176, 13, "DEV_MCASP2_MCASP_ACLKR_PIN_0", "Input clock"},
-       [1286] = {176, 14, "DEV_MCASP2_MCASP_AHCLKX_POUT_0", "Output clock"},
-       [1287] = {176, 15, "DEV_MCASP2_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
-       [1288] = {176, 16, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
-       [1289] = {176, 17, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
-       [1290] = {176, 18, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
-       [1291] = {176, 19, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
-       [1292] = {176, 20, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
-       [1293] = {176, 21, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
-       [1294] = {176, 22, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
-       [1295] = {176, 23, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
-       [1296] = {176, 24, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
-       [1297] = {176, 25, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
-       [1298] = {176, 26, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
-       [1299] = {176, 27, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
-       [1300] = {176, 28, "DEV_MCASP2_MCASP_AHCLKR_POUT_0", "Output clock"},
-       [1301] = {176, 29, "DEV_MCASP2_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
-       [1302] = {176, 30, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
-       [1303] = {176, 31, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
-       [1304] = {176, 32, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
-       [1305] = {176, 33, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
-       [1306] = {176, 34, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
-       [1307] = {176, 35, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
-       [1308] = {176, 36, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
-       [1309] = {176, 37, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
-       [1310] = {176, 38, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
-       [1311] = {176, 39, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
-       [1312] = {176, 40, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
-       [1313] = {176, 41, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
-       [1314] = {177, 1, "DEV_MCASP3_AUX_CLK", "Input muxed clock"},
-       [1315] = {177, 2, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
-       [1316] = {177, 3, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
-       [1317] = {177, 4, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
-       [1318] = {177, 6, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
-       [1319] = {177, 7, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
-       [1320] = {177, 8, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
-       [1321] = {177, 9, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
-       [1322] = {177, 10, "DEV_MCASP3_MCASP_ACLKX_POUT_0", "Output clock"},
-       [1323] = {177, 11, "DEV_MCASP3_MCASP_ACLKX_PIN_0", "Input clock"},
-       [1324] = {177, 12, "DEV_MCASP3_MCASP_ACLKR_POUT_0", "Output clock"},
-       [1325] = {177, 13, "DEV_MCASP3_MCASP_ACLKR_PIN_0", "Input clock"},
-       [1326] = {177, 14, "DEV_MCASP3_MCASP_AHCLKX_POUT_0", "Output clock"},
-       [1327] = {177, 15, "DEV_MCASP3_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
-       [1328] = {177, 16, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
-       [1329] = {177, 17, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
-       [1330] = {177, 18, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
-       [1331] = {177, 19, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
-       [1332] = {177, 20, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
-       [1333] = {177, 21, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
-       [1334] = {177, 22, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
-       [1335] = {177, 23, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
-       [1336] = {177, 24, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
-       [1337] = {177, 25, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
-       [1338] = {177, 26, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
-       [1339] = {177, 27, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
-       [1340] = {177, 28, "DEV_MCASP3_MCASP_AHCLKR_POUT_0", "Output clock"},
-       [1341] = {177, 29, "DEV_MCASP3_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
-       [1342] = {177, 30, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
-       [1343] = {177, 31, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
-       [1344] = {177, 32, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
-       [1345] = {177, 33, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
-       [1346] = {177, 34, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
-       [1347] = {177, 35, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
-       [1348] = {177, 36, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
-       [1349] = {177, 37, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
-       [1350] = {177, 38, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
-       [1351] = {177, 39, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
-       [1352] = {177, 40, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
-       [1353] = {177, 41, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
-       [1354] = {178, 1, "DEV_MCASP4_AUX_CLK", "Input muxed clock"},
-       [1355] = {178, 2, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
-       [1356] = {178, 3, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
-       [1357] = {178, 4, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
-       [1358] = {178, 6, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
-       [1359] = {178, 7, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
-       [1360] = {178, 8, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
-       [1361] = {178, 9, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
-       [1362] = {178, 10, "DEV_MCASP4_MCASP_ACLKX_POUT_0", "Output clock"},
-       [1363] = {178, 11, "DEV_MCASP4_MCASP_ACLKX_PIN_0", "Input clock"},
-       [1364] = {178, 12, "DEV_MCASP4_MCASP_ACLKR_POUT_0", "Output clock"},
-       [1365] = {178, 13, "DEV_MCASP4_MCASP_ACLKR_PIN_0", "Input clock"},
-       [1366] = {178, 14, "DEV_MCASP4_MCASP_AHCLKX_POUT_0", "Output clock"},
-       [1367] = {178, 15, "DEV_MCASP4_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
-       [1368] = {178, 16, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
-       [1369] = {178, 17, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
-       [1370] = {178, 18, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
-       [1371] = {178, 19, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
-       [1372] = {178, 20, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
-       [1373] = {178, 21, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
-       [1374] = {178, 22, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
-       [1375] = {178, 23, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
-       [1376] = {178, 24, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
-       [1377] = {178, 25, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
-       [1378] = {178, 26, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
-       [1379] = {178, 27, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
-       [1380] = {178, 28, "DEV_MCASP4_MCASP_AHCLKR_POUT_0", "Output clock"},
-       [1381] = {178, 29, "DEV_MCASP4_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
-       [1382] = {178, 30, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
-       [1383] = {178, 31, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
-       [1384] = {178, 32, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
-       [1385] = {178, 33, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
-       [1386] = {178, 34, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
-       [1387] = {178, 35, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
-       [1388] = {178, 36, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
-       [1389] = {178, 37, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
-       [1390] = {178, 38, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
-       [1391] = {178, 39, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
-       [1392] = {178, 40, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
-       [1393] = {178, 41, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
-       [1394] = {179, 1, "DEV_MCASP5_AUX_CLK", "Input muxed clock"},
-       [1395] = {179, 2, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
-       [1396] = {179, 3, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
-       [1397] = {179, 4, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
-       [1398] = {179, 6, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
-       [1399] = {179, 7, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
-       [1400] = {179, 8, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
-       [1401] = {179, 9, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
-       [1402] = {179, 10, "DEV_MCASP5_MCASP_ACLKX_POUT_0", "Output clock"},
-       [1403] = {179, 11, "DEV_MCASP5_MCASP_ACLKX_PIN_0", "Input clock"},
-       [1404] = {179, 12, "DEV_MCASP5_MCASP_ACLKR_POUT_0", "Output clock"},
-       [1405] = {179, 13, "DEV_MCASP5_MCASP_ACLKR_PIN_0", "Input clock"},
-       [1406] = {179, 14, "DEV_MCASP5_MCASP_AHCLKX_POUT_0", "Output clock"},
-       [1407] = {179, 15, "DEV_MCASP5_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
-       [1408] = {179, 16, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
-       [1409] = {179, 17, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
-       [1410] = {179, 18, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
-       [1411] = {179, 19, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
-       [1412] = {179, 20, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
-       [1413] = {179, 21, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
-       [1414] = {179, 22, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
-       [1415] = {179, 23, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
-       [1416] = {179, 24, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
-       [1417] = {179, 25, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
-       [1418] = {179, 26, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
-       [1419] = {179, 27, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
-       [1420] = {179, 28, "DEV_MCASP5_MCASP_AHCLKR_POUT_0", "Output clock"},
-       [1421] = {179, 29, "DEV_MCASP5_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
-       [1422] = {179, 30, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
-       [1423] = {179, 31, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
-       [1424] = {179, 32, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
-       [1425] = {179, 33, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
-       [1426] = {179, 34, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
-       [1427] = {179, 35, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
-       [1428] = {179, 36, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
-       [1429] = {179, 37, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
-       [1430] = {179, 38, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
-       [1431] = {179, 39, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
-       [1432] = {179, 40, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
-       [1433] = {179, 41, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
-       [1434] = {180, 1, "DEV_MCASP6_AUX_CLK", "Input muxed clock"},
-       [1435] = {180, 2, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
-       [1436] = {180, 3, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
-       [1437] = {180, 4, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
-       [1438] = {180, 6, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
-       [1439] = {180, 7, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
-       [1440] = {180, 8, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
-       [1441] = {180, 9, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
-       [1442] = {180, 10, "DEV_MCASP6_MCASP_ACLKX_POUT_0", "Output clock"},
-       [1443] = {180, 11, "DEV_MCASP6_MCASP_ACLKX_PIN_0", "Input clock"},
-       [1444] = {180, 12, "DEV_MCASP6_MCASP_ACLKR_POUT_0", "Output clock"},
-       [1445] = {180, 13, "DEV_MCASP6_MCASP_ACLKR_PIN_0", "Input clock"},
-       [1446] = {180, 14, "DEV_MCASP6_MCASP_AHCLKX_POUT_0", "Output clock"},
-       [1447] = {180, 15, "DEV_MCASP6_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
-       [1448] = {180, 16, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
-       [1449] = {180, 17, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
-       [1450] = {180, 18, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
-       [1451] = {180, 19, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
-       [1452] = {180, 20, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
-       [1453] = {180, 21, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
-       [1454] = {180, 22, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
-       [1455] = {180, 23, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
-       [1456] = {180, 24, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
-       [1457] = {180, 25, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
-       [1458] = {180, 26, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
-       [1459] = {180, 27, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
-       [1460] = {180, 28, "DEV_MCASP6_MCASP_AHCLKR_POUT_0", "Output clock"},
-       [1461] = {180, 29, "DEV_MCASP6_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
-       [1462] = {180, 30, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
-       [1463] = {180, 31, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
-       [1464] = {180, 32, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
-       [1465] = {180, 33, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
-       [1466] = {180, 34, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
-       [1467] = {180, 35, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
-       [1468] = {180, 36, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
-       [1469] = {180, 37, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
-       [1470] = {180, 38, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
-       [1471] = {180, 39, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
-       [1472] = {180, 40, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
-       [1473] = {180, 41, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
-       [1474] = {181, 1, "DEV_MCASP7_AUX_CLK", "Input muxed clock"},
-       [1475] = {181, 2, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
-       [1476] = {181, 3, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
-       [1477] = {181, 4, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
-       [1478] = {181, 6, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
-       [1479] = {181, 7, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
-       [1480] = {181, 8, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
-       [1481] = {181, 9, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
-       [1482] = {181, 10, "DEV_MCASP7_MCASP_ACLKX_POUT_0", "Output clock"},
-       [1483] = {181, 11, "DEV_MCASP7_MCASP_ACLKX_PIN_0", "Input clock"},
-       [1484] = {181, 12, "DEV_MCASP7_MCASP_ACLKR_POUT_0", "Output clock"},
-       [1485] = {181, 13, "DEV_MCASP7_MCASP_ACLKR_PIN_0", "Input clock"},
-       [1486] = {181, 14, "DEV_MCASP7_MCASP_AHCLKX_POUT_0", "Output clock"},
-       [1487] = {181, 15, "DEV_MCASP7_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
-       [1488] = {181, 16, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
-       [1489] = {181, 17, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
-       [1490] = {181, 18, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
-       [1491] = {181, 19, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
-       [1492] = {181, 20, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
-       [1493] = {181, 21, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
-       [1494] = {181, 22, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
-       [1495] = {181, 23, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
-       [1496] = {181, 24, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
-       [1497] = {181, 25, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
-       [1498] = {181, 26, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
-       [1499] = {181, 27, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
-       [1500] = {181, 28, "DEV_MCASP7_MCASP_AHCLKR_POUT_0", "Output clock"},
-       [1501] = {181, 29, "DEV_MCASP7_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
-       [1502] = {181, 30, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
-       [1503] = {181, 31, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
-       [1504] = {181, 32, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
-       [1505] = {181, 33, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
-       [1506] = {181, 34, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
-       [1507] = {181, 35, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
-       [1508] = {181, 36, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
-       [1509] = {181, 37, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
-       [1510] = {181, 38, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
-       [1511] = {181, 39, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
-       [1512] = {181, 40, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
-       [1513] = {181, 41, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
-       [1514] = {182, 1, "DEV_MCASP8_AUX_CLK", "Input muxed clock"},
-       [1515] = {182, 2, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
-       [1516] = {182, 3, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
-       [1517] = {182, 4, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
-       [1518] = {182, 6, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
-       [1519] = {182, 7, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
-       [1520] = {182, 8, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
-       [1521] = {182, 9, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
-       [1522] = {182, 10, "DEV_MCASP8_MCASP_ACLKX_POUT_0", "Output clock"},
-       [1523] = {182, 11, "DEV_MCASP8_MCASP_ACLKX_PIN_0", "Input clock"},
-       [1524] = {182, 12, "DEV_MCASP8_MCASP_ACLKR_POUT_0", "Output clock"},
-       [1525] = {182, 13, "DEV_MCASP8_MCASP_ACLKR_PIN_0", "Input clock"},
-       [1526] = {182, 14, "DEV_MCASP8_MCASP_AHCLKX_POUT_0", "Output clock"},
-       [1527] = {182, 15, "DEV_MCASP8_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
-       [1528] = {182, 16, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
-       [1529] = {182, 17, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
-       [1530] = {182, 18, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
-       [1531] = {182, 19, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
-       [1532] = {182, 20, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
-       [1533] = {182, 21, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
-       [1534] = {182, 22, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
-       [1535] = {182, 23, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
-       [1536] = {182, 24, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
-       [1537] = {182, 25, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
-       [1538] = {182, 26, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
-       [1539] = {182, 27, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
-       [1540] = {182, 28, "DEV_MCASP8_MCASP_AHCLKR_POUT_0", "Output clock"},
-       [1541] = {182, 29, "DEV_MCASP8_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
-       [1542] = {182, 30, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
-       [1543] = {182, 31, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
-       [1544] = {182, 32, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
-       [1545] = {182, 33, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
-       [1546] = {182, 34, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
-       [1547] = {182, 35, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
-       [1548] = {182, 36, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
-       [1549] = {182, 37, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
-       [1550] = {182, 38, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
-       [1551] = {182, 39, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
-       [1552] = {182, 40, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
-       [1553] = {182, 41, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
-       [1554] = {183, 1, "DEV_MCASP9_AUX_CLK", "Input muxed clock"},
-       [1555] = {183, 2, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
-       [1556] = {183, 3, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
-       [1557] = {183, 4, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
-       [1558] = {183, 6, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
-       [1559] = {183, 7, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
-       [1560] = {183, 8, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
-       [1561] = {183, 9, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
-       [1562] = {183, 10, "DEV_MCASP9_MCASP_ACLKX_POUT_0", "Output clock"},
-       [1563] = {183, 11, "DEV_MCASP9_MCASP_ACLKX_PIN_0", "Input clock"},
-       [1564] = {183, 12, "DEV_MCASP9_MCASP_ACLKR_POUT_0", "Output clock"},
-       [1565] = {183, 13, "DEV_MCASP9_MCASP_ACLKR_PIN_0", "Input clock"},
-       [1566] = {183, 14, "DEV_MCASP9_MCASP_AHCLKX_POUT_0", "Output clock"},
-       [1567] = {183, 15, "DEV_MCASP9_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
-       [1568] = {183, 16, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
-       [1569] = {183, 17, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
-       [1570] = {183, 18, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
-       [1571] = {183, 19, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
-       [1572] = {183, 20, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
-       [1573] = {183, 21, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
-       [1574] = {183, 22, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
-       [1575] = {183, 23, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
-       [1576] = {183, 24, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
-       [1577] = {183, 25, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
-       [1578] = {183, 26, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
-       [1579] = {183, 27, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
-       [1580] = {183, 28, "DEV_MCASP9_MCASP_AHCLKR_POUT_0", "Output clock"},
-       [1581] = {183, 29, "DEV_MCASP9_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
-       [1582] = {183, 30, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
-       [1583] = {183, 31, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
-       [1584] = {183, 32, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
-       [1585] = {183, 33, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
-       [1586] = {183, 34, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
-       [1587] = {183, 35, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
-       [1588] = {183, 36, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
-       [1589] = {183, 37, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
-       [1590] = {183, 38, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
-       [1591] = {183, 39, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
-       [1592] = {183, 40, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
-       [1593] = {183, 41, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
-       [1594] = {266, 1, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"},
-       [1595] = {266, 2, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"},
-       [1596] = {267, 1, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"},
-       [1597] = {267, 2, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"},
-       [1598] = {268, 1, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"},
-       [1599] = {268, 2, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"},
-       [1600] = {269, 1, "DEV_MCSPI3_CLKSPIREF_CLK", "Input clock"},
-       [1601] = {269, 2, "DEV_MCSPI3_IO_CLKSPII_CLK", "Input muxed clock"},
-       [1602] = {269, 3, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"},
-       [1603] = {269, 4, "DEV_MCSPI3_IO_CLKSPIO_CLK", "Output clock"},
-       [1604] = {270, 1, "DEV_MCSPI4_CLKSPIREF_CLK", "Input clock"},
-       [1605] = {270, 2, "DEV_MCSPI4_IO_CLKSPII_CLK", "Input clock"},
-       [1606] = {270, 3, "DEV_MCSPI4_IO_CLKSPIO_CLK", "Output clock"},
-       [1607] = {271, 1, "DEV_MCSPI5_CLKSPIREF_CLK", "Input clock"},
-       [1608] = {271, 2, "DEV_MCSPI5_IO_CLKSPIO_CLK", "Output clock"},
-       [1609] = {272, 1, "DEV_MCSPI6_CLKSPIREF_CLK", "Input clock"},
-       [1610] = {272, 2, "DEV_MCSPI6_IO_CLKSPIO_CLK", "Output clock"},
-       [1611] = {273, 1, "DEV_MCSPI7_CLKSPIREF_CLK", "Input clock"},
-       [1612] = {273, 2, "DEV_MCSPI7_IO_CLKSPIO_CLK", "Output clock"},
-       [1613] = {0, 1, "DEV_MCU_ADC0_ADC_CLK", "Input muxed clock"},
-       [1614] = {0, 2, "DEV_MCU_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"},
-       [1615] = {0, 3, "DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"},
-       [1616] = {0, 4, "DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"},
-       [1617] = {0, 5, "DEV_MCU_ADC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"},
-       [1618] = {0, 6, "DEV_MCU_ADC0_VBUS_CLK", "Input clock"},
-       [1619] = {1, 1, "DEV_MCU_ADC1_ADC_CLK", "Input muxed clock"},
-       [1620] = {1, 2, "DEV_MCU_ADC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"},
-       [1621] = {1, 3, "DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"},
-       [1622] = {1, 4, "DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"},
-       [1623] = {1, 5, "DEV_MCU_ADC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"},
-       [1624] = {1, 6, "DEV_MCU_ADC1_VBUS_CLK", "Input clock"},
-       [1625] = {18, 1, "DEV_MCU_CPSW0_RGMII_MHZ_250_CLK", "Input clock"},
-       [1626] = {18, 2, "DEV_MCU_CPSW0_CPTS_RFT_CLK", "Input muxed clock"},
-       [1627] = {18, 3, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
-       [1628] = {18, 4, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
-       [1629] = {18, 5, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
-       [1630] = {18, 6, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
-       [1631] = {18, 7, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
-       [1632] = {18, 8, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
-       [1633] = {18, 9, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
-       [1634] = {18, 10, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
-       [1635] = {18, 11, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
-       [1636] = {18, 12, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
-       [1637] = {18, 13, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
-       [1638] = {18, 14, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
-       [1639] = {18, 15, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
-       [1640] = {18, 16, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
-       [1641] = {18, 17, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
-       [1642] = {18, 18, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
-       [1643] = {18, 19, "DEV_MCU_CPSW0_GMII_RFT_CLK", "Input clock"},
-       [1644] = {18, 20, "DEV_MCU_CPSW0_RMII_MHZ_50_CLK", "Input clock"},
-       [1645] = {18, 21, "DEV_MCU_CPSW0_RGMII_MHZ_50_CLK", "Input clock"},
-       [1646] = {18, 22, "DEV_MCU_CPSW0_CPPI_CLK_CLK", "Input clock"},
-       [1647] = {18, 23, "DEV_MCU_CPSW0_RGMII_MHZ_5_CLK", "Input clock"},
-       [1648] = {18, 24, "DEV_MCU_CPSW0_GMII1_MR_CLK", "Input clock"},
-       [1649] = {18, 25, "DEV_MCU_CPSW0_GMII1_MT_CLK", "Input clock"},
-       [1650] = {18, 26, "DEV_MCU_CPSW0_RGMII1_TXC_I", "Input clock"},
-       [1651] = {18, 27, "DEV_MCU_CPSW0_RGMII1_TXC_O", "Output clock"},
-       [1652] = {18, 28, "DEV_MCU_CPSW0_CPTS_GENF0_0", "Output clock"},
-       [1653] = {18, 29, "DEV_MCU_CPSW0_MDIO_MDCLK_O_0", "Output clock"},
-       [1654] = {44, 1, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"},
-       [1655] = {44, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"},
-       [1656] = {44, 3, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"},
-       [1657] = {44, 4, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"},
-       [1658] = {44, 5, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"},
-       [1659] = {44, 6, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"},
-       [1660] = {44, 7, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"},
-       [1661] = {44, 8, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"},
-       [1662] = {44, 9, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"},
-       [1663] = {44, 10, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"},
-       [1664] = {44, 11, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"},
-       [1665] = {44, 12, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"},
-       [1666] = {45, 1, "DEV_MCU_DCC1_DCC_INPUT01_CLK", "Input clock"},
-       [1667] = {45, 2, "DEV_MCU_DCC1_DCC_CLKSRC2_CLK", "Input clock"},
-       [1668] = {45, 3, "DEV_MCU_DCC1_DCC_CLKSRC7_CLK", "Input clock"},
-       [1669] = {45, 4, "DEV_MCU_DCC1_DCC_CLKSRC0_CLK", "Input clock"},
-       [1670] = {45, 5, "DEV_MCU_DCC1_VBUS_CLK", "Input clock"},
-       [1671] = {45, 6, "DEV_MCU_DCC1_DCC_CLKSRC4_CLK", "Input clock"},
-       [1672] = {45, 7, "DEV_MCU_DCC1_DCC_CLKSRC1_CLK", "Input clock"},
-       [1673] = {45, 8, "DEV_MCU_DCC1_DCC_CLKSRC3_CLK", "Input clock"},
-       [1674] = {45, 9, "DEV_MCU_DCC1_DCC_INPUT00_CLK", "Input clock"},
-       [1675] = {45, 10, "DEV_MCU_DCC1_DCC_CLKSRC5_CLK", "Input clock"},
-       [1676] = {45, 11, "DEV_MCU_DCC1_DCC_CLKSRC6_CLK", "Input clock"},
-       [1677] = {45, 12, "DEV_MCU_DCC1_DCC_INPUT02_CLK", "Input clock"},
-       [1678] = {46, 1, "DEV_MCU_DCC2_DCC_INPUT01_CLK", "Input clock"},
-       [1679] = {46, 2, "DEV_MCU_DCC2_DCC_CLKSRC7_CLK", "Input clock"},
-       [1680] = {46, 3, "DEV_MCU_DCC2_DCC_CLKSRC0_CLK", "Input clock"},
-       [1681] = {46, 4, "DEV_MCU_DCC2_VBUS_CLK", "Input clock"},
-       [1682] = {46, 5, "DEV_MCU_DCC2_DCC_CLKSRC4_CLK", "Input clock"},
-       [1683] = {46, 6, "DEV_MCU_DCC2_DCC_CLKSRC1_CLK", "Input clock"},
-       [1684] = {46, 7, "DEV_MCU_DCC2_DCC_CLKSRC3_CLK", "Input clock"},
-       [1685] = {46, 8, "DEV_MCU_DCC2_DCC_INPUT00_CLK", "Input clock"},
-       [1686] = {46, 9, "DEV_MCU_DCC2_DCC_CLKSRC6_CLK", "Input clock"},
-       [1687] = {46, 10, "DEV_MCU_DCC2_DCC_INPUT02_CLK", "Input clock"},
-       [1688] = {102, 1, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK", "Input clock"},
-       [1689] = {102, 2, "DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK", "Input clock"},
-       [1690] = {102, 3, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK", "Input clock"},
-       [1691] = {102, 4, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK", "Input clock"},
-       [1692] = {102, 5, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N", "Output clock"},
-       [1693] = {102, 6, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P", "Output clock"},
-       [1694] = {103, 1, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"},
-       [1695] = {103, 2, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"},
-       [1696] = {103, 3, "DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"},
-       [1697] = {103, 4, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"},
-       [1698] = {103, 5, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"},
-       [1699] = {103, 6, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"},
-       [1700] = {103, 7, "DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"},
-       [1701] = {103, 8, "DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"},
-       [1702] = {103, 9, "DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"},
-       [1703] = {104, 1, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"},
-       [1704] = {104, 2, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"},
-       [1705] = {104, 3, "DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK", "Input clock"},
-       [1706] = {104, 4, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK", "Input muxed clock"},
-       [1707] = {104, 5, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"},
-       [1708] = {104, 6, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"},
-       [1709] = {104, 7, "DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK", "Input clock"},
-       [1710] = {104, 8, "DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK", "Input clock"},
-       [1711] = {104, 9, "DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK", "Output clock"},
-       [1712] = {194, 1, "DEV_MCU_I2C0_PISCL_0", "Input clock"},
-       [1713] = {194, 2, "DEV_MCU_I2C0_CLK", "Input clock"},
-       [1714] = {194, 3, "DEV_MCU_I2C0_PORSCL_0", "Output clock"},
-       [1715] = {195, 1, "DEV_MCU_I2C1_PISCL_0", "Input clock"},
-       [1716] = {195, 2, "DEV_MCU_I2C1_CLK", "Input clock"},
-       [1717] = {117, 1, "DEV_MCU_I3C0_I3C_SCL_DI", "Input clock"},
-       [1718] = {117, 2, "DEV_MCU_I3C0_I3C_SCLK_CLK", "Input clock"},
-       [1719] = {117, 3, "DEV_MCU_I3C0_I3C_SCL_DO_0", "Output clock"},
-       [1720] = {118, 1, "DEV_MCU_I3C1_I3C_SCL_DI", "Input clock"},
-       [1721] = {118, 2, "DEV_MCU_I3C1_I3C_SCLK_CLK", "Input clock"},
-       [1722] = {118, 3, "DEV_MCU_I3C1_I3C_SCL_DO_0", "Output clock"},
-       [1723] = {172, 1, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"},
-       [1724] = {172, 2, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
-       [1725] = {172, 3, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
-       [1726] = {172, 4, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
-       [1727] = {172, 5, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
-       [1728] = {173, 1, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"},
-       [1729] = {173, 2, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
-       [1730] = {173, 3, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
-       [1731] = {173, 4, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
-       [1732] = {173, 5, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
-       [1733] = {274, 1, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"},
-       [1734] = {274, 2, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"},
-       [1735] = {275, 1, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"},
-       [1736] = {275, 2, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"},
-       [1737] = {275, 3, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"},
-       [1738] = {275, 4, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"},
-       [1739] = {276, 1, "DEV_MCU_MCSPI2_CLKSPIREF_CLK", "Input clock"},
-       [1740] = {276, 2, "DEV_MCU_MCSPI2_IO_CLKSPII_CLK", "Input clock"},
-       [1741] = {276, 3, "DEV_MCU_MCSPI2_IO_CLKSPIO_CLK", "Output clock"},
-       [1742] = {250, 1, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"},
-       [1743] = {250, 2, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"},
-       [1744] = {250, 3, "DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"},
-       [1745] = {251, 1, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"},
-       [1746] = {251, 2, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"},
-       [1747] = {251, 3, "DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"},
-       [1748] = {262, 1, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"},
-       [1749] = {262, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
-       [1750] = {262, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
-       [1751] = {262, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
-       [1752] = {262, 5, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
-       [1753] = {263, 1, "DEV_MCU_RTI1_RTI_CLK", "Input muxed clock"},
-       [1754] = {263, 2, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
-       [1755] = {263, 3, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
-       [1756] = {263, 4, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
-       [1757] = {263, 5, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
-       [1758] = {265, 1, "DEV_MCU_SA2_UL0_PKA_IN_CLK", "Input clock"},
-       [1759] = {265, 2, "DEV_MCU_SA2_UL0_X1_CLK", "Input clock"},
-       [1760] = {35, 1, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"},
-       [1761] = {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
-       [1762] = {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK5", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
-       [1763] = {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
-       [1764] = {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
-       [1765] = {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
-       [1766] = {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
-       [1767] = {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
-       [1768] = {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
-       [1769] = {35, 10, "DEV_MCU_TIMER0_TIMER_PWM_0", "Output clock"},
-       [1770] = {71, 1, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"},
-       [1771] = {71, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
-       [1772] = {71, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM_0", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
-       [1773] = {72, 1, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"},
-       [1774] = {72, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
-       [1775] = {72, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK5", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
-       [1776] = {72, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
-       [1777] = {72, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
-       [1778] = {72, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
-       [1779] = {72, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
-       [1780] = {72, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
-       [1781] = {72, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
-       [1782] = {72, 10, "DEV_MCU_TIMER2_TIMER_PWM_0", "Output clock"},
-       [1783] = {73, 1, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"},
-       [1784] = {73, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
-       [1785] = {73, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM_0", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
-       [1786] = {74, 1, "DEV_MCU_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"},
-       [1787] = {74, 2, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
-       [1788] = {74, 3, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK5", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
-       [1789] = {74, 4, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
-       [1790] = {74, 5, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
-       [1791] = {74, 6, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
-       [1792] = {74, 7, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
-       [1793] = {74, 8, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
-       [1794] = {74, 9, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
-       [1795] = {74, 10, "DEV_MCU_TIMER4_TIMER_PWM_0", "Output clock"},
-       [1796] = {75, 1, "DEV_MCU_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"},
-       [1797] = {75, 2, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"},
-       [1798] = {75, 3, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM_0", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"},
-       [1799] = {76, 1, "DEV_MCU_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"},
-       [1800] = {76, 2, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
-       [1801] = {76, 3, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK5", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
-       [1802] = {76, 4, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
-       [1803] = {76, 5, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
-       [1804] = {76, 6, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
-       [1805] = {76, 7, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
-       [1806] = {76, 8, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
-       [1807] = {76, 9, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
-       [1808] = {76, 10, "DEV_MCU_TIMER6_TIMER_PWM_0", "Output clock"},
-       [1809] = {77, 1, "DEV_MCU_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"},
-       [1810] = {77, 2, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"},
-       [1811] = {77, 3, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM_0", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"},
-       [1812] = {78, 1, "DEV_MCU_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"},
-       [1813] = {78, 2, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
-       [1814] = {78, 3, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK5", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
-       [1815] = {78, 4, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
-       [1816] = {78, 5, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
-       [1817] = {78, 6, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
-       [1818] = {78, 7, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
-       [1819] = {78, 8, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
-       [1820] = {78, 9, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
-       [1821] = {78, 10, "DEV_MCU_TIMER8_TIMER_PWM_0", "Output clock"},
-       [1822] = {79, 1, "DEV_MCU_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"},
-       [1823] = {79, 2, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"},
-       [1824] = {79, 3, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM_0", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"},
-       [1825] = {149, 1, "DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"},
-       [1826] = {149, 2, "DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"},
-       [1827] = {149, 3, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"},
-       [1828] = {186, 1, "DEV_MLB0_MLBSS_SCLK_CLK", "Input clock"},
-       [1829] = {186, 2, "DEV_MLB0_MLBSS_HCLK_CLK", "Input clock"},
-       [1830] = {186, 3, "DEV_MLB0_MLBSS_PCLK_CLK", "Input clock"},
-       [1831] = {186, 4, "DEV_MLB0_MLBSS_AMLB_CLK", "Input clock"},
-       [1832] = {91, 1, "DEV_MMCSD0_EMMCSS_XIN_CLK", "Input muxed clock"},
-       [1833] = {91, 2, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
-       [1834] = {91, 3, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
-       [1835] = {91, 4, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
-       [1836] = {91, 5, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
-       [1837] = {91, 6, "DEV_MMCSD0_EMMCSS_IO_CLK_0", "Output clock"},
-       [1838] = {92, 1, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
-       [1839] = {92, 2, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
-       [1840] = {92, 3, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
-       [1841] = {92, 4, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
-       [1842] = {92, 5, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"},
-       [1843] = {92, 6, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I_0", "Input clock"},
-       [1844] = {92, 7, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O_0", "Output clock"},
-       [1845] = {93, 1, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"},
-       [1846] = {93, 2, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"},
-       [1847] = {93, 3, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"},
-       [1848] = {93, 4, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"},
-       [1849] = {93, 5, "DEV_MMCSD2_EMMCSDSS_VBUS_CLK", "Input clock"},
-       [1850] = {93, 6, "DEV_MMCSD2_EMMCSDSS_IO_CLK_I_0", "Input clock"},
-       [1851] = {93, 7, "DEV_MMCSD2_EMMCSDSS_IO_CLK_O_0", "Output clock"},
-       [1852] = {201, 1, "DEV_NAVSS0_CPTS_0_RCLK", "Input muxed clock"},
-       [1853] = {201, 2, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
-       [1854] = {201, 3, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
-       [1855] = {201, 4, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
-       [1856] = {201, 5, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
-       [1857] = {201, 6, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
-       [1858] = {201, 7, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
-       [1859] = {201, 8, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
-       [1860] = {201, 9, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
-       [1861] = {201, 10, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
-       [1862] = {201, 11, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
-       [1863] = {201, 12, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
-       [1864] = {201, 13, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
-       [1865] = {201, 14, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
-       [1866] = {201, 15, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
-       [1867] = {201, 16, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
-       [1868] = {201, 17, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
-       [1869] = {201, 18, "DEV_NAVSS0_CPTS_0_TS_GENF0", "Output clock"},
-       [1870] = {201, 19, "DEV_NAVSS0_CPTS_0_TS_GENF1", "Output clock"},
-       [1871] = {206, 1, "DEV_NAVSS0_DTI_0_EXT0_DTI_CLK_CLK", "Input clock"},
-       [1872] = {206, 2, "DEV_NAVSS0_DTI_0_EXT3_DTI_CLK_CLK", "Input clock"},
-       [1873] = {206, 3, "DEV_NAVSS0_DTI_0_EXT1_DTI_CLK_CLK", "Input clock"},
-       [1874] = {206, 4, "DEV_NAVSS0_DTI_0_EXT2_DTI_CLK_CLK", "Input clock"},
-       [1875] = {230, 1, "DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT", "Input clock"},
-       [1876] = {231, 1, "DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT", "Input clock"},
-       [1877] = {199, 1, "DEV_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Output clock"},
-       [1878] = {239, 1, "DEV_PCIE0_PCIE_CBA_CLK", "Input clock"},
-       [1879] = {239, 2, "DEV_PCIE0_PCIE_LANE1_RXCLK", "Input clock"},
-       [1880] = {239, 3, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
-       [1881] = {239, 4, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
-       [1882] = {239, 5, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
-       [1883] = {239, 6, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
-       [1884] = {239, 7, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
-       [1885] = {239, 8, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
-       [1886] = {239, 9, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
-       [1887] = {239, 10, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
-       [1888] = {239, 11, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
-       [1889] = {239, 12, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
-       [1890] = {239, 13, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
-       [1891] = {239, 14, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
-       [1892] = {239, 15, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
-       [1893] = {239, 16, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
-       [1894] = {239, 17, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
-       [1895] = {239, 18, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
-       [1896] = {239, 19, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
-       [1897] = {239, 20, "DEV_PCIE0_PCIE_LANE1_TXFCLK", "Input clock"},
-       [1898] = {239, 21, "DEV_PCIE0_PCIE_LANE1_REFCLK", "Input clock"},
-       [1899] = {239, 22, "DEV_PCIE0_PCIE_LANE0_REFCLK", "Input clock"},
-       [1900] = {239, 23, "DEV_PCIE0_PCIE_LANE0_TXMCLK", "Input clock"},
-       [1901] = {239, 24, "DEV_PCIE0_PCIE_LANE0_TXFCLK", "Input clock"},
-       [1902] = {239, 25, "DEV_PCIE0_PCIE_PM_CLK", "Input clock"},
-       [1903] = {239, 26, "DEV_PCIE0_PCIE_LANE0_RXFCLK", "Input clock"},
-       [1904] = {239, 27, "DEV_PCIE0_PCIE_LANE1_RXFCLK", "Input clock"},
-       [1905] = {239, 28, "DEV_PCIE0_PCIE_LANE0_RXCLK", "Input clock"},
-       [1906] = {239, 29, "DEV_PCIE0_PCIE_LANE1_TXCLK", "Output clock"},
-       [1907] = {239, 30, "DEV_PCIE0_PCIE_LANE0_TXCLK", "Output clock"},
-       [1908] = {240, 1, "DEV_PCIE1_PCIE_CBA_CLK", "Input clock"},
-       [1909] = {240, 2, "DEV_PCIE1_PCIE_LANE1_RXCLK", "Input clock"},
-       [1910] = {240, 3, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
-       [1911] = {240, 4, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
-       [1912] = {240, 5, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
-       [1913] = {240, 6, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
-       [1914] = {240, 7, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
-       [1915] = {240, 8, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
-       [1916] = {240, 9, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
-       [1917] = {240, 10, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
-       [1918] = {240, 11, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
-       [1919] = {240, 12, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
-       [1920] = {240, 13, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
-       [1921] = {240, 14, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
-       [1922] = {240, 15, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
-       [1923] = {240, 16, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
-       [1924] = {240, 17, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
-       [1925] = {240, 18, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
-       [1926] = {240, 19, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
-       [1927] = {240, 20, "DEV_PCIE1_PCIE_LANE1_TXFCLK", "Input clock"},
-       [1928] = {240, 21, "DEV_PCIE1_PCIE_LANE1_REFCLK", "Input clock"},
-       [1929] = {240, 22, "DEV_PCIE1_PCIE_LANE0_REFCLK", "Input clock"},
-       [1930] = {240, 23, "DEV_PCIE1_PCIE_LANE0_TXMCLK", "Input clock"},
-       [1931] = {240, 24, "DEV_PCIE1_PCIE_LANE0_TXFCLK", "Input clock"},
-       [1932] = {240, 25, "DEV_PCIE1_PCIE_PM_CLK", "Input clock"},
-       [1933] = {240, 26, "DEV_PCIE1_PCIE_LANE0_RXFCLK", "Input clock"},
-       [1934] = {240, 27, "DEV_PCIE1_PCIE_LANE1_RXFCLK", "Input clock"},
-       [1935] = {240, 28, "DEV_PCIE1_PCIE_LANE0_RXCLK", "Input clock"},
-       [1936] = {240, 29, "DEV_PCIE1_PCIE_LANE1_TXCLK", "Output clock"},
-       [1937] = {240, 30, "DEV_PCIE1_PCIE_LANE0_TXCLK", "Output clock"},
-       [1938] = {241, 1, "DEV_PCIE2_PCIE_CBA_CLK", "Input clock"},
-       [1939] = {241, 2, "DEV_PCIE2_PCIE_LANE1_RXCLK", "Input clock"},
-       [1940] = {241, 3, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
-       [1941] = {241, 4, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
-       [1942] = {241, 5, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
-       [1943] = {241, 6, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
-       [1944] = {241, 7, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
-       [1945] = {241, 8, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
-       [1946] = {241, 9, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
-       [1947] = {241, 10, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
-       [1948] = {241, 11, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
-       [1949] = {241, 12, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
-       [1950] = {241, 13, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
-       [1951] = {241, 14, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
-       [1952] = {241, 15, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
-       [1953] = {241, 16, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
-       [1954] = {241, 17, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
-       [1955] = {241, 18, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
-       [1956] = {241, 19, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
-       [1957] = {241, 20, "DEV_PCIE2_PCIE_LANE1_TXFCLK", "Input clock"},
-       [1958] = {241, 21, "DEV_PCIE2_PCIE_LANE1_REFCLK", "Input clock"},
-       [1959] = {241, 22, "DEV_PCIE2_PCIE_LANE0_REFCLK", "Input clock"},
-       [1960] = {241, 23, "DEV_PCIE2_PCIE_LANE0_TXMCLK", "Input clock"},
-       [1961] = {241, 24, "DEV_PCIE2_PCIE_LANE0_TXFCLK", "Input clock"},
-       [1962] = {241, 25, "DEV_PCIE2_PCIE_PM_CLK", "Input clock"},
-       [1963] = {241, 26, "DEV_PCIE2_PCIE_LANE0_RXFCLK", "Input clock"},
-       [1964] = {241, 27, "DEV_PCIE2_PCIE_LANE1_RXFCLK", "Input clock"},
-       [1965] = {241, 28, "DEV_PCIE2_PCIE_LANE0_RXCLK", "Input clock"},
-       [1966] = {241, 29, "DEV_PCIE2_PCIE_LANE1_TXCLK", "Output clock"},
-       [1967] = {241, 30, "DEV_PCIE2_PCIE_LANE0_TXCLK", "Output clock"},
-       [1968] = {242, 1, "DEV_PCIE3_PCIE_CBA_CLK", "Input clock"},
-       [1969] = {242, 2, "DEV_PCIE3_PCIE_LANE1_RXCLK", "Input clock"},
-       [1970] = {242, 3, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
-       [1971] = {242, 4, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
-       [1972] = {242, 5, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
-       [1973] = {242, 6, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
-       [1974] = {242, 7, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
-       [1975] = {242, 8, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
-       [1976] = {242, 9, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
-       [1977] = {242, 10, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
-       [1978] = {242, 11, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
-       [1979] = {242, 12, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
-       [1980] = {242, 13, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
-       [1981] = {242, 14, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
-       [1982] = {242, 15, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
-       [1983] = {242, 16, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
-       [1984] = {242, 17, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
-       [1985] = {242, 18, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
-       [1986] = {242, 19, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
-       [1987] = {242, 20, "DEV_PCIE3_PCIE_LANE1_TXFCLK", "Input clock"},
-       [1988] = {242, 21, "DEV_PCIE3_PCIE_LANE1_REFCLK", "Input clock"},
-       [1989] = {242, 22, "DEV_PCIE3_PCIE_LANE0_REFCLK", "Input clock"},
-       [1990] = {242, 23, "DEV_PCIE3_PCIE_LANE0_TXMCLK", "Input clock"},
-       [1991] = {242, 24, "DEV_PCIE3_PCIE_LANE0_TXFCLK", "Input clock"},
-       [1992] = {242, 25, "DEV_PCIE3_PCIE_PM_CLK", "Input clock"},
-       [1993] = {242, 26, "DEV_PCIE3_PCIE_LANE0_RXFCLK", "Input clock"},
-       [1994] = {242, 27, "DEV_PCIE3_PCIE_LANE1_RXFCLK", "Input clock"},
-       [1995] = {242, 28, "DEV_PCIE3_PCIE_LANE0_RXCLK", "Input clock"},
-       [1996] = {242, 29, "DEV_PCIE3_PCIE_LANE1_TXCLK", "Output clock"},
-       [1997] = {242, 30, "DEV_PCIE3_PCIE_LANE0_TXCLK", "Output clock"},
-       [1998] = {119, 1, "DEV_PRU_ICSSG0_VCLK_CLK", "Input clock"},
-       [1999] = {119, 2, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I_0", "Input clock"},
-       [2000] = {119, 3, "DEV_PRU_ICSSG0_IEP_CLK", "Input muxed clock"},
-       [2001] = {119, 4, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
-       [2002] = {119, 5, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
-       [2003] = {119, 6, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
-       [2004] = {119, 7, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
-       [2005] = {119, 8, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
-       [2006] = {119, 9, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
-       [2007] = {119, 10, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
-       [2008] = {119, 11, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
-       [2009] = {119, 12, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
-       [2010] = {119, 13, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
-       [2011] = {119, 14, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
-       [2012] = {119, 15, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
-       [2013] = {119, 16, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
-       [2014] = {119, 17, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
-       [2015] = {119, 18, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
-       [2016] = {119, 19, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
-       [2017] = {119, 20, "DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK", "Input clock"},
-       [2018] = {119, 21, "DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I_0", "Input clock"},
-       [2019] = {119, 22, "DEV_PRU_ICSSG0_UCLK_CLK", "Input clock"},
-       [2020] = {119, 23, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I_0", "Input clock"},
-       [2021] = {119, 24, "DEV_PRU_ICSSG0_CORE_CLK", "Input muxed clock"},
-       [2022] = {119, 25, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"},
-       [2023] = {119, 26, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"},
-       [2024] = {119, 27, "DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK", "Input clock"},
-       [2025] = {119, 28, "DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK", "Input clock"},
-       [2026] = {119, 29, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O_0", "Output clock"},
-       [2027] = {119, 30, "DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O_0", "Output clock"},
-       [2028] = {119, 31, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O_0", "Output clock"},
-       [2029] = {120, 1, "DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK"},
-       [2030] = {120, 2, "DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK"},
-       [2031] = {120, 3, "DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I_0", "Input clock"},
-       [2032] = {120, 4, "DEV_PRU_ICSSG1_VCLK_CLK", "Input clock"},
-       [2033] = {120, 5, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I_0", "Input clock"},
-       [2034] = {120, 6, "DEV_PRU_ICSSG1_SERDES0_RXFCLK", "Input muxed clock"},
-       [2035] = {120, 7, "DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK"},
-       [2036] = {120, 8, "DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK"},
-       [2037] = {120, 9, "DEV_PRU_ICSSG1_IEP_CLK", "Input muxed clock"},
-       [2038] = {120, 10, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
-       [2039] = {120, 11, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
-       [2040] = {120, 12, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
-       [2041] = {120, 13, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
-       [2042] = {120, 14, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
-       [2043] = {120, 15, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
-       [2044] = {120, 16, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
-       [2045] = {120, 17, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
-       [2046] = {120, 18, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
-       [2047] = {120, 19, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
-       [2048] = {120, 20, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
-       [2049] = {120, 21, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
-       [2050] = {120, 22, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
-       [2051] = {120, 23, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
-       [2052] = {120, 24, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
-       [2053] = {120, 25, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
-       [2054] = {120, 26, "DEV_PRU_ICSSG1_RGMII_MHZ_5_CLK", "Input clock"},
-       [2055] = {120, 27, "DEV_PRU_ICSSG1_SERDES0_TXMCLK", "Input muxed clock"},
-       [2056] = {120, 28, "DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK"},
-       [2057] = {120, 29, "DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK"},
-       [2058] = {120, 30, "DEV_PRU_ICSSG1_SERDES0_REFCLK", "Input muxed clock"},
-       [2059] = {120, 31, "DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK"},
-       [2060] = {120, 32, "DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK"},
-       [2061] = {120, 33, "DEV_PRU_ICSSG1_SERDES1_RXFCLK", "Input muxed clock"},
-       [2062] = {120, 34, "DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK"},
-       [2063] = {120, 35, "DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK"},
-       [2064] = {120, 36, "DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I_0", "Input clock"},
-       [2065] = {120, 37, "DEV_PRU_ICSSG1_SERDES1_RXCLK", "Input muxed clock"},
-       [2066] = {120, 38, "DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK"},
-       [2067] = {120, 39, "DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK"},
-       [2068] = {120, 40, "DEV_PRU_ICSSG1_SERDES1_TXFCLK", "Input muxed clock"},
-       [2069] = {120, 41, "DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK"},
-       [2070] = {120, 42, "DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK"},
-       [2071] = {120, 43, "DEV_PRU_ICSSG1_SERDES1_TXMCLK", "Input muxed clock"},
-       [2072] = {120, 44, "DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK"},
-       [2073] = {120, 45, "DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK"},
-       [2074] = {120, 46, "DEV_PRU_ICSSG1_SERDES0_TXFCLK", "Input muxed clock"},
-       [2075] = {120, 47, "DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK"},
-       [2076] = {120, 48, "DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK"},
-       [2077] = {120, 49, "DEV_PRU_ICSSG1_UCLK_CLK", "Input clock"},
-       [2078] = {120, 50, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I_0", "Input clock"},
-       [2079] = {120, 51, "DEV_PRU_ICSSG1_SERDES1_REFCLK", "Input muxed clock"},
-       [2080] = {120, 52, "DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK"},
-       [2081] = {120, 53, "DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK"},
-       [2082] = {120, 54, "DEV_PRU_ICSSG1_CORE_CLK", "Input muxed clock"},
-       [2083] = {120, 55, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"},
-       [2084] = {120, 56, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"},
-       [2085] = {120, 57, "DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK", "Input clock"},
-       [2086] = {120, 58, "DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK", "Input clock"},
-       [2087] = {120, 59, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O_0", "Output clock"},
-       [2088] = {120, 60, "DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O_0", "Output clock"},
-       [2089] = {120, 61, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O_0", "Output clock"},
-       [2090] = {120, 62, "DEV_PRU_ICSSG1_SERDES0_TXCLK", "Output clock"},
-       [2091] = {120, 63, "DEV_PRU_ICSSG1_SERDES1_TXCLK", "Output clock"},
-       [2092] = {133, 1, "DEV_PSC0_CLK", "Input clock"},
-       [2093] = {243, 1, "DEV_PULSAR_SL_MAIN_0_INTERFACE1_PHASE_0", "Input clock"},
-       [2094] = {244, 1, "DEV_PULSAR_SL_MAIN_1_INTERFACE1_PHASE_0", "Input clock"},
-       [2095] = {249, 1, "DEV_PULSAR_SL_MCU_0_INTERFACE0_PHASE_0_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_PULSAR_SL_MCU_0_INTERFACE0_PHASE_0"},
-       [2096] = {249, 2, "DEV_PULSAR_SL_MCU_0_INTERFACE1_PHASE_0", "Input muxed clock"},
-       [2097] = {249, 3, "DEV_PULSAR_SL_MCU_0_INTERFACE1_PHASE_0_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_PULSAR_SL_MCU_0_INTERFACE1_PHASE_0"},
-       [2098] = {245, 1, "DEV_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"},
-       [2099] = {246, 1, "DEV_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"},
-       [2100] = {247, 1, "DEV_R5FSS1_CORE0_INTERFACE_CLK", "Input clock"},
-       [2101] = {248, 1, "DEV_R5FSS1_CORE1_INTERFACE_CLK", "Input clock"},
-       [2102] = {252, 1, "DEV_RTI0_RTI_CLK", "Input muxed clock"},
-       [2103] = {252, 2, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
-       [2104] = {252, 3, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
-       [2105] = {252, 4, "DEV_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"},
-       [2106] = {252, 5, "DEV_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"},
-       [2107] = {252, 6, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
-       [2108] = {252, 7, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI0_RTI_CLK"},
-       [2109] = {252, 8, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI0_RTI_CLK"},
-       [2110] = {252, 9, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI0_RTI_CLK"},
-       [2111] = {253, 1, "DEV_RTI1_RTI_CLK", "Input muxed clock"},
-       [2112] = {253, 2, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
-       [2113] = {253, 3, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
-       [2114] = {253, 4, "DEV_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"},
-       [2115] = {253, 5, "DEV_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"},
-       [2116] = {253, 6, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
-       [2117] = {253, 7, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI1_RTI_CLK"},
-       [2118] = {253, 8, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI1_RTI_CLK"},
-       [2119] = {253, 9, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI1_RTI_CLK"},
-       [2120] = {257, 1, "DEV_RTI15_RTI_CLK", "Input muxed clock"},
-       [2121] = {257, 2, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"},
-       [2122] = {257, 3, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"},
-       [2123] = {257, 4, "DEV_RTI15_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI15_RTI_CLK"},
-       [2124] = {257, 5, "DEV_RTI15_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI15_RTI_CLK"},
-       [2125] = {257, 6, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI15_RTI_CLK"},
-       [2126] = {257, 7, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI15_RTI_CLK"},
-       [2127] = {257, 8, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI15_RTI_CLK"},
-       [2128] = {257, 9, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI15_RTI_CLK"},
-       [2129] = {256, 1, "DEV_RTI16_RTI_CLK", "Input muxed clock"},
-       [2130] = {256, 2, "DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI16_RTI_CLK"},
-       [2131] = {256, 3, "DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI16_RTI_CLK"},
-       [2132] = {256, 4, "DEV_RTI16_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI16_RTI_CLK"},
-       [2133] = {256, 5, "DEV_RTI16_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI16_RTI_CLK"},
-       [2134] = {256, 6, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI16_RTI_CLK"},
-       [2135] = {256, 7, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI16_RTI_CLK"},
-       [2136] = {256, 8, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI16_RTI_CLK"},
-       [2137] = {256, 9, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI16_RTI_CLK"},
-       [2138] = {254, 1, "DEV_RTI24_RTI_CLK", "Input muxed clock"},
-       [2139] = {254, 2, "DEV_RTI24_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI24_RTI_CLK"},
-       [2140] = {254, 3, "DEV_RTI24_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI24_RTI_CLK"},
-       [2141] = {254, 4, "DEV_RTI24_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI24_RTI_CLK"},
-       [2142] = {254, 5, "DEV_RTI24_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI24_RTI_CLK"},
-       [2143] = {254, 6, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI24_RTI_CLK"},
-       [2144] = {254, 7, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI24_RTI_CLK"},
-       [2145] = {254, 8, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI24_RTI_CLK"},
-       [2146] = {254, 9, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI24_RTI_CLK"},
-       [2147] = {255, 1, "DEV_RTI25_RTI_CLK", "Input muxed clock"},
-       [2148] = {255, 2, "DEV_RTI25_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI25_RTI_CLK"},
-       [2149] = {255, 3, "DEV_RTI25_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI25_RTI_CLK"},
-       [2150] = {255, 4, "DEV_RTI25_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI25_RTI_CLK"},
-       [2151] = {255, 5, "DEV_RTI25_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI25_RTI_CLK"},
-       [2152] = {255, 6, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI25_RTI_CLK"},
-       [2153] = {255, 7, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI25_RTI_CLK"},
-       [2154] = {255, 8, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI25_RTI_CLK"},
-       [2155] = {255, 9, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI25_RTI_CLK"},
-       [2156] = {258, 1, "DEV_RTI28_RTI_CLK", "Input muxed clock"},
-       [2157] = {258, 2, "DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
-       [2158] = {258, 3, "DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
-       [2159] = {258, 4, "DEV_RTI28_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"},
-       [2160] = {258, 5, "DEV_RTI28_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"},
-       [2161] = {258, 6, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
-       [2162] = {258, 7, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI28_RTI_CLK"},
-       [2163] = {258, 8, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI28_RTI_CLK"},
-       [2164] = {258, 9, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI28_RTI_CLK"},
-       [2165] = {259, 1, "DEV_RTI29_RTI_CLK", "Input muxed clock"},
-       [2166] = {259, 2, "DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
-       [2167] = {259, 3, "DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
-       [2168] = {259, 4, "DEV_RTI29_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"},
-       [2169] = {259, 5, "DEV_RTI29_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"},
-       [2170] = {259, 6, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
-       [2171] = {259, 7, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI29_RTI_CLK"},
-       [2172] = {259, 8, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI29_RTI_CLK"},
-       [2173] = {259, 9, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI29_RTI_CLK"},
-       [2174] = {260, 1, "DEV_RTI30_RTI_CLK", "Input muxed clock"},
-       [2175] = {260, 2, "DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI30_RTI_CLK"},
-       [2176] = {260, 3, "DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI30_RTI_CLK"},
-       [2177] = {260, 4, "DEV_RTI30_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI30_RTI_CLK"},
-       [2178] = {260, 5, "DEV_RTI30_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI30_RTI_CLK"},
-       [2179] = {260, 6, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI30_RTI_CLK"},
-       [2180] = {260, 7, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI30_RTI_CLK"},
-       [2181] = {260, 8, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI30_RTI_CLK"},
-       [2182] = {260, 9, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI30_RTI_CLK"},
-       [2183] = {261, 1, "DEV_RTI31_RTI_CLK", "Input muxed clock"},
-       [2184] = {261, 2, "DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI31_RTI_CLK"},
-       [2185] = {261, 3, "DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI31_RTI_CLK"},
-       [2186] = {261, 4, "DEV_RTI31_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI31_RTI_CLK"},
-       [2187] = {261, 5, "DEV_RTI31_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI31_RTI_CLK"},
-       [2188] = {261, 6, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI31_RTI_CLK"},
-       [2189] = {261, 7, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI31_RTI_CLK"},
-       [2190] = {261, 8, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI31_RTI_CLK"},
-       [2191] = {261, 9, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI31_RTI_CLK"},
-       [2192] = {264, 1, "DEV_SA2_UL0_PKA_IN_CLK", "Input clock"},
-       [2193] = {264, 2, "DEV_SA2_UL0_X1_CLK", "Input clock"},
-       [2194] = {297, 1, "DEV_SERDES_10G0_CLK", "Input clock"},
-       [2195] = {297, 2, "DEV_SERDES_10G0_IP3_LN2_TXCLK", "Input clock"},
-       [2196] = {297, 3, "DEV_SERDES_10G0_IP1_LN2_TXCLK", "Input clock"},
-       [2197] = {297, 4, "DEV_SERDES_10G0_IP1_LN0_TXCLK", "Input clock"},
-       [2198] = {297, 5, "DEV_SERDES_10G0_IP3_LN1_TXCLK", "Input clock"},
-       [2199] = {297, 6, "DEV_SERDES_10G0_IP3_LN3_TXCLK", "Input clock"},
-       [2200] = {297, 7, "DEV_SERDES_10G0_IP3_LN0_TXCLK", "Input clock"},
-       [2201] = {297, 8, "DEV_SERDES_10G0_IP1_LN1_TXCLK", "Input clock"},
-       [2202] = {297, 9, "DEV_SERDES_10G0_CORE_REF_CLK", "Input muxed clock"},
-       [2203] = {297, 10, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
-       [2204] = {297, 11, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
-       [2205] = {297, 12, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
-       [2206] = {297, 13, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
-       [2207] = {297, 14, "DEV_SERDES_10G0_IP1_LN1_REFCLK", "Output clock"},
-       [2208] = {297, 15, "DEV_SERDES_10G0_IP1_LN2_RXCLK", "Output clock"},
-       [2209] = {297, 16, "DEV_SERDES_10G0_IP3_LN1_TXFCLK", "Output clock"},
-       [2210] = {297, 17, "DEV_SERDES_10G0_IP1_LN0_RXFCLK", "Output clock"},
-       [2211] = {297, 18, "DEV_SERDES_10G0_IP1_LN3_RXCLK", "Output clock"},
-       [2212] = {297, 19, "DEV_SERDES_10G0_IP3_LN3_RXCLK", "Output clock"},
-       [2213] = {297, 20, "DEV_SERDES_10G0_IP3_LN1_TXMCLK", "Output clock"},
-       [2214] = {297, 21, "DEV_SERDES_10G0_IP3_LN3_RXFCLK", "Output clock"},
-       [2215] = {297, 22, "DEV_SERDES_10G0_IP3_LN3_REFCLK", "Output clock"},
-       [2216] = {297, 23, "DEV_SERDES_10G0_IP3_LN2_RXCLK", "Output clock"},
-       [2217] = {297, 24, "DEV_SERDES_10G0_IP1_LN0_TXFCLK", "Output clock"},
-       [2218] = {297, 25, "DEV_SERDES_10G0_IP3_LN3_TXMCLK", "Output clock"},
-       [2219] = {297, 26, "DEV_SERDES_10G0_IP3_LN1_RXFCLK", "Output clock"},
-       [2220] = {297, 27, "DEV_SERDES_10G0_IP3_LN0_RXFCLK", "Output clock"},
-       [2221] = {297, 28, "DEV_SERDES_10G0_IP1_LN1_TXMCLK", "Output clock"},
-       [2222] = {297, 29, "DEV_SERDES_10G0_IP1_LN1_RXFCLK", "Output clock"},
-       [2223] = {297, 30, "DEV_SERDES_10G0_IP3_LN3_TXFCLK", "Output clock"},
-       [2224] = {297, 31, "DEV_SERDES_10G0_IP1_LN3_TXFCLK", "Output clock"},
-       [2225] = {297, 32, "DEV_SERDES_10G0_IP1_LN3_TXMCLK", "Output clock"},
-       [2226] = {297, 33, "DEV_SERDES_10G0_IP3_LN1_REFCLK", "Output clock"},
-       [2227] = {297, 34, "DEV_SERDES_10G0_IP3_LN0_REFCLK", "Output clock"},
-       [2228] = {297, 35, "DEV_SERDES_10G0_IP1_LN3_REFCLK", "Output clock"},
-       [2229] = {297, 36, "DEV_SERDES_10G0_IP3_LN0_RXCLK", "Output clock"},
-       [2230] = {297, 37, "DEV_SERDES_10G0_IP3_LN2_REFCLK", "Output clock"},
-       [2231] = {297, 38, "DEV_SERDES_10G0_IP1_LN0_RXCLK", "Output clock"},
-       [2232] = {297, 39, "DEV_SERDES_10G0_IP1_LN0_REFCLK", "Output clock"},
-       [2233] = {297, 40, "DEV_SERDES_10G0_IP1_LN2_RXFCLK", "Output clock"},
-       [2234] = {297, 41, "DEV_SERDES_10G0_IP1_LN1_TXFCLK", "Output clock"},
-       [2235] = {297, 42, "DEV_SERDES_10G0_IP3_LN0_TXFCLK", "Output clock"},
-       [2236] = {297, 43, "DEV_SERDES_10G0_REF_OUT_CLK", "Output clock"},
-       [2237] = {297, 44, "DEV_SERDES_10G0_IP3_LN1_RXCLK", "Output clock"},
-       [2238] = {297, 45, "DEV_SERDES_10G0_IP1_LN2_TXFCLK", "Output clock"},
-       [2239] = {297, 46, "DEV_SERDES_10G0_IP1_LN0_TXMCLK", "Output clock"},
-       [2240] = {297, 47, "DEV_SERDES_10G0_IP3_LN2_RXFCLK", "Output clock"},
-       [2241] = {297, 48, "DEV_SERDES_10G0_IP1_LN2_TXMCLK", "Output clock"},
-       [2242] = {297, 49, "DEV_SERDES_10G0_IP3_LN2_TXMCLK", "Output clock"},
-       [2243] = {297, 50, "DEV_SERDES_10G0_IP1_LN2_REFCLK", "Output clock"},
-       [2244] = {297, 51, "DEV_SERDES_10G0_IP3_LN2_TXFCLK", "Output clock"},
-       [2245] = {297, 52, "DEV_SERDES_10G0_IP3_LN0_TXMCLK", "Output clock"},
-       [2246] = {297, 53, "DEV_SERDES_10G0_IP1_LN3_RXFCLK", "Output clock"},
-       [2247] = {297, 54, "DEV_SERDES_10G0_IP1_LN1_RXCLK", "Output clock"},
-       [2248] = {292, 1, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"},
-       [2249] = {292, 2, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"},
-       [2250] = {292, 3, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"},
-       [2251] = {292, 4, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"},
-       [2252] = {292, 5, "DEV_SERDES_16G0_CLK", "Input clock"},
-       [2253] = {292, 6, "DEV_SERDES_16G0_IP1_LN0_TXCLK", "Input clock"},
-       [2254] = {292, 7, "DEV_SERDES_16G0_IP2_LN1_TXCLK", "Input clock"},
-       [2255] = {292, 8, "DEV_SERDES_16G0_IP3_LN1_TXCLK", "Input clock"},
-       [2256] = {292, 9, "DEV_SERDES_16G0_IP2_LN0_TXCLK", "Input clock"},
-       [2257] = {292, 10, "DEV_SERDES_16G0_IP1_LN1_TXCLK", "Input clock"},
-       [2258] = {292, 11, "DEV_SERDES_16G0_CORE_REF_CLK", "Input muxed clock"},
-       [2259] = {292, 12, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"},
-       [2260] = {292, 13, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"},
-       [2261] = {292, 14, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"},
-       [2262] = {292, 15, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"},
-       [2263] = {292, 16, "DEV_SERDES_16G0_IP2_LN0_TXFCLK", "Output clock"},
-       [2264] = {292, 17, "DEV_SERDES_16G0_IP1_LN1_REFCLK", "Output clock"},
-       [2265] = {292, 18, "DEV_SERDES_16G0_IP3_LN1_TXMCLK", "Output clock"},
-       [2266] = {292, 19, "DEV_SERDES_16G0_IP3_LN1_TXFCLK", "Output clock"},
-       [2267] = {292, 20, "DEV_SERDES_16G0_IP1_LN0_RXFCLK", "Output clock"},
-       [2268] = {292, 21, "DEV_SERDES_16G0_IP2_LN1_REFCLK", "Output clock"},
-       [2269] = {292, 22, "DEV_SERDES_16G0_IP2_LN1_TXFCLK", "Output clock"},
-       [2270] = {292, 24, "DEV_SERDES_16G0_IP1_LN0_TXFCLK", "Output clock"},
-       [2271] = {292, 25, "DEV_SERDES_16G0_IP3_LN1_RXFCLK", "Output clock"},
-       [2272] = {292, 26, "DEV_SERDES_16G0_IP1_LN1_TXMCLK", "Output clock"},
-       [2273] = {292, 27, "DEV_SERDES_16G0_IP1_LN1_RXFCLK", "Output clock"},
-       [2274] = {292, 28, "DEV_SERDES_16G0_IP3_LN1_RXCLK", "Output clock"},
-       [2275] = {292, 29, "DEV_SERDES_16G0_IP3_LN1_REFCLK", "Output clock"},
-       [2276] = {292, 30, "DEV_SERDES_16G0_IP2_LN1_RXCLK", "Output clock"},
-       [2277] = {292, 31, "DEV_SERDES_16G0_IP2_LN0_RXFCLK", "Output clock"},
-       [2278] = {292, 32, "DEV_SERDES_16G0_IP1_LN0_RXCLK", "Output clock"},
-       [2279] = {292, 33, "DEV_SERDES_16G0_REF_OUT_CLK", "Output clock"},
-       [2280] = {292, 34, "DEV_SERDES_16G0_REF1_OUT_CLK", "Output clock"},
-       [2281] = {292, 35, "DEV_SERDES_16G0_IP1_LN0_REFCLK", "Output clock"},
-       [2282] = {292, 36, "DEV_SERDES_16G0_IP1_LN0_TXMCLK", "Output clock"},
-       [2283] = {292, 37, "DEV_SERDES_16G0_IP2_LN1_RXFCLK", "Output clock"},
-       [2284] = {292, 38, "DEV_SERDES_16G0_IP2_LN1_TXMCLK", "Output clock"},
-       [2285] = {292, 39, "DEV_SERDES_16G0_IP2_LN0_REFCLK", "Output clock"},
-       [2286] = {292, 40, "DEV_SERDES_16G0_IP2_LN0_TXMCLK", "Output clock"},
-       [2287] = {292, 41, "DEV_SERDES_16G0_IP1_LN1_TXFCLK", "Output clock"},
-       [2288] = {292, 42, "DEV_SERDES_16G0_IP2_LN0_RXCLK", "Output clock"},
-       [2289] = {292, 43, "DEV_SERDES_16G0_IP1_LN1_RXCLK", "Output clock"},
-       [2290] = {292, 49, "DEV_SERDES_16G0_CMN_REFCLK1_M_0", "Input clock"},
-       [2291] = {292, 57, "DEV_SERDES_16G0_CMN_REFCLK1_P_0", "Input clock"},
-       [2292] = {293, 1, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"},
-       [2293] = {293, 2, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"},
-       [2294] = {293, 3, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"},
-       [2295] = {293, 4, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"},
-       [2296] = {293, 5, "DEV_SERDES_16G1_CLK", "Input clock"},
-       [2297] = {293, 6, "DEV_SERDES_16G1_IP1_LN0_TXCLK", "Input clock"},
-       [2298] = {293, 7, "DEV_SERDES_16G1_IP2_LN1_TXCLK", "Input clock"},
-       [2299] = {293, 8, "DEV_SERDES_16G1_IP4_LN1_TXCLK", "Input clock"},
-       [2300] = {293, 9, "DEV_SERDES_16G1_IP4_LN0_TXCLK", "Input clock"},
-       [2301] = {293, 10, "DEV_SERDES_16G1_IP3_LN1_TXCLK", "Input clock"},
-       [2302] = {293, 11, "DEV_SERDES_16G1_IP2_LN0_TXCLK", "Input clock"},
-       [2303] = {293, 12, "DEV_SERDES_16G1_IP1_LN1_TXCLK", "Input clock"},
-       [2304] = {293, 13, "DEV_SERDES_16G1_CORE_REF_CLK", "Input muxed clock"},
-       [2305] = {293, 14, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"},
-       [2306] = {293, 15, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"},
-       [2307] = {293, 16, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"},
-       [2308] = {293, 17, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"},
-       [2309] = {293, 18, "DEV_SERDES_16G1_IP2_LN0_TXFCLK", "Output clock"},
-       [2310] = {293, 19, "DEV_SERDES_16G1_IP1_LN1_REFCLK", "Output clock"},
-       [2311] = {293, 20, "DEV_SERDES_16G1_IP4_LN1_RXFCLK", "Output clock"},
-       [2312] = {293, 21, "DEV_SERDES_16G1_IP3_LN1_TXMCLK", "Output clock"},
-       [2313] = {293, 22, "DEV_SERDES_16G1_IP3_LN1_TXFCLK", "Output clock"},
-       [2314] = {293, 23, "DEV_SERDES_16G1_IP1_LN0_RXFCLK", "Output clock"},
-       [2315] = {293, 24, "DEV_SERDES_16G1_IP2_LN1_REFCLK", "Output clock"},
-       [2316] = {293, 25, "DEV_SERDES_16G1_IP2_LN1_TXFCLK", "Output clock"},
-       [2317] = {293, 27, "DEV_SERDES_16G1_IP1_LN0_TXFCLK", "Output clock"},
-       [2318] = {293, 28, "DEV_SERDES_16G1_IP3_LN1_RXFCLK", "Output clock"},
-       [2319] = {293, 29, "DEV_SERDES_16G1_IP1_LN1_TXMCLK", "Output clock"},
-       [2320] = {293, 30, "DEV_SERDES_16G1_IP1_LN1_RXFCLK", "Output clock"},
-       [2321] = {293, 31, "DEV_SERDES_16G1_IP4_LN1_REFCLK", "Output clock"},
-       [2322] = {293, 32, "DEV_SERDES_16G1_IP3_LN1_RXCLK", "Output clock"},
-       [2323] = {293, 33, "DEV_SERDES_16G1_IP4_LN1_TXMCLK", "Output clock"},
-       [2324] = {293, 34, "DEV_SERDES_16G1_IP3_LN1_REFCLK", "Output clock"},
-       [2325] = {293, 35, "DEV_SERDES_16G1_IP4_LN0_REFCLK", "Output clock"},
-       [2326] = {293, 36, "DEV_SERDES_16G1_IP2_LN1_RXCLK", "Output clock"},
-       [2327] = {293, 37, "DEV_SERDES_16G1_IP2_LN0_RXFCLK", "Output clock"},
-       [2328] = {293, 38, "DEV_SERDES_16G1_IP1_LN0_RXCLK", "Output clock"},
-       [2329] = {293, 39, "DEV_SERDES_16G1_REF_OUT_CLK", "Output clock"},
-       [2330] = {293, 40, "DEV_SERDES_16G1_REF1_OUT_CLK", "Output clock"},
-       [2331] = {293, 41, "DEV_SERDES_16G1_IP4_LN1_RXCLK", "Output clock"},
-       [2332] = {293, 42, "DEV_SERDES_16G1_IP1_LN0_REFCLK", "Output clock"},
-       [2333] = {293, 43, "DEV_SERDES_16G1_IP1_LN0_TXMCLK", "Output clock"},
-       [2334] = {293, 44, "DEV_SERDES_16G1_IP4_LN0_TXFCLK", "Output clock"},
-       [2335] = {293, 45, "DEV_SERDES_16G1_IP4_LN0_RXCLK", "Output clock"},
-       [2336] = {293, 46, "DEV_SERDES_16G1_IP2_LN1_RXFCLK", "Output clock"},
-       [2337] = {293, 47, "DEV_SERDES_16G1_IP2_LN1_TXMCLK", "Output clock"},
-       [2338] = {293, 48, "DEV_SERDES_16G1_IP4_LN0_RXFCLK", "Output clock"},
-       [2339] = {293, 49, "DEV_SERDES_16G1_IP2_LN0_REFCLK", "Output clock"},
-       [2340] = {293, 50, "DEV_SERDES_16G1_IP2_LN0_TXMCLK", "Output clock"},
-       [2341] = {293, 51, "DEV_SERDES_16G1_IP1_LN1_TXFCLK", "Output clock"},
-       [2342] = {293, 52, "DEV_SERDES_16G1_IP2_LN0_RXCLK", "Output clock"},
-       [2343] = {293, 53, "DEV_SERDES_16G1_IP4_LN0_TXMCLK", "Output clock"},
-       [2344] = {293, 54, "DEV_SERDES_16G1_IP1_LN1_RXCLK", "Output clock"},
-       [2345] = {293, 55, "DEV_SERDES_16G1_IP4_LN1_TXFCLK", "Output clock"},
-       [2346] = {293, 60, "DEV_SERDES_16G1_CMN_REFCLK1_M_0", "Input clock"},
-       [2347] = {293, 67, "DEV_SERDES_16G1_CMN_REFCLK1_P_0", "Input clock"},
-       [2348] = {294, 1, "DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK"},
-       [2349] = {294, 2, "DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK"},
-       [2350] = {294, 3, "DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK"},
-       [2351] = {294, 4, "DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK"},
-       [2352] = {294, 5, "DEV_SERDES_16G2_CLK", "Input clock"},
-       [2353] = {294, 6, "DEV_SERDES_16G2_IP2_LN1_TXCLK", "Input clock"},
-       [2354] = {294, 7, "DEV_SERDES_16G2_IP4_LN1_TXCLK", "Input clock"},
-       [2355] = {294, 8, "DEV_SERDES_16G2_IP4_LN0_TXCLK", "Input clock"},
-       [2356] = {294, 9, "DEV_SERDES_16G2_IP3_LN1_TXCLK", "Input clock"},
-       [2357] = {294, 10, "DEV_SERDES_16G2_IP2_LN0_TXCLK", "Input clock"},
-       [2358] = {294, 11, "DEV_SERDES_16G2_CORE_REF_CLK", "Input muxed clock"},
-       [2359] = {294, 12, "DEV_SERDES_16G2_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK"},
-       [2360] = {294, 13, "DEV_SERDES_16G2_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK"},
-       [2361] = {294, 14, "DEV_SERDES_16G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK"},
-       [2362] = {294, 15, "DEV_SERDES_16G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK"},
-       [2363] = {294, 16, "DEV_SERDES_16G2_IP2_LN0_TXFCLK", "Output clock"},
-       [2364] = {294, 17, "DEV_SERDES_16G2_IP4_LN1_RXFCLK", "Output clock"},
-       [2365] = {294, 18, "DEV_SERDES_16G2_IP3_LN1_TXMCLK", "Output clock"},
-       [2366] = {294, 19, "DEV_SERDES_16G2_IP3_LN1_TXFCLK", "Output clock"},
-       [2367] = {294, 20, "DEV_SERDES_16G2_IP2_LN1_REFCLK", "Output clock"},
-       [2368] = {294, 21, "DEV_SERDES_16G2_IP2_LN1_TXFCLK", "Output clock"},
-       [2369] = {294, 23, "DEV_SERDES_16G2_IP3_LN1_RXFCLK", "Output clock"},
-       [2370] = {294, 24, "DEV_SERDES_16G2_IP4_LN1_REFCLK", "Output clock"},
-       [2371] = {294, 25, "DEV_SERDES_16G2_IP3_LN1_RXCLK", "Output clock"},
-       [2372] = {294, 26, "DEV_SERDES_16G2_IP4_LN1_TXMCLK", "Output clock"},
-       [2373] = {294, 27, "DEV_SERDES_16G2_IP3_LN1_REFCLK", "Output clock"},
-       [2374] = {294, 28, "DEV_SERDES_16G2_IP4_LN0_REFCLK", "Output clock"},
-       [2375] = {294, 29, "DEV_SERDES_16G2_IP2_LN1_RXCLK", "Output clock"},
-       [2376] = {294, 30, "DEV_SERDES_16G2_IP2_LN0_RXFCLK", "Output clock"},
-       [2377] = {294, 31, "DEV_SERDES_16G2_REF_OUT_CLK", "Output clock"},
-       [2378] = {294, 32, "DEV_SERDES_16G2_REF1_OUT_CLK", "Output clock"},
-       [2379] = {294, 33, "DEV_SERDES_16G2_IP4_LN1_RXCLK", "Output clock"},
-       [2380] = {294, 34, "DEV_SERDES_16G2_IP4_LN0_TXFCLK", "Output clock"},
-       [2381] = {294, 35, "DEV_SERDES_16G2_IP4_LN0_RXCLK", "Output clock"},
-       [2382] = {294, 36, "DEV_SERDES_16G2_IP2_LN1_RXFCLK", "Output clock"},
-       [2383] = {294, 37, "DEV_SERDES_16G2_IP2_LN1_TXMCLK", "Output clock"},
-       [2384] = {294, 38, "DEV_SERDES_16G2_IP4_LN0_RXFCLK", "Output clock"},
-       [2385] = {294, 39, "DEV_SERDES_16G2_IP2_LN0_REFCLK", "Output clock"},
-       [2386] = {294, 40, "DEV_SERDES_16G2_IP2_LN0_TXMCLK", "Output clock"},
-       [2387] = {294, 41, "DEV_SERDES_16G2_IP2_LN0_RXCLK", "Output clock"},
-       [2388] = {294, 42, "DEV_SERDES_16G2_IP4_LN0_TXMCLK", "Output clock"},
-       [2389] = {294, 43, "DEV_SERDES_16G2_IP4_LN1_TXFCLK", "Output clock"},
-       [2390] = {294, 51, "DEV_SERDES_16G2_CMN_REFCLK1_M_0", "Input clock"},
-       [2391] = {294, 61, "DEV_SERDES_16G2_CMN_REFCLK1_P_0", "Input clock"},
-       [2392] = {295, 1, "DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK"},
-       [2393] = {295, 2, "DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK"},
-       [2394] = {295, 3, "DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK"},
-       [2395] = {295, 4, "DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK"},
-       [2396] = {295, 5, "DEV_SERDES_16G3_CLK", "Input clock"},
-       [2397] = {295, 6, "DEV_SERDES_16G3_IP2_LN1_TXCLK", "Input clock"},
-       [2398] = {295, 7, "DEV_SERDES_16G3_IP3_LN1_TXCLK", "Input clock"},
-       [2399] = {295, 8, "DEV_SERDES_16G3_IP2_LN0_TXCLK", "Input clock"},
-       [2400] = {295, 9, "DEV_SERDES_16G3_CORE_REF_CLK", "Input muxed clock"},
-       [2401] = {295, 10, "DEV_SERDES_16G3_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK"},
-       [2402] = {295, 11, "DEV_SERDES_16G3_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK"},
-       [2403] = {295, 12, "DEV_SERDES_16G3_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK"},
-       [2404] = {295, 13, "DEV_SERDES_16G3_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK"},
-       [2405] = {295, 14, "DEV_SERDES_16G3_IP2_LN0_TXFCLK", "Output clock"},
-       [2406] = {295, 15, "DEV_SERDES_16G3_IP3_LN1_TXMCLK", "Output clock"},
-       [2407] = {295, 16, "DEV_SERDES_16G3_IP3_LN1_TXFCLK", "Output clock"},
-       [2408] = {295, 17, "DEV_SERDES_16G3_IP2_LN1_REFCLK", "Output clock"},
-       [2409] = {295, 18, "DEV_SERDES_16G3_IP2_LN1_TXFCLK", "Output clock"},
-       [2410] = {295, 20, "DEV_SERDES_16G3_IP3_LN1_RXFCLK", "Output clock"},
-       [2411] = {295, 21, "DEV_SERDES_16G3_IP3_LN1_RXCLK", "Output clock"},
-       [2412] = {295, 22, "DEV_SERDES_16G3_IP3_LN1_REFCLK", "Output clock"},
-       [2413] = {295, 23, "DEV_SERDES_16G3_IP2_LN1_RXCLK", "Output clock"},
-       [2414] = {295, 24, "DEV_SERDES_16G3_IP2_LN0_RXFCLK", "Output clock"},
-       [2415] = {295, 25, "DEV_SERDES_16G3_REF_OUT_CLK", "Output clock"},
-       [2416] = {295, 26, "DEV_SERDES_16G3_REF1_OUT_CLK", "Output clock"},
-       [2417] = {295, 27, "DEV_SERDES_16G3_IP2_LN1_RXFCLK", "Output clock"},
-       [2418] = {295, 28, "DEV_SERDES_16G3_IP2_LN1_TXMCLK", "Output clock"},
-       [2419] = {295, 29, "DEV_SERDES_16G3_IP2_LN0_REFCLK", "Output clock"},
-       [2420] = {295, 30, "DEV_SERDES_16G3_IP2_LN0_TXMCLK", "Output clock"},
-       [2421] = {295, 31, "DEV_SERDES_16G3_IP2_LN0_RXCLK", "Output clock"},
-       [2422] = {295, 40, "DEV_SERDES_16G3_CMN_REFCLK1_M_0", "Input clock"},
-       [2423] = {295, 51, "DEV_SERDES_16G3_CMN_REFCLK1_P_0", "Input clock"},
-       [2424] = {29, 1, "DEV_STM0_CORE_CLK", "Input clock"},
-       [2425] = {29, 2, "DEV_STM0_ATB_CLK", "Input clock"},
-       [2426] = {49, 1, "DEV_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2427] = {49, 2, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
-       [2428] = {49, 3, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
-       [2429] = {49, 4, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
-       [2430] = {49, 5, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
-       [2431] = {49, 6, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
-       [2432] = {49, 7, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
-       [2433] = {49, 8, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
-       [2434] = {49, 9, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
-       [2435] = {49, 10, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
-       [2436] = {49, 11, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
-       [2437] = {49, 12, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
-       [2438] = {49, 13, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
-       [2439] = {49, 14, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
-       [2440] = {49, 15, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
-       [2441] = {49, 16, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
-       [2442] = {49, 17, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
-       [2443] = {49, 18, "DEV_TIMER0_TIMER_PWM_0", "Output clock"},
-       [2444] = {50, 1, "DEV_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2445] = {50, 2, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
-       [2446] = {50, 3, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM_0", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
-       [2447] = {60, 1, "DEV_TIMER10_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2448] = {60, 2, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
-       [2449] = {60, 3, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
-       [2450] = {60, 4, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
-       [2451] = {60, 5, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
-       [2452] = {60, 6, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
-       [2453] = {60, 7, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
-       [2454] = {60, 8, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
-       [2455] = {60, 9, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
-       [2456] = {60, 10, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
-       [2457] = {60, 11, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
-       [2458] = {60, 12, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
-       [2459] = {60, 13, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
-       [2460] = {60, 14, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
-       [2461] = {60, 15, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
-       [2462] = {60, 16, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
-       [2463] = {60, 17, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
-       [2464] = {60, 18, "DEV_TIMER10_TIMER_PWM_0", "Output clock"},
-       [2465] = {62, 1, "DEV_TIMER11_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2466] = {62, 2, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
-       [2467] = {62, 3, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM_0", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
-       [2468] = {63, 1, "DEV_TIMER12_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2469] = {63, 2, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
-       [2470] = {63, 3, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
-       [2471] = {63, 4, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
-       [2472] = {63, 5, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
-       [2473] = {63, 6, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
-       [2474] = {63, 7, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
-       [2475] = {63, 8, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
-       [2476] = {63, 9, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
-       [2477] = {63, 10, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
-       [2478] = {63, 11, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
-       [2479] = {63, 12, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
-       [2480] = {63, 13, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
-       [2481] = {63, 14, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
-       [2482] = {63, 15, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
-       [2483] = {63, 16, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
-       [2484] = {63, 17, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
-       [2485] = {63, 18, "DEV_TIMER12_TIMER_PWM_0", "Output clock"},
-       [2486] = {64, 1, "DEV_TIMER13_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2487] = {64, 2, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"},
-       [2488] = {64, 3, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM_0", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"},
-       [2489] = {65, 1, "DEV_TIMER14_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2490] = {65, 2, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
-       [2491] = {65, 3, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
-       [2492] = {65, 4, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
-       [2493] = {65, 5, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
-       [2494] = {65, 6, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
-       [2495] = {65, 7, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
-       [2496] = {65, 8, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
-       [2497] = {65, 9, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
-       [2498] = {65, 10, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
-       [2499] = {65, 11, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
-       [2500] = {65, 12, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
-       [2501] = {65, 13, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
-       [2502] = {65, 14, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
-       [2503] = {65, 15, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
-       [2504] = {65, 16, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
-       [2505] = {65, 17, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
-       [2506] = {65, 18, "DEV_TIMER14_TIMER_PWM_0", "Output clock"},
-       [2507] = {66, 1, "DEV_TIMER15_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2508] = {66, 2, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"},
-       [2509] = {66, 3, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM_0", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"},
-       [2510] = {67, 1, "DEV_TIMER16_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2511] = {67, 2, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
-       [2512] = {67, 3, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
-       [2513] = {67, 4, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
-       [2514] = {67, 5, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
-       [2515] = {67, 6, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
-       [2516] = {67, 7, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
-       [2517] = {67, 8, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
-       [2518] = {67, 9, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
-       [2519] = {67, 10, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
-       [2520] = {67, 11, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
-       [2521] = {67, 12, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
-       [2522] = {67, 13, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
-       [2523] = {67, 14, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
-       [2524] = {67, 15, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
-       [2525] = {67, 16, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
-       [2526] = {67, 17, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
-       [2527] = {67, 18, "DEV_TIMER16_TIMER_PWM_0", "Output clock"},
-       [2528] = {68, 1, "DEV_TIMER17_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2529] = {68, 2, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT17", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"},
-       [2530] = {68, 3, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM_0", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"},
-       [2531] = {69, 1, "DEV_TIMER18_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2532] = {69, 2, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
-       [2533] = {69, 3, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
-       [2534] = {69, 4, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
-       [2535] = {69, 5, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
-       [2536] = {69, 6, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
-       [2537] = {69, 7, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
-       [2538] = {69, 8, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
-       [2539] = {69, 9, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
-       [2540] = {69, 10, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
-       [2541] = {69, 11, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
-       [2542] = {69, 12, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
-       [2543] = {69, 13, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
-       [2544] = {69, 14, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
-       [2545] = {69, 15, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
-       [2546] = {69, 16, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
-       [2547] = {69, 17, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
-       [2548] = {69, 18, "DEV_TIMER18_TIMER_PWM_0", "Output clock"},
-       [2549] = {70, 1, "DEV_TIMER19_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2550] = {70, 2, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT19", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"},
-       [2551] = {70, 3, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM_0", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"},
-       [2552] = {51, 1, "DEV_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2553] = {51, 2, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
-       [2554] = {51, 3, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
-       [2555] = {51, 4, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
-       [2556] = {51, 5, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
-       [2557] = {51, 6, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
-       [2558] = {51, 7, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
-       [2559] = {51, 8, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
-       [2560] = {51, 9, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
-       [2561] = {51, 10, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
-       [2562] = {51, 11, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
-       [2563] = {51, 12, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
-       [2564] = {51, 13, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
-       [2565] = {51, 14, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
-       [2566] = {51, 15, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
-       [2567] = {51, 16, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
-       [2568] = {51, 17, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
-       [2569] = {51, 18, "DEV_TIMER2_TIMER_PWM_0", "Output clock"},
-       [2570] = {52, 1, "DEV_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2571] = {52, 2, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
-       [2572] = {52, 3, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM_0", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
-       [2573] = {53, 1, "DEV_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2574] = {53, 2, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
-       [2575] = {53, 3, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
-       [2576] = {53, 4, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
-       [2577] = {53, 5, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
-       [2578] = {53, 6, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
-       [2579] = {53, 7, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
-       [2580] = {53, 8, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
-       [2581] = {53, 9, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
-       [2582] = {53, 10, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
-       [2583] = {53, 11, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
-       [2584] = {53, 12, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
-       [2585] = {53, 13, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
-       [2586] = {53, 14, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
-       [2587] = {53, 15, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
-       [2588] = {53, 16, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
-       [2589] = {53, 17, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
-       [2590] = {53, 18, "DEV_TIMER4_TIMER_PWM_0", "Output clock"},
-       [2591] = {54, 1, "DEV_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2592] = {54, 2, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
-       [2593] = {54, 3, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM_0", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
-       [2594] = {55, 1, "DEV_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2595] = {55, 2, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
-       [2596] = {55, 3, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
-       [2597] = {55, 4, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
-       [2598] = {55, 5, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
-       [2599] = {55, 6, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
-       [2600] = {55, 7, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
-       [2601] = {55, 8, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
-       [2602] = {55, 9, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
-       [2603] = {55, 10, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
-       [2604] = {55, 11, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
-       [2605] = {55, 12, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
-       [2606] = {55, 13, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
-       [2607] = {55, 14, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
-       [2608] = {55, 15, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
-       [2609] = {55, 16, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
-       [2610] = {55, 17, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
-       [2611] = {55, 18, "DEV_TIMER6_TIMER_PWM_0", "Output clock"},
-       [2612] = {57, 1, "DEV_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2613] = {57, 2, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
-       [2614] = {57, 3, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM_0", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
-       [2615] = {58, 1, "DEV_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2616] = {58, 2, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
-       [2617] = {58, 3, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
-       [2618] = {58, 4, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
-       [2619] = {58, 5, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
-       [2620] = {58, 6, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
-       [2621] = {58, 7, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
-       [2622] = {58, 8, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
-       [2623] = {58, 9, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
-       [2624] = {58, 10, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
-       [2625] = {58, 11, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
-       [2626] = {58, 12, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
-       [2627] = {58, 13, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
-       [2628] = {58, 14, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
-       [2629] = {58, 15, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
-       [2630] = {58, 16, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
-       [2631] = {58, 17, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
-       [2632] = {58, 18, "DEV_TIMER8_TIMER_PWM_0", "Output clock"},
-       [2633] = {59, 1, "DEV_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"},
-       [2634] = {59, 2, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
-       [2635] = {59, 3, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM_0", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
-       [2636] = {146, 1, "DEV_UART0_VBUSP_CLK", "Input clock"},
-       [2637] = {278, 1, "DEV_UART1_VBUSP_CLK", "Input clock"},
-       [2638] = {279, 1, "DEV_UART2_VBUSP_CLK", "Input clock"},
-       [2639] = {280, 1, "DEV_UART3_VBUSP_CLK", "Input clock"},
-       [2640] = {281, 1, "DEV_UART4_VBUSP_CLK", "Input clock"},
-       [2641] = {282, 1, "DEV_UART5_VBUSP_CLK", "Input clock"},
-       [2642] = {283, 1, "DEV_UART6_VBUSP_CLK", "Input clock"},
-       [2643] = {284, 1, "DEV_UART7_VBUSP_CLK", "Input clock"},
-       [2644] = {285, 1, "DEV_UART8_VBUSP_CLK", "Input clock"},
-       [2645] = {286, 1, "DEV_UART9_VBUSP_CLK", "Input clock"},
-       [2646] = {277, 1, "DEV_UFS0_UFSHCI_MCLK_CLK", "Input muxed clock"},
-       [2647] = {277, 2, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"},
-       [2648] = {277, 3, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"},
-       [2649] = {277, 4, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"},
-       [2650] = {277, 5, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"},
-       [2651] = {277, 6, "DEV_UFS0_UFSHCI_MPHY_REFCLK_0", "Output clock"},
-       [2652] = {288, 1, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"},
-       [2653] = {288, 2, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"},
-       [2654] = {288, 3, "DEV_USB0_CLK_LPM_CLK", "Input clock"},
-       [2655] = {288, 4, "DEV_USB0_BUF_CLK", "Input clock"},
-       [2656] = {288, 5, "DEV_USB0_USB2_APB_PCLK_CLK", "Input clock"},
-       [2657] = {288, 6, "DEV_USB0_PIPE_RXCLK", "Input muxed clock"},
-       [2658] = {288, 7, "DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_RXCLK", "Parent input clock option to DEV_USB0_PIPE_RXCLK"},
-       [2659] = {288, 8, "DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_RXCLK", "Parent input clock option to DEV_USB0_PIPE_RXCLK"},
-       [2660] = {288, 9, "DEV_USB0_PIPE_TXMCLK", "Input muxed clock"},
-       [2661] = {288, 10, "DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_TXMCLK", "Parent input clock option to DEV_USB0_PIPE_TXMCLK"},
-       [2662] = {288, 11, "DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_TXMCLK", "Parent input clock option to DEV_USB0_PIPE_TXMCLK"},
-       [2663] = {288, 12, "DEV_USB0_PIPE_RXFCLK", "Input muxed clock"},
-       [2664] = {288, 13, "DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_RXFCLK", "Parent input clock option to DEV_USB0_PIPE_RXFCLK"},
-       [2665] = {288, 14, "DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_RXFCLK", "Parent input clock option to DEV_USB0_PIPE_RXFCLK"},
-       [2666] = {288, 15, "DEV_USB0_USB2_REFCLOCK_CLK", "Input muxed clock"},
-       [2667] = {288, 16, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"},
-       [2668] = {288, 17, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"},
-       [2669] = {288, 18, "DEV_USB0_PCLK_CLK", "Input clock"},
-       [2670] = {288, 19, "DEV_USB0_ACLK_CLK", "Input clock"},
-       [2671] = {288, 20, "DEV_USB0_PIPE_TXFCLK", "Input muxed clock"},
-       [2672] = {288, 21, "DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB0_PIPE_TXFCLK"},
-       [2673] = {288, 22, "DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB0_PIPE_TXFCLK"},
-       [2674] = {288, 23, "DEV_USB0_PIPE_TXCLK", "Output clock"},
-       [2675] = {289, 1, "DEV_USB1_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB1_PIPE_REFCLK"},
-       [2676] = {289, 2, "DEV_USB1_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB1_PIPE_REFCLK"},
-       [2677] = {289, 3, "DEV_USB1_CLK_LPM_CLK", "Input clock"},
-       [2678] = {289, 4, "DEV_USB1_BUF_CLK", "Input clock"},
-       [2679] = {289, 5, "DEV_USB1_USB2_APB_PCLK_CLK", "Input clock"},
-       [2680] = {289, 6, "DEV_USB1_PIPE_RXCLK", "Input muxed clock"},
-       [2681] = {289, 7, "DEV_USB1_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_RXCLK", "Parent input clock option to DEV_USB1_PIPE_RXCLK"},
-       [2682] = {289, 8, "DEV_USB1_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_RXCLK", "Parent input clock option to DEV_USB1_PIPE_RXCLK"},
-       [2683] = {289, 9, "DEV_USB1_PIPE_TXMCLK", "Input muxed clock"},
-       [2684] = {289, 10, "DEV_USB1_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_TXMCLK", "Parent input clock option to DEV_USB1_PIPE_TXMCLK"},
-       [2685] = {289, 11, "DEV_USB1_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_TXMCLK", "Parent input clock option to DEV_USB1_PIPE_TXMCLK"},
-       [2686] = {289, 12, "DEV_USB1_PIPE_RXFCLK", "Input muxed clock"},
-       [2687] = {289, 13, "DEV_USB1_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_RXFCLK", "Parent input clock option to DEV_USB1_PIPE_RXFCLK"},
-       [2688] = {289, 14, "DEV_USB1_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_RXFCLK", "Parent input clock option to DEV_USB1_PIPE_RXFCLK"},
-       [2689] = {289, 15, "DEV_USB1_USB2_REFCLOCK_CLK", "Input muxed clock"},
-       [2690] = {289, 16, "DEV_USB1_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK"},
-       [2691] = {289, 17, "DEV_USB1_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK"},
-       [2692] = {289, 18, "DEV_USB1_PCLK_CLK", "Input clock"},
-       [2693] = {289, 19, "DEV_USB1_ACLK_CLK", "Input clock"},
-       [2694] = {289, 20, "DEV_USB1_PIPE_TXFCLK", "Input muxed clock"},
-       [2695] = {289, 21, "DEV_USB1_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB1_PIPE_TXFCLK"},
-       [2696] = {289, 22, "DEV_USB1_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB1_PIPE_TXFCLK"},
-       [2697] = {289, 23, "DEV_USB1_PIPE_TXCLK", "Output clock"},
-       [2698] = {291, 1, "DEV_VPFE0_VPFE_CLK", "Input clock"},
-       [2699] = {197, 1, "DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK"},
-       [2700] = {197, 2, "DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK"},
-       [2701] = {197, 3, "DEV_WKUP_I2C0_PISCL_0", "Input clock"},
-       [2702] = {197, 4, "DEV_WKUP_I2C0_CLK", "Input clock"},
-       [2703] = {197, 5, "DEV_WKUP_I2C0_PORSCL_0", "Output clock"},
-       [2704] = {138, 1, "DEV_WKUP_PSC0_CLK", "Input clock"},
-       [2705] = {287, 1, "DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_OUT0", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"},
-       [2706] = {287, 2, "DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"},
-       [2707] = {287, 3, "DEV_WKUP_UART0_VBUSP_CLK", "Input clock"},
-       [2708] = {154, 1, "DEV_WKUP_VTM0_VBUSP_CLK", "Input clock"},
-       [2709] = {154, 2, "DEV_WKUP_VTM0_FIX_REF_CLK", "Input clock"},
+       [0] = {4, 0, "DEV_A72SS0_CLUSTER_CLK", "Input clock"},
+       [1] = {202, 0, "DEV_A72SS0_CORE0_PLL_CTRL_CLK", "Input clock"},
+       [2] = {202, 1, "DEV_A72SS0_CORE0_MSMC_CLK", "Input clock"},
+       [3] = {202, 2, "DEV_A72SS0_CORE0_ARM_CLK_CLK", "Input clock"},
+       [4] = {203, 0, "DEV_A72SS0_CORE1_ARM_CLK_CLK", "Input clock"},
+       [5] = {139, 0, "DEV_AASRC0_SYS_CLK", "Input clock"},
+       [6] = {139, 1, "DEV_AASRC0_VBUSP_CLK", "Input clock"},
+       [7] = {139, 2, "DEV_AASRC0_RX0_SYNC_0", "Input muxed clock"},
+       [8] = {139, 3, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [9] = {139, 4, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [10] = {139, 5, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [11] = {139, 6, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [12] = {139, 7, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [13] = {139, 8, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [14] = {139, 9, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [15] = {139, 10, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [16] = {139, 11, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [17] = {139, 12, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [18] = {139, 13, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [19] = {139, 14, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [20] = {139, 15, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [21] = {139, 16, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [22] = {139, 17, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [23] = {139, 18, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [24] = {139, 19, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [25] = {139, 20, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [26] = {139, 21, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [27] = {139, 22, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [28] = {139, 23, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [29] = {139, 24, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [30] = {139, 25, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [31] = {139, 26, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [32] = {139, 27, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [33] = {139, 28, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [34] = {139, 29, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [35] = {139, 30, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [36] = {139, 31, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [37] = {139, 32, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [38] = {139, 33, "DEV_AASRC0_RX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [39] = {139, 34, "DEV_AASRC0_RX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [40] = {139, 35, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [41] = {139, 36, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [42] = {139, 37, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [43] = {139, 38, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+       [44] = {139, 39, "DEV_AASRC0_RX1_SYNC_0", "Input muxed clock"},
+       [45] = {139, 40, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [46] = {139, 41, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [47] = {139, 42, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [48] = {139, 43, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [49] = {139, 44, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [50] = {139, 45, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [51] = {139, 46, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [52] = {139, 47, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [53] = {139, 48, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [54] = {139, 49, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [55] = {139, 50, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [56] = {139, 51, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [57] = {139, 52, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [58] = {139, 53, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [59] = {139, 54, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [60] = {139, 55, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [61] = {139, 56, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [62] = {139, 57, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [63] = {139, 58, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [64] = {139, 59, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [65] = {139, 60, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [66] = {139, 61, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [67] = {139, 62, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [68] = {139, 63, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [69] = {139, 64, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [70] = {139, 65, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [71] = {139, 66, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [72] = {139, 67, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [73] = {139, 68, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [74] = {139, 69, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [75] = {139, 70, "DEV_AASRC0_RX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [76] = {139, 71, "DEV_AASRC0_RX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [77] = {139, 72, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [78] = {139, 73, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [79] = {139, 74, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [80] = {139, 75, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+       [81] = {139, 76, "DEV_AASRC0_RX2_SYNC_0", "Input muxed clock"},
+       [82] = {139, 77, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [83] = {139, 78, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [84] = {139, 79, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [85] = {139, 80, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [86] = {139, 81, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [87] = {139, 82, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [88] = {139, 83, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [89] = {139, 84, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [90] = {139, 85, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [91] = {139, 86, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [92] = {139, 87, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [93] = {139, 88, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [94] = {139, 89, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [95] = {139, 90, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [96] = {139, 91, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [97] = {139, 92, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [98] = {139, 93, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [99] = {139, 94, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [100] = {139, 95, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [101] = {139, 96, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [102] = {139, 97, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [103] = {139, 98, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [104] = {139, 99, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [105] = {139, 100, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [106] = {139, 101, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [107] = {139, 102, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [108] = {139, 103, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [109] = {139, 104, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [110] = {139, 105, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [111] = {139, 106, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [112] = {139, 107, "DEV_AASRC0_RX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [113] = {139, 108, "DEV_AASRC0_RX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [114] = {139, 109, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [115] = {139, 110, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [116] = {139, 111, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [117] = {139, 112, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+       [118] = {139, 113, "DEV_AASRC0_RX3_SYNC_0", "Input muxed clock"},
+       [119] = {139, 114, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [120] = {139, 115, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [121] = {139, 116, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [122] = {139, 117, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [123] = {139, 118, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [124] = {139, 119, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [125] = {139, 120, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [126] = {139, 121, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [127] = {139, 122, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [128] = {139, 123, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [129] = {139, 124, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [130] = {139, 125, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [131] = {139, 126, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [132] = {139, 127, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [133] = {139, 128, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [134] = {139, 129, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [135] = {139, 130, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [136] = {139, 131, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [137] = {139, 132, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [138] = {139, 133, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [139] = {139, 134, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [140] = {139, 135, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [141] = {139, 136, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [142] = {139, 137, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [143] = {139, 138, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [144] = {139, 139, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [145] = {139, 140, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [146] = {139, 141, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [147] = {139, 142, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [148] = {139, 143, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [149] = {139, 144, "DEV_AASRC0_RX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [150] = {139, 145, "DEV_AASRC0_RX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [151] = {139, 146, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [152] = {139, 147, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [153] = {139, 148, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [154] = {139, 149, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+       [155] = {139, 150, "DEV_AASRC0_TX0_SYNC_0", "Input muxed clock"},
+       [156] = {139, 151, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [157] = {139, 152, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [158] = {139, 153, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [159] = {139, 154, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [160] = {139, 155, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [161] = {139, 156, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [162] = {139, 157, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [163] = {139, 158, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [164] = {139, 159, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [165] = {139, 160, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [166] = {139, 161, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [167] = {139, 162, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [168] = {139, 163, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [169] = {139, 164, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [170] = {139, 165, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [171] = {139, 166, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [172] = {139, 167, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [173] = {139, 168, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [174] = {139, 169, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [175] = {139, 170, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [176] = {139, 171, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [177] = {139, 172, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [178] = {139, 173, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [179] = {139, 174, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [180] = {139, 175, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [181] = {139, 176, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [182] = {139, 177, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [183] = {139, 178, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [184] = {139, 179, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [185] = {139, 180, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [186] = {139, 181, "DEV_AASRC0_TX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [187] = {139, 182, "DEV_AASRC0_TX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [188] = {139, 183, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [189] = {139, 184, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [190] = {139, 185, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [191] = {139, 186, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+       [192] = {139, 187, "DEV_AASRC0_TX1_SYNC_0", "Input muxed clock"},
+       [193] = {139, 188, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [194] = {139, 189, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [195] = {139, 190, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [196] = {139, 191, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [197] = {139, 192, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [198] = {139, 193, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [199] = {139, 194, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [200] = {139, 195, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [201] = {139, 196, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [202] = {139, 197, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [203] = {139, 198, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [204] = {139, 199, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [205] = {139, 200, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [206] = {139, 201, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [207] = {139, 202, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [208] = {139, 203, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [209] = {139, 204, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [210] = {139, 205, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [211] = {139, 206, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [212] = {139, 207, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [213] = {139, 208, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [214] = {139, 209, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [215] = {139, 210, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [216] = {139, 211, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [217] = {139, 212, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [218] = {139, 213, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [219] = {139, 214, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [220] = {139, 215, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [221] = {139, 216, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [222] = {139, 217, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [223] = {139, 218, "DEV_AASRC0_TX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [224] = {139, 219, "DEV_AASRC0_TX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [225] = {139, 220, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [226] = {139, 221, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [227] = {139, 222, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [228] = {139, 223, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+       [229] = {139, 224, "DEV_AASRC0_TX2_SYNC_0", "Input muxed clock"},
+       [230] = {139, 225, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [231] = {139, 226, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [232] = {139, 227, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [233] = {139, 228, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [234] = {139, 229, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [235] = {139, 230, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [236] = {139, 231, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [237] = {139, 232, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [238] = {139, 233, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [239] = {139, 234, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [240] = {139, 235, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [241] = {139, 236, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [242] = {139, 237, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [243] = {139, 238, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [244] = {139, 239, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [245] = {139, 240, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [246] = {139, 241, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [247] = {139, 242, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [248] = {139, 243, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [249] = {139, 244, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [250] = {139, 245, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [251] = {139, 246, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [252] = {139, 247, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [253] = {139, 248, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [254] = {139, 249, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [255] = {139, 250, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [256] = {139, 251, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [257] = {139, 252, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [258] = {139, 253, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [259] = {139, 254, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [260] = {139, 255, "DEV_AASRC0_TX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [261] = {139, 256, "DEV_AASRC0_TX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [262] = {139, 257, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [263] = {139, 258, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [264] = {139, 259, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [265] = {139, 260, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+       [266] = {139, 261, "DEV_AASRC0_TX3_SYNC_0", "Input muxed clock"},
+       [267] = {139, 262, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [268] = {139, 263, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [269] = {139, 264, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [270] = {139, 265, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [271] = {139, 266, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [272] = {139, 267, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [273] = {139, 268, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [274] = {139, 269, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [275] = {139, 270, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [276] = {139, 271, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [277] = {139, 272, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [278] = {139, 273, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [279] = {139, 274, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [280] = {139, 275, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [281] = {139, 276, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [282] = {139, 277, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [283] = {139, 278, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [284] = {139, 279, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [285] = {139, 280, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [286] = {139, 281, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [287] = {139, 282, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [288] = {139, 283, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [289] = {139, 284, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [290] = {139, 285, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [291] = {139, 286, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [292] = {139, 287, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [293] = {139, 288, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [294] = {139, 289, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [295] = {139, 290, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [296] = {139, 291, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [297] = {139, 292, "DEV_AASRC0_TX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [298] = {139, 293, "DEV_AASRC0_TX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [299] = {139, 294, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [300] = {139, 295, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [301] = {139, 296, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [302] = {139, 297, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+       [303] = {2, 0, "DEV_ATL0_VBUS_CLK", "Input clock"},
+       [304] = {2, 1, "DEV_ATL0_ATL_CLK", "Input muxed clock"},
+       [305] = {2, 2, "DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT1_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+       [306] = {2, 3, "DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+       [307] = {2, 4, "DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT1_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+       [308] = {2, 5, "DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+       [309] = {2, 6, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+       [310] = {2, 7, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+       [311] = {2, 8, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1", "Output clock"},
+       [312] = {2, 9, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_0", "Output clock"},
+       [313] = {2, 10, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3", "Output clock"},
+       [314] = {2, 11, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2", "Output clock"},
+       [315] = {157, 0, "DEV_BOARD0_SPI0_CLK_IN", "Input clock"},
+       [316] = {157, 2, "DEV_BOARD0_SPI1_CLK_IN", "Input clock"},
+       [317] = {157, 4, "DEV_BOARD0_SPI2_CLK_IN", "Input clock"},
+       [318] = {157, 6, "DEV_BOARD0_SPI3_CLK_IN", "Input clock"},
+       [319] = {157, 8, "DEV_BOARD0_SPI5_CLK_IN", "Input clock"},
+       [320] = {157, 10, "DEV_BOARD0_SPI6_CLK_IN", "Input clock"},
+       [321] = {157, 12, "DEV_BOARD0_SPI7_CLK_IN", "Input clock"},
+       [322] = {157, 14, "DEV_BOARD0_MCU_SPI0_CLK_IN", "Input clock"},
+       [323] = {157, 16, "DEV_BOARD0_MCU_SPI1_CLK_IN", "Input clock"},
+       [324] = {157, 18, "DEV_BOARD0_MCU_OSPI0_CLK_IN", "Input clock"},
+       [325] = {157, 19, "DEV_BOARD0_MCU_OSPI0_LBCLKO_IN", "Input clock"},
+       [326] = {157, 20, "DEV_BOARD0_MCU_OSPI0_DQS_OUT", "Output clock"},
+       [327] = {157, 21, "DEV_BOARD0_MCU_OSPI1_CLK_IN", "Input clock"},
+       [328] = {157, 22, "DEV_BOARD0_MCU_OSPI1_LBCLKO_IN", "Input clock"},
+       [329] = {157, 23, "DEV_BOARD0_MCU_OSPI1_DQS_OUT", "Output clock"},
+       [330] = {157, 25, "DEV_BOARD0_I2C0_SCL_OUT", "Output clock"},
+       [331] = {157, 27, "DEV_BOARD0_I2C1_SCL_OUT", "Output clock"},
+       [332] = {157, 29, "DEV_BOARD0_I2C2_SCL_OUT", "Output clock"},
+       [333] = {157, 31, "DEV_BOARD0_I2C3_SCL_OUT", "Output clock"},
+       [334] = {157, 33, "DEV_BOARD0_I2C4_SCL_OUT", "Output clock"},
+       [335] = {157, 35, "DEV_BOARD0_I2C5_SCL_OUT", "Output clock"},
+       [336] = {157, 37, "DEV_BOARD0_I2C6_SCL_OUT", "Output clock"},
+       [337] = {157, 38, "DEV_BOARD0_MCU_I2C0_SCL_IN", "Input clock"},
+       [338] = {157, 39, "DEV_BOARD0_MCU_I2C0_SCL_OUT", "Output clock"},
+       [339] = {157, 41, "DEV_BOARD0_MCU_I2C1_SCL_OUT", "Output clock"},
+       [340] = {157, 42, "DEV_BOARD0_WKUP_I2C0_SCL_IN", "Input clock"},
+       [341] = {157, 43, "DEV_BOARD0_WKUP_I2C0_SCL_OUT", "Output clock"},
+       [342] = {157, 44, "DEV_BOARD0_I3C0_SCL_IN", "Input clock"},
+       [343] = {157, 45, "DEV_BOARD0_I3C0_SCL_OUT", "Output clock"},
+       [344] = {157, 46, "DEV_BOARD0_MCU_I3C0_SCL_IN", "Input clock"},
+       [345] = {157, 47, "DEV_BOARD0_MCU_I3C0_SCL_OUT", "Output clock"},
+       [346] = {157, 48, "DEV_BOARD0_MCU_I3C1_SCL_IN", "Input clock"},
+       [347] = {157, 49, "DEV_BOARD0_MCU_I3C1_SCL_OUT", "Output clock"},
+       [348] = {157, 50, "DEV_BOARD0_MCU_HYPERBUS0_CK_IN", "Input clock"},
+       [349] = {157, 51, "DEV_BOARD0_MCU_HYPERBUS0_CKN_IN", "Input clock"},
+       [350] = {157, 52, "DEV_BOARD0_DSI_TXCLKP_IN", "Input clock"},
+       [351] = {157, 53, "DEV_BOARD0_DSI_TXCLKN_IN", "Input clock"},
+       [352] = {157, 54, "DEV_BOARD0_PRG0_MDIO0_MDC_IN", "Input clock"},
+       [353] = {157, 55, "DEV_BOARD0_PRG0_RGMII1_TXC_IN", "Input clock"},
+       [354] = {157, 56, "DEV_BOARD0_PRG0_RGMII1_TXC_OUT", "Output clock"},
+       [355] = {157, 57, "DEV_BOARD0_PRG0_RGMII1_RXC_OUT", "Output clock"},
+       [356] = {157, 58, "DEV_BOARD0_PRG0_RGMII2_TXC_IN", "Input clock"},
+       [357] = {157, 59, "DEV_BOARD0_PRG0_RGMII2_TXC_OUT", "Output clock"},
+       [358] = {157, 60, "DEV_BOARD0_PRG0_RGMII2_RXC_OUT", "Output clock"},
+       [359] = {157, 61, "DEV_BOARD0_PRG1_MDIO0_MDC_IN", "Input clock"},
+       [360] = {157, 62, "DEV_BOARD0_PRG1_RGMII1_TXC_IN", "Input clock"},
+       [361] = {157, 63, "DEV_BOARD0_PRG1_RGMII1_TXC_OUT", "Output clock"},
+       [362] = {157, 64, "DEV_BOARD0_PRG1_RGMII1_RXC_OUT", "Output clock"},
+       [363] = {157, 65, "DEV_BOARD0_PRG1_RGMII2_TXC_IN", "Input clock"},
+       [364] = {157, 66, "DEV_BOARD0_PRG1_RGMII2_TXC_OUT", "Output clock"},
+       [365] = {157, 67, "DEV_BOARD0_PRG1_RGMII2_RXC_OUT", "Output clock"},
+       [366] = {157, 68, "DEV_BOARD0_MDIO0_MDC_IN", "Input clock"},
+       [367] = {157, 70, "DEV_BOARD0_RGMII3_RXC_OUT", "Output clock"},
+       [368] = {157, 72, "DEV_BOARD0_RGMII4_RXC_OUT", "Output clock"},
+       [369] = {157, 74, "DEV_BOARD0_RGMII5_RXC_OUT", "Output clock"},
+       [370] = {157, 76, "DEV_BOARD0_RGMII6_RXC_OUT", "Output clock"},
+       [371] = {157, 78, "DEV_BOARD0_RGMII7_RXC_OUT", "Output clock"},
+       [372] = {157, 80, "DEV_BOARD0_RGMII8_RXC_OUT", "Output clock"},
+       [373] = {157, 81, "DEV_BOARD0_RMII_REF_CLK_OUT", "Output clock"},
+       [374] = {157, 82, "DEV_BOARD0_CPTS0_RFT_CLK_OUT", "Output clock"},
+       [375] = {157, 83, "DEV_BOARD0_MCU_MDIO0_MDC_IN", "Input clock"},
+       [376] = {157, 84, "DEV_BOARD0_MCU_RGMII1_TXC_IN", "Input clock"},
+       [377] = {157, 85, "DEV_BOARD0_MCU_RGMII1_TXC_OUT", "Output clock"},
+       [378] = {157, 86, "DEV_BOARD0_MCU_RGMII1_RXC_OUT", "Output clock"},
+       [379] = {157, 87, "DEV_BOARD0_MCU_RMII1_REF_CLK_OUT", "Output clock"},
+       [380] = {157, 88, "DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT", "Output clock"},
+       [381] = {157, 89, "DEV_BOARD0_UFS0_REF_CLK_IN", "Input clock"},
+       [382] = {157, 91, "DEV_BOARD0_DDR0_CK0_IN", "Input clock"},
+       [383] = {157, 92, "DEV_BOARD0_DDR0_CK0_N_IN", "Input clock"},
+       [384] = {157, 99, "DEV_BOARD0_MMC0_CLK_IN", "Input clock"},
+       [385] = {157, 100, "DEV_BOARD0_MMC1_CLK_IN", "Input clock"},
+       [386] = {157, 101, "DEV_BOARD0_MMC2_CLK_IN", "Input clock"},
+       [387] = {157, 102, "DEV_BOARD0_GPMC0_CLK_IN", "Input clock"},
+       [388] = {157, 103, "DEV_BOARD0_GPMC0_CLK_OUT", "Output clock"},
+       [389] = {157, 104, "DEV_BOARD0_GPMC0_FCLK_MUX_IN", "Input clock"},
+       [390] = {157, 105, "DEV_BOARD0_MLB0_MLBCLK_OUT", "Output clock"},
+       [391] = {157, 106, "DEV_BOARD0_MLB0_MLBCP_OUT", "Output clock"},
+       [392] = {157, 108, "DEV_BOARD0_VPFE0_PCLK_OUT", "Output clock"},
+       [393] = {157, 109, "DEV_BOARD0_VOUT1_PCLK_IN", "Input clock"},
+       [394] = {157, 110, "DEV_BOARD0_VOUT1_EXTPCLKIN_OUT", "Output clock"},
+       [395] = {157, 111, "DEV_BOARD0_VOUT2_PCLK_IN", "Input clock"},
+       [396] = {157, 112, "DEV_BOARD0_VOUT2_EXTPCLKIN_OUT", "Output clock"},
+       [397] = {157, 113, "DEV_BOARD0_OBSCLK0_IN", "Input clock"},
+       [398] = {157, 114, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [399] = {157, 115, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [400] = {157, 116, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [401] = {157, 117, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [402] = {157, 118, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [403] = {157, 119, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_5_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [404] = {157, 120, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [405] = {157, 126, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [406] = {157, 127, "DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [407] = {157, 128, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [408] = {157, 129, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [409] = {157, 130, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [410] = {157, 131, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [411] = {157, 132, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [412] = {157, 133, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [413] = {157, 137, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [414] = {157, 138, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_24_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [415] = {157, 139, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [416] = {157, 140, "DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [417] = {157, 141, "DEV_BOARD0_OBSCLK0_IN_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [418] = {157, 142, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [419] = {157, 143, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [420] = {157, 144, "DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [421] = {157, 145, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [422] = {157, 146, "DEV_BOARD0_OBSCLK1_IN", "Input muxed clock"},
+       [423] = {157, 147, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_7_HSDIVOUT0_CLK3", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+       [424] = {157, 148, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK7", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+       [425] = {157, 149, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_13_HSDIVOUT0_CLK3", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+       [426] = {157, 152, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"},
+       [427] = {157, 153, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
+       [428] = {157, 154, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
+       [429] = {157, 169, "DEV_BOARD0_SYSCLKOUT0_IN", "Input clock"},
+       [430] = {157, 170, "DEV_BOARD0_MCU_SYSCLKOUT0_IN", "Input clock"},
+       [431] = {157, 171, "DEV_BOARD0_TRC_CLK_IN", "Input clock"},
+       [432] = {157, 172, "DEV_BOARD0_CLKOUT_IN", "Input muxed clock"},
+       [433] = {157, 173, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"},
+       [434] = {157, 174, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"},
+       [435] = {157, 175, "DEV_BOARD0_MCU_CLKOUT0_IN", "Input muxed clock"},
+       [436] = {157, 176, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK4", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"},
+       [437] = {157, 177, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK9", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"},
+       [438] = {157, 178, "DEV_BOARD0_LED_CLK_OUT", "Output clock"},
+       [439] = {157, 179, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"},
+       [440] = {157, 180, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"},
+       [441] = {157, 181, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"},
+       [442] = {157, 182, "DEV_BOARD0_TCK_OUT", "Output clock"},
+       [443] = {157, 185, "DEV_BOARD0_PCIE_REFCLK0P_OUT", "Output clock"},
+       [444] = {157, 186, "DEV_BOARD0_PCIE_REFCLK0N_OUT", "Output clock"},
+       [445] = {157, 191, "DEV_BOARD0_PCIE_REFCLK1P_OUT", "Output clock"},
+       [446] = {157, 192, "DEV_BOARD0_PCIE_REFCLK1N_OUT", "Output clock"},
+       [447] = {157, 197, "DEV_BOARD0_PCIE_REFCLK2P_OUT", "Output clock"},
+       [448] = {157, 198, "DEV_BOARD0_PCIE_REFCLK2N_OUT", "Output clock"},
+       [449] = {157, 201, "DEV_BOARD0_PCIE_REFCLK3P_OUT", "Output clock"},
+       [450] = {157, 202, "DEV_BOARD0_PCIE_REFCLK3N_OUT", "Output clock"},
+       [451] = {157, 217, "DEV_BOARD0_MCASP0_ACLKR_IN", "Input clock"},
+       [452] = {157, 218, "DEV_BOARD0_MCASP0_ACLKR_OUT", "Output clock"},
+       [453] = {157, 219, "DEV_BOARD0_MCASP0_AFSR_OUT", "Output clock"},
+       [454] = {157, 220, "DEV_BOARD0_MCASP0_ACLKX_IN", "Input clock"},
+       [455] = {157, 221, "DEV_BOARD0_MCASP0_ACLKX_OUT", "Output clock"},
+       [456] = {157, 222, "DEV_BOARD0_MCASP0_AFSX_OUT", "Output clock"},
+       [457] = {157, 223, "DEV_BOARD0_MCASP1_ACLKR_IN", "Input clock"},
+       [458] = {157, 224, "DEV_BOARD0_MCASP1_ACLKR_OUT", "Output clock"},
+       [459] = {157, 225, "DEV_BOARD0_MCASP1_AFSR_OUT", "Output clock"},
+       [460] = {157, 226, "DEV_BOARD0_MCASP1_ACLKX_IN", "Input clock"},
+       [461] = {157, 227, "DEV_BOARD0_MCASP1_ACLKX_OUT", "Output clock"},
+       [462] = {157, 228, "DEV_BOARD0_MCASP1_AFSX_OUT", "Output clock"},
+       [463] = {157, 229, "DEV_BOARD0_MCASP2_ACLKR_IN", "Input clock"},
+       [464] = {157, 230, "DEV_BOARD0_MCASP2_ACLKR_OUT", "Output clock"},
+       [465] = {157, 231, "DEV_BOARD0_MCASP2_AFSR_OUT", "Output clock"},
+       [466] = {157, 232, "DEV_BOARD0_MCASP2_ACLKX_IN", "Input clock"},
+       [467] = {157, 233, "DEV_BOARD0_MCASP2_ACLKX_OUT", "Output clock"},
+       [468] = {157, 234, "DEV_BOARD0_MCASP2_AFSX_OUT", "Output clock"},
+       [469] = {157, 235, "DEV_BOARD0_MCASP3_ACLKR_IN", "Input clock"},
+       [470] = {157, 236, "DEV_BOARD0_MCASP3_ACLKR_OUT", "Output clock"},
+       [471] = {157, 237, "DEV_BOARD0_MCASP3_AFSR_OUT", "Output clock"},
+       [472] = {157, 238, "DEV_BOARD0_MCASP3_ACLKX_IN", "Input clock"},
+       [473] = {157, 239, "DEV_BOARD0_MCASP3_ACLKX_OUT", "Output clock"},
+       [474] = {157, 240, "DEV_BOARD0_MCASP3_AFSX_OUT", "Output clock"},
+       [475] = {157, 241, "DEV_BOARD0_MCASP4_ACLKR_IN", "Input clock"},
+       [476] = {157, 242, "DEV_BOARD0_MCASP4_ACLKR_OUT", "Output clock"},
+       [477] = {157, 243, "DEV_BOARD0_MCASP4_AFSR_OUT", "Output clock"},
+       [478] = {157, 244, "DEV_BOARD0_MCASP4_ACLKX_IN", "Input clock"},
+       [479] = {157, 245, "DEV_BOARD0_MCASP4_ACLKX_OUT", "Output clock"},
+       [480] = {157, 246, "DEV_BOARD0_MCASP4_AFSX_OUT", "Output clock"},
+       [481] = {157, 247, "DEV_BOARD0_MCASP5_ACLKR_IN", "Input clock"},
+       [482] = {157, 248, "DEV_BOARD0_MCASP5_ACLKR_OUT", "Output clock"},
+       [483] = {157, 249, "DEV_BOARD0_MCASP5_AFSR_OUT", "Output clock"},
+       [484] = {157, 250, "DEV_BOARD0_MCASP5_ACLKX_IN", "Input clock"},
+       [485] = {157, 251, "DEV_BOARD0_MCASP5_ACLKX_OUT", "Output clock"},
+       [486] = {157, 252, "DEV_BOARD0_MCASP5_AFSX_OUT", "Output clock"},
+       [487] = {157, 253, "DEV_BOARD0_MCASP6_ACLKR_IN", "Input clock"},
+       [488] = {157, 254, "DEV_BOARD0_MCASP6_ACLKR_OUT", "Output clock"},
+       [489] = {157, 255, "DEV_BOARD0_MCASP6_AFSR_OUT", "Output clock"},
+       [490] = {157, 256, "DEV_BOARD0_MCASP6_ACLKX_IN", "Input clock"},
+       [491] = {157, 257, "DEV_BOARD0_MCASP6_ACLKX_OUT", "Output clock"},
+       [492] = {157, 258, "DEV_BOARD0_MCASP6_AFSX_OUT", "Output clock"},
+       [493] = {157, 259, "DEV_BOARD0_MCASP7_ACLKR_IN", "Input clock"},
+       [494] = {157, 260, "DEV_BOARD0_MCASP7_ACLKR_OUT", "Output clock"},
+       [495] = {157, 261, "DEV_BOARD0_MCASP7_AFSR_OUT", "Output clock"},
+       [496] = {157, 262, "DEV_BOARD0_MCASP7_ACLKX_IN", "Input clock"},
+       [497] = {157, 263, "DEV_BOARD0_MCASP7_ACLKX_OUT", "Output clock"},
+       [498] = {157, 264, "DEV_BOARD0_MCASP7_AFSX_OUT", "Output clock"},
+       [499] = {157, 265, "DEV_BOARD0_MCASP8_ACLKR_IN", "Input clock"},
+       [500] = {157, 267, "DEV_BOARD0_MCASP8_ACLKR_OUT", "Output clock"},
+       [501] = {157, 268, "DEV_BOARD0_MCASP8_AFSR_OUT", "Output clock"},
+       [502] = {157, 269, "DEV_BOARD0_MCASP8_ACLKX_IN", "Input clock"},
+       [503] = {157, 270, "DEV_BOARD0_MCASP8_ACLKX_OUT", "Output clock"},
+       [504] = {157, 271, "DEV_BOARD0_MCASP8_AFSX_OUT", "Output clock"},
+       [505] = {157, 272, "DEV_BOARD0_MCASP9_ACLKR_IN", "Input clock"},
+       [506] = {157, 273, "DEV_BOARD0_MCASP9_ACLKR_OUT", "Output clock"},
+       [507] = {157, 274, "DEV_BOARD0_MCASP9_AFSR_OUT", "Output clock"},
+       [508] = {157, 275, "DEV_BOARD0_MCASP9_ACLKX_IN", "Input clock"},
+       [509] = {157, 276, "DEV_BOARD0_MCASP9_ACLKX_OUT", "Output clock"},
+       [510] = {157, 278, "DEV_BOARD0_MCASP9_AFSX_OUT", "Output clock"},
+       [511] = {157, 279, "DEV_BOARD0_MCASP10_ACLKR_IN", "Input clock"},
+       [512] = {157, 280, "DEV_BOARD0_MCASP10_ACLKR_OUT", "Output clock"},
+       [513] = {157, 281, "DEV_BOARD0_MCASP10_AFSR_OUT", "Output clock"},
+       [514] = {157, 282, "DEV_BOARD0_MCASP10_ACLKX_IN", "Input clock"},
+       [515] = {157, 283, "DEV_BOARD0_MCASP10_ACLKX_OUT", "Output clock"},
+       [516] = {157, 284, "DEV_BOARD0_MCASP10_AFSX_OUT", "Output clock"},
+       [517] = {157, 285, "DEV_BOARD0_MCASP11_ACLKR_IN", "Input clock"},
+       [518] = {157, 286, "DEV_BOARD0_MCASP11_ACLKR_OUT", "Output clock"},
+       [519] = {157, 287, "DEV_BOARD0_MCASP11_AFSR_OUT", "Output clock"},
+       [520] = {157, 288, "DEV_BOARD0_MCASP11_ACLKX_IN", "Input clock"},
+       [521] = {157, 289, "DEV_BOARD0_MCASP11_ACLKX_OUT", "Output clock"},
+       [522] = {157, 290, "DEV_BOARD0_MCASP11_AFSX_OUT", "Output clock"},
+       [523] = {157, 300, "DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT", "Output clock"},
+       [524] = {157, 301, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN", "Input muxed clock"},
+       [525] = {157, 302, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [526] = {157, 303, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [527] = {157, 304, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [528] = {157, 305, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [529] = {157, 306, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [530] = {157, 307, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [531] = {157, 308, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [532] = {157, 309, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [533] = {157, 310, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [534] = {157, 311, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [535] = {157, 312, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [536] = {157, 313, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [537] = {157, 314, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [538] = {157, 315, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [539] = {157, 316, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [540] = {157, 317, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [541] = {157, 318, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [542] = {157, 319, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [543] = {157, 320, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [544] = {157, 321, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [545] = {157, 322, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [546] = {157, 323, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [547] = {157, 324, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [548] = {157, 325, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [549] = {157, 326, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [550] = {157, 327, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [551] = {157, 328, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [552] = {157, 329, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [553] = {157, 330, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [554] = {157, 331, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [555] = {157, 334, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [556] = {157, 335, "DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT", "Output clock"},
+       [557] = {157, 336, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN", "Input muxed clock"},
+       [558] = {157, 337, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [559] = {157, 338, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [560] = {157, 339, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [561] = {157, 340, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [562] = {157, 341, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [563] = {157, 342, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [564] = {157, 343, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [565] = {157, 344, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [566] = {157, 345, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [567] = {157, 346, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [568] = {157, 347, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [569] = {157, 348, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [570] = {157, 349, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [571] = {157, 350, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [572] = {157, 351, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [573] = {157, 352, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [574] = {157, 353, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [575] = {157, 354, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [576] = {157, 355, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [577] = {157, 356, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [578] = {157, 357, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [579] = {157, 358, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [580] = {157, 359, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [581] = {157, 360, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [582] = {157, 361, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [583] = {157, 362, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [584] = {157, 363, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [585] = {157, 364, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [586] = {157, 365, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [587] = {157, 366, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [588] = {157, 369, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [589] = {157, 370, "DEV_BOARD0_AUDIO_EXT_REFCLK2_OUT", "Output clock"},
+       [590] = {157, 371, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN", "Input muxed clock"},
+       [591] = {157, 372, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [592] = {157, 373, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [593] = {157, 374, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [594] = {157, 375, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [595] = {157, 376, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [596] = {157, 377, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [597] = {157, 378, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [598] = {157, 379, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [599] = {157, 380, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [600] = {157, 381, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [601] = {157, 382, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [602] = {157, 383, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [603] = {157, 384, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [604] = {157, 385, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [605] = {157, 386, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [606] = {157, 387, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [607] = {157, 388, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [608] = {157, 389, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [609] = {157, 390, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [610] = {157, 391, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [611] = {157, 392, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [612] = {157, 393, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [613] = {157, 394, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [614] = {157, 395, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [615] = {157, 396, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [616] = {157, 397, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [617] = {157, 398, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [618] = {157, 399, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [619] = {157, 400, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [620] = {157, 401, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [621] = {157, 404, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+       [622] = {157, 405, "DEV_BOARD0_AUDIO_EXT_REFCLK3_OUT", "Output clock"},
+       [623] = {157, 406, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN", "Input muxed clock"},
+       [624] = {157, 407, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [625] = {157, 408, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [626] = {157, 409, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [627] = {157, 410, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [628] = {157, 411, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [629] = {157, 412, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [630] = {157, 413, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [631] = {157, 414, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [632] = {157, 415, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [633] = {157, 416, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [634] = {157, 417, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [635] = {157, 418, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [636] = {157, 419, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [637] = {157, 420, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [638] = {157, 421, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [639] = {157, 422, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [640] = {157, 423, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [641] = {157, 424, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [642] = {157, 425, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [643] = {157, 426, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [644] = {157, 427, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [645] = {157, 428, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [646] = {157, 429, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [647] = {157, 430, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [648] = {157, 431, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [649] = {157, 432, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [650] = {157, 433, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [651] = {157, 434, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [652] = {157, 435, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [653] = {157, 436, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [654] = {157, 439, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK3_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+       [655] = {142, 0, "DEV_C66SS0_CORE0_GEM_TRC_CLK", "Input clock"},
+       [656] = {142, 1, "DEV_C66SS0_CORE0_GEM_CLK2_OUT_CLK", "Output clock"},
+       [657] = {142, 4, "DEV_C66SS0_CORE0_GEM_PBIST_ROM_CLK", "Output clock"},
+       [658] = {121, 0, "DEV_C66SS0_INTROUTER0_INTR_CLK", "Input clock"},
+       [659] = {143, 0, "DEV_C66SS1_CORE0_GEM_TRC_CLK", "Input clock"},
+       [660] = {143, 1, "DEV_C66SS1_CORE0_GEM_CLK2_OUT_CLK", "Output clock"},
+       [661] = {143, 4, "DEV_C66SS1_CORE0_GEM_PBIST_ROM_CLK", "Output clock"},
+       [662] = {122, 0, "DEV_C66SS1_INTROUTER0_INTR_CLK", "Input clock"},
+       [663] = {15, 0, "DEV_C71SS0_C7X_CLK", "Input clock"},
+       [664] = {15, 1, "DEV_C71SS0_PLL_CTRL_CLK", "Input clock"},
+       [665] = {16, 0, "DEV_C71SS0_MMA_PLL_CTRL_CLK", "Input clock"},
+       [666] = {16, 1, "DEV_C71SS0_MMA_MMA_CLK", "Input clock"},
+       [667] = {123, 0, "DEV_CMPEVENT_INTRTR0_INTR_CLK", "Input clock"},
+       [668] = {5, 0, "DEV_COMPUTE_CLUSTER0_CFG_WRAP_CLK4_CLK", "Input clock"},
+       [669] = {6, 0, "DEV_COMPUTE_CLUSTER0_CLEC_CLK4_CLK", "Input clock"},
+       [670] = {6, 1, "DEV_COMPUTE_CLUSTER0_CLEC_CLK1_CLK", "Input clock"},
+       [671] = {7, 0, "DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK", "Input clock"},
+       [672] = {7, 1, "DEV_COMPUTE_CLUSTER0_CORE_CORE_CLK1_CLK", "Input clock"},
+       [673] = {8, 0, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_PLL_CTRL_CLK", "Input clock"},
+       [674] = {8, 1, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_DDRSS_DDR_PLL_CLK", "Input clock"},
+       [675] = {9, 0, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK1_CLK_CLK", "Input clock"},
+       [676] = {9, 1, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK2_CLK_CLK", "Input clock"},
+       [677] = {12, 0, "DEV_COMPUTE_CLUSTER0_DMSC_WRAP_CLK4_CLK_CLK", "Input clock"},
+       [678] = {13, 0, "DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_MSMC_CLK1_CLK", "Input clock"},
+       [679] = {14, 0, "DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK", "Input clock"},
+       [680] = {17, 0, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVP_CLK1_CLK_CLK", "Input clock"},
+       [681] = {17, 1, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK4_CLK_CLK", "Input clock"},
+       [682] = {17, 2, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK2_CLK_CLK", "Input clock"},
+       [683] = {19, 0, "DEV_CPSW0_GMII3_MT_CLK", "Input clock"},
+       [684] = {19, 1, "DEV_CPSW0_SERDES6_TXFCLK", "Input clock"},
+       [685] = {19, 2, "DEV_CPSW0_SERDES8_TXMCLK", "Input clock"},
+       [686] = {19, 3, "DEV_CPSW0_GMII2_MR_CLK", "Input clock"},
+       [687] = {19, 4, "DEV_CPSW0_SERDES2_TXFCLK", "Input clock"},
+       [688] = {19, 5, "DEV_CPSW0_SERDES4_RXCLK", "Input clock"},
+       [689] = {19, 6, "DEV_CPSW0_SERDES7_TXMCLK", "Input clock"},
+       [690] = {19, 7, "DEV_CPSW0_SERDES7_RXCLK", "Input clock"},
+       [691] = {19, 8, "DEV_CPSW0_SERDES6_REFCLK", "Input clock"},
+       [692] = {19, 9, "DEV_CPSW0_SERDES5_TXFCLK", "Input clock"},
+       [693] = {19, 10, "DEV_CPSW0_SERDES5_RXCLK", "Input clock"},
+       [694] = {19, 11, "DEV_CPSW0_GMII4_MT_CLK", "Input clock"},
+       [695] = {19, 12, "DEV_CPSW0_SERDES3_TXFCLK", "Input clock"},
+       [696] = {19, 13, "DEV_CPSW0_SERDES2_REFCLK", "Input clock"},
+       [697] = {19, 14, "DEV_CPSW0_SERDES4_RXFCLK", "Input clock"},
+       [698] = {19, 15, "DEV_CPSW0_SERDES6_RXFCLK", "Input clock"},
+       [699] = {19, 16, "DEV_CPSW0_CPTS_RFT_CLK", "Input muxed clock"},
+       [700] = {19, 17, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [701] = {19, 18, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [702] = {19, 19, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [703] = {19, 20, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [704] = {19, 21, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [705] = {19, 22, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [706] = {19, 23, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [707] = {19, 24, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [708] = {19, 25, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [709] = {19, 26, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [710] = {19, 27, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [711] = {19, 28, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [712] = {19, 29, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [713] = {19, 30, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [714] = {19, 31, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [715] = {19, 32, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [716] = {19, 33, "DEV_CPSW0_SERDES5_RXFCLK", "Input clock"},
+       [717] = {19, 34, "DEV_CPSW0_SERDES5_TXMCLK", "Input clock"},
+       [718] = {19, 35, "DEV_CPSW0_GMII5_MT_CLK", "Input clock"},
+       [719] = {19, 36, "DEV_CPSW0_SERDES2_RXCLK", "Input clock"},
+       [720] = {19, 37, "DEV_CPSW0_SERDES8_RXFCLK", "Input clock"},
+       [721] = {19, 38, "DEV_CPSW0_SERDES1_RXFCLK", "Input clock"},
+       [722] = {19, 39, "DEV_CPSW0_SERDES8_RXCLK", "Input clock"},
+       [723] = {19, 40, "DEV_CPSW0_GMII_RFT_CLK", "Input clock"},
+       [724] = {19, 41, "DEV_CPSW0_SERDES3_REFCLK", "Input clock"},
+       [725] = {19, 42, "DEV_CPSW0_RGMII_MHZ_250_CLK", "Input clock"},
+       [726] = {19, 43, "DEV_CPSW0_SERDES7_REFCLK", "Input clock"},
+       [727] = {19, 44, "DEV_CPSW0_GMII6_MT_CLK", "Input clock"},
+       [728] = {19, 45, "DEV_CPSW0_SERDES6_TXMCLK", "Input clock"},
+       [729] = {19, 46, "DEV_CPSW0_RMII_MHZ_50_CLK", "Input clock"},
+       [730] = {19, 47, "DEV_CPSW0_GMII4_MR_CLK", "Input clock"},
+       [731] = {19, 48, "DEV_CPSW0_SERDES2_TXMCLK", "Input clock"},
+       [732] = {19, 49, "DEV_CPSW0_RGMII_MHZ_50_CLK", "Input clock"},
+       [733] = {19, 50, "DEV_CPSW0_SERDES4_TXMCLK", "Input clock"},
+       [734] = {19, 51, "DEV_CPSW0_SERDES3_RXFCLK", "Input clock"},
+       [735] = {19, 52, "DEV_CPSW0_GMII8_MT_CLK", "Input clock"},
+       [736] = {19, 53, "DEV_CPSW0_SERDES7_TXFCLK", "Input clock"},
+       [737] = {19, 54, "DEV_CPSW0_GMII7_MT_CLK", "Input clock"},
+       [738] = {19, 55, "DEV_CPSW0_GMII7_MR_CLK", "Input clock"},
+       [739] = {19, 56, "DEV_CPSW0_SERDES6_RXCLK", "Input clock"},
+       [740] = {19, 57, "DEV_CPSW0_SERDES3_RXCLK", "Input clock"},
+       [741] = {19, 58, "DEV_CPSW0_SERDES4_REFCLK", "Input clock"},
+       [742] = {19, 59, "DEV_CPSW0_SERDES1_RXCLK", "Input clock"},
+       [743] = {19, 60, "DEV_CPSW0_SERDES1_TXFCLK", "Input clock"},
+       [744] = {19, 61, "DEV_CPSW0_GMII6_MR_CLK", "Input clock"},
+       [745] = {19, 62, "DEV_CPSW0_SERDES1_REFCLK", "Input clock"},
+       [746] = {19, 63, "DEV_CPSW0_RGMII_MHZ_5_CLK", "Input clock"},
+       [747] = {19, 64, "DEV_CPSW0_SERDES5_REFCLK", "Input clock"},
+       [748] = {19, 65, "DEV_CPSW0_GMII2_MT_CLK", "Input clock"},
+       [749] = {19, 66, "DEV_CPSW0_SERDES8_TXFCLK", "Input clock"},
+       [750] = {19, 67, "DEV_CPSW0_GMII8_MR_CLK", "Input clock"},
+       [751] = {19, 68, "DEV_CPSW0_GMII1_MR_CLK", "Input clock"},
+       [752] = {19, 69, "DEV_CPSW0_SERDES8_REFCLK", "Input clock"},
+       [753] = {19, 70, "DEV_CPSW0_SERDES3_TXMCLK", "Input clock"},
+       [754] = {19, 71, "DEV_CPSW0_GMII3_MR_CLK", "Input clock"},
+       [755] = {19, 72, "DEV_CPSW0_SERDES1_TXMCLK", "Input clock"},
+       [756] = {19, 73, "DEV_CPSW0_SERDES7_RXFCLK", "Input clock"},
+       [757] = {19, 74, "DEV_CPSW0_GMII5_MR_CLK", "Input clock"},
+       [758] = {19, 75, "DEV_CPSW0_GMII1_MT_CLK", "Input clock"},
+       [759] = {19, 76, "DEV_CPSW0_SERDES2_RXFCLK", "Input clock"},
+       [760] = {19, 77, "DEV_CPSW0_SERDES4_TXFCLK", "Input clock"},
+       [761] = {19, 78, "DEV_CPSW0_SERDES3_TXCLK", "Output clock"},
+       [762] = {19, 79, "DEV_CPSW0_CPTS_GENF0_0", "Output clock"},
+       [763] = {19, 80, "DEV_CPSW0_SERDES5_TXCLK", "Output clock"},
+       [764] = {19, 81, "DEV_CPSW0_SERDES6_TXCLK", "Output clock"},
+       [765] = {19, 82, "DEV_CPSW0_SERDES8_TXCLK", "Output clock"},
+       [766] = {19, 83, "DEV_CPSW0_SERDES1_TXCLK", "Output clock"},
+       [767] = {19, 84, "DEV_CPSW0_SERDES4_TXCLK", "Output clock"},
+       [768] = {19, 85, "DEV_CPSW0_SERDES2_TXCLK", "Output clock"},
+       [769] = {19, 86, "DEV_CPSW0_SERDES7_TXCLK", "Output clock"},
+       [770] = {19, 87, "DEV_CPSW0_MDIO_MDCLK_O_0", "Output clock"},
+       [771] = {19, 89, "DEV_CPSW0_CPPI_CLK_CLK", "Input clock"},
+       [772] = {20, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"},
+       [773] = {21, 0, "DEV_CPT2_AGGR1_VCLK_CLK", "Input clock"},
+       [774] = {23, 0, "DEV_CPT2_AGGR2_VCLK_CLK", "Input clock"},
+       [775] = {25, 0, "DEV_CSI_PSILSS0_MAIN_CLK", "Input clock"},
+       [776] = {26, 0, "DEV_CSI_RX_IF0_VBUS_CLK_CLK", "Input clock"},
+       [777] = {26, 1, "DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK", "Input clock"},
+       [778] = {26, 2, "DEV_CSI_RX_IF0_MAIN_CLK_CLK", "Input clock"},
+       [779] = {26, 3, "DEV_CSI_RX_IF0_VP_CLK_CLK", "Input clock"},
+       [780] = {27, 0, "DEV_CSI_RX_IF1_VBUS_CLK_CLK", "Input clock"},
+       [781] = {27, 1, "DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK", "Input clock"},
+       [782] = {27, 2, "DEV_CSI_RX_IF1_MAIN_CLK_CLK", "Input clock"},
+       [783] = {27, 3, "DEV_CSI_RX_IF1_VP_CLK_CLK", "Input clock"},
+       [784] = {28, 0, "DEV_CSI_TX_IF0_ESC_CLK_CLK", "Input clock"},
+       [785] = {28, 1, "DEV_CSI_TX_IF0_DPHY_TXBYTECLKHS_CL_CLK", "Input clock"},
+       [786] = {28, 2, "DEV_CSI_TX_IF0_VBUS_CLK_CLK", "Input clock"},
+       [787] = {28, 3, "DEV_CSI_TX_IF0_MAIN_CLK_CLK", "Input clock"},
+       [788] = {30, 0, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"},
+       [789] = {30, 1, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"},
+       [790] = {30, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"},
+       [791] = {30, 3, "DEV_DCC0_DCC_CLKSRC7_CLK", "Input clock"},
+       [792] = {30, 4, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"},
+       [793] = {30, 5, "DEV_DCC0_VBUS_CLK", "Input clock"},
+       [794] = {30, 6, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"},
+       [795] = {30, 7, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"},
+       [796] = {30, 8, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"},
+       [797] = {30, 9, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"},
+       [798] = {30, 10, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"},
+       [799] = {30, 11, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"},
+       [800] = {30, 12, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"},
+       [801] = {31, 0, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"},
+       [802] = {31, 1, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"},
+       [803] = {31, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"},
+       [804] = {31, 3, "DEV_DCC1_DCC_CLKSRC7_CLK", "Input clock"},
+       [805] = {31, 4, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"},
+       [806] = {31, 5, "DEV_DCC1_VBUS_CLK", "Input clock"},
+       [807] = {31, 6, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"},
+       [808] = {31, 7, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"},
+       [809] = {31, 8, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"},
+       [810] = {31, 9, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"},
+       [811] = {31, 10, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"},
+       [812] = {31, 11, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"},
+       [813] = {31, 12, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"},
+       [814] = {41, 0, "DEV_DCC10_DCC_INPUT10_CLK", "Input clock"},
+       [815] = {41, 1, "DEV_DCC10_DCC_INPUT01_CLK", "Input clock"},
+       [816] = {41, 2, "DEV_DCC10_DCC_CLKSRC2_CLK", "Input clock"},
+       [817] = {41, 3, "DEV_DCC10_DCC_CLKSRC7_CLK", "Input clock"},
+       [818] = {41, 4, "DEV_DCC10_DCC_CLKSRC0_CLK", "Input clock"},
+       [819] = {41, 5, "DEV_DCC10_VBUS_CLK", "Input clock"},
+       [820] = {41, 6, "DEV_DCC10_DCC_CLKSRC4_CLK", "Input clock"},
+       [821] = {41, 7, "DEV_DCC10_DCC_CLKSRC1_CLK", "Input clock"},
+       [822] = {41, 8, "DEV_DCC10_DCC_CLKSRC3_CLK", "Input clock"},
+       [823] = {41, 9, "DEV_DCC10_DCC_INPUT00_CLK", "Input clock"},
+       [824] = {41, 10, "DEV_DCC10_DCC_CLKSRC5_CLK", "Input clock"},
+       [825] = {41, 11, "DEV_DCC10_DCC_CLKSRC6_CLK", "Input clock"},
+       [826] = {41, 12, "DEV_DCC10_DCC_INPUT02_CLK", "Input clock"},
+       [827] = {42, 0, "DEV_DCC11_DCC_INPUT10_CLK", "Input clock"},
+       [828] = {42, 1, "DEV_DCC11_DCC_INPUT01_CLK", "Input clock"},
+       [829] = {42, 2, "DEV_DCC11_DCC_CLKSRC2_CLK", "Input clock"},
+       [830] = {42, 3, "DEV_DCC11_DCC_CLKSRC7_CLK", "Input clock"},
+       [831] = {42, 4, "DEV_DCC11_DCC_CLKSRC0_CLK", "Input clock"},
+       [832] = {42, 5, "DEV_DCC11_VBUS_CLK", "Input clock"},
+       [833] = {42, 6, "DEV_DCC11_DCC_CLKSRC4_CLK", "Input clock"},
+       [834] = {42, 7, "DEV_DCC11_DCC_CLKSRC1_CLK", "Input clock"},
+       [835] = {42, 8, "DEV_DCC11_DCC_CLKSRC3_CLK", "Input clock"},
+       [836] = {42, 9, "DEV_DCC11_DCC_INPUT00_CLK", "Input clock"},
+       [837] = {42, 10, "DEV_DCC11_DCC_CLKSRC5_CLK", "Input clock"},
+       [838] = {42, 11, "DEV_DCC11_DCC_CLKSRC6_CLK", "Input clock"},
+       [839] = {42, 12, "DEV_DCC11_DCC_INPUT02_CLK", "Input clock"},
+       [840] = {43, 0, "DEV_DCC12_DCC_INPUT10_CLK", "Input clock"},
+       [841] = {43, 1, "DEV_DCC12_DCC_INPUT01_CLK", "Input clock"},
+       [842] = {43, 2, "DEV_DCC12_DCC_CLKSRC2_CLK", "Input clock"},
+       [843] = {43, 3, "DEV_DCC12_DCC_CLKSRC7_CLK", "Input clock"},
+       [844] = {43, 4, "DEV_DCC12_DCC_CLKSRC0_CLK", "Input clock"},
+       [845] = {43, 5, "DEV_DCC12_VBUS_CLK", "Input clock"},
+       [846] = {43, 6, "DEV_DCC12_DCC_CLKSRC4_CLK", "Input clock"},
+       [847] = {43, 7, "DEV_DCC12_DCC_CLKSRC1_CLK", "Input clock"},
+       [848] = {43, 8, "DEV_DCC12_DCC_CLKSRC3_CLK", "Input clock"},
+       [849] = {43, 9, "DEV_DCC12_DCC_INPUT00_CLK", "Input clock"},
+       [850] = {43, 10, "DEV_DCC12_DCC_CLKSRC5_CLK", "Input clock"},
+       [851] = {43, 11, "DEV_DCC12_DCC_CLKSRC6_CLK", "Input clock"},
+       [852] = {43, 12, "DEV_DCC12_DCC_INPUT02_CLK", "Input clock"},
+       [853] = {32, 0, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"},
+       [854] = {32, 1, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"},
+       [855] = {32, 2, "DEV_DCC2_DCC_CLKSRC2_CLK", "Input clock"},
+       [856] = {32, 3, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"},
+       [857] = {32, 4, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"},
+       [858] = {32, 5, "DEV_DCC2_VBUS_CLK", "Input clock"},
+       [859] = {32, 6, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"},
+       [860] = {32, 7, "DEV_DCC2_DCC_CLKSRC1_CLK", "Input clock"},
+       [861] = {32, 8, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"},
+       [862] = {32, 9, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"},
+       [863] = {32, 10, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"},
+       [864] = {32, 11, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"},
+       [865] = {32, 12, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"},
+       [866] = {33, 0, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"},
+       [867] = {33, 1, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"},
+       [868] = {33, 2, "DEV_DCC3_DCC_CLKSRC2_CLK", "Input clock"},
+       [869] = {33, 3, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"},
+       [870] = {33, 4, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"},
+       [871] = {33, 5, "DEV_DCC3_VBUS_CLK", "Input clock"},
+       [872] = {33, 6, "DEV_DCC3_DCC_CLKSRC4_CLK", "Input clock"},
+       [873] = {33, 7, "DEV_DCC3_DCC_CLKSRC1_CLK", "Input clock"},
+       [874] = {33, 8, "DEV_DCC3_DCC_CLKSRC3_CLK", "Input clock"},
+       [875] = {33, 9, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"},
+       [876] = {33, 10, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"},
+       [877] = {33, 11, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"},
+       [878] = {33, 12, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"},
+       [879] = {34, 0, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"},
+       [880] = {34, 1, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"},
+       [881] = {34, 2, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"},
+       [882] = {34, 3, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"},
+       [883] = {34, 4, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input clock"},
+       [884] = {34, 5, "DEV_DCC4_VBUS_CLK", "Input clock"},
+       [885] = {34, 6, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"},
+       [886] = {34, 7, "DEV_DCC4_DCC_CLKSRC1_CLK", "Input clock"},
+       [887] = {34, 8, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"},
+       [888] = {34, 9, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"},
+       [889] = {34, 10, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"},
+       [890] = {34, 11, "DEV_DCC4_DCC_CLKSRC6_CLK", "Input clock"},
+       [891] = {34, 12, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"},
+       [892] = {36, 0, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"},
+       [893] = {36, 1, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"},
+       [894] = {36, 2, "DEV_DCC5_DCC_CLKSRC2_CLK", "Input clock"},
+       [895] = {36, 3, "DEV_DCC5_DCC_CLKSRC7_CLK", "Input clock"},
+       [896] = {36, 4, "DEV_DCC5_DCC_CLKSRC0_CLK", "Input clock"},
+       [897] = {36, 5, "DEV_DCC5_VBUS_CLK", "Input clock"},
+       [898] = {36, 6, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"},
+       [899] = {36, 7, "DEV_DCC5_DCC_CLKSRC1_CLK", "Input clock"},
+       [900] = {36, 8, "DEV_DCC5_DCC_CLKSRC3_CLK", "Input clock"},
+       [901] = {36, 9, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"},
+       [902] = {36, 10, "DEV_DCC5_DCC_CLKSRC5_CLK", "Input clock"},
+       [903] = {36, 11, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"},
+       [904] = {36, 12, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"},
+       [905] = {37, 0, "DEV_DCC6_DCC_INPUT10_CLK", "Input clock"},
+       [906] = {37, 1, "DEV_DCC6_DCC_INPUT01_CLK", "Input clock"},
+       [907] = {37, 2, "DEV_DCC6_DCC_CLKSRC2_CLK", "Input clock"},
+       [908] = {37, 3, "DEV_DCC6_DCC_CLKSRC7_CLK", "Input clock"},
+       [909] = {37, 4, "DEV_DCC6_DCC_CLKSRC0_CLK", "Input clock"},
+       [910] = {37, 5, "DEV_DCC6_VBUS_CLK", "Input clock"},
+       [911] = {37, 6, "DEV_DCC6_DCC_CLKSRC4_CLK", "Input clock"},
+       [912] = {37, 7, "DEV_DCC6_DCC_CLKSRC1_CLK", "Input clock"},
+       [913] = {37, 8, "DEV_DCC6_DCC_CLKSRC3_CLK", "Input clock"},
+       [914] = {37, 9, "DEV_DCC6_DCC_INPUT00_CLK", "Input clock"},
+       [915] = {37, 10, "DEV_DCC6_DCC_CLKSRC5_CLK", "Input clock"},
+       [916] = {37, 11, "DEV_DCC6_DCC_CLKSRC6_CLK", "Input clock"},
+       [917] = {37, 12, "DEV_DCC6_DCC_INPUT02_CLK", "Input clock"},
+       [918] = {38, 0, "DEV_DCC7_DCC_INPUT10_CLK", "Input clock"},
+       [919] = {38, 1, "DEV_DCC7_DCC_INPUT01_CLK", "Input clock"},
+       [920] = {38, 2, "DEV_DCC7_DCC_CLKSRC2_CLK", "Input clock"},
+       [921] = {38, 3, "DEV_DCC7_DCC_CLKSRC7_CLK", "Input clock"},
+       [922] = {38, 4, "DEV_DCC7_DCC_CLKSRC0_CLK", "Input clock"},
+       [923] = {38, 5, "DEV_DCC7_VBUS_CLK", "Input clock"},
+       [924] = {38, 6, "DEV_DCC7_DCC_CLKSRC4_CLK", "Input clock"},
+       [925] = {38, 7, "DEV_DCC7_DCC_CLKSRC1_CLK", "Input clock"},
+       [926] = {38, 8, "DEV_DCC7_DCC_CLKSRC3_CLK", "Input clock"},
+       [927] = {38, 9, "DEV_DCC7_DCC_INPUT00_CLK", "Input clock"},
+       [928] = {38, 10, "DEV_DCC7_DCC_CLKSRC5_CLK", "Input clock"},
+       [929] = {38, 11, "DEV_DCC7_DCC_CLKSRC6_CLK", "Input clock"},
+       [930] = {38, 12, "DEV_DCC7_DCC_INPUT02_CLK", "Input clock"},
+       [931] = {39, 0, "DEV_DCC8_DCC_INPUT10_CLK", "Input clock"},
+       [932] = {39, 1, "DEV_DCC8_DCC_INPUT01_CLK", "Input clock"},
+       [933] = {39, 2, "DEV_DCC8_DCC_CLKSRC2_CLK", "Input clock"},
+       [934] = {39, 3, "DEV_DCC8_DCC_CLKSRC7_CLK", "Input clock"},
+       [935] = {39, 4, "DEV_DCC8_DCC_CLKSRC0_CLK", "Input clock"},
+       [936] = {39, 5, "DEV_DCC8_VBUS_CLK", "Input clock"},
+       [937] = {39, 6, "DEV_DCC8_DCC_CLKSRC4_CLK", "Input clock"},
+       [938] = {39, 7, "DEV_DCC8_DCC_CLKSRC1_CLK", "Input clock"},
+       [939] = {39, 8, "DEV_DCC8_DCC_CLKSRC3_CLK", "Input clock"},
+       [940] = {39, 9, "DEV_DCC8_DCC_INPUT00_CLK", "Input clock"},
+       [941] = {39, 10, "DEV_DCC8_DCC_CLKSRC5_CLK", "Input clock"},
+       [942] = {39, 11, "DEV_DCC8_DCC_CLKSRC6_CLK", "Input clock"},
+       [943] = {39, 12, "DEV_DCC8_DCC_INPUT02_CLK", "Input clock"},
+       [944] = {40, 0, "DEV_DCC9_DCC_INPUT10_CLK", "Input clock"},
+       [945] = {40, 1, "DEV_DCC9_DCC_INPUT01_CLK", "Input clock"},
+       [946] = {40, 2, "DEV_DCC9_DCC_CLKSRC2_CLK", "Input clock"},
+       [947] = {40, 3, "DEV_DCC9_DCC_CLKSRC7_CLK", "Input clock"},
+       [948] = {40, 4, "DEV_DCC9_DCC_CLKSRC0_CLK", "Input clock"},
+       [949] = {40, 5, "DEV_DCC9_VBUS_CLK", "Input clock"},
+       [950] = {40, 6, "DEV_DCC9_DCC_CLKSRC4_CLK", "Input clock"},
+       [951] = {40, 7, "DEV_DCC9_DCC_CLKSRC1_CLK", "Input clock"},
+       [952] = {40, 8, "DEV_DCC9_DCC_CLKSRC3_CLK", "Input clock"},
+       [953] = {40, 9, "DEV_DCC9_DCC_INPUT00_CLK", "Input clock"},
+       [954] = {40, 10, "DEV_DCC9_DCC_CLKSRC5_CLK", "Input clock"},
+       [955] = {40, 11, "DEV_DCC9_DCC_CLKSRC6_CLK", "Input clock"},
+       [956] = {40, 12, "DEV_DCC9_DCC_INPUT02_CLK", "Input clock"},
+       [957] = {47, 0, "DEV_DDR0_DDRSS_VBUS_CLK", "Input clock"},
+       [958] = {47, 1, "DEV_DDR0_PLL_CTRL_CLK", "Input clock"},
+       [959] = {47, 2, "DEV_DDR0_DDRSS_DDR_PLL_CLK", "Input clock"},
+       [960] = {47, 3, "DEV_DDR0_DDRSS_CFG_CLK", "Input clock"},
+       [961] = {47, 4, "DEV_DDR0_DDRSS_IO_CK_N_0", "Output clock"},
+       [962] = {47, 5, "DEV_DDR0_DDRSS_IO_CK_0", "Output clock"},
+       [963] = {304, 5, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"},
+       [964] = {304, 9, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"},
+       [965] = {304, 25, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"},
+       [966] = {304, 32, "DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK_0", "Output clock"},
+       [967] = {304, 35, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"},
+       [968] = {144, 0, "DEV_DECODER0_SYS_CLK", "Input clock"},
+       [969] = {305, 0, "DEV_DMPAC0_SDE_0_CLK", "Input clock"},
+       [970] = {48, 0, "DEV_DMPAC_TOP_MAIN_0_CLK", "Input clock"},
+       [971] = {48, 1, "DEV_DMPAC_TOP_MAIN_0_PLL_DCO_CLK", "Input clock"},
+       [972] = {147, 0, "DEV_DPHY_RX0_MAIN_CLK_CLK", "Input clock"},
+       [973] = {147, 1, "DEV_DPHY_RX0_PPI_RX_BYTE_CLK", "Output clock"},
+       [974] = {148, 0, "DEV_DPHY_RX1_MAIN_CLK_CLK", "Input clock"},
+       [975] = {148, 1, "DEV_DPHY_RX1_PPI_RX_BYTE_CLK", "Output clock"},
+       [976] = {296, 0, "DEV_DPHY_TX0_CLK", "Input clock"},
+       [977] = {296, 1, "DEV_DPHY_TX0_PSM_CLK", "Input clock"},
+       [978] = {296, 2, "DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK", "Input clock"},
+       [979] = {296, 3, "DEV_DPHY_TX0_DPHY_REF_CLK", "Input muxed clock"},
+       [980] = {296, 4, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
+       [981] = {296, 5, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
+       [982] = {296, 6, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
+       [983] = {296, 7, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
+       [984] = {296, 8, "DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK", "Output clock"},
+       [985] = {296, 9, "DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK", "Output clock"},
+       [986] = {296, 10, "DEV_DPHY_TX0_CK_P_0", "Output clock"},
+       [987] = {296, 11, "DEV_DPHY_TX0_CK_M_0", "Output clock"},
+       [988] = {296, 12, "DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK", "Output clock"},
+       [989] = {152, 0, "DEV_DSS0_DSS_FUNC_CLK", "Input clock"},
+       [990] = {152, 1, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK", "Input muxed clock"},
+       [991] = {152, 2, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"},
+       [992] = {152, 3, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"},
+       [993] = {152, 4, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK", "Input muxed clock"},
+       [994] = {152, 5, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
+       [995] = {152, 6, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
+       [996] = {152, 7, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
+       [997] = {152, 8, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
+       [998] = {152, 9, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK", "Input muxed clock"},
+       [999] = {152, 10, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"},
+       [1000] = {152, 11, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"},
+       [1001] = {152, 12, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"},
+       [1002] = {152, 13, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK", "Input muxed clock"},
+       [1003] = {152, 14, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
+       [1004] = {152, 15, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
+       [1005] = {152, 16, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
+       [1006] = {152, 17, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
+       [1007] = {152, 18, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
+       [1008] = {152, 23, "DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK", "Output clock"},
+       [1009] = {152, 24, "DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK", "Output clock"},
+       [1010] = {152, 25, "DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK", "Output clock"},
+       [1011] = {152, 27, "DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK", "Output clock"},
+       [1012] = {152, 29, "DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK", "Output clock"},
+       [1013] = {152, 31, "DEV_DSS0_DPI0_EXT_CLKSEL", "Input muxed clock"},
+       [1014] = {152, 32, "DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL"},
+       [1015] = {152, 33, "DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_BOARD_0_VOUT1_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL"},
+       [1016] = {152, 34, "DEV_DSS0_DPI1_EXT_CLKSEL", "Input muxed clock"},
+       [1017] = {152, 35, "DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL"},
+       [1018] = {152, 36, "DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_BOARD_0_VOUT2_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL"},
+       [1019] = {150, 0, "DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK", "Input clock"},
+       [1020] = {150, 1, "DEV_DSS_DSI0_DPI_0_CLK", "Input clock"},
+       [1021] = {150, 2, "DEV_DSS_DSI0_PLL_CTRL_CLK", "Input clock"},
+       [1022] = {150, 3, "DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK", "Input clock"},
+       [1023] = {150, 4, "DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK", "Input clock"},
+       [1024] = {150, 5, "DEV_DSS_DSI0_SYS_CLK", "Input clock"},
+       [1025] = {151, 0, "DEV_DSS_EDP0_PHY_LN1_TXFCLK", "Input clock"},
+       [1026] = {151, 1, "DEV_DSS_EDP0_DPI_2_CLK", "Input clock"},
+       [1027] = {151, 2, "DEV_DSS_EDP0_PHY_LN2_TXFCLK", "Input clock"},
+       [1028] = {151, 3, "DEV_DSS_EDP0_PHY_LN0_RXCLK", "Input clock"},
+       [1029] = {151, 4, "DEV_DSS_EDP0_PHY_LN2_TXMCLK", "Input clock"},
+       [1030] = {151, 5, "DEV_DSS_EDP0_PHY_LN0_RXFCLK", "Input clock"},
+       [1031] = {151, 6, "DEV_DSS_EDP0_PHY_LN0_REFCLK", "Input clock"},
+       [1032] = {151, 7, "DEV_DSS_EDP0_PHY_LN1_RXCLK", "Input clock"},
+       [1033] = {151, 8, "DEV_DSS_EDP0_PHY_LN2_RXFCLK", "Input clock"},
+       [1034] = {151, 9, "DEV_DSS_EDP0_DPI_4_CLK", "Input clock"},
+       [1035] = {151, 10, "DEV_DSS_EDP0_DPI_2_2X_CLK", "Input clock"},
+       [1036] = {151, 11, "DEV_DSS_EDP0_PHY_LN0_TXFCLK", "Input clock"},
+       [1037] = {151, 12, "DEV_DSS_EDP0_PHY_LN2_RXCLK", "Input clock"},
+       [1038] = {151, 13, "DEV_DSS_EDP0_PHY_LN2_REFCLK", "Input clock"},
+       [1039] = {151, 14, "DEV_DSS_EDP0_PHY_LN3_REFCLK", "Input clock"},
+       [1040] = {151, 15, "DEV_DSS_EDP0_DPI_5_CLK", "Input clock"},
+       [1041] = {151, 16, "DEV_DSS_EDP0_PHY_LN3_RXCLK", "Input clock"},
+       [1042] = {151, 17, "DEV_DSS_EDP0_PHY_LN1_REFCLK", "Input clock"},
+       [1043] = {151, 18, "DEV_DSS_EDP0_AIF_I2S_CLK", "Input clock"},
+       [1044] = {151, 19, "DEV_DSS_EDP0_PHY_LN3_TXFCLK", "Input clock"},
+       [1045] = {151, 20, "DEV_DSS_EDP0_DPI_3_CLK", "Input clock"},
+       [1046] = {151, 21, "DEV_DSS_EDP0_PHY_LN1_RXFCLK", "Input clock"},
+       [1047] = {151, 22, "DEV_DSS_EDP0_PHY_LN1_TXMCLK", "Input clock"},
+       [1048] = {151, 23, "DEV_DSS_EDP0_PLL_CTRL_CLK", "Input clock"},
+       [1049] = {151, 24, "DEV_DSS_EDP0_PHY_LN3_TXMCLK", "Input clock"},
+       [1050] = {151, 25, "DEV_DSS_EDP0_PHY_LN3_RXFCLK", "Input clock"},
+       [1051] = {151, 26, "DEV_DSS_EDP0_PHY_LN0_TXMCLK", "Input clock"},
+       [1052] = {151, 27, "DEV_DSS_EDP0_PHY_LN2_TXCLK", "Output clock"},
+       [1053] = {151, 28, "DEV_DSS_EDP0_PHY_LN3_TXCLK", "Output clock"},
+       [1054] = {151, 29, "DEV_DSS_EDP0_PHY_LN0_TXCLK", "Output clock"},
+       [1055] = {151, 30, "DEV_DSS_EDP0_PHY_LN1_TXCLK", "Output clock"},
+       [1056] = {151, 36, "DEV_DSS_EDP0_DPTX_MOD_CLK", "Input clock"},
+       [1057] = {80, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"},
+       [1058] = {81, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"},
+       [1059] = {82, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"},
+       [1060] = {83, 0, "DEV_EHRPWM0_VBUSP_CLK", "Input clock"},
+       [1061] = {84, 0, "DEV_EHRPWM1_VBUSP_CLK", "Input clock"},
+       [1062] = {85, 0, "DEV_EHRPWM2_VBUSP_CLK", "Input clock"},
+       [1063] = {86, 0, "DEV_EHRPWM3_VBUSP_CLK", "Input clock"},
+       [1064] = {87, 0, "DEV_EHRPWM4_VBUSP_CLK", "Input clock"},
+       [1065] = {88, 0, "DEV_EHRPWM5_VBUSP_CLK", "Input clock"},
+       [1066] = {89, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"},
+       [1067] = {153, 0, "DEV_ENCODER0_SYS_CLK", "Input clock"},
+       [1068] = {94, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"},
+       [1069] = {95, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"},
+       [1070] = {96, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"},
+       [1071] = {97, 0, "DEV_ESM0_CLK", "Input clock"},
+       [1072] = {105, 0, "DEV_GPIO0_MMR_CLK", "Input clock"},
+       [1073] = {106, 0, "DEV_GPIO1_MMR_CLK", "Input clock"},
+       [1074] = {107, 0, "DEV_GPIO2_MMR_CLK", "Input clock"},
+       [1075] = {108, 0, "DEV_GPIO3_MMR_CLK", "Input clock"},
+       [1076] = {109, 0, "DEV_GPIO4_MMR_CLK", "Input clock"},
+       [1077] = {110, 0, "DEV_GPIO5_MMR_CLK", "Input clock"},
+       [1078] = {111, 0, "DEV_GPIO6_MMR_CLK", "Input clock"},
+       [1079] = {112, 0, "DEV_GPIO7_MMR_CLK", "Input clock"},
+       [1080] = {131, 0, "DEV_GPIOMUX_INTRTR0_INTR_CLK", "Input clock"},
+       [1081] = {115, 0, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"},
+       [1082] = {115, 1, "DEV_GPMC0_VBUSP_CLK", "Input clock"},
+       [1083] = {115, 2, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"},
+       [1084] = {115, 3, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
+       [1085] = {115, 4, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
+       [1086] = {115, 5, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK3", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
+       [1087] = {115, 6, "DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
+       [1088] = {115, 7, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"},
+       [1089] = {125, 0, "DEV_GPU0_GPU_0_GPU_PLL_CLK", "Input clock"},
+       [1090] = {61, 0, "DEV_GTC0_VBUSP_CLK", "Input clock"},
+       [1091] = {61, 1, "DEV_GTC0_GTC_CLK", "Input muxed clock"},
+       [1092] = {61, 2, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [1093] = {61, 3, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [1094] = {61, 4, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [1095] = {61, 5, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [1096] = {61, 6, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [1097] = {61, 7, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [1098] = {61, 8, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [1099] = {61, 9, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [1100] = {61, 10, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [1101] = {61, 11, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [1102] = {61, 12, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [1103] = {61, 13, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [1104] = {61, 14, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [1105] = {61, 15, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [1106] = {61, 16, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [1107] = {61, 17, "DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [1108] = {187, 0, "DEV_I2C0_PISYS_CLK", "Input clock"},
+       [1109] = {187, 1, "DEV_I2C0_PISCL_0", "Input clock"},
+       [1110] = {187, 2, "DEV_I2C0_CLK", "Input clock"},
+       [1111] = {188, 0, "DEV_I2C1_PISYS_CLK", "Input clock"},
+       [1112] = {188, 1, "DEV_I2C1_PISCL_0", "Input clock"},
+       [1113] = {188, 2, "DEV_I2C1_CLK", "Input clock"},
+       [1114] = {189, 0, "DEV_I2C2_PISYS_CLK", "Input clock"},
+       [1115] = {189, 1, "DEV_I2C2_PISCL_0", "Input clock"},
+       [1116] = {189, 2, "DEV_I2C2_CLK", "Input clock"},
+       [1117] = {190, 0, "DEV_I2C3_PISYS_CLK", "Input clock"},
+       [1118] = {190, 1, "DEV_I2C3_PISCL_0", "Input clock"},
+       [1119] = {190, 2, "DEV_I2C3_CLK", "Input clock"},
+       [1120] = {191, 0, "DEV_I2C4_PISYS_CLK", "Input clock"},
+       [1121] = {191, 1, "DEV_I2C4_PISCL_0", "Input clock"},
+       [1122] = {191, 2, "DEV_I2C4_CLK", "Input clock"},
+       [1123] = {192, 0, "DEV_I2C5_PISYS_CLK", "Input clock"},
+       [1124] = {192, 1, "DEV_I2C5_PISCL_0", "Input clock"},
+       [1125] = {192, 2, "DEV_I2C5_CLK", "Input clock"},
+       [1126] = {193, 0, "DEV_I2C6_PISYS_CLK", "Input clock"},
+       [1127] = {193, 1, "DEV_I2C6_PISCL_0", "Input clock"},
+       [1128] = {193, 2, "DEV_I2C6_CLK", "Input clock"},
+       [1129] = {116, 0, "DEV_I3C0_I3C_PCLK_CLK", "Input clock"},
+       [1130] = {116, 1, "DEV_I3C0_I3C_SCL_DI", "Input clock"},
+       [1131] = {116, 2, "DEV_I3C0_I3C_SCLK_CLK", "Input clock"},
+       [1132] = {116, 3, "DEV_I3C0_I3C_SCL_DO_0", "Output clock"},
+       [1133] = {127, 0, "DEV_LED0_LED_CLK", "Input clock"},
+       [1134] = {127, 1, "DEV_LED0_VBUS_CLK", "Input clock"},
+       [1135] = {128, 0, "DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK", "Input clock"},
+       [1136] = {130, 0, "DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK", "Input clock"},
+       [1137] = {156, 0, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"},
+       [1138] = {156, 1, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [1139] = {156, 2, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+       [1140] = {156, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+       [1141] = {156, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+       [1142] = {156, 5, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+       [1143] = {158, 0, "DEV_MCAN1_MCANSS_HCLK_CLK", "Input clock"},
+       [1144] = {158, 1, "DEV_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [1145] = {158, 2, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
+       [1146] = {158, 3, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
+       [1147] = {158, 4, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
+       [1148] = {158, 5, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
+       [1149] = {168, 0, "DEV_MCAN10_MCANSS_HCLK_CLK", "Input clock"},
+       [1150] = {168, 1, "DEV_MCAN10_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [1151] = {168, 2, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
+       [1152] = {168, 3, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
+       [1153] = {168, 4, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
+       [1154] = {168, 5, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
+       [1155] = {169, 0, "DEV_MCAN11_MCANSS_HCLK_CLK", "Input clock"},
+       [1156] = {169, 1, "DEV_MCAN11_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [1157] = {169, 2, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
+       [1158] = {169, 3, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
+       [1159] = {169, 4, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
+       [1160] = {169, 5, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
+       [1161] = {170, 0, "DEV_MCAN12_MCANSS_HCLK_CLK", "Input clock"},
+       [1162] = {170, 1, "DEV_MCAN12_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [1163] = {170, 2, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
+       [1164] = {170, 3, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
+       [1165] = {170, 4, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
+       [1166] = {170, 5, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
+       [1167] = {171, 0, "DEV_MCAN13_MCANSS_HCLK_CLK", "Input clock"},
+       [1168] = {171, 1, "DEV_MCAN13_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [1169] = {171, 2, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
+       [1170] = {171, 3, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
+       [1171] = {171, 4, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
+       [1172] = {171, 5, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
+       [1173] = {160, 0, "DEV_MCAN2_MCANSS_HCLK_CLK", "Input clock"},
+       [1174] = {160, 1, "DEV_MCAN2_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [1175] = {160, 2, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
+       [1176] = {160, 3, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
+       [1177] = {160, 4, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
+       [1178] = {160, 5, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
+       [1179] = {161, 0, "DEV_MCAN3_MCANSS_HCLK_CLK", "Input clock"},
+       [1180] = {161, 1, "DEV_MCAN3_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [1181] = {161, 2, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
+       [1182] = {161, 3, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
+       [1183] = {161, 4, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
+       [1184] = {161, 5, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
+       [1185] = {162, 0, "DEV_MCAN4_MCANSS_HCLK_CLK", "Input clock"},
+       [1186] = {162, 1, "DEV_MCAN4_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [1187] = {162, 2, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
+       [1188] = {162, 3, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
+       [1189] = {162, 4, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
+       [1190] = {162, 5, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
+       [1191] = {163, 0, "DEV_MCAN5_MCANSS_HCLK_CLK", "Input clock"},
+       [1192] = {163, 1, "DEV_MCAN5_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [1193] = {163, 2, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
+       [1194] = {163, 3, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
+       [1195] = {163, 4, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
+       [1196] = {163, 5, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
+       [1197] = {164, 0, "DEV_MCAN6_MCANSS_HCLK_CLK", "Input clock"},
+       [1198] = {164, 1, "DEV_MCAN6_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [1199] = {164, 2, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
+       [1200] = {164, 3, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
+       [1201] = {164, 4, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
+       [1202] = {164, 5, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
+       [1203] = {165, 0, "DEV_MCAN7_MCANSS_HCLK_CLK", "Input clock"},
+       [1204] = {165, 1, "DEV_MCAN7_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [1205] = {165, 2, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
+       [1206] = {165, 3, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
+       [1207] = {165, 4, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
+       [1208] = {165, 5, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
+       [1209] = {166, 0, "DEV_MCAN8_MCANSS_HCLK_CLK", "Input clock"},
+       [1210] = {166, 1, "DEV_MCAN8_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [1211] = {166, 2, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
+       [1212] = {166, 3, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
+       [1213] = {166, 4, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
+       [1214] = {166, 5, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
+       [1215] = {167, 0, "DEV_MCAN9_MCANSS_HCLK_CLK", "Input clock"},
+       [1216] = {167, 1, "DEV_MCAN9_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [1217] = {167, 2, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
+       [1218] = {167, 3, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
+       [1219] = {167, 4, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
+       [1220] = {167, 5, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
+       [1221] = {174, 0, "DEV_MCASP0_VBUSP_CLK", "Input clock"},
+       [1222] = {174, 1, "DEV_MCASP0_AUX_CLK", "Input muxed clock"},
+       [1223] = {174, 2, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+       [1224] = {174, 3, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+       [1225] = {174, 4, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+       [1226] = {174, 6, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+       [1227] = {174, 7, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+       [1228] = {174, 8, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+       [1229] = {174, 9, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+       [1230] = {174, 10, "DEV_MCASP0_MCASP_ACLKX_POUT_0", "Output clock"},
+       [1231] = {174, 11, "DEV_MCASP0_MCASP_ACLKX_PIN_0", "Input clock"},
+       [1232] = {174, 12, "DEV_MCASP0_MCASP_ACLKR_POUT_0", "Output clock"},
+       [1233] = {174, 13, "DEV_MCASP0_MCASP_ACLKR_PIN_0", "Input clock"},
+       [1234] = {174, 14, "DEV_MCASP0_MCASP_AHCLKX_POUT_0", "Output clock"},
+       [1235] = {174, 15, "DEV_MCASP0_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+       [1236] = {174, 16, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+       [1237] = {174, 17, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+       [1238] = {174, 18, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+       [1239] = {174, 19, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+       [1240] = {174, 20, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+       [1241] = {174, 21, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+       [1242] = {174, 22, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+       [1243] = {174, 23, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+       [1244] = {174, 24, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+       [1245] = {174, 25, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+       [1246] = {174, 26, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+       [1247] = {174, 27, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+       [1248] = {174, 28, "DEV_MCASP0_MCASP_AHCLKR_POUT_0", "Output clock"},
+       [1249] = {174, 29, "DEV_MCASP0_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+       [1250] = {174, 30, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+       [1251] = {174, 31, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+       [1252] = {174, 32, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+       [1253] = {174, 33, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+       [1254] = {174, 34, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+       [1255] = {174, 35, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+       [1256] = {174, 36, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+       [1257] = {174, 37, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+       [1258] = {174, 38, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+       [1259] = {174, 39, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+       [1260] = {174, 40, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+       [1261] = {174, 41, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+       [1262] = {175, 0, "DEV_MCASP1_VBUSP_CLK", "Input clock"},
+       [1263] = {175, 1, "DEV_MCASP1_AUX_CLK", "Input muxed clock"},
+       [1264] = {175, 2, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+       [1265] = {175, 3, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+       [1266] = {175, 4, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+       [1267] = {175, 6, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+       [1268] = {175, 7, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+       [1269] = {175, 8, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+       [1270] = {175, 9, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+       [1271] = {175, 10, "DEV_MCASP1_MCASP_ACLKX_POUT_0", "Output clock"},
+       [1272] = {175, 11, "DEV_MCASP1_MCASP_ACLKX_PIN_0", "Input clock"},
+       [1273] = {175, 12, "DEV_MCASP1_MCASP_ACLKR_POUT_0", "Output clock"},
+       [1274] = {175, 13, "DEV_MCASP1_MCASP_ACLKR_PIN_0", "Input clock"},
+       [1275] = {175, 14, "DEV_MCASP1_MCASP_AHCLKX_POUT_0", "Output clock"},
+       [1276] = {175, 15, "DEV_MCASP1_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+       [1277] = {175, 16, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+       [1278] = {175, 17, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+       [1279] = {175, 18, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+       [1280] = {175, 19, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+       [1281] = {175, 20, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+       [1282] = {175, 21, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+       [1283] = {175, 22, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+       [1284] = {175, 23, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+       [1285] = {175, 24, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+       [1286] = {175, 25, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+       [1287] = {175, 26, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+       [1288] = {175, 27, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+       [1289] = {175, 28, "DEV_MCASP1_MCASP_AHCLKR_POUT_0", "Output clock"},
+       [1290] = {175, 29, "DEV_MCASP1_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+       [1291] = {175, 30, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+       [1292] = {175, 31, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+       [1293] = {175, 32, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+       [1294] = {175, 33, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+       [1295] = {175, 34, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+       [1296] = {175, 35, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+       [1297] = {175, 36, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+       [1298] = {175, 37, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+       [1299] = {175, 38, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+       [1300] = {175, 39, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+       [1301] = {175, 40, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+       [1302] = {175, 41, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+       [1303] = {184, 0, "DEV_MCASP10_VBUSP_CLK", "Input clock"},
+       [1304] = {184, 1, "DEV_MCASP10_AUX_CLK", "Input muxed clock"},
+       [1305] = {184, 2, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
+       [1306] = {184, 3, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
+       [1307] = {184, 4, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
+       [1308] = {184, 6, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
+       [1309] = {184, 7, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
+       [1310] = {184, 8, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
+       [1311] = {184, 9, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
+       [1312] = {184, 10, "DEV_MCASP10_MCASP_ACLKX_POUT_0", "Output clock"},
+       [1313] = {184, 11, "DEV_MCASP10_MCASP_ACLKX_PIN_0", "Input clock"},
+       [1314] = {184, 12, "DEV_MCASP10_MCASP_ACLKR_POUT_0", "Output clock"},
+       [1315] = {184, 13, "DEV_MCASP10_MCASP_ACLKR_PIN_0", "Input clock"},
+       [1316] = {184, 14, "DEV_MCASP10_MCASP_AHCLKX_POUT_0", "Output clock"},
+       [1317] = {184, 15, "DEV_MCASP10_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+       [1318] = {184, 16, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+       [1319] = {184, 17, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+       [1320] = {184, 18, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+       [1321] = {184, 19, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+       [1322] = {184, 20, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+       [1323] = {184, 21, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+       [1324] = {184, 22, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+       [1325] = {184, 23, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+       [1326] = {184, 24, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+       [1327] = {184, 25, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+       [1328] = {184, 26, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+       [1329] = {184, 27, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+       [1330] = {184, 28, "DEV_MCASP10_MCASP_AHCLKR_POUT_0", "Output clock"},
+       [1331] = {184, 29, "DEV_MCASP10_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+       [1332] = {184, 30, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+       [1333] = {184, 31, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+       [1334] = {184, 32, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+       [1335] = {184, 33, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+       [1336] = {184, 34, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+       [1337] = {184, 35, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+       [1338] = {184, 36, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+       [1339] = {184, 37, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+       [1340] = {184, 38, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+       [1341] = {184, 39, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+       [1342] = {184, 40, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+       [1343] = {184, 41, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+       [1344] = {185, 0, "DEV_MCASP11_VBUSP_CLK", "Input clock"},
+       [1345] = {185, 1, "DEV_MCASP11_AUX_CLK", "Input muxed clock"},
+       [1346] = {185, 2, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
+       [1347] = {185, 3, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
+       [1348] = {185, 4, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
+       [1349] = {185, 6, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
+       [1350] = {185, 7, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
+       [1351] = {185, 8, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
+       [1352] = {185, 9, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
+       [1353] = {185, 10, "DEV_MCASP11_MCASP_ACLKX_POUT_0", "Output clock"},
+       [1354] = {185, 11, "DEV_MCASP11_MCASP_ACLKX_PIN_0", "Input clock"},
+       [1355] = {185, 12, "DEV_MCASP11_MCASP_ACLKR_POUT_0", "Output clock"},
+       [1356] = {185, 13, "DEV_MCASP11_MCASP_ACLKR_PIN_0", "Input clock"},
+       [1357] = {185, 14, "DEV_MCASP11_MCASP_AHCLKX_POUT_0", "Output clock"},
+       [1358] = {185, 15, "DEV_MCASP11_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+       [1359] = {185, 16, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+       [1360] = {185, 17, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+       [1361] = {185, 18, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+       [1362] = {185, 19, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+       [1363] = {185, 20, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+       [1364] = {185, 21, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+       [1365] = {185, 22, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+       [1366] = {185, 23, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+       [1367] = {185, 24, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+       [1368] = {185, 25, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+       [1369] = {185, 26, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+       [1370] = {185, 27, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+       [1371] = {185, 28, "DEV_MCASP11_MCASP_AHCLKR_POUT_0", "Output clock"},
+       [1372] = {185, 29, "DEV_MCASP11_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+       [1373] = {185, 30, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+       [1374] = {185, 31, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+       [1375] = {185, 32, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+       [1376] = {185, 33, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+       [1377] = {185, 34, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+       [1378] = {185, 35, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+       [1379] = {185, 36, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+       [1380] = {185, 37, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+       [1381] = {185, 38, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+       [1382] = {185, 39, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+       [1383] = {185, 40, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+       [1384] = {185, 41, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+       [1385] = {176, 0, "DEV_MCASP2_VBUSP_CLK", "Input clock"},
+       [1386] = {176, 1, "DEV_MCASP2_AUX_CLK", "Input muxed clock"},
+       [1387] = {176, 2, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+       [1388] = {176, 3, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+       [1389] = {176, 4, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+       [1390] = {176, 6, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+       [1391] = {176, 7, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+       [1392] = {176, 8, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+       [1393] = {176, 9, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+       [1394] = {176, 10, "DEV_MCASP2_MCASP_ACLKX_POUT_0", "Output clock"},
+       [1395] = {176, 11, "DEV_MCASP2_MCASP_ACLKX_PIN_0", "Input clock"},
+       [1396] = {176, 12, "DEV_MCASP2_MCASP_ACLKR_POUT_0", "Output clock"},
+       [1397] = {176, 13, "DEV_MCASP2_MCASP_ACLKR_PIN_0", "Input clock"},
+       [1398] = {176, 14, "DEV_MCASP2_MCASP_AHCLKX_POUT_0", "Output clock"},
+       [1399] = {176, 15, "DEV_MCASP2_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+       [1400] = {176, 16, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+       [1401] = {176, 17, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+       [1402] = {176, 18, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+       [1403] = {176, 19, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+       [1404] = {176, 20, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+       [1405] = {176, 21, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+       [1406] = {176, 22, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+       [1407] = {176, 23, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+       [1408] = {176, 24, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+       [1409] = {176, 25, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+       [1410] = {176, 26, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+       [1411] = {176, 27, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+       [1412] = {176, 28, "DEV_MCASP2_MCASP_AHCLKR_POUT_0", "Output clock"},
+       [1413] = {176, 29, "DEV_MCASP2_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+       [1414] = {176, 30, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+       [1415] = {176, 31, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+       [1416] = {176, 32, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+       [1417] = {176, 33, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+       [1418] = {176, 34, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+       [1419] = {176, 35, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+       [1420] = {176, 36, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+       [1421] = {176, 37, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+       [1422] = {176, 38, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+       [1423] = {176, 39, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+       [1424] = {176, 40, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+       [1425] = {176, 41, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+       [1426] = {177, 0, "DEV_MCASP3_VBUSP_CLK", "Input clock"},
+       [1427] = {177, 1, "DEV_MCASP3_AUX_CLK", "Input muxed clock"},
+       [1428] = {177, 2, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+       [1429] = {177, 3, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+       [1430] = {177, 4, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+       [1431] = {177, 6, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+       [1432] = {177, 7, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+       [1433] = {177, 8, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+       [1434] = {177, 9, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+       [1435] = {177, 10, "DEV_MCASP3_MCASP_ACLKX_POUT_0", "Output clock"},
+       [1436] = {177, 11, "DEV_MCASP3_MCASP_ACLKX_PIN_0", "Input clock"},
+       [1437] = {177, 12, "DEV_MCASP3_MCASP_ACLKR_POUT_0", "Output clock"},
+       [1438] = {177, 13, "DEV_MCASP3_MCASP_ACLKR_PIN_0", "Input clock"},
+       [1439] = {177, 14, "DEV_MCASP3_MCASP_AHCLKX_POUT_0", "Output clock"},
+       [1440] = {177, 15, "DEV_MCASP3_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+       [1441] = {177, 16, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+       [1442] = {177, 17, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+       [1443] = {177, 18, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+       [1444] = {177, 19, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+       [1445] = {177, 20, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+       [1446] = {177, 21, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+       [1447] = {177, 22, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+       [1448] = {177, 23, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+       [1449] = {177, 24, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+       [1450] = {177, 25, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+       [1451] = {177, 26, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+       [1452] = {177, 27, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+       [1453] = {177, 28, "DEV_MCASP3_MCASP_AHCLKR_POUT_0", "Output clock"},
+       [1454] = {177, 29, "DEV_MCASP3_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+       [1455] = {177, 30, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+       [1456] = {177, 31, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+       [1457] = {177, 32, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+       [1458] = {177, 33, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+       [1459] = {177, 34, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+       [1460] = {177, 35, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+       [1461] = {177, 36, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+       [1462] = {177, 37, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+       [1463] = {177, 38, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+       [1464] = {177, 39, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+       [1465] = {177, 40, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+       [1466] = {177, 41, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+       [1467] = {178, 0, "DEV_MCASP4_VBUSP_CLK", "Input clock"},
+       [1468] = {178, 1, "DEV_MCASP4_AUX_CLK", "Input muxed clock"},
+       [1469] = {178, 2, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+       [1470] = {178, 3, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+       [1471] = {178, 4, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+       [1472] = {178, 6, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+       [1473] = {178, 7, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+       [1474] = {178, 8, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+       [1475] = {178, 9, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+       [1476] = {178, 10, "DEV_MCASP4_MCASP_ACLKX_POUT_0", "Output clock"},
+       [1477] = {178, 11, "DEV_MCASP4_MCASP_ACLKX_PIN_0", "Input clock"},
+       [1478] = {178, 12, "DEV_MCASP4_MCASP_ACLKR_POUT_0", "Output clock"},
+       [1479] = {178, 13, "DEV_MCASP4_MCASP_ACLKR_PIN_0", "Input clock"},
+       [1480] = {178, 14, "DEV_MCASP4_MCASP_AHCLKX_POUT_0", "Output clock"},
+       [1481] = {178, 15, "DEV_MCASP4_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+       [1482] = {178, 16, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+       [1483] = {178, 17, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+       [1484] = {178, 18, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+       [1485] = {178, 19, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+       [1486] = {178, 20, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+       [1487] = {178, 21, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+       [1488] = {178, 22, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+       [1489] = {178, 23, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+       [1490] = {178, 24, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+       [1491] = {178, 25, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+       [1492] = {178, 26, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+       [1493] = {178, 27, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+       [1494] = {178, 28, "DEV_MCASP4_MCASP_AHCLKR_POUT_0", "Output clock"},
+       [1495] = {178, 29, "DEV_MCASP4_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+       [1496] = {178, 30, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+       [1497] = {178, 31, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+       [1498] = {178, 32, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+       [1499] = {178, 33, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+       [1500] = {178, 34, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+       [1501] = {178, 35, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+       [1502] = {178, 36, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+       [1503] = {178, 37, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+       [1504] = {178, 38, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+       [1505] = {178, 39, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+       [1506] = {178, 40, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+       [1507] = {178, 41, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+       [1508] = {179, 0, "DEV_MCASP5_VBUSP_CLK", "Input clock"},
+       [1509] = {179, 1, "DEV_MCASP5_AUX_CLK", "Input muxed clock"},
+       [1510] = {179, 2, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
+       [1511] = {179, 3, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
+       [1512] = {179, 4, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
+       [1513] = {179, 6, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
+       [1514] = {179, 7, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
+       [1515] = {179, 8, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
+       [1516] = {179, 9, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
+       [1517] = {179, 10, "DEV_MCASP5_MCASP_ACLKX_POUT_0", "Output clock"},
+       [1518] = {179, 11, "DEV_MCASP5_MCASP_ACLKX_PIN_0", "Input clock"},
+       [1519] = {179, 12, "DEV_MCASP5_MCASP_ACLKR_POUT_0", "Output clock"},
+       [1520] = {179, 13, "DEV_MCASP5_MCASP_ACLKR_PIN_0", "Input clock"},
+       [1521] = {179, 14, "DEV_MCASP5_MCASP_AHCLKX_POUT_0", "Output clock"},
+       [1522] = {179, 15, "DEV_MCASP5_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+       [1523] = {179, 16, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+       [1524] = {179, 17, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+       [1525] = {179, 18, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+       [1526] = {179, 19, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+       [1527] = {179, 20, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+       [1528] = {179, 21, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+       [1529] = {179, 22, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+       [1530] = {179, 23, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+       [1531] = {179, 24, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+       [1532] = {179, 25, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+       [1533] = {179, 26, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+       [1534] = {179, 27, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+       [1535] = {179, 28, "DEV_MCASP5_MCASP_AHCLKR_POUT_0", "Output clock"},
+       [1536] = {179, 29, "DEV_MCASP5_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+       [1537] = {179, 30, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+       [1538] = {179, 31, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+       [1539] = {179, 32, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+       [1540] = {179, 33, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+       [1541] = {179, 34, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+       [1542] = {179, 35, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+       [1543] = {179, 36, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+       [1544] = {179, 37, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+       [1545] = {179, 38, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+       [1546] = {179, 39, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+       [1547] = {179, 40, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+       [1548] = {179, 41, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+       [1549] = {180, 0, "DEV_MCASP6_VBUSP_CLK", "Input clock"},
+       [1550] = {180, 1, "DEV_MCASP6_AUX_CLK", "Input muxed clock"},
+       [1551] = {180, 2, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
+       [1552] = {180, 3, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
+       [1553] = {180, 4, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
+       [1554] = {180, 6, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
+       [1555] = {180, 7, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
+       [1556] = {180, 8, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
+       [1557] = {180, 9, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
+       [1558] = {180, 10, "DEV_MCASP6_MCASP_ACLKX_POUT_0", "Output clock"},
+       [1559] = {180, 11, "DEV_MCASP6_MCASP_ACLKX_PIN_0", "Input clock"},
+       [1560] = {180, 12, "DEV_MCASP6_MCASP_ACLKR_POUT_0", "Output clock"},
+       [1561] = {180, 13, "DEV_MCASP6_MCASP_ACLKR_PIN_0", "Input clock"},
+       [1562] = {180, 14, "DEV_MCASP6_MCASP_AHCLKX_POUT_0", "Output clock"},
+       [1563] = {180, 15, "DEV_MCASP6_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+       [1564] = {180, 16, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+       [1565] = {180, 17, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+       [1566] = {180, 18, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+       [1567] = {180, 19, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+       [1568] = {180, 20, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+       [1569] = {180, 21, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+       [1570] = {180, 22, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+       [1571] = {180, 23, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+       [1572] = {180, 24, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+       [1573] = {180, 25, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+       [1574] = {180, 26, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+       [1575] = {180, 27, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+       [1576] = {180, 28, "DEV_MCASP6_MCASP_AHCLKR_POUT_0", "Output clock"},
+       [1577] = {180, 29, "DEV_MCASP6_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+       [1578] = {180, 30, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+       [1579] = {180, 31, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+       [1580] = {180, 32, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+       [1581] = {180, 33, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+       [1582] = {180, 34, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+       [1583] = {180, 35, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+       [1584] = {180, 36, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+       [1585] = {180, 37, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+       [1586] = {180, 38, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+       [1587] = {180, 39, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+       [1588] = {180, 40, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+       [1589] = {180, 41, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+       [1590] = {181, 0, "DEV_MCASP7_VBUSP_CLK", "Input clock"},
+       [1591] = {181, 1, "DEV_MCASP7_AUX_CLK", "Input muxed clock"},
+       [1592] = {181, 2, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
+       [1593] = {181, 3, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
+       [1594] = {181, 4, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
+       [1595] = {181, 6, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
+       [1596] = {181, 7, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
+       [1597] = {181, 8, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
+       [1598] = {181, 9, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
+       [1599] = {181, 10, "DEV_MCASP7_MCASP_ACLKX_POUT_0", "Output clock"},
+       [1600] = {181, 11, "DEV_MCASP7_MCASP_ACLKX_PIN_0", "Input clock"},
+       [1601] = {181, 12, "DEV_MCASP7_MCASP_ACLKR_POUT_0", "Output clock"},
+       [1602] = {181, 13, "DEV_MCASP7_MCASP_ACLKR_PIN_0", "Input clock"},
+       [1603] = {181, 14, "DEV_MCASP7_MCASP_AHCLKX_POUT_0", "Output clock"},
+       [1604] = {181, 15, "DEV_MCASP7_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+       [1605] = {181, 16, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+       [1606] = {181, 17, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+       [1607] = {181, 18, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+       [1608] = {181, 19, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+       [1609] = {181, 20, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+       [1610] = {181, 21, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+       [1611] = {181, 22, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+       [1612] = {181, 23, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+       [1613] = {181, 24, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+       [1614] = {181, 25, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+       [1615] = {181, 26, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+       [1616] = {181, 27, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+       [1617] = {181, 28, "DEV_MCASP7_MCASP_AHCLKR_POUT_0", "Output clock"},
+       [1618] = {181, 29, "DEV_MCASP7_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+       [1619] = {181, 30, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
+       [1620] = {181, 31, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
+       [1621] = {181, 32, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
+       [1622] = {181, 33, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
+     &nb