soc: am65x_sr2: Add sec proxy info
authorLokesh Vutla <lokeshvutla@ti.com>
Fri, 10 Apr 2020 10:43:33 +0000 (16:13 +0530)
committerLokesh Vutla <lokeshvutla@ti.com>
Wed, 15 Apr 2020 03:29:23 +0000 (08:59 +0530)
Add TISCI Secure proxy info for AM65x sr2 devices. Data derived from
sysfw 2020.02 Documentation.

Tested-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Makefile
common/socinfo.c
soc/am65x_sr2/am65x_sr2_sec_proxy_info.c [new file with mode: 0644]
soc/am65x_sr2/am65x_sr2_sec_proxy_info.h [new file with mode: 0644]

index f4fec0c448f8857e06a9212a8132018a84245b9a..6a6c52deb71a67d0ec78221721029fab08906bba 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -79,7 +79,8 @@ AM65XSOURCES =\
              soc/am65x/am65x_processors_info.c \
              soc/am65x/am65x_devices_info.c \
              soc/am65x/am65x_clocks_info.c \
-             soc/am65x_sr2/am65x_sr2_host_info.c
+             soc/am65x_sr2/am65x_sr2_host_info.c \
+             soc/am65x_sr2/am65x_sr2_sec_proxy_info.c
 
 J721ESOURCES =\
              soc/j721e/j721e_host_info.c \
index fb0cbaf8a9b0dc61150678407e1133653644a046..dc26cf8dd2e071df393cba54a81ed38883f3f436 100644 (file)
@@ -43,6 +43,7 @@
 #include <soc/am65x/am65x_devices_info.h>
 #include <soc/am65x/am65x_clocks_info.h>
 #include <soc/am65x_sr2/am65x_sr2_host_info.h>
+#include <soc/am65x_sr2/am65x_sr2_sec_proxy_info.h>
 #include <soc/j721e/j721e_host_info.h>
 #include <soc/j721e/j721e_sec_proxy_info.h>
 #include <soc/j721e/j721e_processors_info.h>
@@ -111,6 +112,10 @@ static void am654_sr2_init(void)
 
        sci_info->host_info = am65x_sr2_host_info;
        sci_info->num_hosts = AM65X_SR2_MAX_HOST_IDS;
+       sci_info->sp_info[MAIN_SEC_PROXY] = am65x_sr2_main_sp_info;
+       sci_info->num_sp_threads[MAIN_SEC_PROXY] = AM65X_SR2_MAIN_SEC_PROXY_THREADS;
+       sci_info->sp_info[MCU_SEC_PROXY] = am65x_sr2_mcu_sp_info;
+       sci_info->num_sp_threads[MCU_SEC_PROXY] = AM65X_SR2_MCU_SEC_PROXY_THREADS;
 }
 
 static void j721e_init(void)
diff --git a/soc/am65x_sr2/am65x_sr2_sec_proxy_info.c b/soc/am65x_sr2/am65x_sr2_sec_proxy_info.c
new file mode 100644 (file)
index 0000000..7af4796
--- /dev/null
@@ -0,0 +1,127 @@
+/*
+ * AM65X_SR2 Sec Proxy Info
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <tisci.h>
+#include <socinfo.h>
+
+struct ti_sci_sec_proxy_info am65x_sr2_main_sp_info[] = {
+       [0] = {0, "read", 2, "A53_0", "notify"},
+       [1] = {1, "read", 30, "A53_0", "response"},
+       [2] = {2, "write", 10, "A53_0", "high_priority"},
+       [3] = {3, "write", 20, "A53_0", "low_priority"},
+       [4] = {4, "write", 2, "A53_0", "notify_resp"},
+       [5] = {5, "read", 2, "A53_1", "notify"},
+       [6] = {6, "read", 30, "A53_1", "response"},
+       [7] = {7, "write", 10, "A53_1", "high_priority"},
+       [8] = {8, "write", 20, "A53_1", "low_priority"},
+       [9] = {9, "write", 2, "A53_1", "notify_resp"},
+       [10] = {10, "read", 2, "A53_2", "notify"},
+       [11] = {11, "read", 22, "A53_2", "response"},
+       [12] = {12, "write", 2, "A53_2", "high_priority"},
+       [13] = {13, "write", 20, "A53_2", "low_priority"},
+       [14] = {14, "write", 2, "A53_2", "notify_resp"},
+       [15] = {15, "read", 2, "A53_3", "notify"},
+       [16] = {16, "read", 7, "A53_3", "response"},
+       [17] = {17, "write", 2, "A53_3", "high_priority"},
+       [18] = {18, "write", 5, "A53_3", "low_priority"},
+       [19] = {19, "write", 2, "A53_3", "notify_resp"},
+       [20] = {20, "read", 2, "A53_4", "notify"},
+       [21] = {21, "read", 5, "A53_4", "response"},
+       [22] = {22, "write", 2, "A53_4", "high_priority"},
+       [23] = {23, "write", 5, "A53_4", "low_priority"},
+       [24] = {24, "write", 2, "A53_4", "notify_resp"},
+       [25] = {25, "read", 2, "A53_5", "notify"},
+       [26] = {26, "read", 5, "A53_5", "response"},
+       [27] = {27, "write", 2, "A53_5", "high_priority"},
+       [28] = {28, "write", 5, "A53_5", "low_priority"},
+       [29] = {29, "write", 2, "A53_5", "notify_resp"},
+       [30] = {30, "read", 2, "A53_6", "notify"},
+       [31] = {31, "read", 5, "A53_6", "response"},
+       [32] = {32, "write", 2, "A53_6", "high_priority"},
+       [33] = {33, "write", 5, "A53_6", "low_priority"},
+       [34] = {34, "write", 2, "A53_6", "notify_resp"},
+       [35] = {35, "read", 2, "A53_7", "notify"},
+       [36] = {36, "read", 5, "A53_7", "response"},
+       [37] = {37, "write", 2, "A53_7", "high_priority"},
+       [38] = {38, "write", 5, "A53_7", "low_priority"},
+       [39] = {39, "write", 2, "A53_7", "notify_resp"},
+       [40] = {40, "read", 2, "ICSSG_0", "notify"},
+       [41] = {41, "read", 7, "ICSSG_0", "response"},
+       [42] = {42, "write", 2, "ICSSG_0", "high_priority"},
+       [43] = {43, "write", 5, "ICSSG_0", "low_priority"},
+       [44] = {44, "write", 2, "ICSSG_0", "notify_resp"},
+       [45] = {45, "read", 2, "ICSSG_1", "notify"},
+       [46] = {46, "read", 4, "ICSSG_1", "response"},
+       [47] = {47, "write", 2, "ICSSG_1", "high_priority"},
+       [48] = {48, "write", 2, "ICSSG_1", "low_priority"},
+       [49] = {49, "write", 2, "ICSSG_1", "notify_resp"},
+       [50] = {50, "read", 2, "ICSSG_2", "notify"},
+       [51] = {51, "read", 4, "ICSSG_2", "response"},
+       [52] = {52, "write", 2, "ICSSG_2", "high_priority"},
+       [53] = {53, "write", 2, "ICSSG_2", "low_priority"},
+       [54] = {54, "write", 2, "ICSSG_2", "notify_resp"},
+       [55] = {55, "read", 2, "GPU_0", "notify"},
+       [56] = {56, "read", 7, "GPU_0", "response"},
+       [57] = {57, "write", 2, "GPU_0", "high_priority"},
+       [58] = {58, "write", 5, "GPU_0", "low_priority"},
+       [59] = {59, "write", 2, "GPU_0", "notify_resp"},
+       [60] = {60, "read", 2, "GPU_1", "notify"},
+       [61] = {61, "read", 5, "GPU_1", "response"},
+       [62] = {62, "write", 2, "GPU_1", "high_priority"},
+       [63] = {63, "write", 3, "GPU_1", "low_priority"},
+       [64] = {64, "write", 2, "GPU_1", "notify_resp"},
+};
+
+struct ti_sci_sec_proxy_info am65x_sr2_mcu_sp_info[] = {
+       [0] = {0, "read", 2, "R5_0", "notify"},
+       [1] = {1, "read", 7, "R5_0", "response"},
+       [2] = {2, "write", 2, "R5_0", "high_priority"},
+       [3] = {3, "write", 5, "R5_0", "low_priority"},
+       [4] = {4, "write", 2, "R5_0", "notify_resp"},
+       [5] = {5, "read", 2, "R5_1", "notify"},
+       [6] = {6, "read", 7, "R5_1", "response"},
+       [7] = {7, "write", 2, "R5_1", "high_priority"},
+       [8] = {8, "write", 5, "R5_1", "low_priority"},
+       [9] = {9, "write", 2, "R5_1", "notify_resp"},
+       [10] = {10, "read", 1, "R5_2", "notify"},
+       [11] = {11, "read", 2, "R5_2", "response"},
+       [12] = {12, "write", 1, "R5_2", "high_priority"},
+       [13] = {13, "write", 1, "R5_2", "low_priority"},
+       [14] = {14, "write", 1, "R5_2", "notify_resp"},
+       [15] = {15, "read", 1, "R5_3", "notify"},
+       [16] = {16, "read", 2, "R5_3", "response"},
+       [17] = {17, "write", 1, "R5_3", "high_priority"},
+       [18] = {18, "write", 1, "R5_3", "low_priority"},
+       [19] = {19, "write", 1, "R5_3", "notify_resp"},
+};
diff --git a/soc/am65x_sr2/am65x_sr2_sec_proxy_info.h b/soc/am65x_sr2/am65x_sr2_sec_proxy_info.h
new file mode 100644 (file)
index 0000000..9da12bd
--- /dev/null
@@ -0,0 +1,44 @@
+/*
+ * AM65X_SR2 Sec Proxy Info
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __AM65X_SR2_SEC_PROXY_INFO_H
+#define __AM65X_SR2_SEC_PROXY_INFO_H
+
+#define AM65X_SR2_MAIN_SEC_PROXY_THREADS       65
+#define AM65X_SR2_MCU_SEC_PROXY_THREADS        20
+
+extern struct ti_sci_sec_proxy_info am65x_sr2_main_sp_info[];
+extern struct ti_sci_sec_proxy_info am65x_sr2_mcu_sp_info[];
+
+#endif /* __AM65X_SR2_SEC_PROXY_INFO_H */
\ No newline at end of file