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raw | patch | inline | side by side (parent: cd36389)
raw | patch | inline | side by side (parent: cd36389)
author | Bryan Brattlof <bb@ti.com> | |
Wed, 20 Apr 2022 15:05:42 +0000 (10:05 -0500) | ||
committer | Bryan Brattlof <bb@ti.com> | |
Wed, 18 May 2022 22:24:19 +0000 (17:24 -0500) |
TISCI power management APIs define Device IDs and Clock IDs as
parameters, allowing us granular control of the clocks for a
particular subsystem
Provide the information for the Clock IDs that identify incoming and
outgoing clock signals for subsystems in the J721S2
Signed-off-by: Bryan Brattlof <bb@ti.com>
parameters, allowing us granular control of the clocks for a
particular subsystem
Provide the information for the Clock IDs that identify incoming and
outgoing clock signals for subsystems in the J721S2
Signed-off-by: Bryan Brattlof <bb@ti.com>
Makefile | patch | blob | history | |
common/socinfo.c | patch | blob | history | |
soc/j721s2/j721s2_clocks_info.c | [new file with mode: 0644] | patch | blob |
soc/j721s2/j721s2_clocks_info.h | [new file with mode: 0644] | patch | blob |
diff --git a/Makefile b/Makefile
index d384db1b784701f222e8af01a7832b304814b770..53d67dd6721e9ef4f260cf87f21ccf0e7764b92e 100644 (file)
--- a/Makefile
+++ b/Makefile
soc/am62x/am62x_sec_proxy_info.c
J721S2SOURCES =\
- soc/j721s2/j721s2_devices_info.c
+ soc/j721s2/j721s2_devices_info.c \
+ soc/j721s2/j721s2_clocks_info.c
COMMONOBJECTS= $(COMMONSOURCES:.c=.o)
AM65XOBJECTS= $(AM65XSOURCES:.c=.o)
diff --git a/common/socinfo.c b/common/socinfo.c
index 5fb5c1791e3eda931a60e2519fd4d1e2430d19e4..c9297749405c12acb90b71515c0d32e1295a6385 100644 (file)
--- a/common/socinfo.c
+++ b/common/socinfo.c
#include <soc/am62x/am62x_rm_info.h>
#include <soc/am62x/am62x_sec_proxy_info.h>
#include <soc/j721s2/j721s2_devices_info.h>
+#include <soc/j721s2/j721s2_clocks_info.h>
/* Assuming these addresses and definitions stay common across K3 devices */
#define CTRLMMR_WKUP_JTAG_DEVICE_ID 0x43000018
{
struct ti_sci_info *sci_info = &soc_info.sci_info;
+ sci_info->clocks_info = j721s2_clocks_info;
+ sci_info->num_clocks = J721S2_MAX_CLOCKS;
sci_info->devices_info = j721s2_devices_info;
sci_info->num_devices = J721S2_MAX_DEVICES;
soc_info.host_id = DEFAULT_HOST_ID;
diff --git a/soc/j721s2/j721s2_clocks_info.c b/soc/j721s2/j721s2_clocks_info.c
--- /dev/null
@@ -0,0 +1,2062 @@
+/*
+ * J721S2 Clocks Info
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <tisci.h>
+#include <socinfo.h>
+
+struct ti_sci_clocks_info j721s2_clocks_info[] = {
+ [0] = {4, 0, "DEV_A72SS0_ARM_CLK_CLK", "Input clock"},
+ [1] = {4, 1, "DEV_A72SS0_MSMC_CLK", "Input clock"},
+ [2] = {4, 2, "DEV_A72SS0_PLL_CTRL_CLK", "Input clock"},
+ [3] = {4, 6, "DEV_A72SS0_A72_DIVH_CLK8_OBSCLK_OUT_CLK", "Output clock"},
+ [4] = {202, 0, "DEV_A72SS0_CORE0_ARM_CLK_CLK", "Input clock"},
+ [5] = {203, 0, "DEV_A72SS0_CORE1_ARM_CLK_CLK", "Input clock"},
+ [6] = {134, 0, "DEV_AGGR_ATB0_DBG_CLK", "Input clock"},
+ [7] = {2, 0, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT", "Output clock"},
+ [8] = {2, 1, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1", "Output clock"},
+ [9] = {2, 2, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2", "Output clock"},
+ [10] = {2, 3, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3", "Output clock"},
+ [11] = {2, 4, "DEV_ATL0_ATL_CLK", "Input muxed clock"},
+ [12] = {2, 5, "DEV_ATL0_ATL_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT1_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+ [13] = {2, 6, "DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+ [14] = {2, 9, "DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+ [15] = {2, 10, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+ [16] = {2, 11, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+ [17] = {2, 13, "DEV_ATL0_VBUS_CLK", "Input clock"},
+ [18] = {2, 14, "DEV_ATL0_ATL_IO_PORT_AWS", "Input muxed clock"},
+ [19] = {2, 15, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"},
+ [20] = {2, 16, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"},
+ [21] = {2, 17, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"},
+ [22] = {2, 18, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"},
+ [23] = {2, 19, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"},
+ [24] = {2, 27, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"},
+ [25] = {2, 28, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"},
+ [26] = {2, 29, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"},
+ [27] = {2, 30, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"},
+ [28] = {2, 31, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"},
+ [29] = {2, 39, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"},
+ [30] = {2, 40, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"},
+ [31] = {2, 47, "DEV_ATL0_ATL_IO_PORT_AWS_1", "Input muxed clock"},
+ [32] = {2, 48, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"},
+ [33] = {2, 49, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"},
+ [34] = {2, 50, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"},
+ [35] = {2, 51, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"},
+ [36] = {2, 52, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"},
+ [37] = {2, 60, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"},
+ [38] = {2, 61, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"},
+ [39] = {2, 62, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"},
+ [40] = {2, 63, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"},
+ [41] = {2, 64, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"},
+ [42] = {2, 72, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"},
+ [43] = {2, 73, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"},
+ [44] = {2, 80, "DEV_ATL0_ATL_IO_PORT_AWS_2", "Input muxed clock"},
+ [45] = {2, 81, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"},
+ [46] = {2, 82, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"},
+ [47] = {2, 83, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"},
+ [48] = {2, 84, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"},
+ [49] = {2, 85, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"},
+ [50] = {2, 93, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"},
+ [51] = {2, 94, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"},
+ [52] = {2, 95, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"},
+ [53] = {2, 96, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"},
+ [54] = {2, 97, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"},
+ [55] = {2, 105, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"},
+ [56] = {2, 106, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"},
+ [57] = {2, 113, "DEV_ATL0_ATL_IO_PORT_AWS_3", "Input muxed clock"},
+ [58] = {2, 114, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"},
+ [59] = {2, 115, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"},
+ [60] = {2, 116, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"},
+ [61] = {2, 117, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"},
+ [62] = {2, 118, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"},
+ [63] = {2, 126, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"},
+ [64] = {2, 127, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"},
+ [65] = {2, 128, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"},
+ [66] = {2, 129, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"},
+ [67] = {2, 130, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"},
+ [68] = {2, 138, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"},
+ [69] = {2, 139, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"},
+ [70] = {2, 146, "DEV_ATL0_ATL_IO_PORT_BWS", "Input muxed clock"},
+ [71] = {2, 147, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"},
+ [72] = {2, 148, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"},
+ [73] = {2, 149, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"},
+ [74] = {2, 150, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"},
+ [75] = {2, 151, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"},
+ [76] = {2, 159, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"},
+ [77] = {2, 160, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"},
+ [78] = {2, 161, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"},
+ [79] = {2, 162, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"},
+ [80] = {2, 163, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"},
+ [81] = {2, 171, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"},
+ [82] = {2, 172, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"},
+ [83] = {2, 179, "DEV_ATL0_ATL_IO_PORT_BWS_1", "Input muxed clock"},
+ [84] = {2, 180, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"},
+ [85] = {2, 181, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"},
+ [86] = {2, 182, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"},
+ [87] = {2, 183, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"},
+ [88] = {2, 184, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"},
+ [89] = {2, 192, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"},
+ [90] = {2, 193, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"},
+ [91] = {2, 194, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"},
+ [92] = {2, 195, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"},
+ [93] = {2, 196, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"},
+ [94] = {2, 204, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"},
+ [95] = {2, 205, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"},
+ [96] = {2, 212, "DEV_ATL0_ATL_IO_PORT_BWS_2", "Input muxed clock"},
+ [97] = {2, 213, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"},
+ [98] = {2, 214, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"},
+ [99] = {2, 215, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"},
+ [100] = {2, 216, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"},
+ [101] = {2, 217, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"},
+ [102] = {2, 225, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"},
+ [103] = {2, 226, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"},
+ [104] = {2, 227, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"},
+ [105] = {2, 228, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"},
+ [106] = {2, 229, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"},
+ [107] = {2, 237, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"},
+ [108] = {2, 238, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"},
+ [109] = {2, 245, "DEV_ATL0_ATL_IO_PORT_BWS_3", "Input muxed clock"},
+ [110] = {2, 246, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"},
+ [111] = {2, 247, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"},
+ [112] = {2, 248, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"},
+ [113] = {2, 249, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"},
+ [114] = {2, 250, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"},
+ [115] = {2, 258, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"},
+ [116] = {2, 259, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"},
+ [117] = {2, 260, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"},
+ [118] = {2, 261, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"},
+ [119] = {2, 262, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"},
+ [120] = {2, 270, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"},
+ [121] = {2, 271, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"},
+ [122] = {157, 1, "DEV_BOARD0_DSI0_TXCLKN_IN", "Input clock"},
+ [123] = {157, 2, "DEV_BOARD0_I2C4_SCL_OUT", "Output clock"},
+ [124] = {157, 4, "DEV_BOARD0_CSI0_TXCLKN_IN", "Input clock"},
+ [125] = {157, 5, "DEV_BOARD0_CSI0_RXCLKP_OUT", "Output clock"},
+ [126] = {157, 6, "DEV_BOARD0_HYP0_TXPMCLK_IN", "Input clock"},
+ [127] = {157, 7, "DEV_BOARD0_MCAN1_RX_OUT", "Output clock"},
+ [128] = {157, 8, "DEV_BOARD0_MCAN17_RX_OUT", "Output clock"},
+ [129] = {157, 9, "DEV_BOARD0_MMC1_CLK_IN", "Input clock"},
+ [130] = {157, 10, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"},
+ [131] = {157, 11, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
+ [132] = {157, 12, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
+ [133] = {157, 43, "DEV_BOARD0_I2C0_SCL_IN", "Input clock"},
+ [134] = {157, 44, "DEV_BOARD0_SPI7_CLK_OUT", "Output clock"},
+ [135] = {157, 45, "DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT", "Output clock"},
+ [136] = {157, 46, "DEV_BOARD0_MCASP3_ACLKR_IN", "Input clock"},
+ [137] = {157, 47, "DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT", "Output clock"},
+ [138] = {157, 48, "DEV_BOARD0_MCU_OSPI0_DQS_OUT", "Output clock"},
+ [139] = {157, 49, "DEV_BOARD0_HYP0_TXFLCLK_OUT", "Output clock"},
+ [140] = {157, 50, "DEV_BOARD0_MCU_OSPI0_LBCLKO_OUT", "Output clock"},
+ [141] = {157, 51, "DEV_BOARD0_MCASP3_ACLKX_IN", "Input clock"},
+ [142] = {157, 52, "DEV_BOARD0_HYP0_RXPMCLK_OUT", "Output clock"},
+ [143] = {157, 54, "DEV_BOARD0_MCASP1_ACLKX_IN", "Input clock"},
+ [144] = {157, 55, "DEV_BOARD0_MCU_SPI1_CLK_IN", "Input clock"},
+ [145] = {157, 56, "DEV_BOARD0_MCAN9_RX_OUT", "Output clock"},
+ [146] = {157, 57, "DEV_BOARD0_I2C6_SCL_OUT", "Output clock"},
+ [147] = {157, 58, "DEV_BOARD0_MCU_SPI0_CLK_OUT", "Output clock"},
+ [148] = {157, 59, "DEV_BOARD0_OBSCLK1_IN", "Input clock"},
+ [149] = {157, 60, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [150] = {157, 61, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [151] = {157, 62, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [152] = {157, 63, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [153] = {157, 64, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [154] = {157, 65, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [155] = {157, 66, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [156] = {157, 67, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [157] = {157, 72, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [158] = {157, 73, "DEV_BOARD0_OBSCLK1_IN_PARENT_OBSCLK1_MUX_OUT0", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [159] = {157, 74, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [160] = {157, 76, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [161] = {157, 77, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [162] = {157, 79, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [163] = {157, 85, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [164] = {157, 86, "DEV_BOARD0_OBSCLK1_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [165] = {157, 87, "DEV_BOARD0_OBSCLK1_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [166] = {157, 88, "DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [167] = {157, 89, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [168] = {157, 90, "DEV_BOARD0_OBSCLK1_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [169] = {157, 91, "DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+ [170] = {157, 92, "DEV_BOARD0_MCU_OSPI1_LBCLKO_OUT", "Output clock"},
+ [171] = {157, 93, "DEV_BOARD0_MCASP3_ACLKX_OUT", "Output clock"},
+ [172] = {157, 95, "DEV_BOARD0_MCASP2_AFSR_OUT", "Output clock"},
+ [173] = {157, 96, "DEV_BOARD0_TRC_CLK_IN", "Input clock"},
+ [174] = {157, 100, "DEV_BOARD0_CSI1_RXCLKN_OUT", "Output clock"},
+ [175] = {157, 102, "DEV_BOARD0_MCASP0_ACLKX_OUT", "Output clock"},
+ [176] = {157, 103, "DEV_BOARD0_MCU_OSPI0_CLK_IN", "Input clock"},
+ [177] = {157, 105, "DEV_BOARD0_GPMC0_FCLK_MUX_IN", "Input clock"},
+ [178] = {157, 106, "DEV_BOARD0_MCU_SPI0_CLK_IN", "Input clock"},
+ [179] = {157, 108, "DEV_BOARD0_MCU_RGMII1_RXC_OUT", "Output clock"},
+ [180] = {157, 109, "DEV_BOARD0_MCASP0_AFSR_OUT", "Output clock"},
+ [181] = {157, 110, "DEV_BOARD0_CSI1_RXCLKP_OUT", "Output clock"},
+ [182] = {157, 111, "DEV_BOARD0_MCU_SYSCLKOUT0_IN", "Input clock"},
+ [183] = {157, 112, "DEV_BOARD0_SPI5_CLK_OUT", "Output clock"},
+ [184] = {157, 113, "DEV_BOARD0_MCU_RMII1_REF_CLK_OUT", "Output clock"},
+ [185] = {157, 114, "DEV_BOARD0_SPI0_CLK_OUT", "Output clock"},
+ [186] = {157, 116, "DEV_BOARD0_SPI6_CLK_OUT", "Output clock"},
+ [187] = {157, 117, "DEV_BOARD0_I2C1_SCL_IN", "Input clock"},
+ [188] = {157, 118, "DEV_BOARD0_DSI1_TXCLKP_IN", "Input clock"},
+ [189] = {157, 119, "DEV_BOARD0_MCAN0_RX_OUT", "Output clock"},
+ [190] = {157, 120, "DEV_BOARD0_MCASP0_ACLKR_OUT", "Output clock"},
+ [191] = {157, 121, "DEV_BOARD0_RMII_REF_CLK_OUT", "Output clock"},
+ [192] = {157, 123, "DEV_BOARD0_MCAN14_RX_OUT", "Output clock"},
+ [193] = {157, 125, "DEV_BOARD0_MCU_I2C0_SCL_OUT", "Output clock"},
+ [194] = {157, 126, "DEV_BOARD0_SPI6_CLK_IN", "Input clock"},
+ [195] = {157, 128, "DEV_BOARD0_MCASP3_AFSX_OUT", "Output clock"},
+ [196] = {157, 129, "DEV_BOARD0_MCU_SPI1_CLK_OUT", "Output clock"},
+ [197] = {157, 130, "DEV_BOARD0_SERDES0_REFCLK_P_IN", "Input clock"},
+ [198] = {157, 131, "DEV_BOARD0_SERDES0_REFCLK_P_OUT", "Output clock"},
+ [199] = {157, 132, "DEV_BOARD0_MCASP1_ACLKR_IN", "Input clock"},
+ [200] = {157, 134, "DEV_BOARD0_MCASP1_AFSX_OUT", "Output clock"},
+ [201] = {157, 135, "DEV_BOARD0_SPI1_CLK_OUT", "Output clock"},
+ [202] = {157, 136, "DEV_BOARD0_I2C3_SCL_IN", "Input clock"},
+ [203] = {157, 137, "DEV_BOARD0_MCU_I2C0_SCL_IN", "Input clock"},
+ [204] = {157, 138, "DEV_BOARD0_HYP1_TXPMCLK_IN", "Input clock"},
+ [205] = {157, 139, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN", "Input muxed clock"},
+ [206] = {157, 140, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [207] = {157, 141, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [208] = {157, 142, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [209] = {157, 143, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [210] = {157, 144, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [211] = {157, 152, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [212] = {157, 153, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [213] = {157, 154, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [214] = {157, 155, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [215] = {157, 156, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [216] = {157, 164, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [217] = {157, 165, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [218] = {157, 166, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [219] = {157, 167, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [220] = {157, 168, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+ [221] = {157, 173, "DEV_BOARD0_MCASP2_ACLKX_OUT", "Output clock"},
+ [222] = {157, 175, "DEV_BOARD0_MMC1_CLKLB_OUT", "Output clock"},
+ [223] = {157, 176, "DEV_BOARD0_WKUP_I2C0_SCL_OUT", "Output clock"},
+ [224] = {157, 177, "DEV_BOARD0_SYSCLKOUT0_IN", "Input clock"},
+ [225] = {157, 178, "DEV_BOARD0_I2C1_SCL_OUT", "Output clock"},
+ [226] = {157, 179, "DEV_BOARD0_MCU_OSPI0_LBCLKO_IN", "Input clock"},
+ [227] = {157, 180, "DEV_BOARD0_SPI3_CLK_IN", "Input clock"},
+ [228] = {157, 181, "DEV_BOARD0_MCAN13_RX_OUT", "Output clock"},
+ [229] = {157, 182, "DEV_BOARD0_WKUP_I2C0_SCL_IN", "Input clock"},
+ [230] = {157, 183, "DEV_BOARD0_DSI1_TXCLKN_IN", "Input clock"},
+ [231] = {157, 184, "DEV_BOARD0_CPTS0_RFT_CLK_OUT", "Output clock"},
+ [232] = {157, 185, "DEV_BOARD0_MCU_I2C1_SCL_OUT", "Output clock"},
+ [233] = {157, 186, "DEV_BOARD0_MCASP0_ACLKR_IN", "Input clock"},
+ [234] = {157, 187, "DEV_BOARD0_MCU_OSPI1_LBCLKO_IN", "Input clock"},
+ [235] = {157, 188, "DEV_BOARD0_MCASP0_AFSX_OUT", "Output clock"},
+ [236] = {157, 190, "DEV_BOARD0_MCU_I3C0_SDA_OUT", "Output clock"},
+ [237] = {157, 191, "DEV_BOARD0_MCASP0_ACLKX_IN", "Input clock"},
+ [238] = {157, 192, "DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT", "Output clock"},
+ [239] = {157, 193, "DEV_BOARD0_MCAN3_RX_OUT", "Output clock"},
+ [240] = {157, 194, "DEV_BOARD0_MMC1_CLKLB_IN", "Input clock"},
+ [241] = {157, 195, "DEV_BOARD0_MCASP2_ACLKR_OUT", "Output clock"},
+ [242] = {157, 198, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"},
+ [243] = {157, 199, "DEV_BOARD0_MCASP1_ACLKR_OUT", "Output clock"},
+ [244] = {157, 200, "DEV_BOARD0_MCAN4_RX_OUT", "Output clock"},
+ [245] = {157, 201, "DEV_BOARD0_MCASP4_ACLKX_OUT", "Output clock"},
+ [246] = {157, 202, "DEV_BOARD0_CSI1_TXCLKP_IN", "Input clock"},
+ [247] = {157, 203, "DEV_BOARD0_MCASP3_AFSR_OUT", "Output clock"},
+ [248] = {157, 204, "DEV_BOARD0_LED_CLK_OUT", "Output clock"},
+ [249] = {157, 206, "DEV_BOARD0_MCAN7_RX_OUT", "Output clock"},
+ [250] = {157, 207, "DEV_BOARD0_MCU_MDIO0_MDC_IN", "Input clock"},
+ [251] = {157, 209, "DEV_BOARD0_MCASP4_ACLKR_IN", "Input clock"},
+ [252] = {157, 210, "DEV_BOARD0_I2C2_SCL_IN", "Input clock"},
+ [253] = {157, 212, "DEV_BOARD0_SPI1_CLK_IN", "Input clock"},
+ [254] = {157, 213, "DEV_BOARD0_HYP1_RXPMCLK_OUT", "Output clock"},
+ [255] = {157, 214, "DEV_BOARD0_MCU_HYPERBUS0_CK_IN", "Input clock"},
+ [256] = {157, 215, "DEV_BOARD0_MCASP2_AFSX_OUT", "Output clock"},
+ [257] = {157, 216, "DEV_BOARD0_MCASP3_ACLKR_OUT", "Output clock"},
+ [258] = {157, 217, "DEV_BOARD0_MCAN15_RX_OUT", "Output clock"},
+ [259] = {157, 218, "DEV_BOARD0_SPI0_CLK_IN", "Input clock"},
+ [260] = {157, 219, "DEV_BOARD0_MCAN12_RX_OUT", "Output clock"},
+ [261] = {157, 220, "DEV_BOARD0_MCASP2_ACLKR_IN", "Input clock"},
+ [262] = {157, 221, "DEV_BOARD0_MCU_CLKOUT0_IN", "Input muxed clock"},
+ [263] = {157, 222, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"},
+ [264] = {157, 223, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"},
+ [265] = {157, 224, "DEV_BOARD0_MCU_OSPI1_DQS_OUT", "Output clock"},
+ [266] = {157, 226, "DEV_BOARD0_CSI0_RXCLKN_OUT", "Output clock"},
+ [267] = {157, 227, "DEV_BOARD0_TCK_OUT", "Output clock"},
+ [268] = {157, 228, "DEV_BOARD0_CSI1_TXCLKN_IN", "Input clock"},
+ [269] = {157, 229, "DEV_BOARD0_MCU_MCAN0_RX_OUT", "Output clock"},
+ [270] = {157, 230, "DEV_BOARD0_MCASP4_AFSR_OUT", "Output clock"},
+ [271] = {157, 231, "DEV_BOARD0_MCU_HYPERBUS0_CKN_IN", "Input clock"},
+ [272] = {157, 232, "DEV_BOARD0_MCASP4_ACLKR_OUT", "Output clock"},
+ [273] = {157, 233, "DEV_BOARD0_MCAN11_RX_OUT", "Output clock"},
+ [274] = {157, 234, "DEV_BOARD0_I2C5_SCL_IN", "Input clock"},
+ [275] = {157, 235, "DEV_BOARD0_MCU_I2C1_SCL_IN", "Input clock"},
+ [276] = {157, 236, "DEV_BOARD0_I2C0_SCL_OUT", "Output clock"},
+ [277] = {157, 237, "DEV_BOARD0_MCAN6_RX_OUT", "Output clock"},
+ [278] = {157, 238, "DEV_BOARD0_MCU_I3C0_SCL_IN", "Input clock"},
+ [279] = {157, 239, "DEV_BOARD0_MMC1_CLK_OUT", "Output clock"},
+ [280] = {157, 240, "DEV_BOARD0_VOUT0_EXTPCLKIN_OUT", "Output clock"},
+ [281] = {157, 241, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"},
+ [282] = {157, 242, "DEV_BOARD0_I2C5_SCL_OUT", "Output clock"},
+ [283] = {157, 243, "DEV_BOARD0_MCAN16_RX_OUT", "Output clock"},
+ [284] = {157, 244, "DEV_BOARD0_MCU_RGMII1_TXC_IN", "Input clock"},
+ [285] = {157, 245, "DEV_BOARD0_MCASP4_ACLKX_IN", "Input clock"},
+ [286] = {157, 246, "DEV_BOARD0_GPMC0_CLKOUT_IN", "Input clock"},
+ [287] = {157, 247, "DEV_BOARD0_GPMC0_CLK_OUT", "Output clock"},
+ [288] = {157, 248, "DEV_BOARD0_I2C6_SCL_IN", "Input clock"},
+ [289] = {157, 249, "DEV_BOARD0_I2C4_SCL_IN", "Input clock"},
+ [290] = {157, 250, "DEV_BOARD0_SERDES0_REFCLK_N_IN", "Input clock"},
+ [291] = {157, 251, "DEV_BOARD0_OBSCLK0_IN", "Input clock"},
+ [292] = {157, 252, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [293] = {157, 253, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [294] = {157, 254, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [295] = {157, 255, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [296] = {157, 256, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [297] = {157, 257, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [298] = {157, 258, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [299] = {157, 259, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [300] = {157, 264, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [301] = {157, 265, "DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [302] = {157, 266, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [303] = {157, 268, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [304] = {157, 269, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [305] = {157, 271, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [306] = {157, 277, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [307] = {157, 278, "DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [308] = {157, 279, "DEV_BOARD0_OBSCLK0_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [309] = {157, 280, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [310] = {157, 281, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [311] = {157, 282, "DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [312] = {157, 283, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+ [313] = {157, 284, "DEV_BOARD0_MCAN2_RX_OUT", "Output clock"},
+ [314] = {157, 285, "DEV_BOARD0_MCASP2_ACLKX_IN", "Input clock"},
+ [315] = {157, 287, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"},
+ [316] = {157, 288, "DEV_BOARD0_MCASP1_ACLKX_OUT", "Output clock"},
+ [317] = {157, 289, "DEV_BOARD0_SPI2_CLK_OUT", "Output clock"},
+ [318] = {157, 290, "DEV_BOARD0_HYP0_RXFLCLK_IN", "Input clock"},
+ [319] = {157, 291, "DEV_BOARD0_SPI3_CLK_OUT", "Output clock"},
+ [320] = {157, 292, "DEV_BOARD0_MCASP1_AFSR_OUT", "Output clock"},
+ [321] = {157, 293, "DEV_BOARD0_I2C2_SCL_OUT", "Output clock"},
+ [322] = {157, 294, "DEV_BOARD0_MCAN10_RX_OUT", "Output clock"},
+ [323] = {157, 295, "DEV_BOARD0_MCAN5_RX_OUT", "Output clock"},
+ [324] = {157, 296, "DEV_BOARD0_MCU_I3C0_SCL_OUT", "Output clock"},
+ [325] = {157, 297, "DEV_BOARD0_MCU_MCAN1_RX_OUT", "Output clock"},
+ [326] = {157, 299, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN", "Input muxed clock"},
+ [327] = {157, 300, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [328] = {157, 301, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [329] = {157, 302, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [330] = {157, 303, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [331] = {157, 304, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [332] = {157, 312, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [333] = {157, 313, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [334] = {157, 314, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [335] = {157, 315, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [336] = {157, 316, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [337] = {157, 324, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [338] = {157, 325, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [339] = {157, 326, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [340] = {157, 327, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [341] = {157, 328, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+ [342] = {157, 333, "DEV_BOARD0_HYP1_TXFLCLK_OUT", "Output clock"},
+ [343] = {157, 334, "DEV_BOARD0_SPI5_CLK_IN", "Input clock"},
+ [344] = {157, 335, "DEV_BOARD0_I2C3_SCL_OUT", "Output clock"},
+ [345] = {157, 336, "DEV_BOARD0_MCAN8_RX_OUT", "Output clock"},
+ [346] = {157, 338, "DEV_BOARD0_RGMII1_RXC_OUT", "Output clock"},
+ [347] = {157, 339, "DEV_BOARD0_SERDES0_REFCLK_N_OUT", "Output clock"},
+ [348] = {157, 340, "DEV_BOARD0_CSI0_TXCLKP_IN", "Input clock"},
+ [349] = {157, 341, "DEV_BOARD0_SPI7_CLK_IN", "Input clock"},
+ [350] = {157, 342, "DEV_BOARD0_RGMII1_TXC_IN", "Input clock"},
+ [351] = {157, 343, "DEV_BOARD0_HYP1_RXFLCLK_IN", "Input clock"},
+ [352] = {157, 344, "DEV_BOARD0_MDIO1_MDC_IN", "Input clock"},
+ [353] = {157, 345, "DEV_BOARD0_SPI2_CLK_IN", "Input clock"},
+ [354] = {157, 346, "DEV_BOARD0_DSI0_TXCLKP_IN", "Input clock"},
+ [355] = {157, 347, "DEV_BOARD0_MCASP4_AFSX_OUT", "Output clock"},
+ [356] = {157, 352, "DEV_BOARD0_VOUT0_PCLK_IN", "Input clock"},
+ [357] = {150, 0, "DEV_CMPEVENT_INTRTR0_INTR_CLK", "Input clock"},
+ [358] = {179, 0, "DEV_CODEC0_VPU_PCLK_CLK", "Input clock"},
+ [359] = {179, 1, "DEV_CODEC0_VPU_BCLK_CLK", "Input clock"},
+ [360] = {179, 2, "DEV_CODEC0_VPU_CCLK_CLK", "Input clock"},
+ [361] = {179, 3, "DEV_CODEC0_VPU_ACLK_CLK", "Input clock"},
+ [362] = {8, 0, "DEV_COMPUTE_CLUSTER0_C71SS0_0_C7X_CLK", "Input clock"},
+ [363] = {8, 1, "DEV_COMPUTE_CLUSTER0_C71SS0_0_PLL_CTRL_CLK", "Input clock"},
+ [364] = {8, 3, "DEV_COMPUTE_CLUSTER0_C71SS0_0_C7X_DIVH_CLK4_OBSCLK_OUT_CLK", "Output clock"},
+ [365] = {11, 0, "DEV_COMPUTE_CLUSTER0_C71SS1_0_C7X_CLK", "Input clock"},
+ [366] = {11, 1, "DEV_COMPUTE_CLUSTER0_C71SS1_0_PLL_CTRL_CLK", "Input clock"},
+ [367] = {14, 1, "DEV_COMPUTE_CLUSTER0_CLEC_CLK1_CLK", "Input clock"},
+ [368] = {15, 1, "DEV_COMPUTE_CLUSTER0_CORE_CORE_CLK1_CLK", "Input clock"},
+ [369] = {15, 2, "DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK", "Input clock"},
+ [370] = {18, 0, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK1_CLK_CLK", "Input clock"},
+ [371] = {18, 1, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK2_CLK_CLK", "Input clock"},
+ [372] = {25, 0, "DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_0_MSMC_CLK1_CLK", "Input clock"},
+ [373] = {26, 0, "DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK", "Input clock"},
+ [374] = {27, 3, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_0_DIVP_CLK1_CLK_CLK", "Input clock"},
+ [375] = {27, 4, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_0_DIVH_CLK2_CLK_CLK", "Input clock"},
+ [376] = {28, 0, "DEV_CPSW1_MDIO_MDCLK_O", "Output clock"},
+ [377] = {28, 1, "DEV_CPSW1_CPTS_GENF0", "Output clock"},
+ [378] = {28, 3, "DEV_CPSW1_CPTS_RFT_CLK", "Input muxed clock"},
+ [379] = {28, 4, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"},
+ [380] = {28, 5, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"},
+ [381] = {28, 6, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"},
+ [382] = {28, 7, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"},
+ [383] = {28, 8, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"},
+ [384] = {28, 9, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"},
+ [385] = {28, 10, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"},
+ [386] = {28, 11, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"},
+ [387] = {28, 12, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"},
+ [388] = {28, 13, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"},
+ [389] = {28, 18, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"},
+ [390] = {28, 19, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"},
+ [391] = {28, 20, "DEV_CPSW1_GMII1_MR_CLK", "Input clock"},
+ [392] = {28, 21, "DEV_CPSW1_GMII_RFT_CLK", "Input clock"},
+ [393] = {28, 22, "DEV_CPSW1_RGMII1_RXC_I", "Input clock"},
+ [394] = {28, 26, "DEV_CPSW1_RMII_MHZ_50_CLK", "Input clock"},
+ [395] = {28, 27, "DEV_CPSW1_RGMII1_TXC_O", "Output clock"},
+ [396] = {28, 28, "DEV_CPSW1_CPPI_CLK_CLK", "Input clock"},
+ [397] = {28, 29, "DEV_CPSW1_RGMII_MHZ_5_CLK", "Input clock"},
+ [398] = {28, 30, "DEV_CPSW1_GMII1_MT_CLK", "Input clock"},
+ [399] = {28, 32, "DEV_CPSW1_RGMII_MHZ_50_CLK", "Input clock"},
+ [400] = {28, 33, "DEV_CPSW1_RGMII_MHZ_250_CLK", "Input clock"},
+ [401] = {36, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"},
+ [402] = {30, 0, "DEV_CPT2_AGGR1_VCLK_CLK", "Input clock"},
+ [403] = {32, 0, "DEV_CPT2_AGGR2_VCLK_CLK", "Input clock"},
+ [404] = {34, 0, "DEV_CPT2_AGGR3_VCLK_CLK", "Input clock"},
+ [405] = {33, 0, "DEV_CPT2_AGGR4_VCLK_CLK", "Input clock"},
+ [406] = {31, 0, "DEV_CPT2_AGGR5_VCLK_CLK", "Input clock"},
+ [407] = {136, 0, "DEV_CSI_PSILSS0_MAIN_CLK", "Input clock"},
+ [408] = {38, 0, "DEV_CSI_RX_IF0_PPI_D_RX_ULPS_ESC", "Input clock"},
+ [409] = {38, 1, "DEV_CSI_RX_IF0_VBUS_CLK_CLK", "Input clock"},
+ [410] = {38, 2, "DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK", "Input clock"},
+ [411] = {38, 3, "DEV_CSI_RX_IF0_MAIN_CLK_CLK", "Input clock"},
+ [412] = {38, 4, "DEV_CSI_RX_IF0_VP_CLK_CLK", "Input clock"},
+ [413] = {39, 0, "DEV_CSI_RX_IF1_PPI_D_RX_ULPS_ESC", "Input clock"},
+ [414] = {39, 1, "DEV_CSI_RX_IF1_VBUS_CLK_CLK", "Input clock"},
+ [415] = {39, 2, "DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK", "Input clock"},
+ [416] = {39, 3, "DEV_CSI_RX_IF1_MAIN_CLK_CLK", "Input clock"},
+ [417] = {39, 4, "DEV_CSI_RX_IF1_VP_CLK_CLK", "Input clock"},
+ [418] = {40, 1, "DEV_CSI_TX_IF_V2_0_VBUS_CLK_CLK", "Input clock"},
+ [419] = {40, 2, "DEV_CSI_TX_IF_V2_0_MAIN_CLK_CLK", "Input clock"},
+ [420] = {40, 3, "DEV_CSI_TX_IF_V2_0_DPHY_TXBYTECLKHS_CL_CLK", "Input clock"},
+ [421] = {40, 5, "DEV_CSI_TX_IF_V2_0_ESC_CLK_CLK", "Input clock"},
+ [422] = {41, 1, "DEV_CSI_TX_IF_V2_1_VBUS_CLK_CLK", "Input clock"},
+ [423] = {41, 2, "DEV_CSI_TX_IF_V2_1_MAIN_CLK_CLK", "Input clock"},
+ [424] = {41, 3, "DEV_CSI_TX_IF_V2_1_DPHY_TXBYTECLKHS_CL_CLK", "Input clock"},
+ [425] = {41, 5, "DEV_CSI_TX_IF_V2_1_ESC_CLK_CLK", "Input clock"},
+ [426] = {43, 0, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"},
+ [427] = {43, 1, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"},
+ [428] = {43, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"},
+ [429] = {43, 3, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"},
+ [430] = {43, 4, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"},
+ [431] = {43, 5, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"},
+ [432] = {43, 6, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"},
+ [433] = {43, 7, "DEV_DCC0_DCC_CLKSRC7_CLK", "Input clock"},
+ [434] = {43, 8, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"},
+ [435] = {43, 9, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"},
+ [436] = {43, 10, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"},
+ [437] = {43, 11, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"},
+ [438] = {43, 12, "DEV_DCC0_VBUS_CLK", "Input clock"},
+ [439] = {44, 0, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"},
+ [440] = {44, 1, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"},
+ [441] = {44, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"},
+ [442] = {44, 3, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"},
+ [443] = {44, 4, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"},
+ [444] = {44, 5, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"},
+ [445] = {44, 6, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"},
+ [446] = {44, 7, "DEV_DCC1_DCC_CLKSRC7_CLK", "Input clock"},
+ [447] = {44, 8, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"},
+ [448] = {44, 9, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"},
+ [449] = {44, 10, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"},
+ [450] = {44, 11, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"},
+ [451] = {44, 12, "DEV_DCC1_VBUS_CLK", "Input clock"},
+ [452] = {45, 0, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"},
+ [453] = {45, 1, "DEV_DCC2_DCC_CLKSRC1_CLK", "Input clock"},
+ [454] = {45, 3, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"},
+ [455] = {45, 4, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"},
+ [456] = {45, 5, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"},
+ [457] = {45, 6, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"},
+ [458] = {45, 7, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"},
+ [459] = {45, 8, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"},
+ [460] = {45, 9, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"},
+ [461] = {45, 10, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"},
+ [462] = {45, 11, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"},
+ [463] = {45, 12, "DEV_DCC2_VBUS_CLK", "Input clock"},
+ [464] = {46, 0, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"},
+ [465] = {46, 1, "DEV_DCC3_DCC_CLKSRC1_CLK", "Input clock"},
+ [466] = {46, 2, "DEV_DCC3_DCC_CLKSRC2_CLK", "Input clock"},
+ [467] = {46, 5, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"},
+ [468] = {46, 6, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"},
+ [469] = {46, 7, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"},
+ [470] = {46, 8, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"},
+ [471] = {46, 9, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"},
+ [472] = {46, 10, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"},
+ [473] = {46, 11, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"},
+ [474] = {46, 12, "DEV_DCC3_VBUS_CLK", "Input clock"},
+ [475] = {47, 0, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input clock"},
+ [476] = {47, 2, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"},
+ [477] = {47, 3, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"},
+ [478] = {47, 4, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"},
+ [479] = {47, 5, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"},
+ [480] = {47, 7, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"},
+ [481] = {47, 8, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"},
+ [482] = {47, 9, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"},
+ [483] = {47, 10, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"},
+ [484] = {47, 11, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"},
+ [485] = {47, 12, "DEV_DCC4_VBUS_CLK", "Input clock"},
+ [486] = {48, 1, "DEV_DCC5_DCC_CLKSRC1_CLK", "Input clock"},
+ [487] = {48, 2, "DEV_DCC5_DCC_CLKSRC2_CLK", "Input clock"},
+ [488] = {48, 3, "DEV_DCC5_DCC_CLKSRC3_CLK", "Input clock"},
+ [489] = {48, 4, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"},
+ [490] = {48, 6, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"},
+ [491] = {48, 7, "DEV_DCC5_DCC_CLKSRC7_CLK", "Input clock"},
+ [492] = {48, 8, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"},
+ [493] = {48, 9, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"},
+ [494] = {48, 10, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"},
+ [495] = {48, 11, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"},
+ [496] = {48, 12, "DEV_DCC5_VBUS_CLK", "Input clock"},
+ [497] = {49, 0, "DEV_DCC6_DCC_CLKSRC0_CLK", "Input clock"},
+ [498] = {49, 1, "DEV_DCC6_DCC_CLKSRC1_CLK", "Input clock"},
+ [499] = {49, 2, "DEV_DCC6_DCC_CLKSRC2_CLK", "Input clock"},
+ [500] = {49, 3, "DEV_DCC6_DCC_CLKSRC3_CLK", "Input clock"},
+ [501] = {49, 4, "DEV_DCC6_DCC_CLKSRC4_CLK", "Input clock"},
+ [502] = {49, 5, "DEV_DCC6_DCC_CLKSRC5_CLK", "Input clock"},
+ [503] = {49, 6, "DEV_DCC6_DCC_CLKSRC6_CLK", "Input clock"},
+ [504] = {49, 7, "DEV_DCC6_DCC_CLKSRC7_CLK", "Input clock"},
+ [505] = {49, 8, "DEV_DCC6_DCC_INPUT00_CLK", "Input clock"},
+ [506] = {49, 9, "DEV_DCC6_DCC_INPUT01_CLK", "Input clock"},
+ [507] = {49, 10, "DEV_DCC6_DCC_INPUT02_CLK", "Input clock"},
+ [508] = {49, 11, "DEV_DCC6_DCC_INPUT10_CLK", "Input clock"},
+ [509] = {49, 12, "DEV_DCC6_VBUS_CLK", "Input clock"},
+ [510] = {50, 0, "DEV_DCC7_DCC_CLKSRC0_CLK", "Input clock"},
+ [511] = {50, 1, "DEV_DCC7_DCC_CLKSRC1_CLK", "Input clock"},
+ [512] = {50, 2, "DEV_DCC7_DCC_CLKSRC2_CLK", "Input clock"},
+ [513] = {50, 5, "DEV_DCC7_DCC_CLKSRC5_CLK", "Input clock"},
+ [514] = {50, 6, "DEV_DCC7_DCC_CLKSRC6_CLK", "Input clock"},
+ [515] = {50, 7, "DEV_DCC7_DCC_CLKSRC7_CLK", "Input clock"},
+ [516] = {50, 8, "DEV_DCC7_DCC_INPUT00_CLK", "Input clock"},
+ [517] = {50, 9, "DEV_DCC7_DCC_INPUT01_CLK", "Input clock"},
+ [518] = {50, 10, "DEV_DCC7_DCC_INPUT02_CLK", "Input clock"},
+ [519] = {50, 11, "DEV_DCC7_DCC_INPUT10_CLK", "Input clock"},
+ [520] = {50, 12, "DEV_DCC7_VBUS_CLK", "Input clock"},
+ [521] = {51, 0, "DEV_DCC8_DCC_CLKSRC0_CLK", "Input clock"},
+ [522] = {51, 1, "DEV_DCC8_DCC_CLKSRC1_CLK", "Input clock"},
+ [523] = {51, 2, "DEV_DCC8_DCC_CLKSRC2_CLK", "Input clock"},
+ [524] = {51, 3, "DEV_DCC8_DCC_CLKSRC3_CLK", "Input clock"},
+ [525] = {51, 4, "DEV_DCC8_DCC_CLKSRC4_CLK", "Input clock"},
+ [526] = {51, 6, "DEV_DCC8_DCC_CLKSRC6_CLK", "Input clock"},
+ [527] = {51, 7, "DEV_DCC8_DCC_CLKSRC7_CLK", "Input clock"},
+ [528] = {51, 8, "DEV_DCC8_DCC_INPUT00_CLK", "Input clock"},
+ [529] = {51, 9, "DEV_DCC8_DCC_INPUT01_CLK", "Input clock"},
+ [530] = {51, 10, "DEV_DCC8_DCC_INPUT02_CLK", "Input clock"},
+ [531] = {51, 11, "DEV_DCC8_DCC_INPUT10_CLK", "Input clock"},
+ [532] = {51, 12, "DEV_DCC8_VBUS_CLK", "Input clock"},
+ [533] = {52, 0, "DEV_DCC9_DCC_CLKSRC0_CLK", "Input clock"},
+ [534] = {52, 1, "DEV_DCC9_DCC_CLKSRC1_CLK", "Input clock"},
+ [535] = {52, 2, "DEV_DCC9_DCC_CLKSRC2_CLK", "Input clock"},
+ [536] = {52, 3, "DEV_DCC9_DCC_CLKSRC3_CLK", "Input clock"},
+ [537] = {52, 4, "DEV_DCC9_DCC_CLKSRC4_CLK", "Input clock"},
+ [538] = {52, 5, "DEV_DCC9_DCC_CLKSRC5_CLK", "Input clock"},
+ [539] = {52, 6, "DEV_DCC9_DCC_CLKSRC6_CLK", "Input clock"},
+ [540] = {52, 8, "DEV_DCC9_DCC_INPUT00_CLK", "Input clock"},
+ [541] = {52, 9, "DEV_DCC9_DCC_INPUT01_CLK", "Input clock"},
+ [542] = {52, 10, "DEV_DCC9_DCC_INPUT02_CLK", "Input clock"},
+ [543] = {52, 11, "DEV_DCC9_DCC_INPUT10_CLK", "Input clock"},
+ [544] = {52, 12, "DEV_DCC9_VBUS_CLK", "Input clock"},
+ [545] = {138, 0, "DEV_DDR0_DDRSS_DDR_PLL_CLK", "Input clock"},
+ [546] = {138, 1, "DEV_DDR0_DDRSS_VBUS_CLK", "Input clock"},
+ [547] = {138, 2, "DEV_DDR0_PLL_CTRL_CLK", "Input clock"},
+ [548] = {138, 7, "DEV_DDR0_DDRSS_CFG_CLK", "Input clock"},
+ [549] = {139, 0, "DEV_DDR1_DDRSS_DDR_PLL_CLK", "Input clock"},
+ [550] = {139, 1, "DEV_DDR1_DDRSS_VBUS_CLK", "Input clock"},
+ [551] = {139, 2, "DEV_DDR1_PLL_CTRL_CLK", "Input clock"},
+ [552] = {139, 7, "DEV_DDR1_DDRSS_CFG_CLK", "Input clock"},
+ [553] = {57, 1, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"},
+ [554] = {57, 16, "DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK", "Output clock"},
+ [555] = {57, 17, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"},
+ [556] = {57, 28, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"},
+ [557] = {57, 41, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"},
+ [558] = {137, 0, "DEV_DEBUGSUSPENDRTR0_INTR_CLK", "Input clock"},
+ [559] = {58, 0, "DEV_DMPAC0_CLK", "Input clock"},
+ [560] = {62, 0, "DEV_DMPAC0_SDE_0_CLK", "Input clock"},
+ [561] = {374, 0, "DEV_DMPAC0_UTC_0_PSIL_LEAF_CLK", "Input clock"},
+ [562] = {140, 0, "DEV_DMPAC_VPAC_PSILSS0_MAIN_CLK", "Input clock"},
+ [563] = {152, 0, "DEV_DPHY_RX0_IO_RX_CL_L_M", "Input clock"},
+ [564] = {152, 1, "DEV_DPHY_RX0_PPI_RX_BYTE_CLK", "Output clock"},
+ [565] = {152, 2, "DEV_DPHY_RX0_MAIN_CLK_CLK", "Input clock"},
+ [566] = {152, 3, "DEV_DPHY_RX0_IO_RX_CL_L_P", "Input clock"},
+ [567] = {152, 4, "DEV_DPHY_RX0_JTAG_TCK", "Input clock"},
+ [568] = {152, 8, "DEV_DPHY_RX0_PPI_D_RX_ULPS_ESC", "Output clock"},
+ [569] = {153, 0, "DEV_DPHY_RX1_IO_RX_CL_L_M", "Input clock"},
+ [570] = {153, 1, "DEV_DPHY_RX1_PPI_RX_BYTE_CLK", "Output clock"},
+ [571] = {153, 2, "DEV_DPHY_RX1_MAIN_CLK_CLK", "Input clock"},
+ [572] = {153, 3, "DEV_DPHY_RX1_IO_RX_CL_L_P", "Input clock"},
+ [573] = {153, 4, "DEV_DPHY_RX1_JTAG_TCK", "Input clock"},
+ [574] = {153, 8, "DEV_DPHY_RX1_PPI_D_RX_ULPS_ESC", "Output clock"},
+ [575] = {363, 1, "DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK", "Output clock"},
+ [576] = {363, 2, "DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK", "Output clock"},
+ [577] = {363, 5, "DEV_DPHY_TX0_CLK", "Input clock"},
+ [578] = {363, 8, "DEV_DPHY_TX0_PSM_CLK", "Input clock"},
+ [579] = {363, 12, "DEV_DPHY_TX0_CK_M", "Output clock"},
+ [580] = {363, 14, "DEV_DPHY_TX0_DPHY_REF_CLK", "Input muxed clock"},
+ [581] = {363, 15, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
+ [582] = {363, 16, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
+ [583] = {363, 17, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
+ [584] = {363, 18, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
+ [585] = {363, 19, "DEV_DPHY_TX0_TAP_TCK", "Input clock"},
+ [586] = {363, 20, "DEV_DPHY_TX0_CK_P", "Output clock"},
+ [587] = {363, 22, "DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK", "Input clock"},
+ [588] = {363, 23, "DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK", "Output clock"},
+ [589] = {363, 24, "DEV_DPHY_TX0_IP2_PPI_M_TXCLKESC_CLK", "Input clock"},
+ [590] = {364, 1, "DEV_DPHY_TX1_IP2_PPI_TXBYTECLKHS_CL_CLK", "Output clock"},
+ [591] = {364, 2, "DEV_DPHY_TX1_IP1_PPI_TXBYTECLKHS_CL_CLK", "Output clock"},
+ [592] = {364, 5, "DEV_DPHY_TX1_CLK", "Input clock"},
+ [593] = {364, 8, "DEV_DPHY_TX1_PSM_CLK", "Input clock"},
+ [594] = {364, 12, "DEV_DPHY_TX1_CK_M", "Output clock"},
+ [595] = {364, 14, "DEV_DPHY_TX1_DPHY_REF_CLK", "Input muxed clock"},
+ [596] = {364, 15, "DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK"},
+ [597] = {364, 16, "DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK"},
+ [598] = {364, 17, "DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK"},
+ [599] = {364, 18, "DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK"},
+ [600] = {364, 19, "DEV_DPHY_TX1_TAP_TCK", "Input clock"},
+ [601] = {364, 20, "DEV_DPHY_TX1_CK_P", "Output clock"},
+ [602] = {364, 22, "DEV_DPHY_TX1_IP1_PPI_M_TXCLKESC_CLK", "Input clock"},
+ [603] = {364, 23, "DEV_DPHY_TX1_IP1_PPI_M_RXCLKESC_CLK", "Output clock"},
+ [604] = {158, 0, "DEV_DSS0_DSS_FUNC_CLK", "Input clock"},
+ [605] = {158, 1, "DEV_DSS0_DSS_INST0_DPI_0_IN_CLK", "Input clock"},
+ [606] = {158, 2, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK", "Input muxed clock"},
+ [607] = {158, 3, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"},
+ [608] = {158, 4, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"},
+ [609] = {158, 5, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK", "Input muxed clock"},
+ [610] = {158, 6, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
+ [611] = {158, 7, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
+ [612] = {158, 8, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
+ [613] = {158, 9, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
+ [614] = {158, 10, "DEV_DSS0_DSS_INST0_DPI_2_IN_CLK", "Input muxed clock"},
+ [615] = {158, 11, "DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_CLK"},
+ [616] = {158, 12, "DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_CLK"},
+ [617] = {158, 13, "DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_CLK"},
+ [618] = {158, 14, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK", "Input muxed clock"},
+ [619] = {158, 15, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"},
+ [620] = {158, 16, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"},
+ [621] = {158, 17, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"},
+ [622] = {158, 18, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK", "Input muxed clock"},
+ [623] = {158, 19, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
+ [624] = {158, 20, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
+ [625] = {158, 21, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK_DUP0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
+ [626] = {158, 22, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
+ [627] = {158, 23, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
+ [628] = {158, 24, "DEV_DSS0_DSS_INST0_PARA_1_OUT_CLK", "Output clock"},
+ [629] = {158, 25, "DEV_DSS0_DSS_INST0_PARA_3_OUT_CLK", "Output clock"},
+ [630] = {158, 26, "DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK", "Output clock"},
+ [631] = {158, 27, "DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK", "Output clock"},
+ [632] = {158, 28, "DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK", "Output clock"},
+ [633] = {158, 29, "DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK", "Output clock"},
+ [634] = {158, 30, "DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK", "Output clock"},
+ [635] = {154, 0, "DEV_DSS_DSI0_PLL_CTRL_CLK", "Input clock"},
+ [636] = {154, 1, "DEV_DSS_DSI0_SYS_CLK", "Input clock"},
+ [637] = {154, 2, "DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK", "Input clock"},
+ [638] = {154, 3, "DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK", "Input clock"},
+ [639] = {154, 4, "DEV_DSS_DSI0_DPI_0_CLK", "Input clock"},
+ [640] = {154, 5, "DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK", "Input clock"},
+ [641] = {155, 0, "DEV_DSS_DSI1_PLL_CTRL_CLK", "Input clock"},
+ [642] = {155, 1, "DEV_DSS_DSI1_SYS_CLK", "Input clock"},
+ [643] = {155, 2, "DEV_DSS_DSI1_DPHY_0_RX_ESC_CLK", "Input clock"},
+ [644] = {155, 3, "DEV_DSS_DSI1_DPHY_0_TX_ESC_CLK", "Input clock"},
+ [645] = {155, 4, "DEV_DSS_DSI1_DPI_0_CLK", "Input clock"},
+ [646] = {155, 5, "DEV_DSS_DSI1_PPI_0_TXBYTECLKHS_CL_CLK", "Input clock"},
+ [647] = {156, 0, "DEV_DSS_EDP0_PHY_LN0_RXCLK", "Input clock"},
+ [648] = {156, 1, "DEV_DSS_EDP0_PHY_LN2_TXCLK", "Output clock"},
+ [649] = {156, 2, "DEV_DSS_EDP0_PHY_LN3_RXFCLK", "Input clock"},
+ [650] = {156, 3, "DEV_DSS_EDP0_PHY_LN2_TXMCLK", "Input clock"},
+ [651] = {156, 4, "DEV_DSS_EDP0_PHY_LN3_REFCLK", "Input clock"},
+ [652] = {156, 6, "DEV_DSS_EDP0_DPI_2_2X_CLK", "Input clock"},
+ [653] = {156, 7, "DEV_DSS_EDP0_PHY_LN0_TXCLK", "Output clock"},
+ [654] = {156, 8, "DEV_DSS_EDP0_PHY_LN2_TXFCLK", "Input clock"},
+ [655] = {156, 9, "DEV_DSS_EDP0_DPI_3_CLK", "Input clock"},
+ [656] = {156, 10, "DEV_DSS_EDP0_PHY_LN1_RXCLK", "Input clock"},
+ [657] = {156, 11, "DEV_DSS_EDP0_PHY_LN1_TXCLK", "Output clock"},
+ [658] = {156, 12, "DEV_DSS_EDP0_PHY_LN1_RXFCLK", "Input clock"},
+ [659] = {156, 13, "DEV_DSS_EDP0_DPI_5_CLK", "Input clock"},
+ [660] = {156, 14, "DEV_DSS_EDP0_PHY_LN2_RXCLK", "Input clock"},
+ [661] = {156, 16, "DEV_DSS_EDP0_PHY_LN1_TXMCLK", "Input clock"},
+ [662] = {156, 18, "DEV_DSS_EDP0_DPI_2_CLK", "Input clock"},
+ [663] = {156, 19, "DEV_DSS_EDP0_DPTX_MOD_CLK", "Input clock"},
+ [664] = {156, 20, "DEV_DSS_EDP0_PHY_LN1_REFCLK", "Input clock"},
+ [665] = {156, 21, "DEV_DSS_EDP0_PHY_LN1_TXFCLK", "Input clock"},
+ [666] = {156, 22, "DEV_DSS_EDP0_PHY_LN0_RXFCLK", "Input clock"},
+ [667] = {156, 24, "DEV_DSS_EDP0_PHY_LN3_TXMCLK", "Input clock"},
+ [668] = {156, 25, "DEV_DSS_EDP0_PLL_CTRL_CLK", "Input clock"},
+ [669] = {156, 26, "DEV_DSS_EDP0_PHY_LN0_TXFCLK", "Input clock"},
+ [670] = {156, 27, "DEV_DSS_EDP0_PHY_LN3_TXFCLK", "Input clock"},
+ [671] = {156, 28, "DEV_DSS_EDP0_PHY_LN3_TXCLK", "Output clock"},
+ [672] = {156, 29, "DEV_DSS_EDP0_PHY_LN2_REFCLK", "Input clock"},
+ [673] = {156, 30, "DEV_DSS_EDP0_DPI_4_CLK", "Input clock"},
+ [674] = {156, 31, "DEV_DSS_EDP0_PHY_LN0_TXMCLK", "Input clock"},
+ [675] = {156, 33, "DEV_DSS_EDP0_PHY_LN0_REFCLK", "Input clock"},
+ [676] = {156, 34, "DEV_DSS_EDP0_PHY_LN3_RXCLK", "Input clock"},
+ [677] = {156, 35, "DEV_DSS_EDP0_AIF_I2S_CLK", "Input clock"},
+ [678] = {156, 36, "DEV_DSS_EDP0_PHY_LN2_RXFCLK", "Input clock"},
+ [679] = {92, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"},
+ [680] = {93, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"},
+ [681] = {94, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"},
+ [682] = {95, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"},
+ [683] = {160, 0, "DEV_EPWM0_VBUSP_CLK", "Input clock"},
+ [684] = {161, 0, "DEV_EPWM1_VBUSP_CLK", "Input clock"},
+ [685] = {162, 0, "DEV_EPWM2_VBUSP_CLK", "Input clock"},
+ [686] = {163, 0, "DEV_EPWM3_VBUSP_CLK", "Input clock"},
+ [687] = {164, 0, "DEV_EPWM4_VBUSP_CLK", "Input clock"},
+ [688] = {165, 0, "DEV_EPWM5_VBUSP_CLK", "Input clock"},
+ [689] = {100, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"},
+ [690] = {101, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"},
+ [691] = {102, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"},
+ [692] = {103, 0, "DEV_ESM0_CLK", "Input clock"},
+ [693] = {111, 0, "DEV_GPIO0_MMR_CLK", "Input clock"},
+ [694] = {112, 0, "DEV_GPIO2_MMR_CLK", "Input clock"},
+ [695] = {113, 0, "DEV_GPIO4_MMR_CLK", "Input clock"},
+ [696] = {114, 0, "DEV_GPIO6_MMR_CLK", "Input clock"},
+ [697] = {148, 0, "DEV_GPIOMUX_INTRTR0_INTR_CLK", "Input clock"},
+ [698] = {117, 0, "DEV_GPMC0_VBUSM_CLK", "Input clock"},
+ [699] = {117, 1, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"},
+ [700] = {117, 2, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"},
+ [701] = {117, 3, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
+ [702] = {117, 4, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
+ [703] = {117, 5, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
+ [704] = {117, 6, "DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
+ [705] = {117, 7, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"},
+ [706] = {61, 0, "DEV_GTC0_VBUSP_CLK", "Input clock"},
+ [707] = {61, 1, "DEV_GTC0_GTC_CLK", "Input muxed clock"},
+ [708] = {61, 2, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+ [709] = {61, 3, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+ [710] = {61, 4, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+ [711] = {61, 5, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+ [712] = {61, 6, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+ [713] = {61, 7, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+ [714] = {61, 8, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+ [715] = {61, 9, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+ [716] = {61, 10, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+ [717] = {61, 11, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+ [718] = {61, 16, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+ [719] = {61, 17, "DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+ [720] = {214, 0, "DEV_I2C0_PORSCL", "Output clock"},
+ [721] = {214, 1, "DEV_I2C0_PISYS_CLK", "Input clock"},
+ [722] = {214, 2, "DEV_I2C0_CLK", "Input clock"},
+ [723] = {214, 3, "DEV_I2C0_PISCL", "Input clock"},
+ [724] = {215, 0, "DEV_I2C1_PORSCL", "Output clock"},
+ [725] = {215, 1, "DEV_I2C1_PISYS_CLK", "Input clock"},
+ [726] = {215, 2, "DEV_I2C1_CLK", "Input clock"},
+ [727] = {215, 3, "DEV_I2C1_PISCL", "Input clock"},
+ [728] = {216, 0, "DEV_I2C2_PORSCL", "Output clock"},
+ [729] = {216, 1, "DEV_I2C2_PISYS_CLK", "Input clock"},
+ [730] = {216, 2, "DEV_I2C2_CLK", "Input clock"},
+ [731] = {216, 3, "DEV_I2C2_PISCL", "Input clock"},
+ [732] = {217, 0, "DEV_I2C3_PORSCL", "Output clock"},
+ [733] = {217, 1, "DEV_I2C3_PISYS_CLK", "Input clock"},
+ [734] = {217, 2, "DEV_I2C3_CLK", "Input clock"},
+ [735] = {217, 3, "DEV_I2C3_PISCL", "Input clock"},
+ [736] = {218, 0, "DEV_I2C4_PORSCL", "Output clock"},
+ [737] = {218, 1, "DEV_I2C4_PISYS_CLK", "Input clock"},
+ [738] = {218, 2, "DEV_I2C4_CLK", "Input clock"},
+ [739] = {218, 3, "DEV_I2C4_PISCL", "Input clock"},
+ [740] = {219, 0, "DEV_I2C5_PORSCL", "Output clock"},
+ [741] = {219, 1, "DEV_I2C5_PISYS_CLK", "Input clock"},
+ [742] = {219, 2, "DEV_I2C5_CLK", "Input clock"},
+ [743] = {219, 3, "DEV_I2C5_PISCL", "Input clock"},
+ [744] = {220, 0, "DEV_I2C6_PORSCL", "Output clock"},
+ [745] = {220, 1, "DEV_I2C6_PISYS_CLK", "Input clock"},
+ [746] = {220, 2, "DEV_I2C6_CLK", "Input clock"},
+ [747] = {220, 3, "DEV_I2C6_PISCL", "Input clock"},
+ [748] = {130, 0, "DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_PLL_CTRL_CLK", "Input clock"},
+ [749] = {130, 1, "DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_GPU_PLL_CLK", "Input clock"},
+ [750] = {131, 0, "DEV_J7AM_32_64_ATB_FUNNEL0_DBG_CLK", "Input clock"},
+ [751] = {132, 0, "DEV_J7AM_32_64_ATB_FUNNEL1_DBG_CLK", "Input clock"},
+ [752] = {133, 0, "DEV_J7AM_32_64_ATB_FUNNEL2_DBG_CLK", "Input clock"},
+ [753] = {135, 0, "DEV_J7AM_BOLT_PGD0_WKUP_OSC0_CLK", "Input clock"},
+ [754] = {141, 0, "DEV_J7AM_HWA_ATB_FUNNEL0_DBG_CLK", "Input clock"},
+ [755] = {142, 0, "DEV_J7AM_MAIN_16FF0_WKUP_OSC0_CLK", "Input clock"},
+ [756] = {144, 0, "DEV_J7AM_PULSAR_ATB_FUNNEL0_DBG_CLK", "Input clock"},
+ [757] = {120, 0, "DEV_LED0_VBUS_CLK", "Input clock"},
+ [758] = {120, 1, "DEV_LED0_LED_CLK", "Input clock"},
+ [759] = {121, 0, "DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK", "Input clock"},
+ [760] = {122, 0, "DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK", "Input clock"},
+ [761] = {182, 0, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"},
+ [762] = {182, 1, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [763] = {182, 2, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+ [764] = {182, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+ [765] = {182, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+ [766] = {182, 5, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+ [767] = {182, 6, "DEV_MCAN0_MCANSS_CAN_RXD", "Input clock"},
+ [768] = {183, 0, "DEV_MCAN1_MCANSS_HCLK_CLK", "Input clock"},
+ [769] = {183, 1, "DEV_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [770] = {183, 2, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
+ [771] = {183, 3, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
+ [772] = {183, 4, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
+ [773] = {183, 5, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
+ [774] = {183, 6, "DEV_MCAN1_MCANSS_CAN_RXD", "Input clock"},
+ [775] = {192, 0, "DEV_MCAN10_MCANSS_HCLK_CLK", "Input clock"},
+ [776] = {192, 1, "DEV_MCAN10_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [777] = {192, 2, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
+ [778] = {192, 3, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
+ [779] = {192, 4, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
+ [780] = {192, 5, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
+ [781] = {192, 6, "DEV_MCAN10_MCANSS_CAN_RXD", "Input clock"},
+ [782] = {193, 0, "DEV_MCAN11_MCANSS_HCLK_CLK", "Input clock"},
+ [783] = {193, 1, "DEV_MCAN11_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [784] = {193, 2, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
+ [785] = {193, 3, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
+ [786] = {193, 4, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
+ [787] = {193, 5, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
+ [788] = {193, 6, "DEV_MCAN11_MCANSS_CAN_RXD", "Input clock"},
+ [789] = {194, 0, "DEV_MCAN12_MCANSS_HCLK_CLK", "Input clock"},
+ [790] = {194, 1, "DEV_MCAN12_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [791] = {194, 2, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
+ [792] = {194, 3, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
+ [793] = {194, 4, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
+ [794] = {194, 5, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
+ [795] = {194, 6, "DEV_MCAN12_MCANSS_CAN_RXD", "Input clock"},
+ [796] = {195, 0, "DEV_MCAN13_MCANSS_HCLK_CLK", "Input clock"},
+ [797] = {195, 1, "DEV_MCAN13_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [798] = {195, 2, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
+ [799] = {195, 3, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
+ [800] = {195, 4, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
+ [801] = {195, 5, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
+ [802] = {195, 6, "DEV_MCAN13_MCANSS_CAN_RXD", "Input clock"},
+ [803] = {197, 0, "DEV_MCAN14_MCANSS_HCLK_CLK", "Input clock"},
+ [804] = {197, 1, "DEV_MCAN14_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [805] = {197, 2, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"},
+ [806] = {197, 3, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"},
+ [807] = {197, 4, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"},
+ [808] = {197, 5, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"},
+ [809] = {197, 6, "DEV_MCAN14_MCANSS_CAN_RXD", "Input clock"},
+ [810] = {199, 0, "DEV_MCAN15_MCANSS_HCLK_CLK", "Input clock"},
+ [811] = {199, 1, "DEV_MCAN15_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [812] = {199, 2, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"},
+ [813] = {199, 3, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"},
+ [814] = {199, 4, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"},
+ [815] = {199, 5, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"},
+ [816] = {199, 6, "DEV_MCAN15_MCANSS_CAN_RXD", "Input clock"},
+ [817] = {201, 0, "DEV_MCAN16_MCANSS_HCLK_CLK", "Input clock"},
+ [818] = {201, 1, "DEV_MCAN16_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [819] = {201, 2, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"},
+ [820] = {201, 3, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"},
+ [821] = {201, 4, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"},
+ [822] = {201, 5, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"},
+ [823] = {201, 6, "DEV_MCAN16_MCANSS_CAN_RXD", "Input clock"},
+ [824] = {206, 0, "DEV_MCAN17_MCANSS_HCLK_CLK", "Input clock"},
+ [825] = {206, 1, "DEV_MCAN17_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [826] = {206, 2, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"},
+ [827] = {206, 3, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"},
+ [828] = {206, 4, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"},
+ [829] = {206, 5, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"},
+ [830] = {206, 6, "DEV_MCAN17_MCANSS_CAN_RXD", "Input clock"},
+ [831] = {184, 0, "DEV_MCAN2_MCANSS_HCLK_CLK", "Input clock"},
+ [832] = {184, 1, "DEV_MCAN2_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [833] = {184, 2, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
+ [834] = {184, 3, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
+ [835] = {184, 4, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
+ [836] = {184, 5, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
+ [837] = {184, 6, "DEV_MCAN2_MCANSS_CAN_RXD", "Input clock"},
+ [838] = {185, 0, "DEV_MCAN3_MCANSS_HCLK_CLK", "Input clock"},
+ [839] = {185, 1, "DEV_MCAN3_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [840] = {185, 2, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
+ [841] = {185, 3, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
+ [842] = {185, 4, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
+ [843] = {185, 5, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
+ [844] = {185, 6, "DEV_MCAN3_MCANSS_CAN_RXD", "Input clock"},
+ [845] = {186, 0, "DEV_MCAN4_MCANSS_HCLK_CLK", "Input clock"},
+ [846] = {186, 1, "DEV_MCAN4_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [847] = {186, 2, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
+ [848] = {186, 3, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
+ [849] = {186, 4, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
+ [850] = {186, 5, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
+ [851] = {186, 6, "DEV_MCAN4_MCANSS_CAN_RXD", "Input clock"},
+ [852] = {187, 0, "DEV_MCAN5_MCANSS_HCLK_CLK", "Input clock"},
+ [853] = {187, 1, "DEV_MCAN5_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [854] = {187, 2, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
+ [855] = {187, 3, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
+ [856] = {187, 4, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
+ [857] = {187, 5, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
+ [858] = {187, 6, "DEV_MCAN5_MCANSS_CAN_RXD", "Input clock"},
+ [859] = {188, 0, "DEV_MCAN6_MCANSS_HCLK_CLK", "Input clock"},
+ [860] = {188, 1, "DEV_MCAN6_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [861] = {188, 2, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
+ [862] = {188, 3, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
+ [863] = {188, 4, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
+ [864] = {188, 5, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
+ [865] = {188, 6, "DEV_MCAN6_MCANSS_CAN_RXD", "Input clock"},
+ [866] = {189, 0, "DEV_MCAN7_MCANSS_HCLK_CLK", "Input clock"},
+ [867] = {189, 1, "DEV_MCAN7_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [868] = {189, 2, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
+ [869] = {189, 3, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
+ [870] = {189, 4, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
+ [871] = {189, 5, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
+ [872] = {189, 6, "DEV_MCAN7_MCANSS_CAN_RXD", "Input clock"},
+ [873] = {190, 0, "DEV_MCAN8_MCANSS_HCLK_CLK", "Input clock"},
+ [874] = {190, 1, "DEV_MCAN8_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [875] = {190, 2, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
+ [876] = {190, 3, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
+ [877] = {190, 4, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
+ [878] = {190, 5, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
+ [879] = {190, 6, "DEV_MCAN8_MCANSS_CAN_RXD", "Input clock"},
+ [880] = {191, 0, "DEV_MCAN9_MCANSS_HCLK_CLK", "Input clock"},
+ [881] = {191, 1, "DEV_MCAN9_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [882] = {191, 2, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
+ [883] = {191, 3, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
+ [884] = {191, 4, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
+ [885] = {191, 5, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
+ [886] = {191, 6, "DEV_MCAN9_MCANSS_CAN_RXD", "Input clock"},
+ [887] = {209, 0, "DEV_MCASP0_AUX_CLK", "Input muxed clock"},
+ [888] = {209, 1, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+ [889] = {209, 2, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+ [890] = {209, 5, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+ [891] = {209, 6, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+ [892] = {209, 7, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+ [893] = {209, 8, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+ [894] = {209, 9, "DEV_MCASP0_MCASP_AFSX_POUT", "Output clock"},
+ [895] = {209, 10, "DEV_MCASP0_MCASP_AHCLKR_POUT", "Output clock"},
+ [896] = {209, 11, "DEV_MCASP0_MCASP_AHCLKR_PIN", "Input muxed clock"},
+ [897] = {209, 12, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+ [898] = {209, 13, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+ [899] = {209, 14, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+ [900] = {209, 15, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+ [901] = {209, 20, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+ [902] = {209, 21, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+ [903] = {209, 22, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+ [904] = {209, 23, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+ [905] = {209, 28, "DEV_MCASP0_MCASP_ACLKX_POUT", "Output clock"},
+ [906] = {209, 29, "DEV_MCASP0_MCASP_AFSR_POUT", "Output clock"},
+ [907] = {209, 30, "DEV_MCASP0_VBUSP_CLK", "Input clock"},
+ [908] = {209, 31, "DEV_MCASP0_MCASP_ACLKR_POUT", "Output clock"},
+ [909] = {209, 32, "DEV_MCASP0_MCASP_AHCLKX_POUT", "Output clock"},
+ [910] = {209, 33, "DEV_MCASP0_MCASP_ACLKX_PIN", "Input clock"},
+ [911] = {209, 34, "DEV_MCASP0_MCASP_AHCLKX_PIN", "Input muxed clock"},
+ [912] = {209, 35, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+ [913] = {209, 36, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+ [914] = {209, 37, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+ [915] = {209, 38, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+ [916] = {209, 43, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+ [917] = {209, 44, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+ [918] = {209, 45, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+ [919] = {209, 46, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+ [920] = {209, 51, "DEV_MCASP0_MCASP_ACLKR_PIN", "Input clock"},
+ [921] = {210, 0, "DEV_MCASP1_AUX_CLK", "Input muxed clock"},
+ [922] = {210, 1, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+ [923] = {210, 2, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+ [924] = {210, 5, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+ [925] = {210, 6, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+ [926] = {210, 7, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+ [927] = {210, 8, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+ [928] = {210, 9, "DEV_MCASP1_MCASP_AFSX_POUT", "Output clock"},
+ [929] = {210, 10, "DEV_MCASP1_MCASP_AHCLKR_POUT", "Output clock"},
+ [930] = {210, 11, "DEV_MCASP1_MCASP_AHCLKR_PIN", "Input muxed clock"},
+ [931] = {210, 12, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+ [932] = {210, 13, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+ [933] = {210, 14, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+ [934] = {210, 15, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+ [935] = {210, 20, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+ [936] = {210, 21, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+ [937] = {210, 22, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+ [938] = {210, 23, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+ [939] = {210, 28, "DEV_MCASP1_MCASP_ACLKX_POUT", "Output clock"},
+ [940] = {210, 29, "DEV_MCASP1_MCASP_AFSR_POUT", "Output clock"},
+ [941] = {210, 30, "DEV_MCASP1_VBUSP_CLK", "Input clock"},
+ [942] = {210, 31, "DEV_MCASP1_MCASP_ACLKR_POUT", "Output clock"},
+ [943] = {210, 32, "DEV_MCASP1_MCASP_AHCLKX_POUT", "Output clock"},
+ [944] = {210, 33, "DEV_MCASP1_MCASP_ACLKX_PIN", "Input clock"},
+ [945] = {210, 34, "DEV_MCASP1_MCASP_AHCLKX_PIN", "Input muxed clock"},
+ [946] = {210, 35, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+ [947] = {210, 36, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+ [948] = {210, 37, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+ [949] = {210, 38, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+ [950] = {210, 43, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+ [951] = {210, 44, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+ [952] = {210, 45, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+ [953] = {210, 46, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+ [954] = {210, 51, "DEV_MCASP1_MCASP_ACLKR_PIN", "Input clock"},
+ [955] = {211, 0, "DEV_MCASP2_AUX_CLK", "Input muxed clock"},
+ [956] = {211, 1, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+ [957] = {211, 2, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+ [958] = {211, 5, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+ [959] = {211, 6, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+ [960] = {211, 7, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+ [961] = {211, 8, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+ [962] = {211, 9, "DEV_MCASP2_MCASP_AFSX_POUT", "Output clock"},
+ [963] = {211, 10, "DEV_MCASP2_MCASP_AHCLKR_POUT", "Output clock"},
+ [964] = {211, 11, "DEV_MCASP2_MCASP_AHCLKR_PIN", "Input muxed clock"},
+ [965] = {211, 12, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+ [966] = {211, 13, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+ [967] = {211, 14, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+ [968] = {211, 15, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+ [969] = {211, 20, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+ [970] = {211, 21, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+ [971] = {211, 22, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+ [972] = {211, 23, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+ [973] = {211, 28, "DEV_MCASP2_MCASP_ACLKX_POUT", "Output clock"},
+ [974] = {211, 29, "DEV_MCASP2_MCASP_AFSR_POUT", "Output clock"},
+ [975] = {211, 30, "DEV_MCASP2_VBUSP_CLK", "Input clock"},
+ [976] = {211, 31, "DEV_MCASP2_MCASP_ACLKR_POUT", "Output clock"},
+ [977] = {211, 32, "DEV_MCASP2_MCASP_AHCLKX_POUT", "Output clock"},
+ [978] = {211, 33, "DEV_MCASP2_MCASP_ACLKX_PIN", "Input clock"},
+ [979] = {211, 34, "DEV_MCASP2_MCASP_AHCLKX_PIN", "Input muxed clock"},
+ [980] = {211, 35, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+ [981] = {211, 36, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+ [982] = {211, 37, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+ [983] = {211, 38, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+ [984] = {211, 43, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+ [985] = {211, 44, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+ [986] = {211, 45, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+ [987] = {211, 46, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+ [988] = {211, 51, "DEV_MCASP2_MCASP_ACLKR_PIN", "Input clock"},
+ [989] = {212, 0, "DEV_MCASP3_AUX_CLK", "Input muxed clock"},
+ [990] = {212, 1, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+ [991] = {212, 2, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+ [992] = {212, 5, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+ [993] = {212, 6, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+ [994] = {212, 7, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+ [995] = {212, 8, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+ [996] = {212, 9, "DEV_MCASP3_MCASP_AFSX_POUT", "Output clock"},
+ [997] = {212, 10, "DEV_MCASP3_MCASP_AHCLKR_POUT", "Output clock"},
+ [998] = {212, 11, "DEV_MCASP3_MCASP_AHCLKR_PIN", "Input muxed clock"},
+ [999] = {212, 12, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
+ [1000] = {212, 13, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
+ [1001] = {212, 14, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
+ [1002] = {212, 15, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
+ [1003] = {212, 20, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
+ [1004] = {212, 21, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
+ [1005] = {212, 22, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
+ [1006] = {212, 23, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
+ [1007] = {212, 28, "DEV_MCASP3_MCASP_ACLKX_POUT", "Output clock"},
+ [1008] = {212, 29, "DEV_MCASP3_MCASP_AFSR_POUT", "Output clock"},
+ [1009] = {212, 30, "DEV_MCASP3_VBUSP_CLK", "Input clock"},
+ [1010] = {212, 31, "DEV_MCASP3_MCASP_ACLKR_POUT", "Output clock"},
+ [1011] = {212, 32, "DEV_MCASP3_MCASP_AHCLKX_POUT", "Output clock"},
+ [1012] = {212, 33, "DEV_MCASP3_MCASP_ACLKX_PIN", "Input clock"},
+ [1013] = {212, 34, "DEV_MCASP3_MCASP_AHCLKX_PIN", "Input muxed clock"},
+ [1014] = {212, 35, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
+ [1015] = {212, 36, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
+ [1016] = {212, 37, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
+ [1017] = {212, 38, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
+ [1018] = {212, 43, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
+ [1019] = {212, 44, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
+ [1020] = {212, 45, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
+ [1021] = {212, 46, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
+ [1022] = {212, 51, "DEV_MCASP3_MCASP_ACLKR_PIN", "Input clock"},
+ [1023] = {213, 0, "DEV_MCASP4_AUX_CLK", "Input muxed clock"},
+ [1024] = {213, 1, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+ [1025] = {213, 2, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+ [1026] = {213, 5, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+ [1027] = {213, 6, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+ [1028] = {213, 7, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+ [1029] = {213, 8, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+ [1030] = {213, 9, "DEV_MCASP4_MCASP_AFSX_POUT", "Output clock"},
+ [1031] = {213, 10, "DEV_MCASP4_MCASP_AHCLKR_POUT", "Output clock"},
+ [1032] = {213, 11, "DEV_MCASP4_MCASP_AHCLKR_PIN", "Input muxed clock"},
+ [1033] = {213, 12, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
+ [1034] = {213, 13, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
+ [1035] = {213, 14, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
+ [1036] = {213, 15, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
+ [1037] = {213, 20, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
+ [1038] = {213, 21, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
+ [1039] = {213, 22, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
+ [1040] = {213, 23, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
+ [1041] = {213, 28, "DEV_MCASP4_MCASP_ACLKX_POUT", "Output clock"},
+ [1042] = {213, 29, "DEV_MCASP4_MCASP_AFSR_POUT", "Output clock"},
+ [1043] = {213, 30, "DEV_MCASP4_VBUSP_CLK", "Input clock"},
+ [1044] = {213, 31, "DEV_MCASP4_MCASP_ACLKR_POUT", "Output clock"},
+ [1045] = {213, 32, "DEV_MCASP4_MCASP_AHCLKX_POUT", "Output clock"},
+ [1046] = {213, 33, "DEV_MCASP4_MCASP_ACLKX_PIN", "Input clock"},
+ [1047] = {213, 34, "DEV_MCASP4_MCASP_AHCLKX_PIN", "Input muxed clock"},
+ [1048] = {213, 35, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
+ [1049] = {213, 36, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
+ [1050] = {213, 37, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
+ [1051] = {213, 38, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
+ [1052] = {213, 43, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
+ [1053] = {213, 44, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
+ [1054] = {213, 45, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
+ [1055] = {213, 46, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
+ [1056] = {213, 51, "DEV_MCASP4_MCASP_ACLKR_PIN", "Input clock"},
+ [1057] = {339, 0, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"},
+ [1058] = {339, 1, "DEV_MCSPI0_VBUSP_CLK", "Input clock"},
+ [1059] = {339, 2, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"},
+ [1060] = {339, 3, "DEV_MCSPI0_IO_CLKSPII_CLK", "Input muxed clock"},
+ [1061] = {339, 4, "DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT", "Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK"},
+ [1062] = {339, 5, "DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK"},
+ [1063] = {340, 0, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"},
+ [1064] = {340, 1, "DEV_MCSPI1_VBUSP_CLK", "Input clock"},
+ [1065] = {340, 2, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"},
+ [1066] = {340, 3, "DEV_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"},
+ [1067] = {340, 4, "DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT", "Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK"},
+ [1068] = {340, 5, "DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK"},
+ [1069] = {341, 0, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"},
+ [1070] = {341, 1, "DEV_MCSPI2_VBUSP_CLK", "Input clock"},
+ [1071] = {341, 2, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"},
+ [1072] = {341, 3, "DEV_MCSPI2_IO_CLKSPII_CLK", "Input muxed clock"},
+ [1073] = {341, 4, "DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT", "Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK"},
+ [1074] = {341, 5, "DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK"},
+ [1075] = {342, 0, "DEV_MCSPI3_IO_CLKSPIO_CLK", "Output clock"},
+ [1076] = {342, 1, "DEV_MCSPI3_VBUSP_CLK", "Input clock"},
+ [1077] = {342, 2, "DEV_MCSPI3_CLKSPIREF_CLK", "Input clock"},
+ [1078] = {342, 3, "DEV_MCSPI3_IO_CLKSPII_CLK", "Input muxed clock"},
+ [1079] = {342, 4, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"},
+ [1080] = {342, 5, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI3_CLK_LPBK_MUX_OUT0", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"},
+ [1081] = {343, 0, "DEV_MCSPI4_IO_CLKSPIO_CLK", "Output clock"},
+ [1082] = {343, 1, "DEV_MCSPI4_VBUSP_CLK", "Input clock"},
+ [1083] = {343, 2, "DEV_MCSPI4_CLKSPIREF_CLK", "Input clock"},
+ [1084] = {343, 3, "DEV_MCSPI4_IO_CLKSPII_CLK", "Input clock"},
+ [1085] = {344, 0, "DEV_MCSPI5_IO_CLKSPIO_CLK", "Output clock"},
+ [1086] = {344, 1, "DEV_MCSPI5_VBUSP_CLK", "Input clock"},
+ [1087] = {344, 2, "DEV_MCSPI5_CLKSPIREF_CLK", "Input clock"},
+ [1088] = {344, 3, "DEV_MCSPI5_IO_CLKSPII_CLK", "Input muxed clock"},
+ [1089] = {344, 4, "DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI5_CLK_OUT", "Parent input clock option to DEV_MCSPI5_IO_CLKSPII_CLK"},
+ [1090] = {344, 5, "DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_SPI_MAIN_5_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI5_IO_CLKSPII_CLK"},
+ [1091] = {345, 0, "DEV_MCSPI6_IO_CLKSPIO_CLK", "Output clock"},
+ [1092] = {345, 1, "DEV_MCSPI6_VBUSP_CLK", "Input clock"},
+ [1093] = {345, 2, "DEV_MCSPI6_CLKSPIREF_CLK", "Input clock"},
+ [1094] = {345, 3, "DEV_MCSPI6_IO_CLKSPII_CLK", "Input muxed clock"},
+ [1095] = {345, 4, "DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI6_CLK_OUT", "Parent input clock option to DEV_MCSPI6_IO_CLKSPII_CLK"},
+ [1096] = {345, 5, "DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_SPI_MAIN_6_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI6_IO_CLKSPII_CLK"},
+ [1097] = {346, 0, "DEV_MCSPI7_IO_CLKSPIO_CLK", "Output clock"},
+ [1098] = {346, 1, "DEV_MCSPI7_VBUSP_CLK", "Input clock"},
+ [1099] = {346, 2, "DEV_MCSPI7_CLKSPIREF_CLK", "Input clock"},
+ [1100] = {346, 3, "DEV_MCSPI7_IO_CLKSPII_CLK", "Input muxed clock"},
+ [1101] = {346, 4, "DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI7_CLK_OUT", "Parent input clock option to DEV_MCSPI7_IO_CLKSPII_CLK"},
+ [1102] = {346, 5, "DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_SPI_MAIN_7_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI7_IO_CLKSPII_CLK"},
+ [1103] = {0, 0, "DEV_MCU_ADC12FC_16FFC0_ADC_CLK", "Input muxed clock"},
+ [1104] = {0, 1, "DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK"},
+ [1105] = {0, 2, "DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK"},
+ [1106] = {0, 3, "DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK"},
+ [1107] = {0, 4, "DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK"},
+ [1108] = {0, 5, "DEV_MCU_ADC12FC_16FFC0_VBUS_CLK", "Input clock"},
+ [1109] = {0, 6, "DEV_MCU_ADC12FC_16FFC0_SYS_CLK", "Input clock"},
+ [1110] = {1, 0, "DEV_MCU_ADC12FC_16FFC1_ADC_CLK", "Input muxed clock"},
+ [1111] = {1, 1, "DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK"},
+ [1112] = {1, 2, "DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK"},
+ [1113] = {1, 3, "DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK"},
+ [1114] = {1, 4, "DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK"},
+ [1115] = {1, 5, "DEV_MCU_ADC12FC_16FFC1_VBUS_CLK", "Input clock"},
+ [1116] = {1, 6, "DEV_MCU_ADC12FC_16FFC1_SYS_CLK", "Input clock"},
+ [1117] = {29, 0, "DEV_MCU_CPSW0_MDIO_MDCLK_O", "Output clock"},
+ [1118] = {29, 1, "DEV_MCU_CPSW0_CPTS_GENF0", "Output clock"},
+ [1119] = {29, 3, "DEV_MCU_CPSW0_CPTS_RFT_CLK", "Input muxed clock"},
+ [1120] = {29, 4, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+ [1121] = {29, 5, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+ [1122] = {29, 6, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+ [1123] = {29, 7, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+ [1124] = {29, 8, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+ [1125] = {29, 9, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+ [1126] = {29, 10, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+ [1127] = {29, 11, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+ [1128] = {29, 12, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+ [1129] = {29, 13, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+ [1130] = {29, 18, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+ [1131] = {29, 19, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+ [1132] = {29, 20, "DEV_MCU_CPSW0_GMII1_MR_CLK", "Input clock"},
+ [1133] = {29, 21, "DEV_MCU_CPSW0_GMII_RFT_CLK", "Input clock"},
+ [1134] = {29, 22, "DEV_MCU_CPSW0_RGMII1_RXC_I", "Input clock"},
+ [1135] = {29, 26, "DEV_MCU_CPSW0_RMII_MHZ_50_CLK", "Input clock"},
+ [1136] = {29, 27, "DEV_MCU_CPSW0_RGMII1_TXC_O", "Output clock"},
+ [1137] = {29, 28, "DEV_MCU_CPSW0_CPPI_CLK_CLK", "Input clock"},
+ [1138] = {29, 29, "DEV_MCU_CPSW0_RGMII_MHZ_5_CLK", "Input clock"},
+ [1139] = {29, 30, "DEV_MCU_CPSW0_GMII1_MT_CLK", "Input clock"},
+ [1140] = {29, 32, "DEV_MCU_CPSW0_RGMII_MHZ_50_CLK", "Input clock"},
+ [1141] = {29, 33, "DEV_MCU_CPSW0_RGMII_MHZ_250_CLK", "Input clock"},
+ [1142] = {37, 0, "DEV_MCU_CPT2_AGGR0_VCLK_CLK", "Input clock"},
+ [1143] = {53, 0, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"},
+ [1144] = {53, 1, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"},
+ [1145] = {53, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"},
+ [1146] = {53, 3, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"},
+ [1147] = {53, 4, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"},
+ [1148] = {53, 5, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"},
+ [1149] = {53, 6, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"},
+ [1150] = {53, 7, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"},
+ [1151] = {53, 8, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"},
+ [1152] = {53, 9, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"},
+ [1153] = {53, 10, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"},
+ [1154] = {53, 11, "DEV_MCU_DCC0_DCC_INPUT10_CLK", "Input clock"},
+ [1155] = {53, 12, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"},
+ [1156] = {54, 0, "DEV_MCU_DCC1_DCC_CLKSRC0_CLK", "Input clock"},
+ [1157] = {54, 1, "DEV_MCU_DCC1_DCC_CLKSRC1_CLK", "Input clock"},
+ [1158] = {54, 2, "DEV_MCU_DCC1_DCC_CLKSRC2_CLK", "Input clock"},
+ [1159] = {54, 3, "DEV_MCU_DCC1_DCC_CLKSRC3_CLK", "Input clock"},
+ [1160] = {54, 4, "DEV_MCU_DCC1_DCC_CLKSRC4_CLK", "Input clock"},
+ [1161] = {54, 5, "DEV_MCU_DCC1_DCC_CLKSRC5_CLK", "Input clock"},
+ [1162] = {54, 6, "DEV_MCU_DCC1_DCC_CLKSRC6_CLK", "Input clock"},
+ [1163] = {54, 7, "DEV_MCU_DCC1_DCC_CLKSRC7_CLK", "Input clock"},
+ [1164] = {54, 8, "DEV_MCU_DCC1_DCC_INPUT00_CLK", "Input clock"},
+ [1165] = {54, 9, "DEV_MCU_DCC1_DCC_INPUT01_CLK", "Input clock"},
+ [1166] = {54, 10, "DEV_MCU_DCC1_DCC_INPUT02_CLK", "Input clock"},
+ [1167] = {54, 11, "DEV_MCU_DCC1_DCC_INPUT10_CLK", "Input clock"},
+ [1168] = {54, 12, "DEV_MCU_DCC1_VBUS_CLK", "Input clock"},
+ [1169] = {55, 0, "DEV_MCU_DCC2_DCC_CLKSRC0_CLK", "Input clock"},
+ [1170] = {55, 1, "DEV_MCU_DCC2_DCC_CLKSRC1_CLK", "Input clock"},
+ [1171] = {55, 2, "DEV_MCU_DCC2_DCC_CLKSRC2_CLK", "Input clock"},
+ [1172] = {55, 3, "DEV_MCU_DCC2_DCC_CLKSRC3_CLK", "Input clock"},
+ [1173] = {55, 4, "DEV_MCU_DCC2_DCC_CLKSRC4_CLK", "Input clock"},
+ [1174] = {55, 6, "DEV_MCU_DCC2_DCC_CLKSRC6_CLK", "Input clock"},
+ [1175] = {55, 7, "DEV_MCU_DCC2_DCC_CLKSRC7_CLK", "Input clock"},
+ [1176] = {55, 8, "DEV_MCU_DCC2_DCC_INPUT00_CLK", "Input clock"},
+ [1177] = {55, 9, "DEV_MCU_DCC2_DCC_INPUT01_CLK", "Input clock"},
+ [1178] = {55, 10, "DEV_MCU_DCC2_DCC_INPUT02_CLK", "Input clock"},
+ [1179] = {55, 11, "DEV_MCU_DCC2_DCC_INPUT10_CLK", "Input clock"},
+ [1180] = {55, 12, "DEV_MCU_DCC2_VBUS_CLK", "Input clock"},
+ [1181] = {105, 0, "DEV_MCU_ESM0_CLK", "Input clock"},
+ [1182] = {107, 0, "DEV_MCU_FSS0_FSAS_0_GCLK", "Input clock"},
+ [1183] = {108, 1, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK", "Input clock"},
+ [1184] = {108, 2, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK", "Input clock"},
+ [1185] = {108, 3, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK", "Input clock"},
+ [1186] = {108, 6, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK", "Input clock"},
+ [1187] = {108, 7, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N", "Output clock"},
+ [1188] = {108, 8, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P", "Output clock"},
+ [1189] = {108, 11, "DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK", "Input clock"},
+ [1190] = {109, 0, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"},
+ [1191] = {109, 1, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"},
+ [1192] = {109, 2, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"},
+ [1193] = {109, 3, "DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"},
+ [1194] = {109, 4, "DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"},
+ [1195] = {109, 5, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK", "Input muxed clock"},
+ [1196] = {109, 6, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"},
+ [1197] = {109, 7, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"},
+ [1198] = {109, 8, "DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"},
+ [1199] = {109, 9, "DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"},
+ [1200] = {110, 0, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK", "Input muxed clock"},
+ [1201] = {110, 1, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"},
+ [1202] = {110, 2, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"},
+ [1203] = {110, 3, "DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK", "Input clock"},
+ [1204] = {110, 4, "DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK", "Output clock"},
+ [1205] = {110, 5, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK", "Input muxed clock"},
+ [1206] = {110, 6, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"},
+ [1207] = {110, 7, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"},
+ [1208] = {110, 8, "DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK", "Input clock"},
+ [1209] = {110, 9, "DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK", "Input clock"},
+ [1210] = {221, 0, "DEV_MCU_I2C0_PORSCL", "Output clock"},
+ [1211] = {221, 1, "DEV_MCU_I2C0_PISYS_CLK", "Input clock"},
+ [1212] = {221, 2, "DEV_MCU_I2C0_CLK", "Input clock"},
+ [1213] = {221, 3, "DEV_MCU_I2C0_PISCL", "Input clock"},
+ [1214] = {222, 0, "DEV_MCU_I2C1_PORSCL", "Output clock"},
+ [1215] = {222, 1, "DEV_MCU_I2C1_PISYS_CLK", "Input clock"},
+ [1216] = {222, 2, "DEV_MCU_I2C1_CLK", "Input clock"},
+ [1217] = {222, 3, "DEV_MCU_I2C1_PISCL", "Input clock"},
+ [1218] = {118, 0, "DEV_MCU_I3C0_I3C_SCL_DI", "Input clock"},
+ [1219] = {118, 1, "DEV_MCU_I3C0_I3C_SCL_DO", "Output clock"},
+ [1220] = {118, 2, "DEV_MCU_I3C0_I3C_SCLK_CLK", "Input clock"},
+ [1221] = {118, 3, "DEV_MCU_I3C0_I3C_PCLK_CLK", "Input clock"},
+ [1222] = {118, 4, "DEV_MCU_I3C0_I3C_SDA_DI", "Input clock"},
+ [1223] = {119, 2, "DEV_MCU_I3C1_I3C_SCLK_CLK", "Input clock"},
+ [1224] = {119, 3, "DEV_MCU_I3C1_I3C_PCLK_CLK", "Input clock"},
+ [1225] = {207, 0, "DEV_MCU_MCAN0_MCANSS_HCLK_CLK", "Input clock"},
+ [1226] = {207, 1, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [1227] = {207, 2, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
+ [1228] = {207, 3, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
+ [1229] = {207, 4, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
+ [1230] = {207, 5, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
+ [1231] = {207, 6, "DEV_MCU_MCAN0_MCANSS_CAN_RXD", "Input clock"},
+ [1232] = {208, 0, "DEV_MCU_MCAN1_MCANSS_HCLK_CLK", "Input clock"},
+ [1233] = {208, 1, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"},
+ [1234] = {208, 2, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
+ [1235] = {208, 3, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
+ [1236] = {208, 4, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
+ [1237] = {208, 5, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
+ [1238] = {208, 6, "DEV_MCU_MCAN1_MCANSS_CAN_RXD", "Input clock"},
+ [1239] = {347, 0, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"},
+ [1240] = {347, 1, "DEV_MCU_MCSPI0_VBUSP_CLK", "Input clock"},
+ [1241] = {347, 2, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"},
+ [1242] = {347, 3, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK", "Input muxed clock"},
+ [1243] = {347, 4, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT", "Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK"},
+ [1244] = {347, 5, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK"},
+ [1245] = {348, 0, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"},
+ [1246] = {348, 1, "DEV_MCU_MCSPI1_VBUSP_CLK", "Input clock"},
+ [1247] = {348, 2, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"},
+ [1248] = {348, 3, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"},
+ [1249] = {348, 4, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"},
+ [1250] = {348, 5, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_MCU_SPI1_CLK_LPBK_MUX_OUT0", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"},
+ [1251] = {349, 0, "DEV_MCU_MCSPI2_IO_CLKSPIO_CLK", "Output clock"},
+ [1252] = {349, 1, "DEV_MCU_MCSPI2_VBUSP_CLK", "Input clock"},
+ [1253] = {349, 2, "DEV_MCU_MCSPI2_CLKSPIREF_CLK", "Input clock"},
+ [1254] = {349, 3, "DEV_MCU_MCSPI2_IO_CLKSPII_CLK", "Input clock"},
+ [1255] = {268, 0, "DEV_MCU_NAVSS0_INTR_ROUTER_0_INTR_CLK", "Input clock"},
+ [1256] = {269, 0, "DEV_MCU_NAVSS0_MCRC_0_CLK", "Input clock"},
+ [1257] = {270, 0, "DEV_MCU_NAVSS0_MODSS_VD2CLK", "Input clock"},
+ [1258] = {271, 0, "DEV_MCU_NAVSS0_PROXY0_CLK_CLK", "Input clock"},
+ [1259] = {272, 0, "DEV_MCU_NAVSS0_RINGACC0_SYS_CLK", "Input clock"},
+ [1260] = {273, 0, "DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"},
+ [1261] = {274, 0, "DEV_MCU_NAVSS0_UDMASS_VD2CLK", "Input clock"},
+ [1262] = {275, 0, "DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK", "Input clock"},
+ [1263] = {176, 0, "DEV_MCU_PBIST0_CLK6_CLK", "Input clock"},
+ [1264] = {176, 1, "DEV_MCU_PBIST0_CLK8_CLK", "Input clock"},
+ [1265] = {176, 3, "DEV_MCU_PBIST0_CLK3_CLK", "Input clock"},
+ [1266] = {176, 4, "DEV_MCU_PBIST0_CLK7_CLK", "Input clock"},
+ [1267] = {176, 6, "DEV_MCU_PBIST0_CLK4_CLK", "Input clock"},
+ [1268] = {176, 7, "DEV_MCU_PBIST0_CLK5_CLK", "Input clock"},
+ [1269] = {176, 8, "DEV_MCU_PBIST0_CLK1_CLK", "Input clock"},
+ [1270] = {176, 9, "DEV_MCU_PBIST0_CLK2_CLK", "Input clock"},
+ [1271] = {177, 0, "DEV_MCU_PBIST1_CLK6_CLK", "Input clock"},
+ [1272] = {177, 1, "DEV_MCU_PBIST1_CLK8_CLK", "Input clock"},
+ [1273] = {177, 3, "DEV_MCU_PBIST1_CLK3_CLK", "Input clock"},
+ [1274] = {177, 4, "DEV_MCU_PBIST1_CLK7_CLK", "Input clock"},
+ [1275] = {177, 6, "DEV_MCU_PBIST1_CLK4_CLK", "Input clock"},
+ [1276] = {177, 7, "DEV_MCU_PBIST1_CLK5_CLK", "Input clock"},
+ [1277] = {177, 8, "DEV_MCU_PBIST1_CLK1_CLK", "Input clock"},
+ [1278] = {177, 9, "DEV_MCU_PBIST1_CLK2_CLK", "Input clock"},
+ [1279] = {178, 1, "DEV_MCU_PBIST2_CLK8_CLK", "Input clock"},
+ [1280] = {284, 0, "DEV_MCU_R5FSS0_CORE0_CPU_CLK", "Input muxed clock"},
+ [1281] = {284, 1, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"},
+ [1282] = {284, 2, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"},
+ [1283] = {284, 3, "DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"},
+ [1284] = {284, 4, "DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE", "Input clock"},
+ [1285] = {285, 0, "DEV_MCU_R5FSS0_CORE1_CPU_CLK", "Input muxed clock"},
+ [1286] = {285, 1, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"},
+ [1287] = {285, 2, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"},
+ [1288] = {285, 3, "DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"},
+ [1289] = {285, 4, "DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE", "Input clock"},
+ [1290] = {295, 0, "DEV_MCU_RTI0_VBUSP_CLK", "Input clock"},
+ [1291] = {295, 1, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"},
+ [1292] = {295, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
+ [1293] = {295, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
+ [1294] = {295, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
+ [1295] = {295, 5, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
+ [1296] = {296, 0, "DEV_MCU_RTI1_VBUSP_CLK", "Input clock"},
+ [1297] = {296, 1, "DEV_MCU_RTI1_RTI_CLK", "Input muxed clock"},
+ [1298] = {296, 2, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
+ [1299] = {296, 3, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
+ [1300] = {296, 4, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
+ [1301] = {296, 5, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
+ [1302] = {299, 0, "DEV_MCU_SA3_SS0_DMSS_ECCAGGR_0_X1_CLK", "Input clock"},
+ [1303] = {300, 0, "DEV_MCU_SA3_SS0_INTAGGR_0_X1_CLK", "Input clock"},
+ [1304] = {301, 0, "DEV_MCU_SA3_SS0_PKTDMA_0_X1_CLK", "Input clock"},
+ [1305] = {302, 0, "DEV_MCU_SA3_SS0_RINGACC_0_X1_CLK", "Input clock"},
+ [1306] = {303, 0, "DEV_MCU_SA3_SS0_SA_UL_0_PKA_IN_CLK", "Input clock"},
+ [1307] = {303, 1, "DEV_MCU_SA3_SS0_SA_UL_0_X1_CLK", "Input clock"},
+ [1308] = {303, 2, "DEV_MCU_SA3_SS0_SA_UL_0_X2_CLK", "Input clock"},
+ [1309] = {35, 0, "DEV_MCU_TIMER0_TIMER_PWM", "Output clock"},
+ [1310] = {35, 1, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1311] = {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+ [1312] = {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+ [1313] = {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+ [1314] = {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+ [1315] = {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+ [1316] = {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+ [1317] = {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+ [1318] = {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+ [1319] = {35, 10, "DEV_MCU_TIMER0_TIMER_HCLK_CLK", "Input clock"},
+ [1320] = {83, 1, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1321] = {83, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
+ [1322] = {83, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
+ [1323] = {83, 10, "DEV_MCU_TIMER1_TIMER_HCLK_CLK", "Input clock"},
+ [1324] = {84, 0, "DEV_MCU_TIMER2_TIMER_PWM", "Output clock"},
+ [1325] = {84, 1, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1326] = {84, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+ [1327] = {84, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+ [1328] = {84, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+ [1329] = {84, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+ [1330] = {84, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+ [1331] = {84, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+ [1332] = {84, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+ [1333] = {84, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+ [1334] = {84, 10, "DEV_MCU_TIMER2_TIMER_HCLK_CLK", "Input clock"},
+ [1335] = {85, 1, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1336] = {85, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
+ [1337] = {85, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
+ [1338] = {85, 10, "DEV_MCU_TIMER3_TIMER_HCLK_CLK", "Input clock"},
+ [1339] = {86, 0, "DEV_MCU_TIMER4_TIMER_PWM", "Output clock"},
+ [1340] = {86, 1, "DEV_MCU_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1341] = {86, 2, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+ [1342] = {86, 3, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+ [1343] = {86, 4, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+ [1344] = {86, 5, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+ [1345] = {86, 6, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+ [1346] = {86, 7, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+ [1347] = {86, 8, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+ [1348] = {86, 9, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+ [1349] = {86, 10, "DEV_MCU_TIMER4_TIMER_HCLK_CLK", "Input clock"},
+ [1350] = {87, 1, "DEV_MCU_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1351] = {87, 2, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"},
+ [1352] = {87, 3, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"},
+ [1353] = {87, 10, "DEV_MCU_TIMER5_TIMER_HCLK_CLK", "Input clock"},
+ [1354] = {88, 0, "DEV_MCU_TIMER6_TIMER_PWM", "Output clock"},
+ [1355] = {88, 1, "DEV_MCU_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1356] = {88, 2, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+ [1357] = {88, 3, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+ [1358] = {88, 4, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+ [1359] = {88, 5, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+ [1360] = {88, 6, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+ [1361] = {88, 7, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+ [1362] = {88, 8, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+ [1363] = {88, 9, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+ [1364] = {88, 10, "DEV_MCU_TIMER6_TIMER_HCLK_CLK", "Input clock"},
+ [1365] = {89, 1, "DEV_MCU_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1366] = {89, 2, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"},
+ [1367] = {89, 3, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"},
+ [1368] = {89, 10, "DEV_MCU_TIMER7_TIMER_HCLK_CLK", "Input clock"},
+ [1369] = {90, 0, "DEV_MCU_TIMER8_TIMER_PWM", "Output clock"},
+ [1370] = {90, 1, "DEV_MCU_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1371] = {90, 2, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+ [1372] = {90, 3, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+ [1373] = {90, 4, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+ [1374] = {90, 5, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+ [1375] = {90, 6, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+ [1376] = {90, 7, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+ [1377] = {90, 8, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+ [1378] = {90, 9, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+ [1379] = {90, 10, "DEV_MCU_TIMER8_TIMER_HCLK_CLK", "Input clock"},
+ [1380] = {91, 1, "DEV_MCU_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1381] = {91, 2, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"},
+ [1382] = {91, 3, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"},
+ [1383] = {91, 10, "DEV_MCU_TIMER9_TIMER_HCLK_CLK", "Input clock"},
+ [1384] = {149, 2, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"},
+ [1385] = {149, 3, "DEV_MCU_UART0_FCLK_CLK", "Input muxed clock"},
+ [1386] = {149, 4, "DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"},
+ [1387] = {149, 5, "DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"},
+ [1388] = {98, 1, "DEV_MMCSD0_EMMCSS_XIN_CLK", "Input muxed clock"},
+ [1389] = {98, 2, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
+ [1390] = {98, 3, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
+ [1391] = {98, 4, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
+ [1392] = {98, 5, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
+ [1393] = {98, 7, "DEV_MMCSD0_EMMCSS_VBUS_CLK", "Input clock"},
+ [1394] = {99, 1, "DEV_MMCSD1_EMMCSDSS_XIN_CLK", "Input muxed clock"},
+ [1395] = {99, 2, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
+ [1396] = {99, 3, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
+ [1397] = {99, 4, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
+ [1398] = {99, 5, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
+ [1399] = {99, 6, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O", "Output clock"},
+ [1400] = {99, 7, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I", "Input clock"},
+ [1401] = {99, 8, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"},
+ [1402] = {224, 0, "DEV_NAVSS0_CPTS0_GENF2", "Output clock"},
+ [1403] = {224, 1, "DEV_NAVSS0_CPTS0_GENF3", "Output clock"},
+ [1404] = {225, 0, "DEV_NAVSS0_BCDMA_0_CLK", "Input clock"},
+ [1405] = {226, 0, "DEV_NAVSS0_CPTS_0_TS_GENF0", "Output clock"},
+ [1406] = {226, 2, "DEV_NAVSS0_CPTS_0_TS_GENF1", "Output clock"},
+ [1407] = {226, 4, "DEV_NAVSS0_CPTS_0_VBUSP_GCLK", "Input clock"},
+ [1408] = {226, 5, "DEV_NAVSS0_CPTS_0_RCLK", "Input muxed clock"},
+ [1409] = {226, 6, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+ [1410] = {226, 7, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+ [1411] = {226, 8, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+ [1412] = {226, 9, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+ [1413] = {226, 10, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+ [1414] = {226, 11, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+ [1415] = {226, 12, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+ [1416] = {226, 13, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+ [1417] = {226, 14, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+ [1418] = {226, 15, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+ [1419] = {226, 20, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+ [1420] = {226, 21, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+ [1421] = {227, 0, "DEV_NAVSS0_INTR_0_INTR_CLK", "Input clock"},
+ [1422] = {228, 0, "DEV_NAVSS0_MAILBOX1_0_VCLK_CLK", "Input clock"},
+ [1423] = {229, 0, "DEV_NAVSS0_MAILBOX1_1_VCLK_CLK", "Input clock"},
+ [1424] = {238, 0, "DEV_NAVSS0_MAILBOX1_10_VCLK_CLK", "Input clock"},
+ [1425] = {239, 0, "DEV_NAVSS0_MAILBOX1_11_VCLK_CLK", "Input clock"},
+ [1426] = {230, 0, "DEV_NAVSS0_MAILBOX1_2_VCLK_CLK", "Input clock"},
+ [1427] = {231, 0, "DEV_NAVSS0_MAILBOX1_3_VCLK_CLK", "Input clock"},
+ [1428] = {232, 0, "DEV_NAVSS0_MAILBOX1_4_VCLK_CLK", "Input clock"},
+ [1429] = {233, 0, "DEV_NAVSS0_MAILBOX1_5_VCLK_CLK", "Input clock"},
+ [1430] = {234, 0, "DEV_NAVSS0_MAILBOX1_6_VCLK_CLK", "Input clock"},
+ [1431] = {235, 0, "DEV_NAVSS0_MAILBOX1_7_VCLK_CLK", "Input clock"},
+ [1432] = {236, 0, "DEV_NAVSS0_MAILBOX1_8_VCLK_CLK", "Input clock"},
+ [1433] = {237, 0, "DEV_NAVSS0_MAILBOX1_9_VCLK_CLK", "Input clock"},
+ [1434] = {240, 0, "DEV_NAVSS0_MAILBOX_0_VCLK_CLK", "Input clock"},
+ [1435] = {241, 0, "DEV_NAVSS0_MAILBOX_1_VCLK_CLK", "Input clock"},
+ [1436] = {250, 0, "DEV_NAVSS0_MAILBOX_10_VCLK_CLK", "Input clock"},
+ [1437] = {251, 0, "DEV_NAVSS0_MAILBOX_11_VCLK_CLK", "Input clock"},
+ [1438] = {242, 0, "DEV_NAVSS0_MAILBOX_2_VCLK_CLK", "Input clock"},
+ [1439] = {243, 0, "DEV_NAVSS0_MAILBOX_3_VCLK_CLK", "Input clock"},
+ [1440] = {244, 0, "DEV_NAVSS0_MAILBOX_4_VCLK_CLK", "Input clock"},
+ [1441] = {245, 0, "DEV_NAVSS0_MAILBOX_5_VCLK_CLK", "Input clock"},
+ [1442] = {246, 0, "DEV_NAVSS0_MAILBOX_6_VCLK_CLK", "Input clock"},
+ [1443] = {247, 0, "DEV_NAVSS0_MAILBOX_7_VCLK_CLK", "Input clock"},
+ [1444] = {248, 0, "DEV_NAVSS0_MAILBOX_8_VCLK_CLK", "Input clock"},
+ [1445] = {249, 0, "DEV_NAVSS0_MAILBOX_9_VCLK_CLK", "Input clock"},
+ [1446] = {252, 0, "DEV_NAVSS0_MCRC_0_CLK", "Input clock"},
+ [1447] = {253, 0, "DEV_NAVSS0_MODSS_VD2CLK", "Input clock"},
+ [1448] = {254, 0, "DEV_NAVSS0_MODSS_INTA_0_SYS_CLK", "Input clock"},
+ [1449] = {255, 0, "DEV_NAVSS0_MODSS_INTA_1_SYS_CLK", "Input clock"},
+ [1450] = {256, 0, "DEV_NAVSS0_PROXY_0_CLK_CLK", "Input clock"},
+ [1451] = {257, 0, "DEV_NAVSS0_PVU_0_CLK_CLK", "Input clock"},
+ [1452] = {258, 0, "DEV_NAVSS0_PVU_1_CLK_CLK", "Input clock"},
+ [1453] = {259, 0, "DEV_NAVSS0_RINGACC_0_SYS_CLK", "Input clock"},
+ [1454] = {260, 0, "DEV_NAVSS0_SPINLOCK_0_CLK", "Input clock"},
+ [1455] = {261, 0, "DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT", "Input clock"},
+ [1456] = {261, 1, "DEV_NAVSS0_TIMERMGR_0_VCLK_CLK", "Input clock"},
+ [1457] = {262, 0, "DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT", "Input clock"},
+ [1458] = {262, 1, "DEV_NAVSS0_TIMERMGR_1_VCLK_CLK", "Input clock"},
+ [1459] = {263, 0, "DEV_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"},
+ [1460] = {264, 0, "DEV_NAVSS0_UDMASS_VD2CLK", "Input clock"},
+ [1461] = {265, 0, "DEV_NAVSS0_UDMASS_INTA_0_SYS_CLK", "Input clock"},
+ [1462] = {266, 0, "DEV_NAVSS0_VIRTSS_VD2CLK", "Input clock"},
+ [1463] = {171, 1, "DEV_PBIST0_CLK8_CLK", "Input clock"},
+ [1464] = {172, 1, "DEV_PBIST1_CLK8_CLK", "Input clock"},
+ [1465] = {175, 1, "DEV_PBIST10_CLK8_CLK", "Input clock"},
+ [1466] = {168, 4, "DEV_PBIST11_CLK7_CLK", "Input clock"},
+ [1467] = {174, 1, "DEV_PBIST2_CLK8_CLK", "Input clock"},
+ [1468] = {170, 1, "DEV_PBIST3_CLK8_CLK", "Input clock"},
+ [1469] = {173, 1, "DEV_PBIST4_CLK8_CLK", "Input clock"},
+ [1470] = {167, 1, "DEV_PBIST5_CLK8_CLK", "Input clock"},
+ [1471] = {276, 0, "DEV_PCIE1_PCIE_LANE0_TXMCLK", "Input clock"},
+ [1472] = {276, 1, "DEV_PCIE1_PCIE_LANE0_TXFCLK", "Input clock"},
+ [1473] = {276, 2, "DEV_PCIE1_PCIE_LANE0_RXFCLK", "Input clock"},
+ [1474] = {276, 3, "DEV_PCIE1_PCIE_LANE0_TXCLK", "Output clock"},
+ [1475] = {276, 4, "DEV_PCIE1_PCIE_LANE3_RXFCLK", "Input clock"},
+ [1476] = {276, 5, "DEV_PCIE1_PCIE_LANE3_RXCLK", "Input clock"},
+ [1477] = {276, 6, "DEV_PCIE1_PCIE_LANE2_RXFCLK", "Input clock"},
+ [1478] = {276, 7, "DEV_PCIE1_PCIE_LANE1_TXCLK", "Output clock"},
+ [1479] = {276, 8, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
+ [1480] = {276, 9, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+ [1481] = {276, 10, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+ [1482] = {276, 11, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+ [1483] = {276, 12, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+ [1484] = {276, 13, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+ [1485] = {276, 14, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+ [1486] = {276, 15, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+ [1487] = {276, 16, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+ [1488] = {276, 17, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+ [1489] = {276, 18, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+ [1490] = {276, 23, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+ [1491] = {276, 24, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+ [1492] = {276, 26, "DEV_PCIE1_PCIE_LANE3_TXMCLK", "Input clock"},
+ [1493] = {276, 27, "DEV_PCIE1_PCIE_LANE2_RXCLK", "Input clock"},
+ [1494] = {276, 28, "DEV_PCIE1_PCIE_LANE1_RXFCLK", "Input clock"},
+ [1495] = {276, 29, "DEV_PCIE1_PCIE_LANE0_RXCLK", "Input clock"},
+ [1496] = {276, 30, "DEV_PCIE1_PCIE_LANE2_REFCLK", "Input clock"},
+ [1497] = {276, 31, "DEV_PCIE1_PCIE_LANE3_REFCLK", "Input clock"},
+ [1498] = {276, 32, "DEV_PCIE1_PCIE_LANE2_TXMCLK", "Input clock"},
+ [1499] = {276, 33, "DEV_PCIE1_PCIE_LANE1_REFCLK", "Input clock"},
+ [1500] = {276, 34, "DEV_PCIE1_PCIE_LANE2_TXFCLK", "Input clock"},
+ [1501] = {276, 35, "DEV_PCIE1_PCIE_PM_CLK", "Input clock"},
+ [1502] = {276, 36, "DEV_PCIE1_PCIE_LANE1_TXFCLK", "Input clock"},
+ [1503] = {276, 37, "DEV_PCIE1_PCIE_LANE1_TXMCLK", "Input clock"},
+ [1504] = {276, 38, "DEV_PCIE1_PCIE_LANE0_REFCLK", "Input clock"},
+ [1505] = {276, 39, "DEV_PCIE1_PCIE_LANE1_RXCLK", "Input clock"},
+ [1506] = {276, 40, "DEV_PCIE1_PCIE_LANE3_TXFCLK", "Input clock"},
+ [1507] = {276, 41, "DEV_PCIE1_PCIE_CBA_CLK", "Input clock"},
+ [1508] = {276, 42, "DEV_PCIE1_PCIE_LANE2_TXCLK", "Output clock"},
+ [1509] = {276, 43, "DEV_PCIE1_PCIE_LANE3_TXCLK", "Output clock"},
+ [1510] = {143, 0, "DEV_PSC0_SLOW_CLK", "Input clock"},
+ [1511] = {143, 1, "DEV_PSC0_CLK", "Input clock"},
+ [1512] = {279, 0, "DEV_R5FSS0_CORE0_CPU_CLK", "Input clock"},
+ [1513] = {279, 1, "DEV_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"},
+ [1514] = {280, 0, "DEV_R5FSS0_CORE1_CPU_CLK", "Input clock"},
+ [1515] = {280, 1, "DEV_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"},
+ [1516] = {281, 0, "DEV_R5FSS1_CORE0_CPU_CLK", "Input clock"},
+ [1517] = {281, 1, "DEV_R5FSS1_CORE0_INTERFACE_CLK", "Input clock"},
+ [1518] = {282, 0, "DEV_R5FSS1_CORE1_CPU_CLK", "Input clock"},
+ [1519] = {282, 1, "DEV_R5FSS1_CORE1_INTERFACE_CLK", "Input clock"},
+ [1520] = {286, 0, "DEV_RTI0_VBUSP_CLK", "Input clock"},
+ [1521] = {286, 1, "DEV_RTI0_RTI_CLK", "Input muxed clock"},
+ [1522] = {286, 2, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+ [1523] = {286, 3, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+ [1524] = {286, 4, "DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+ [1525] = {286, 5, "DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+ [1526] = {286, 6, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+ [1527] = {286, 7, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+ [1528] = {286, 8, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+ [1529] = {286, 9, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+ [1530] = {287, 0, "DEV_RTI1_VBUSP_CLK", "Input clock"},
+ [1531] = {287, 1, "DEV_RTI1_RTI_CLK", "Input muxed clock"},
+ [1532] = {287, 2, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+ [1533] = {287, 3, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+ [1534] = {287, 4, "DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+ [1535] = {287, 5, "DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+ [1536] = {287, 6, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+ [1537] = {287, 7, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+ [1538] = {287, 8, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+ [1539] = {287, 9, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+ [1540] = {290, 0, "DEV_RTI15_VBUSP_CLK", "Input clock"},
+ [1541] = {290, 1, "DEV_RTI15_RTI_CLK", "Input muxed clock"},
+ [1542] = {290, 2, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+ [1543] = {290, 3, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+ [1544] = {290, 4, "DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+ [1545] = {290, 5, "DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+ [1546] = {290, 6, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+ [1547] = {290, 7, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+ [1548] = {290, 8, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+ [1549] = {290, 9, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+ [1550] = {288, 0, "DEV_RTI16_VBUSP_CLK", "Input clock"},
+ [1551] = {288, 1, "DEV_RTI16_RTI_CLK", "Input muxed clock"},
+ [1552] = {288, 2, "DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI16_RTI_CLK"},
+ [1553] = {288, 3, "DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI16_RTI_CLK"},
+ [1554] = {288, 4, "DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI16_RTI_CLK"},
+ [1555] = {288, 5, "DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI16_RTI_CLK"},
+ [1556] = {288, 6, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI16_RTI_CLK"},
+ [1557] = {288, 7, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI16_RTI_CLK"},
+ [1558] = {288, 8, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI16_RTI_CLK"},
+ [1559] = {288, 9, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI16_RTI_CLK"},
+ [1560] = {289, 0, "DEV_RTI17_VBUSP_CLK", "Input clock"},
+ [1561] = {289, 1, "DEV_RTI17_RTI_CLK", "Input muxed clock"},
+ [1562] = {289, 2, "DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI17_RTI_CLK"},
+ [1563] = {289, 3, "DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI17_RTI_CLK"},
+ [1564] = {289, 4, "DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI17_RTI_CLK"},
+ [1565] = {289, 5, "DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI17_RTI_CLK"},
+ [1566] = {289, 6, "DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI17_RTI_CLK"},
+ [1567] = {289, 7, "DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI17_RTI_CLK"},
+ [1568] = {289, 8, "DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI17_RTI_CLK"},
+ [1569] = {289, 9, "DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI17_RTI_CLK"},
+ [1570] = {291, 0, "DEV_RTI28_VBUSP_CLK", "Input clock"},
+ [1571] = {291, 1, "DEV_RTI28_RTI_CLK", "Input muxed clock"},
+ [1572] = {291, 2, "DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+ [1573] = {291, 3, "DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+ [1574] = {291, 4, "DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+ [1575] = {291, 5, "DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+ [1576] = {291, 6, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+ [1577] = {291, 7, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+ [1578] = {291, 8, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+ [1579] = {291, 9, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+ [1580] = {292, 0, "DEV_RTI29_VBUSP_CLK", "Input clock"},
+ [1581] = {292, 1, "DEV_RTI29_RTI_CLK", "Input muxed clock"},
+ [1582] = {292, 2, "DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+ [1583] = {292, 3, "DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+ [1584] = {292, 4, "DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+ [1585] = {292, 5, "DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+ [1586] = {292, 6, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+ [1587] = {292, 7, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+ [1588] = {292, 8, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+ [1589] = {292, 9, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+ [1590] = {293, 0, "DEV_RTI30_VBUSP_CLK", "Input clock"},
+ [1591] = {293, 1, "DEV_RTI30_RTI_CLK", "Input muxed clock"},
+ [1592] = {293, 2, "DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI30_RTI_CLK"},
+ [1593] = {293, 3, "DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI30_RTI_CLK"},
+ [1594] = {293, 4, "DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI30_RTI_CLK"},
+ [1595] = {293, 5, "DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI30_RTI_CLK"},
+ [1596] = {293, 6, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI30_RTI_CLK"},
+ [1597] = {293, 7, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI30_RTI_CLK"},
+ [1598] = {293, 8, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI30_RTI_CLK"},
+ [1599] = {293, 9, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI30_RTI_CLK"},
+ [1600] = {294, 0, "DEV_RTI31_VBUSP_CLK", "Input clock"},
+ [1601] = {294, 1, "DEV_RTI31_RTI_CLK", "Input muxed clock"},
+ [1602] = {294, 2, "DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI31_RTI_CLK"},
+ [1603] = {294, 3, "DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI31_RTI_CLK"},
+ [1604] = {294, 4, "DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI31_RTI_CLK"},
+ [1605] = {294, 5, "DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI31_RTI_CLK"},
+ [1606] = {294, 6, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI31_RTI_CLK"},
+ [1607] = {294, 7, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI31_RTI_CLK"},
+ [1608] = {294, 8, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI31_RTI_CLK"},
+ [1609] = {294, 9, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI31_RTI_CLK"},
+ [1610] = {145, 0, "DEV_SA2_CPSW_PSILSS0_MAIN_CLK", "Input clock"},
+ [1611] = {145, 1, "DEV_SA2_CPSW_PSILSS0_MAIN_2_CLK", "Input clock"},
+ [1612] = {297, 0, "DEV_SA2_UL0_PKA_IN_CLK", "Input clock"},
+ [1613] = {297, 1, "DEV_SA2_UL0_X1_CLK", "Input clock"},
+ [1614] = {297, 2, "DEV_SA2_UL0_X2_CLK", "Input clock"},
+ [1615] = {365, 0, "DEV_SERDES_10G0_CLK", "Input clock"},
+ [1616] = {365, 1, "DEV_SERDES_10G0_CMN_REFCLK_M", "Input clock"},
+ [1617] = {365, 1, "DEV_SERDES_10G0_CMN_REFCLK_M", "Output clock"},
+ [1618] = {365, 2, "DEV_SERDES_10G0_CMN_REFCLK_P", "Input clock"},
+ [1619] = {365, 2, "DEV_SERDES_10G0_CMN_REFCLK_P", "Output clock"},
+ [1620] = {365, 3, "DEV_SERDES_10G0_CORE_REF_CLK", "Input muxed clock"},
+ [1621] = {365, 4, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
+ [1622] = {365, 5, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
+ [1623] = {365, 6, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
+ [1624] = {365, 7, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
+ [1625] = {365, 9, "DEV_SERDES_10G0_IP1_LN0_REFCLK", "Output clock"},
+ [1626] = {365, 10, "DEV_SERDES_10G0_IP1_LN0_RXCLK", "Output clock"},
+ [1627] = {365, 11, "DEV_SERDES_10G0_IP1_LN0_RXFCLK", "Output clock"},
+ [1628] = {365, 12, "DEV_SERDES_10G0_IP1_LN0_TXCLK", "Input clock"},
+ [1629] = {365, 13, "DEV_SERDES_10G0_IP1_LN0_TXFCLK", "Output clock"},
+ [1630] = {365, 14, "DEV_SERDES_10G0_IP1_LN0_TXMCLK", "Output clock"},
+ [1631] = {365, 15, "DEV_SERDES_10G0_IP1_LN1_REFCLK", "Output clock"},
+ [1632] = {365, 16, "DEV_SERDES_10G0_IP1_LN1_RXCLK", "Output clock"},
+ [1633] = {365, 17, "DEV_SERDES_10G0_IP1_LN1_RXFCLK", "Output clock"},
+ [1634] = {365, 18, "DEV_SERDES_10G0_IP1_LN1_TXCLK", "Input clock"},
+ [1635] = {365, 19, "DEV_SERDES_10G0_IP1_LN1_TXFCLK", "Output clock"},
+ [1636] = {365, 20, "DEV_SERDES_10G0_IP1_LN1_TXMCLK", "Output clock"},
+ [1637] = {365, 21, "DEV_SERDES_10G0_IP1_LN2_REFCLK", "Output clock"},
+ [1638] = {365, 22, "DEV_SERDES_10G0_IP1_LN2_RXCLK", "Output clock"},
+ [1639] = {365, 23, "DEV_SERDES_10G0_IP1_LN2_RXFCLK", "Output clock"},
+ [1640] = {365, 24, "DEV_SERDES_10G0_IP1_LN2_TXCLK", "Input muxed clock"},
+ [1641] = {365, 25, "DEV_SERDES_10G0_IP1_LN2_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN2_TXCLK", "Parent input clock option to DEV_SERDES_10G0_IP1_LN2_TXCLK"},
+ [1642] = {365, 26, "DEV_SERDES_10G0_IP1_LN2_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN0_TXCLK", "Parent input clock option to DEV_SERDES_10G0_IP1_LN2_TXCLK"},
+ [1643] = {365, 27, "DEV_SERDES_10G0_IP1_LN2_TXFCLK", "Output clock"},
+ [1644] = {365, 28, "DEV_SERDES_10G0_IP1_LN2_TXMCLK", "Output clock"},
+ [1645] = {365, 29, "DEV_SERDES_10G0_IP1_LN3_REFCLK", "Output clock"},
+ [1646] = {365, 30, "DEV_SERDES_10G0_IP1_LN3_RXCLK", "Output clock"},
+ [1647] = {365, 31, "DEV_SERDES_10G0_IP1_LN3_RXFCLK", "Output clock"},
+ [1648] = {365, 32, "DEV_SERDES_10G0_IP1_LN3_TXCLK", "Input muxed clock"},
+ [1649] = {365, 33, "DEV_SERDES_10G0_IP1_LN3_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN3_TXCLK", "Parent input clock option to DEV_SERDES_10G0_IP1_LN3_TXCLK"},
+ [1650] = {365, 34, "DEV_SERDES_10G0_IP1_LN3_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN1_TXCLK", "Parent input clock option to DEV_SERDES_10G0_IP1_LN3_TXCLK"},
+ [1651] = {365, 35, "DEV_SERDES_10G0_IP1_LN3_TXFCLK", "Output clock"},
+ [1652] = {365, 36, "DEV_SERDES_10G0_IP1_LN3_TXMCLK", "Output clock"},
+ [1653] = {365, 37, "DEV_SERDES_10G0_IP2_LN0_REFCLK", "Output clock"},
+ [1654] = {365, 38, "DEV_SERDES_10G0_IP2_LN0_RXCLK", "Output clock"},
+ [1655] = {365, 39, "DEV_SERDES_10G0_IP2_LN0_RXFCLK", "Output clock"},
+ [1656] = {365, 40, "DEV_SERDES_10G0_IP2_LN0_TXCLK", "Input clock"},
+ [1657] = {365, 41, "DEV_SERDES_10G0_IP2_LN0_TXFCLK", "Output clock"},
+ [1658] = {365, 42, "DEV_SERDES_10G0_IP2_LN0_TXMCLK", "Output clock"},
+ [1659] = {365, 43, "DEV_SERDES_10G0_IP2_LN1_REFCLK", "Output clock"},
+ [1660] = {365, 44, "DEV_SERDES_10G0_IP2_LN1_RXCLK", "Output clock"},
+ [1661] = {365, 45, "DEV_SERDES_10G0_IP2_LN1_RXFCLK", "Output clock"},
+ [1662] = {365, 46, "DEV_SERDES_10G0_IP2_LN1_TXCLK", "Input clock"},
+ [1663] = {365, 47, "DEV_SERDES_10G0_IP2_LN1_TXFCLK", "Output clock"},
+ [1664] = {365, 48, "DEV_SERDES_10G0_IP2_LN1_TXMCLK", "Output clock"},
+ [1665] = {365, 49, "DEV_SERDES_10G0_IP2_LN2_REFCLK", "Output clock"},
+ [1666] = {365, 50, "DEV_SERDES_10G0_IP2_LN2_RXCLK", "Output clock"},
+ [1667] = {365, 51, "DEV_SERDES_10G0_IP2_LN2_RXFCLK", "Output clock"},
+ [1668] = {365, 52, "DEV_SERDES_10G0_IP2_LN2_TXCLK", "Input clock"},
+ [1669] = {365, 53, "DEV_SERDES_10G0_IP2_LN2_TXFCLK", "Output clock"},
+ [1670] = {365, 54, "DEV_SERDES_10G0_IP2_LN2_TXMCLK", "Output clock"},
+ [1671] = {365, 55, "DEV_SERDES_10G0_IP2_LN3_REFCLK", "Output clock"},
+ [1672] = {365, 56, "DEV_SERDES_10G0_IP2_LN3_RXCLK", "Output clock"},
+ [1673] = {365, 57, "DEV_SERDES_10G0_IP2_LN3_RXFCLK", "Output clock"},
+ [1674] = {365, 58, "DEV_SERDES_10G0_IP2_LN3_TXCLK", "Input clock"},
+ [1675] = {365, 59, "DEV_SERDES_10G0_IP2_LN3_TXFCLK", "Output clock"},
+ [1676] = {365, 60, "DEV_SERDES_10G0_IP2_LN3_TXMCLK", "Output clock"},
+ [1677] = {365, 67, "DEV_SERDES_10G0_IP3_LN1_REFCLK", "Output clock"},
+ [1678] = {365, 68, "DEV_SERDES_10G0_IP3_LN1_RXCLK", "Output clock"},
+ [1679] = {365, 69, "DEV_SERDES_10G0_IP3_LN1_RXFCLK", "Output clock"},
+ [1680] = {365, 70, "DEV_SERDES_10G0_IP3_LN1_TXCLK", "Input clock"},
+ [1681] = {365, 71, "DEV_SERDES_10G0_IP3_LN1_TXFCLK", "Output clock"},
+ [1682] = {365, 72, "DEV_SERDES_10G0_IP3_LN1_TXMCLK", "Output clock"},
+ [1683] = {365, 79, "DEV_SERDES_10G0_IP3_LN3_REFCLK", "Output clock"},
+ [1684] = {365, 80, "DEV_SERDES_10G0_IP3_LN3_RXCLK", "Output clock"},
+ [1685] = {365, 81, "DEV_SERDES_10G0_IP3_LN3_RXFCLK", "Output clock"},
+ [1686] = {365, 82, "DEV_SERDES_10G0_IP3_LN3_TXCLK", "Input clock"},
+ [1687] = {365, 83, "DEV_SERDES_10G0_IP3_LN3_TXFCLK", "Output clock"},
+ [1688] = {365, 84, "DEV_SERDES_10G0_IP3_LN3_TXMCLK", "Output clock"},
+ [1689] = {365, 85, "DEV_SERDES_10G0_IP4_LN0_REFCLK", "Output clock"},
+ [1690] = {365, 86, "DEV_SERDES_10G0_IP4_LN0_RXCLK", "Output clock"},
+ [1691] = {365, 87, "DEV_SERDES_10G0_IP4_LN0_RXFCLK", "Output clock"},
+ [1692] = {365, 88, "DEV_SERDES_10G0_IP4_LN0_TXCLK", "Input clock"},
+ [1693] = {365, 89, "DEV_SERDES_10G0_IP4_LN0_TXFCLK", "Output clock"},
+ [1694] = {365, 90, "DEV_SERDES_10G0_IP4_LN0_TXMCLK", "Output clock"},
+ [1695] = {365, 91, "DEV_SERDES_10G0_IP4_LN1_REFCLK", "Output clock"},
+ [1696] = {365, 92, "DEV_SERDES_10G0_IP4_LN1_RXCLK", "Output clock"},
+ [1697] = {365, 93, "DEV_SERDES_10G0_IP4_LN1_RXFCLK", "Output clock"},
+ [1698] = {365, 94, "DEV_SERDES_10G0_IP4_LN1_TXCLK", "Input clock"},
+ [1699] = {365, 95, "DEV_SERDES_10G0_IP4_LN1_TXFCLK", "Output clock"},
+ [1700] = {365, 96, "DEV_SERDES_10G0_IP4_LN1_TXMCLK", "Output clock"},
+ [1701] = {365, 97, "DEV_SERDES_10G0_IP4_LN2_REFCLK", "Output clock"},
+ [1702] = {365, 98, "DEV_SERDES_10G0_IP4_LN2_RXCLK", "Output clock"},
+ [1703] = {365, 99, "DEV_SERDES_10G0_IP4_LN2_RXFCLK", "Output clock"},
+ [1704] = {365, 100, "DEV_SERDES_10G0_IP4_LN2_TXCLK", "Input clock"},
+ [1705] = {365, 101, "DEV_SERDES_10G0_IP4_LN2_TXFCLK", "Output clock"},
+ [1706] = {365, 102, "DEV_SERDES_10G0_IP4_LN2_TXMCLK", "Output clock"},
+ [1707] = {365, 103, "DEV_SERDES_10G0_IP4_LN3_REFCLK", "Output clock"},
+ [1708] = {365, 104, "DEV_SERDES_10G0_IP4_LN3_RXCLK", "Output clock"},
+ [1709] = {365, 105, "DEV_SERDES_10G0_IP4_LN3_RXFCLK", "Output clock"},
+ [1710] = {365, 106, "DEV_SERDES_10G0_IP4_LN3_TXCLK", "Input clock"},
+ [1711] = {365, 107, "DEV_SERDES_10G0_IP4_LN3_TXFCLK", "Output clock"},
+ [1712] = {365, 108, "DEV_SERDES_10G0_IP4_LN3_TXMCLK", "Output clock"},
+ [1713] = {365, 130, "DEV_SERDES_10G0_TAP_TCK", "Input clock"},
+ [1714] = {42, 0, "DEV_STM0_CORE_CLK", "Input clock"},
+ [1715] = {42, 1, "DEV_STM0_VBUSP_CLK", "Input clock"},
+ [1716] = {42, 2, "DEV_STM0_ATB_CLK", "Input clock"},
+ [1717] = {63, 0, "DEV_TIMER0_TIMER_PWM", "Output clock"},
+ [1718] = {63, 1, "DEV_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1719] = {63, 2, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [1720] = {63, 3, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [1721] = {63, 4, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [1722] = {63, 5, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [1723] = {63, 6, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [1724] = {63, 7, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [1725] = {63, 8, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [1726] = {63, 9, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [1727] = {63, 10, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [1728] = {63, 11, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [1729] = {63, 12, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [1730] = {63, 13, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [1731] = {63, 14, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [1732] = {63, 15, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [1733] = {63, 16, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+ [1734] = {63, 18, "DEV_TIMER0_TIMER_HCLK_CLK", "Input clock"},
+ [1735] = {64, 1, "DEV_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1736] = {64, 2, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
+ [1737] = {64, 3, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
+ [1738] = {64, 18, "DEV_TIMER1_TIMER_HCLK_CLK", "Input clock"},
+ [1739] = {73, 0, "DEV_TIMER10_TIMER_PWM", "Output clock"},
+ [1740] = {73, 1, "DEV_TIMER10_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1741] = {73, 2, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+ [1742] = {73, 3, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+ [1743] = {73, 4, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+ [1744] = {73, 5, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+ [1745] = {73, 6, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+ [1746] = {73, 7, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+ [1747] = {73, 8, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+ [1748] = {73, 9, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+ [1749] = {73, 10, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+ [1750] = {73, 11, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+ [1751] = {73, 12, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+ [1752] = {73, 13, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+ [1753] = {73, 14, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+ [1754] = {73, 15, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+ [1755] = {73, 16, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+ [1756] = {73, 18, "DEV_TIMER10_TIMER_HCLK_CLK", "Input clock"},
+ [1757] = {74, 1, "DEV_TIMER11_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1758] = {74, 2, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
+ [1759] = {74, 3, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
+ [1760] = {74, 18, "DEV_TIMER11_TIMER_HCLK_CLK", "Input clock"},
+ [1761] = {75, 0, "DEV_TIMER12_TIMER_PWM", "Output clock"},
+ [1762] = {75, 1, "DEV_TIMER12_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1763] = {75, 2, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+ [1764] = {75, 3, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+ [1765] = {75, 4, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+ [1766] = {75, 5, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+ [1767] = {75, 6, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+ [1768] = {75, 7, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+ [1769] = {75, 8, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+ [1770] = {75, 9, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+ [1771] = {75, 10, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+ [1772] = {75, 11, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+ [1773] = {75, 12, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+ [1774] = {75, 13, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+ [1775] = {75, 14, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+ [1776] = {75, 15, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+ [1777] = {75, 16, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+ [1778] = {75, 18, "DEV_TIMER12_TIMER_HCLK_CLK", "Input clock"},
+ [1779] = {76, 1, "DEV_TIMER13_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1780] = {76, 2, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"},
+ [1781] = {76, 3, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"},
+ [1782] = {76, 18, "DEV_TIMER13_TIMER_HCLK_CLK", "Input clock"},
+ [1783] = {77, 0, "DEV_TIMER14_TIMER_PWM", "Output clock"},
+ [1784] = {77, 1, "DEV_TIMER14_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1785] = {77, 2, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+ [1786] = {77, 3, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+ [1787] = {77, 4, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+ [1788] = {77, 5, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+ [1789] = {77, 6, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+ [1790] = {77, 7, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+ [1791] = {77, 8, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+ [1792] = {77, 9, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+ [1793] = {77, 10, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+ [1794] = {77, 11, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+ [1795] = {77, 12, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+ [1796] = {77, 13, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+ [1797] = {77, 14, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+ [1798] = {77, 15, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+ [1799] = {77, 16, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+ [1800] = {77, 18, "DEV_TIMER14_TIMER_HCLK_CLK", "Input clock"},
+ [1801] = {78, 1, "DEV_TIMER15_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1802] = {78, 2, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"},
+ [1803] = {78, 3, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"},
+ [1804] = {78, 18, "DEV_TIMER15_TIMER_HCLK_CLK", "Input clock"},
+ [1805] = {79, 0, "DEV_TIMER16_TIMER_PWM", "Output clock"},
+ [1806] = {79, 1, "DEV_TIMER16_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1807] = {79, 2, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT16", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+ [1808] = {79, 3, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER16_AFS_SEL_OUT0", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+ [1809] = {79, 34, "DEV_TIMER16_TIMER_HCLK_CLK", "Input clock"},
+ [1810] = {80, 1, "DEV_TIMER17_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1811] = {80, 2, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER17_AFS_EN_OUT0", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"},
+ [1812] = {80, 3, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"},
+ [1813] = {80, 34, "DEV_TIMER17_TIMER_HCLK_CLK", "Input clock"},
+ [1814] = {81, 0, "DEV_TIMER18_TIMER_PWM", "Output clock"},
+ [1815] = {81, 1, "DEV_TIMER18_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1816] = {81, 2, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT18", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+ [1817] = {81, 3, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER18_AFS_SEL_OUT0", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+ [1818] = {81, 34, "DEV_TIMER18_TIMER_HCLK_CLK", "Input clock"},
+ [1819] = {82, 1, "DEV_TIMER19_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1820] = {82, 2, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER19_AFS_EN_OUT0", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"},
+ [1821] = {82, 3, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"},
+ [1822] = {82, 34, "DEV_TIMER19_TIMER_HCLK_CLK", "Input clock"},
+ [1823] = {65, 0, "DEV_TIMER2_TIMER_PWM", "Output clock"},
+ [1824] = {65, 1, "DEV_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1825] = {65, 2, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [1826] = {65, 3, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [1827] = {65, 4, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [1828] = {65, 5, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [1829] = {65, 6, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [1830] = {65, 7, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [1831] = {65, 8, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [1832] = {65, 9, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [1833] = {65, 10, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [1834] = {65, 11, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [1835] = {65, 12, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [1836] = {65, 13, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [1837] = {65, 14, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [1838] = {65, 15, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [1839] = {65, 16, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+ [1840] = {65, 18, "DEV_TIMER2_TIMER_HCLK_CLK", "Input clock"},
+ [1841] = {66, 1, "DEV_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1842] = {66, 2, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
+ [1843] = {66, 3, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
+ [1844] = {66, 18, "DEV_TIMER3_TIMER_HCLK_CLK", "Input clock"},
+ [1845] = {67, 0, "DEV_TIMER4_TIMER_PWM", "Output clock"},
+ [1846] = {67, 1, "DEV_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1847] = {67, 2, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [1848] = {67, 3, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [1849] = {67, 4, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [1850] = {67, 5, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [1851] = {67, 6, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [1852] = {67, 7, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [1853] = {67, 8, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [1854] = {67, 9, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [1855] = {67, 10, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [1856] = {67, 11, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [1857] = {67, 12, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [1858] = {67, 13, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [1859] = {67, 14, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [1860] = {67, 15, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [1861] = {67, 16, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+ [1862] = {67, 18, "DEV_TIMER4_TIMER_HCLK_CLK", "Input clock"},
+ [1863] = {68, 1, "DEV_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1864] = {68, 2, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
+ [1865] = {68, 3, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
+ [1866] = {68, 18, "DEV_TIMER5_TIMER_HCLK_CLK", "Input clock"},
+ [1867] = {69, 0, "DEV_TIMER6_TIMER_PWM", "Output clock"},
+ [1868] = {69, 1, "DEV_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1869] = {69, 2, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [1870] = {69, 3, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [1871] = {69, 4, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [1872] = {69, 5, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [1873] = {69, 6, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [1874] = {69, 7, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [1875] = {69, 8, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [1876] = {69, 9, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [1877] = {69, 10, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [1878] = {69, 11, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [1879] = {69, 12, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [1880] = {69, 13, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [1881] = {69, 14, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [1882] = {69, 15, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [1883] = {69, 16, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+ [1884] = {69, 18, "DEV_TIMER6_TIMER_HCLK_CLK", "Input clock"},
+ [1885] = {70, 1, "DEV_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1886] = {70, 2, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
+ [1887] = {70, 3, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
+ [1888] = {70, 18, "DEV_TIMER7_TIMER_HCLK_CLK", "Input clock"},
+ [1889] = {71, 0, "DEV_TIMER8_TIMER_PWM", "Output clock"},
+ [1890] = {71, 1, "DEV_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1891] = {71, 2, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+ [1892] = {71, 3, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+ [1893] = {71, 4, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+ [1894] = {71, 5, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+ [1895] = {71, 6, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+ [1896] = {71, 7, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+ [1897] = {71, 8, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+ [1898] = {71, 9, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+ [1899] = {71, 10, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+ [1900] = {71, 11, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+ [1901] = {71, 12, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+ [1902] = {71, 13, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+ [1903] = {71, 14, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+ [1904] = {71, 15, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+ [1905] = {71, 16, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+ [1906] = {71, 18, "DEV_TIMER8_TIMER_HCLK_CLK", "Input clock"},
+ [1907] = {72, 1, "DEV_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"},
+ [1908] = {72, 2, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
+ [1909] = {72, 3, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
+ [1910] = {72, 18, "DEV_TIMER9_TIMER_HCLK_CLK", "Input clock"},
+ [1911] = {124, 0, "DEV_TIMESYNC_INTRTR0_INTR_CLK", "Input clock"},
+ [1912] = {146, 2, "DEV_UART0_VBUSP_CLK", "Input clock"},
+ [1913] = {146, 3, "DEV_UART0_FCLK_CLK", "Input clock"},
+ [1914] = {350, 2, "DEV_UART1_VBUSP_CLK", "Input clock"},
+ [1915] = {350, 3, "DEV_UART1_FCLK_CLK", "Input clock"},
+ [1916] = {351, 2, "DEV_UART2_VBUSP_CLK", "Input clock"},
+ [1917] = {351, 3, "DEV_UART2_FCLK_CLK", "Input clock"},
+ [1918] = {352, 2, "DEV_UART3_VBUSP_CLK", "Input clock"},
+ [1919] = {352, 3, "DEV_UART3_FCLK_CLK", "Input clock"},
+ [1920] = {353, 2, "DEV_UART4_VBUSP_CLK", "Input clock"},
+ [1921] = {353, 3, "DEV_UART4_FCLK_CLK", "Input clock"},
+ [1922] = {354, 2, "DEV_UART5_VBUSP_CLK", "Input clock"},
+ [1923] = {354, 3, "DEV_UART5_FCLK_CLK", "Input clock"},
+ [1924] = {355, 2, "DEV_UART6_VBUSP_CLK", "Input clock"},
+ [1925] = {355, 3, "DEV_UART6_FCLK_CLK", "Input clock"},
+ [1926] = {356, 2, "DEV_UART7_VBUSP_CLK", "Input clock"},
+ [1927] = {356, 3, "DEV_UART7_FCLK_CLK", "Input clock"},
+ [1928] = {357, 2, "DEV_UART8_VBUSP_CLK", "Input clock"},
+ [1929] = {357, 3, "DEV_UART8_FCLK_CLK", "Input clock"},
+ [1930] = {358, 2, "DEV_UART9_VBUSP_CLK", "Input clock"},
+ [1931] = {358, 3, "DEV_UART9_FCLK_CLK", "Input clock"},
+ [1932] = {360, 1, "DEV_USB0_PIPE_RXFCLK", "Input muxed clock"},
+ [1933] = {360, 2, "DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_RXFCLK", "Parent input clock option to DEV_USB0_PIPE_RXFCLK"},
+ [1934] = {360, 3, "DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_RXFCLK", "Parent input clock option to DEV_USB0_PIPE_RXFCLK"},
+ [1935] = {360, 4, "DEV_USB0_USB2_APB_PCLK_CLK", "Input clock"},
+ [1936] = {360, 5, "DEV_USB0_PIPE_TXCLK", "Output clock"},
+ [1937] = {360, 7, "DEV_USB0_PIPE_TXFCLK", "Input muxed clock"},
+ [1938] = {360, 8, "DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_TXFCLK", "Parent input clock option to DEV_USB0_PIPE_TXFCLK"},
+ [1939] = {360, 9, "DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB0_PIPE_TXFCLK"},
+ [1940] = {360, 10, "DEV_USB0_PIPE_REFCLK", "Input muxed clock"},
+ [1941] = {360, 11, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"},
+ [1942] = {360, 12, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"},
+ [1943] = {360, 13, "DEV_USB0_PCLK_CLK", "Input clock"},
+ [1944] = {360, 15, "DEV_USB0_CLK_LPM_CLK", "Input clock"},
+ [1945] = {360, 16, "DEV_USB0_USB2_REFCLOCK_CLK", "Input muxed clock"},
+ [1946] = {360, 17, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"},
+ [1947] = {360, 18, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"},
+ [1948] = {360, 19, "DEV_USB0_PIPE_RXCLK", "Input muxed clock"},
+ [1949] = {360, 20, "DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_RXCLK", "Parent input clock option to DEV_USB0_PIPE_RXCLK"},
+ [1950] = {360, 21, "DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_RXCLK", "Parent input clock option to DEV_USB0_PIPE_RXCLK"},
+ [1951] = {360, 22, "DEV_USB0_ACLK_CLK", "Input clock"},
+ [1952] = {360, 23, "DEV_USB0_BUF_CLK", "Input clock"},
+ [1953] = {360, 25, "DEV_USB0_USB2_TAP_TCK", "Input clock"},
+ [1954] = {360, 26, "DEV_USB0_PIPE_TXMCLK", "Input muxed clock"},
+ [1955] = {360, 27, "DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_TXMCLK", "Parent input clock option to DEV_USB0_PIPE_TXMCLK"},
+ [1956] = {360, 28, "DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_TXMCLK", "Parent input clock option to DEV_USB0_PIPE_TXMCLK"},
+ [1957] = {361, 0, "DEV_VPAC0_LDC0_CLK_CLK", "Input clock"},
+ [1958] = {361, 1, "DEV_VPAC0_NF_CLK_CLK", "Input clock"},
+ [1959] = {361, 2, "DEV_VPAC0_MAIN_CLK", "Input muxed clock"},
+ [1960] = {361, 3, "DEV_VPAC0_MAIN_CLK_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT1_CLK", "Parent input clock option to DEV_VPAC0_MAIN_CLK"},
+ [1961] = {361, 4, "DEV_VPAC0_MAIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_VPAC0_MAIN_CLK"},
+ [1962] = {361, 5, "DEV_VPAC0_VISS0_CLK_CLK", "Input clock"},
+ [1963] = {361, 6, "DEV_VPAC0_PSIL_LEAF_CLK", "Input clock"},
+ [1964] = {361, 7, "DEV_VPAC0_MSC_CLK", "Input clock"},
+ [1965] = {362, 0, "DEV_VUSR_DUAL0_V0_RXFL_CLK", "Output clock"},
+ [1966] = {362, 1, "DEV_VUSR_DUAL0_VUSRX_LN0_TXFCLK", "Input clock"},
+ [1967] = {362, 2, "DEV_VUSR_DUAL0_V0_CLK", "Input clock"},
+ [1968] = {362, 3, "DEV_VUSR_DUAL0_V1_TXPM_CLK", "Output clock"},
+ [1969] = {362, 4, "DEV_VUSR_DUAL0_VUSRX_LN1_TXMCLK", "Input clock"},
+ [1970] = {362, 5, "DEV_VUSR_DUAL0_V1_TXFL_CLK", "Input clock"},
+ [1971] = {362, 6, "DEV_VUSR_DUAL0_VUSRX_LN0_RXCLK", "Input clock"},
+ [1972] = {362, 7, "DEV_VUSR_DUAL0_VUSRX_LN2_RXFCLK", "Input clock"},
+ [1973] = {362, 8, "DEV_VUSR_DUAL0_VUSRX_LN2_REFCLK", "Input clock"},
+ [1974] = {362, 9, "DEV_VUSR_DUAL0_VUSRX_LN3_RXCLK", "Input clock"},
+ [1975] = {362, 10, "DEV_VUSR_DUAL0_VUSRX_LN1_RXFCLK", "Input clock"},
+ [1976] = {362, 11, "DEV_VUSR_DUAL0_VUSRX_LN0_REFCLK", "Input clock"},
+ [1977] = {362, 12, "DEV_VUSR_DUAL0_VUSRX_LN1_TXCLK", "Output clock"},
+ [1978] = {362, 13, "DEV_VUSR_DUAL0_VUSRX_LN3_RXFCLK", "Input clock"},
+ [1979] = {362, 14, "DEV_VUSR_DUAL0_VUSRX_LN3_TXCLK", "Output clock"},
+ [1980] = {362, 15, "DEV_VUSR_DUAL0_VUSRX_LN3_TXMCLK", "Input clock"},
+ [1981] = {362, 16, "DEV_VUSR_DUAL0_VUSRX_LN3_TXFCLK", "Input clock"},
+ [1982] = {362, 17, "DEV_VUSR_DUAL0_VUSRX_LN0_TXCLK", "Output clock"},
+ [1983] = {362, 18, "DEV_VUSR_DUAL0_V1_CLK", "Input clock"},
+ [1984] = {362, 19, "DEV_VUSR_DUAL0_V0_TXFL_CLK", "Input clock"},
+ [1985] = {362, 20, "DEV_VUSR_DUAL0_VUSRX_LN0_RXFCLK", "Input clock"},
+ [1986] = {362, 21, "DEV_VUSR_DUAL0_VUSRX_LN2_RXCLK", "Input clock"},
+ [1987] = {362, 22, "DEV_VUSR_DUAL0_V0_TXPM_CLK", "Output clock"},
+ [1988] = {362, 23, "DEV_VUSR_DUAL0_V0_RXPM_CLK", "Input clock"},
+ [1989] = {362, 24, "DEV_VUSR_DUAL0_VUSRX_LN1_REFCLK", "Input clock"},
+ [1990] = {362, 25, "DEV_VUSR_DUAL0_V1_RXPM_CLK", "Input clock"},
+ [1991] = {362, 26, "DEV_VUSR_DUAL0_V1_RXFL_CLK", "Output clock"},
+ [1992] = {362, 27, "DEV_VUSR_DUAL0_VUSRX_LN2_TXCLK", "Output clock"},
+ [1993] = {362, 28, "DEV_VUSR_DUAL0_VUSRX_LN2_TXFCLK", "Input clock"},
+ [1994] = {362, 29, "DEV_VUSR_DUAL0_VUSRX_LN0_TXMCLK", "Input clock"},
+ [1995] = {362, 30, "DEV_VUSR_DUAL0_VUSRX_LN2_TXMCLK", "Input clock"},
+ [1996] = {362, 31, "DEV_VUSR_DUAL0_VUSRX_LN1_TXFCLK", "Input clock"},
+ [1997] = {362, 32, "DEV_VUSR_DUAL0_VUSRX_LN3_REFCLK", "Input clock"},
+ [1998] = {362, 33, "DEV_VUSR_DUAL0_VUSRX_LN1_RXCLK", "Input clock"},
+ [1999] = {151, 0, "DEV_WKUP_DDPA0_DDPA_CLK", "Input clock"},
+ [2000] = {104, 0, "DEV_WKUP_ESM0_CLK", "Input clock"},
+ [2001] = {115, 0, "DEV_WKUP_GPIO0_MMR_CLK", "Input clock"},
+ [2002] = {116, 0, "DEV_WKUP_GPIO1_MMR_CLK", "Input clock"},
+ [2003] = {125, 0, "DEV_WKUP_GPIOMUX_INTRTR0_INTR_CLK", "Input clock"},
+ [2004] = {223, 0, "DEV_WKUP_I2C0_PORSCL", "Output clock"},
+ [2005] = {223, 1, "DEV_WKUP_I2C0_PISYS_CLK", "Input muxed clock"},
+ [2006] = {223, 2, "DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK"},
+ [2007] = {223, 3, "DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK"},
+ [2008] = {223, 4, "DEV_WKUP_I2C0_CLK", "Input clock"},
+ [2009] = {223, 5, "DEV_WKUP_I2C0_PISCL", "Input clock"},
+ [2010] = {147, 0, "DEV_WKUP_J7AM_WAKEUP_16FF0_PLL_CTRL_WKUP_CLK24_CLK", "Input clock"},
+ [2011] = {147, 1, "DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_12P5M_CLK", "Output clock"},
+ [2012] = {147, 2, "DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_32K_CLK", "Output clock"},
+ [2013] = {123, 0, "DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK", "Input clock"},
+ [2014] = {126, 0, "DEV_WKUP_PSC0_SLOW_CLK", "Input clock"},
+ [2015] = {126, 1, "DEV_WKUP_PSC0_CLK", "Input clock"},
+ [2016] = {359, 2, "DEV_WKUP_UART0_VBUSP_CLK", "Input clock"},
+ [2017] = {359, 3, "DEV_WKUP_UART0_FCLK_CLK", "Input muxed clock"},
+ [2018] = {359, 4, "DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUP_USART_CLKSEL_OUT0", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"},
+ [2019] = {359, 5, "DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"},
+ [2020] = {180, 0, "DEV_WKUP_VTM0_FIX_REF_CLK", "Input clock"},
+ [2021] = {180, 1, "DEV_WKUP_VTM0_FIX_REF2_CLK", "Input clock"},
+ [2022] = {180, 2, "DEV_WKUP_VTM0_VBUSP_CLK", "Input clock"},
+};
diff --git a/soc/j721s2/j721s2_clocks_info.h b/soc/j721s2/j721s2_clocks_info.h
--- /dev/null
@@ -0,0 +1,42 @@
+/*
+ * J721S2 Clocks Info
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __J721S2_CLOCKS_INFO_H
+#define __J721S2_CLOCKS_INFO_H
+
+#define J721S2_MAX_CLOCKS 2023
+
+extern struct ti_sci_clocks_info j721s2_clocks_info[];
+
+#endif /* __J721S2_CLOCKS_INFO_H */