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| author | Lokesh Vutla <lokeshvutla@ti.com> | |
| Fri, 10 Jul 2020 04:53:33 +0000 (10:23 +0530) | ||
| committer | Lokesh Vutla <lokeshvutla@ti.com> | |
| Mon, 28 Sep 2020 09:46:13 +0000 (15:16 +0530) |
Add TISCI device information for J7200 devices.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| Makefile | patch | blob | history | |
| common/socinfo.c | patch | blob | history | |
| soc/j7200/j7200_devices_info.c | [new file with mode: 0644] | patch | blob |
| soc/j7200/j7200_devices_info.h | [new file with mode: 0644] | patch | blob |
diff --git a/Makefile b/Makefile
index 4df21f9d90606465ac374fae46b98fcb8a600552..b163b071cc2374d0a55f15753a399b4738df3c40 100644 (file)
--- a/Makefile
+++ b/Makefile
soc/j721e/j721e_clocks_info.c \
soc/j7200/j7200_host_info.c \
soc/j7200/j7200_sec_proxy_info.c \
- soc/j7200/j7200_processors_info.c
+ soc/j7200/j7200_processors_info.c \
+ soc/j7200/j7200_devices_info.c
COMMONOBJECTS= $(COMMONSOURCES:.c=.o)
diff --git a/common/socinfo.c b/common/socinfo.c
index a736ae6a52484c2ea43a14346f2be26695125395..4485c11068e3737a4fac3534414f12f11319e411 100644 (file)
--- a/common/socinfo.c
+++ b/common/socinfo.c
#include <soc/j7200/j7200_host_info.h>
#include <soc/j7200/j7200_sec_proxy_info.h>
#include <soc/j7200/j7200_processors_info.h>
+#include <soc/j7200/j7200_devices_info.h>
/* Assuming these addresses and definitions stay common across K3 devices */
#define CTRLMMR_WKUP_JTAG_DEVICE_ID 0x43000018
sci_info->num_sp_threads[MCU_SEC_PROXY] = J7200_MCU_SEC_PROXY_THREADS;
sci_info->processors_info = j7200_processors_info;
sci_info->num_processors = J7200_MAX_PROCESSORS_IDS;
+ sci_info->devices_info = j7200_devices_info;
+ sci_info->num_devices = J7200_MAX_DEVICES;
}
int soc_init(uint32_t host_id)
diff --git a/soc/j7200/j7200_devices_info.c b/soc/j7200/j7200_devices_info.c
--- /dev/null
@@ -0,0 +1,280 @@
+/*
+ * J7200 Devices Info
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <tisci.h>
+#include <socinfo.h>
+
+struct ti_sci_devices_info j7200_devices_info[] = {
+ [0] = {0, "J7200_DEV_MCU_ADC0"},
+ [1] = {1, "J7200_DEV_MCU_ADC1"},
+ [2] = {2, "J7200_DEV_ATL0"},
+ [3] = {3, "J7200_DEV_COMPUTE_CLUSTER0"},
+ [4] = {4, "J7200_DEV_A72SS0"},
+ [5] = {5, "J7200_DEV_COMPUTE_CLUSTER0_CFG_WRAP"},
+ [6] = {6, "J7200_DEV_COMPUTE_CLUSTER0_CLEC"},
+ [7] = {7, "J7200_DEV_COMPUTE_CLUSTER0_CORE_CORE"},
+ [8] = {8, "J7200_DEV_DDR0"},
+ [9] = {9, "J7200_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP"},
+ [10] = {10, "J7200_DEV_COMPUTE_CLUSTER0_DIVH2_DIVH0"},
+ [11] = {11, "J7200_DEV_COMPUTE_CLUSTER0_DIVP_TFT0"},
+ [12] = {12, "J7200_DEV_COMPUTE_CLUSTER0_DMSC_WRAP"},
+ [13] = {13, "J7200_DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN"},
+ [14] = {14, "J7200_DEV_COMPUTE_CLUSTER0_GIC500SS"},
+ [15] = {17, "J7200_DEV_COMPUTE_CLUSTER0_PBIST_WRAP"},
+ [16] = {18, "J7200_DEV_MCU_CPSW0"},
+ [17] = {19, "J7200_DEV_CPSW0"},
+ [18] = {20, "J7200_DEV_CPT2_AGGR0"},
+ [19] = {21, "J7200_DEV_CPT2_AGGR1"},
+ [20] = {22, "J7200_DEV_WKUP_DMSC0"},
+ [21] = {23, "J7200_DEV_CPT2_AGGR2"},
+ [22] = {24, "J7200_DEV_MCU_CPT2_AGGR0"},
+ [23] = {25, "J7200_DEV_CPT2_AGGR3"},
+ [24] = {26, "J7200_DEV_CPSW_TX_RGMII0"},
+ [25] = {29, "J7200_DEV_STM0"},
+ [26] = {30, "J7200_DEV_DCC0"},
+ [27] = {31, "J7200_DEV_DCC1"},
+ [28] = {32, "J7200_DEV_DCC2"},
+ [29] = {33, "J7200_DEV_DCC3"},
+ [30] = {34, "J7200_DEV_DCC4"},
+ [31] = {35, "J7200_DEV_MCU_TIMER0"},
+ [32] = {36, "J7200_DEV_DCC5"},
+ [33] = {37, "J7200_DEV_DCC6"},
+ [34] = {39, "J7200_DEV_MAIN0"},
+ [35] = {40, "J7200_DEV_WKUP_WAKEUP0"},
+ [36] = {44, "J7200_DEV_MCU_DCC0"},
+ [37] = {45, "J7200_DEV_MCU_DCC1"},
+ [38] = {46, "J7200_DEV_MCU_DCC2"},
+ [39] = {49, "J7200_DEV_TIMER0"},
+ [40] = {50, "J7200_DEV_TIMER1"},
+ [41] = {51, "J7200_DEV_TIMER2"},
+ [42] = {52, "J7200_DEV_TIMER3"},
+ [43] = {53, "J7200_DEV_TIMER4"},
+ [44] = {54, "J7200_DEV_TIMER5"},
+ [45] = {55, "J7200_DEV_TIMER6"},
+ [46] = {57, "J7200_DEV_TIMER7"},
+ [47] = {58, "J7200_DEV_TIMER8"},
+ [48] = {59, "J7200_DEV_TIMER9"},
+ [49] = {60, "J7200_DEV_TIMER10"},
+ [50] = {61, "J7200_DEV_GTC0"},
+ [51] = {62, "J7200_DEV_TIMER11"},
+ [52] = {63, "J7200_DEV_TIMER12"},
+ [53] = {64, "J7200_DEV_TIMER13"},
+ [54] = {65, "J7200_DEV_TIMER14"},
+ [55] = {66, "J7200_DEV_TIMER15"},
+ [56] = {67, "J7200_DEV_TIMER16"},
+ [57] = {68, "J7200_DEV_TIMER17"},
+ [58] = {69, "J7200_DEV_TIMER18"},
+ [59] = {70, "J7200_DEV_TIMER19"},
+ [60] = {71, "J7200_DEV_MCU_TIMER1"},
+ [61] = {72, "J7200_DEV_MCU_TIMER2"},
+ [62] = {73, "J7200_DEV_MCU_TIMER3"},
+ [63] = {74, "J7200_DEV_MCU_TIMER4"},
+ [64] = {75, "J7200_DEV_MCU_TIMER5"},
+ [65] = {76, "J7200_DEV_MCU_TIMER6"},
+ [66] = {77, "J7200_DEV_MCU_TIMER7"},
+ [67] = {78, "J7200_DEV_MCU_TIMER8"},
+ [68] = {79, "J7200_DEV_MCU_TIMER9"},
+ [69] = {80, "J7200_DEV_ECAP0"},
+ [70] = {81, "J7200_DEV_ECAP1"},
+ [71] = {82, "J7200_DEV_ECAP2"},
+ [72] = {83, "J7200_DEV_EHRPWM0"},
+ [73] = {84, "J7200_DEV_EHRPWM1"},
+ [74] = {85, "J7200_DEV_EHRPWM2"},
+ [75] = {86, "J7200_DEV_EHRPWM3"},
+ [76] = {87, "J7200_DEV_EHRPWM4"},
+ [77] = {88, "J7200_DEV_EHRPWM5"},
+ [78] = {89, "J7200_DEV_ELM0"},
+ [79] = {90, "J7200_DEV_EMIF_DATA_0_VD"},
+ [80] = {91, "J7200_DEV_MMCSD0"},
+ [81] = {92, "J7200_DEV_MMCSD1"},
+ [82] = {94, "J7200_DEV_EQEP0"},
+ [83] = {95, "J7200_DEV_EQEP1"},
+ [84] = {96, "J7200_DEV_EQEP2"},
+ [85] = {97, "J7200_DEV_ESM0"},
+ [86] = {98, "J7200_DEV_MCU_ESM0"},
+ [87] = {99, "J7200_DEV_WKUP_ESM0"},
+ [88] = {100, "J7200_DEV_MCU_FSS0"},
+ [89] = {101, "J7200_DEV_MCU_FSS0_FSAS_0"},
+ [90] = {102, "J7200_DEV_MCU_FSS0_HYPERBUS1P0_0"},
+ [91] = {103, "J7200_DEV_MCU_FSS0_OSPI_0"},
+ [92] = {104, "J7200_DEV_MCU_FSS0_OSPI_1"},
+ [93] = {105, "J7200_DEV_GPIO0"},
+ [94] = {107, "J7200_DEV_GPIO2"},
+ [95] = {109, "J7200_DEV_GPIO4"},
+ [96] = {111, "J7200_DEV_GPIO6"},
+ [97] = {113, "J7200_DEV_WKUP_GPIO0"},
+ [98] = {114, "J7200_DEV_WKUP_GPIO1"},
+ [99] = {115, "J7200_DEV_GPMC0"},
+ [100] = {116, "J7200_DEV_I3C0"},
+ [101] = {117, "J7200_DEV_MCU_I3C0"},
+ [102] = {118, "J7200_DEV_MCU_I3C1"},
+ [103] = {123, "J7200_DEV_CMPEVENT_INTRTR0"},
+ [104] = {127, "J7200_DEV_LED0"},
+ [105] = {128, "J7200_DEV_MAIN2MCU_LVL_INTRTR0"},
+ [106] = {130, "J7200_DEV_MAIN2MCU_PLS_INTRTR0"},
+ [107] = {131, "J7200_DEV_GPIOMUX_INTRTR0"},
+ [108] = {132, "J7200_DEV_WKUP_PORZ_SYNC0"},
+ [109] = {133, "J7200_DEV_PSC0"},
+ [110] = {136, "J7200_DEV_TIMESYNC_INTRTR0"},
+ [111] = {137, "J7200_DEV_WKUP_GPIOMUX_INTRTR0"},
+ [112] = {138, "J7200_DEV_WKUP_PSC0"},
+ [113] = {139, "J7200_DEV_PBIST0"},
+ [114] = {140, "J7200_DEV_PBIST1"},
+ [115] = {141, "J7200_DEV_PBIST2"},
+ [116] = {142, "J7200_DEV_MCU_PBIST0"},
+ [117] = {143, "J7200_DEV_MCU_PBIST1"},
+ [118] = {144, "J7200_DEV_MCU_PBIST2"},
+ [119] = {145, "J7200_DEV_WKUP_DDPA0"},
+ [120] = {146, "J7200_DEV_UART0"},
+ [121] = {149, "J7200_DEV_MCU_UART0"},
+ [122] = {150, "J7200_DEV_MCAN14"},
+ [123] = {151, "J7200_DEV_MCAN15"},
+ [124] = {152, "J7200_DEV_MCAN16"},
+ [125] = {153, "J7200_DEV_MCAN17"},
+ [126] = {154, "J7200_DEV_WKUP_VTM0"},
+ [127] = {155, "J7200_DEV_MAIN2WKUPMCU_VD"},
+ [128] = {156, "J7200_DEV_MCAN0"},
+ [129] = {157, "J7200_DEV_BOARD0"},
+ [130] = {158, "J7200_DEV_MCAN1"},
+ [131] = {160, "J7200_DEV_MCAN2"},
+ [132] = {161, "J7200_DEV_MCAN3"},
+ [133] = {162, "J7200_DEV_MCAN4"},
+ [134] = {163, "J7200_DEV_MCAN5"},
+ [135] = {164, "J7200_DEV_MCAN6"},
+ [136] = {165, "J7200_DEV_MCAN7"},
+ [137] = {166, "J7200_DEV_MCAN8"},
+ [138] = {167, "J7200_DEV_MCAN9"},
+ [139] = {168, "J7200_DEV_MCAN10"},
+ [140] = {169, "J7200_DEV_MCAN11"},
+ [141] = {170, "J7200_DEV_MCAN12"},
+ [142] = {171, "J7200_DEV_MCAN13"},
+ [143] = {172, "J7200_DEV_MCU_MCAN0"},
+ [144] = {173, "J7200_DEV_MCU_MCAN1"},
+ [145] = {174, "J7200_DEV_MCASP0"},
+ [146] = {175, "J7200_DEV_MCASP1"},
+ [147] = {176, "J7200_DEV_MCASP2"},
+ [148] = {187, "J7200_DEV_I2C0"},
+ [149] = {188, "J7200_DEV_I2C1"},
+ [150] = {189, "J7200_DEV_I2C2"},
+ [151] = {190, "J7200_DEV_I2C3"},
+ [152] = {191, "J7200_DEV_I2C4"},
+ [153] = {192, "J7200_DEV_I2C5"},
+ [154] = {193, "J7200_DEV_I2C6"},
+ [155] = {194, "J7200_DEV_MCU_I2C0"},
+ [156] = {195, "J7200_DEV_MCU_I2C1"},
+ [157] = {197, "J7200_DEV_WKUP_I2C0"},
+ [158] = {199, "J7200_DEV_NAVSS0"},
+ [159] = {201, "J7200_DEV_NAVSS0_CPTS_0"},
+ [160] = {202, "J7200_DEV_A72SS0_CORE0"},
+ [161] = {203, "J7200_DEV_A72SS0_CORE1"},
+ [162] = {206, "J7200_DEV_NAVSS0_DTI_0"},
+ [163] = {207, "J7200_DEV_NAVSS0_MODSS_INTA_0"},
+ [164] = {208, "J7200_DEV_NAVSS0_MODSS_INTA_1"},
+ [165] = {209, "J7200_DEV_NAVSS0_UDMASS_INTA_0"},
+ [166] = {210, "J7200_DEV_NAVSS0_PROXY_0"},
+ [167] = {211, "J7200_DEV_NAVSS0_RINGACC_0"},
+ [168] = {212, "J7200_DEV_NAVSS0_UDMAP_0"},
+ [169] = {213, "J7200_DEV_NAVSS0_INTR_ROUTER_0"},
+ [170] = {214, "J7200_DEV_NAVSS0_MAILBOX_0"},
+ [171] = {215, "J7200_DEV_NAVSS0_MAILBOX_1"},
+ [172] = {216, "J7200_DEV_NAVSS0_MAILBOX_2"},
+ [173] = {217, "J7200_DEV_NAVSS0_MAILBOX_3"},
+ [174] = {218, "J7200_DEV_NAVSS0_MAILBOX_4"},
+ [175] = {219, "J7200_DEV_NAVSS0_MAILBOX_5"},
+ [176] = {220, "J7200_DEV_NAVSS0_MAILBOX_6"},
+ [177] = {221, "J7200_DEV_NAVSS0_MAILBOX_7"},
+ [178] = {222, "J7200_DEV_NAVSS0_MAILBOX_8"},
+ [179] = {223, "J7200_DEV_NAVSS0_MAILBOX_9"},
+ [180] = {224, "J7200_DEV_NAVSS0_MAILBOX_10"},
+ [181] = {225, "J7200_DEV_NAVSS0_MAILBOX_11"},
+ [182] = {226, "J7200_DEV_NAVSS0_SPINLOCK_0"},
+ [183] = {227, "J7200_DEV_NAVSS0_MCRC_0"},
+ [184] = {228, "J7200_DEV_NAVSS0_TBU_0"},
+ [185] = {230, "J7200_DEV_NAVSS0_TIMERMGR_0"},
+ [186] = {231, "J7200_DEV_NAVSS0_TIMERMGR_1"},
+ [187] = {232, "J7200_DEV_MCU_NAVSS0"},
+ [188] = {233, "J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0"},
+ [189] = {234, "J7200_DEV_MCU_NAVSS0_PROXY0"},
+ [190] = {235, "J7200_DEV_MCU_NAVSS0_RINGACC0"},
+ [191] = {236, "J7200_DEV_MCU_NAVSS0_UDMAP_0"},
+ [192] = {237, "J7200_DEV_MCU_NAVSS0_INTR_0"},
+ [193] = {238, "J7200_DEV_MCU_NAVSS0_MCRC_0"},
+ [194] = {240, "J7200_DEV_PCIE1"},
+ [195] = {243, "J7200_DEV_R5FSS0"},
+ [196] = {245, "J7200_DEV_R5FSS0_CORE0"},
+ [197] = {246, "J7200_DEV_R5FSS0_CORE1"},
+ [198] = {249, "J7200_DEV_MCU_R5FSS0"},
+ [199] = {250, "J7200_DEV_MCU_R5FSS0_CORE0"},
+ [200] = {251, "J7200_DEV_MCU_R5FSS0_CORE1"},
+ [201] = {252, "J7200_DEV_RTI0"},
+ [202] = {253, "J7200_DEV_RTI1"},
+ [203] = {258, "J7200_DEV_RTI28"},
+ [204] = {259, "J7200_DEV_RTI29"},
+ [205] = {262, "J7200_DEV_MCU_RTI0"},
+ [206] = {263, "J7200_DEV_MCU_RTI1"},
+ [207] = {265, "J7200_DEV_MCU_SA2_UL0"},
+ [208] = {266, "J7200_DEV_MCSPI0"},
+ [209] = {267, "J7200_DEV_MCSPI1"},
+ [210] = {268, "J7200_DEV_MCSPI2"},
+ [211] = {269, "J7200_DEV_MCSPI3"},
+ [212] = {270, "J7200_DEV_MCSPI4"},
+ [213] = {271, "J7200_DEV_MCSPI5"},
+ [214] = {272, "J7200_DEV_MCSPI6"},
+ [215] = {273, "J7200_DEV_MCSPI7"},
+ [216] = {274, "J7200_DEV_MCU_MCSPI0"},
+ [217] = {275, "J7200_DEV_MCU_MCSPI1"},
+ [218] = {276, "J7200_DEV_MCU_MCSPI2"},
+ [219] = {278, "J7200_DEV_UART1"},
+ [220] = {279, "J7200_DEV_UART2"},
+ [221] = {280, "J7200_DEV_UART3"},
+ [222] = {281, "J7200_DEV_UART4"},
+ [223] = {282, "J7200_DEV_UART5"},
+ [224] = {283, "J7200_DEV_UART6"},
+ [225] = {284, "J7200_DEV_UART7"},
+ [226] = {285, "J7200_DEV_UART8"},
+ [227] = {286, "J7200_DEV_UART9"},
+ [228] = {287, "J7200_DEV_WKUP_UART0"},
+ [229] = {288, "J7200_DEV_USB0"},
+ [230] = {292, "J7200_DEV_SERDES_10G1"},
+ [231] = {298, "J7200_DEV_WKUPMCU2MAIN_VD"},
+ [232] = {299, "J7200_DEV_NAVSS0_MODSS"},
+ [233] = {300, "J7200_DEV_NAVSS0_UDMASS"},
+ [234] = {301, "J7200_DEV_NAVSS0_VIRTSS"},
+ [235] = {302, "J7200_DEV_MCU_NAVSS0_MODSS"},
+ [236] = {303, "J7200_DEV_MCU_NAVSS0_UDMASS"},
+ [237] = {304, "J7200_DEV_DEBUGSS_WRAP0"},
+ [238] = {305, "J7200_DEV_FFI_MAIN_INFRA_CBASS_VD"},
+ [239] = {306, "J7200_DEV_FFI_MAIN_IP_CBASS_VD"},
+ [240] = {307, "J7200_DEV_FFI_MAIN_RC_CBASS_VD"},
+};
diff --git a/soc/j7200/j7200_devices_info.h b/soc/j7200/j7200_devices_info.h
--- /dev/null
@@ -0,0 +1,42 @@
+/*
+ * J7200 Devices Info
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __J7200_DEVICES_INFO_H
+#define __J7200_DEVICES_INFO_H
+
+#define J7200_MAX_DEVICES 241
+
+extern struct ti_sci_devices_info j7200_devices_info[];
+
+#endif /* __J7200_DEVICES_INFO_H */
\ No newline at end of file