soc: j7200: Add clocks information
authorLokesh Vutla <lokeshvutla@ti.com>
Fri, 10 Jul 2020 04:56:08 +0000 (10:26 +0530)
committerLokesh Vutla <lokeshvutla@ti.com>
Mon, 28 Sep 2020 09:46:13 +0000 (15:16 +0530)
Add TISCI clock information for J7200 devices.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Makefile
common/socinfo.c
soc/j7200/j7200_clocks_info.c [new file with mode: 0644]
soc/j7200/j7200_clocks_info.h [new file with mode: 0644]

index b163b071cc2374d0a55f15753a399b4738df3c40..c5d0880e4be60405e5ba3a6a835ffe9d626cdf19 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -94,7 +94,8 @@ J721ESOURCES =\
              soc/j7200/j7200_host_info.c \
              soc/j7200/j7200_sec_proxy_info.c \
              soc/j7200/j7200_processors_info.c \
-             soc/j7200/j7200_devices_info.c
+             soc/j7200/j7200_devices_info.c \
+             soc/j7200/j7200_clocks_info.c
 
 
 COMMONOBJECTS= $(COMMONSOURCES:.c=.o)
index 4485c11068e3737a4fac3534414f12f11319e411..d7624f6be1831fd6639aad77587d12175a7c3d15 100644 (file)
@@ -56,6 +56,7 @@
 #include <soc/j7200/j7200_sec_proxy_info.h>
 #include <soc/j7200/j7200_processors_info.h>
 #include <soc/j7200/j7200_devices_info.h>
+#include <soc/j7200/j7200_clocks_info.h>
 
 /* Assuming these addresses and definitions stay common across K3 devices */
 #define CTRLMMR_WKUP_JTAG_DEVICE_ID    0x43000018
@@ -157,6 +158,8 @@ static void j7200_init(void)
        sci_info->num_processors = J7200_MAX_PROCESSORS_IDS;
        sci_info->devices_info = j7200_devices_info;
        sci_info->num_devices = J7200_MAX_DEVICES;
+       sci_info->clocks_info = j7200_clocks_info;
+       sci_info->num_clocks = J7200_MAX_CLOCKS;
 }
 
 int soc_init(uint32_t host_id)
diff --git a/soc/j7200/j7200_clocks_info.c b/soc/j7200/j7200_clocks_info.c
new file mode 100644 (file)
index 0000000..b58a667
--- /dev/null
@@ -0,0 +1,1465 @@
+/*
+ * J7200 Clocks Info
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <tisci.h>
+#include <socinfo.h>
+
+struct ti_sci_clocks_info j7200_clocks_info[] = {
+       [0] = {4, 0, "DEV_A72SS0_CORE0_ARM_CLK_CLK", "Input clock"},
+       [1] = {4, 1, "DEV_A72SS0_CORE0_MSMC_CLK", "Input clock"},
+       [2] = {4, 2, "DEV_A72SS0_CORE0_PLL_CTRL_CLK", "Input clock"},
+       [3] = {202, 2, "DEV_A72SS0_CORE0_0_ARM_CLK_CLK", "Input clock"},
+       [4] = {203, 0, "DEV_A72SS0_CORE0_1_ARM_CLK_CLK", "Input clock"},
+       [5] = {2, 0, "DEV_ATL0_VBUS_CLK", "Input clock"},
+       [6] = {2, 1, "DEV_ATL0_ATL_CLK", "Input muxed clock"},
+       [7] = {2, 2, "DEV_ATL0_ATL_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT1_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+       [8] = {2, 3, "DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+       [9] = {2, 6, "DEV_ATL0_ATL_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+       [10] = {2, 7, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+       [11] = {2, 8, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+       [12] = {2, 10, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1", "Output clock"},
+       [13] = {2, 11, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3", "Output clock"},
+       [14] = {2, 12, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2", "Output clock"},
+       [15] = {2, 13, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT", "Output clock"},
+       [16] = {157, 1, "DEV_BOARD0_I2C1_SCL_OUT", "Output clock"},
+       [17] = {157, 2, "DEV_BOARD0_MCASP0_ACLKR_OUT", "Output clock"},
+       [18] = {157, 3, "DEV_BOARD0_SPI2_CLK_IN", "Input clock"},
+       [19] = {157, 4, "DEV_BOARD0_I2C3_SCL_OUT", "Output clock"},
+       [20] = {157, 5, "DEV_BOARD0_OBSCLK2_IN", "Input clock"},
+       [21] = {157, 6, "DEV_BOARD0_MCU_I3C0_SCL_IN", "Input clock"},
+       [22] = {157, 7, "DEV_BOARD0_MCU_HYPERBUS0_CKN_IN", "Input clock"},
+       [23] = {157, 8, "DEV_BOARD0_I2C4_SCL_OUT", "Output clock"},
+       [24] = {157, 9, "DEV_BOARD0_RGMII3_TXC_IN", "Input clock"},
+       [25] = {157, 11, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"},
+       [26] = {157, 12, "DEV_BOARD0_SPI1_CLK_IN", "Input clock"},
+       [27] = {157, 13, "DEV_BOARD0_GPMC0_CLKOUT_IN", "Input clock"},
+       [28] = {157, 14, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"},
+       [29] = {157, 15, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
+       [30] = {157, 16, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
+       [31] = {157, 31, "DEV_BOARD0_MCU_I3C0_SCL_OUT", "Output clock"},
+       [32] = {157, 32, "DEV_BOARD0_SPI3_CLK_IN", "Input clock"},
+       [33] = {157, 33, "DEV_BOARD0_MCASP0_ACLKX_OUT", "Output clock"},
+       [34] = {157, 34, "DEV_BOARD0_MCASP1_ACLKR_IN", "Input clock"},
+       [35] = {157, 35, "DEV_BOARD0_CLKOUT_IN", "Input muxed clock"},
+       [36] = {157, 36, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"},
+       [37] = {157, 37, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"},
+       [38] = {157, 38, "DEV_BOARD0_OBSCLK1_IN", "Input clock"},
+       [39] = {157, 39, "DEV_BOARD0_MCU_RMII1_REF_CLK_OUT", "Output clock"},
+       [40] = {157, 40, "DEV_BOARD0_GPMC0_CLK_OUT", "Output clock"},
+       [41] = {157, 41, "DEV_BOARD0_I3C0_SCL_OUT", "Output clock"},
+       [42] = {157, 43, "DEV_BOARD0_TCK_OUT", "Output clock"},
+       [43] = {157, 44, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"},
+       [44] = {157, 45, "DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT", "Output clock"},
+       [45] = {157, 46, "DEV_BOARD0_I2C6_SCL_OUT", "Output clock"},
+       [46] = {157, 48, "DEV_BOARD0_I2C5_SCL_OUT", "Output clock"},
+       [47] = {157, 49, "DEV_BOARD0_MCU_OSPI0_DQS_OUT", "Output clock"},
+       [48] = {157, 52, "DEV_BOARD0_RGMII2_RXC_OUT", "Output clock"},
+       [49] = {157, 53, "DEV_BOARD0_MCASP2_ACLKX_IN", "Input clock"},
+       [50] = {157, 54, "DEV_BOARD0_I2C0_SCL_OUT", "Output clock"},
+       [51] = {157, 57, "DEV_BOARD0_MCU_HYPERBUS0_CK_IN", "Input clock"},
+       [52] = {157, 59, "DEV_BOARD0_MCASP1_ACLKX_OUT", "Output clock"},
+       [53] = {157, 61, "DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT", "Output clock"},
+       [54] = {157, 62, "DEV_BOARD0_MDIO0_MDC_IN", "Input clock"},
+       [55] = {157, 63, "DEV_BOARD0_RGMII1_TXC_IN", "Input clock"},
+       [56] = {157, 65, "DEV_BOARD0_MMC1_CLK_IN", "Input clock"},
+       [57] = {157, 66, "DEV_BOARD0_MCASP2_ACLKR_IN", "Input clock"},
+       [58] = {157, 68, "DEV_BOARD0_WKUP_I2C0_SCL_OUT", "Output clock"},
+       [59] = {157, 69, "DEV_BOARD0_MCU_CLKOUT0_IN", "Input muxed clock"},
+       [60] = {157, 70, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"},
+       [61] = {157, 71, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"},
+       [62] = {157, 73, "DEV_BOARD0_MCASP0_ACLKR_IN", "Input clock"},
+       [63] = {157, 74, "DEV_BOARD0_MCU_MDIO0_MDC_IN", "Input clock"},
+       [64] = {157, 77, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN", "Input muxed clock"},
+       [65] = {157, 78, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [66] = {157, 79, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [67] = {157, 80, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [68] = {157, 90, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [69] = {157, 91, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [70] = {157, 92, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [71] = {157, 102, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [72] = {157, 103, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [73] = {157, 104, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [74] = {157, 105, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [75] = {157, 106, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+       [76] = {157, 110, "DEV_BOARD0_MCU_OSPI0_CLK_IN", "Input clock"},
+       [77] = {157, 114, "DEV_BOARD0_MCU_SYSCLKOUT0_IN", "Input clock"},
+       [78] = {157, 115, "DEV_BOARD0_RGMII1_RXC_OUT", "Output clock"},
+       [79] = {157, 116, "DEV_BOARD0_LED_CLK_OUT", "Output clock"},
+       [80] = {157, 118, "DEV_BOARD0_RGMII2_TXC_IN", "Input clock"},
+       [81] = {157, 119, "DEV_BOARD0_I3C0_SCL_IN", "Input clock"},
+       [82] = {157, 120, "DEV_BOARD0_MCU_I2C0_SCL_OUT", "Output clock"},
+       [83] = {157, 122, "DEV_BOARD0_SPI6_CLK_IN", "Input clock"},
+       [84] = {157, 123, "DEV_BOARD0_WKUP_I2C0_SCL_IN", "Input clock"},
+       [85] = {157, 124, "DEV_BOARD0_WKUP_LF_CLKIN_OUT", "Output clock"},
+       [86] = {157, 126, "DEV_BOARD0_MCU_SPI1_CLK_IN", "Input clock"},
+       [87] = {157, 127, "DEV_BOARD0_MCASP0_ACLKX_IN", "Input clock"},
+       [88] = {157, 128, "DEV_BOARD0_MCASP1_ACLKX_IN", "Input clock"},
+       [89] = {157, 130, "DEV_BOARD0_MCU_SPI0_CLK_IN", "Input clock"},
+       [90] = {157, 131, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN", "Input muxed clock"},
+       [91] = {157, 132, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [92] = {157, 133, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [93] = {157, 134, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [94] = {157, 144, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [95] = {157, 145, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [96] = {157, 146, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [97] = {157, 156, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [98] = {157, 157, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [99] = {157, 158, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [100] = {157, 159, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [101] = {157, 160, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+       [102] = {157, 164, "DEV_BOARD0_MCU_RGMII1_TXC_IN", "Input clock"},
+       [103] = {157, 165, "DEV_BOARD0_CPTS0_RFT_CLK_OUT", "Output clock"},
+       [104] = {157, 166, "DEV_BOARD0_MCU_I2C1_SCL_OUT", "Output clock"},
+       [105] = {157, 168, "DEV_BOARD0_MCASP2_ACLKR_OUT", "Output clock"},
+       [106] = {157, 169, "DEV_BOARD0_MCU_I2C0_SCL_IN", "Input clock"},
+       [107] = {157, 170, "DEV_BOARD0_RMII_REF_CLK_OUT", "Output clock"},
+       [108] = {157, 171, "DEV_BOARD0_GPMC0_CLK_IN", "Input clock"},
+       [109] = {157, 172, "DEV_BOARD0_TRC_CLK_IN", "Input clock"},
+       [110] = {157, 174, "DEV_BOARD0_MCASP2_ACLKX_OUT", "Output clock"},
+       [111] = {157, 176, "DEV_BOARD0_RGMII4_RXC_OUT", "Output clock"},
+       [112] = {157, 177, "DEV_BOARD0_SYSCLKOUT0_IN", "Input clock"},
+       [113] = {157, 178, "DEV_BOARD0_MCASP1_ACLKR_OUT", "Output clock"},
+       [114] = {157, 179, "DEV_BOARD0_SPI5_CLK_IN", "Input clock"},
+       [115] = {157, 180, "DEV_BOARD0_MCU_RGMII1_RXC_OUT", "Output clock"},
+       [116] = {157, 181, "DEV_BOARD0_RGMII3_RXC_OUT", "Output clock"},
+       [117] = {157, 183, "DEV_BOARD0_SPI0_CLK_IN", "Input clock"},
+       [118] = {157, 184, "DEV_BOARD0_GPMC0_FCLK_MUX_IN", "Input clock"},
+       [119] = {157, 185, "DEV_BOARD0_I2C2_SCL_OUT", "Output clock"},
+       [120] = {157, 186, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"},
+       [121] = {157, 187, "DEV_BOARD0_MCU_OSPI0_LBCLKO_IN", "Input clock"},
+       [122] = {157, 189, "DEV_BOARD0_SPI7_CLK_IN", "Input clock"},
+       [123] = {157, 190, "DEV_BOARD0_RGMII4_TXC_IN", "Input clock"},
+       [124] = {157, 191, "DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT", "Output clock"},
+       [125] = {157, 192, "DEV_BOARD0_OBSCLK0_IN", "Input clock"},
+       [126] = {157, 193, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [127] = {157, 194, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [128] = {157, 195, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [129] = {157, 196, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [130] = {157, 197, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [131] = {157, 205, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [132] = {157, 206, "DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [133] = {157, 207, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [134] = {157, 219, "DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [135] = {157, 220, "DEV_BOARD0_OBSCLK0_IN_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [136] = {157, 221, "DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [137] = {157, 222, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [138] = {157, 223, "DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [139] = {157, 224, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+       [140] = {123, 0, "DEV_CMPEVENT_INTRTR0_INTR_CLK", "Input clock"},
+       [141] = {3, 0, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_PLL_CTRL_CLK", "Input clock"},
+       [142] = {3, 2, "DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_DBG_CLK", "Input clock"},
+       [143] = {3, 3, "DEV_COMPUTE_CLUSTER0_TB_SOC_GIC_CLK", "Input clock"},
+       [144] = {3, 4, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_DDR_PLL_CLK", "Input clock"},
+       [145] = {3, 5, "DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_CFG_CLK", "Input clock"},
+       [146] = {3, 6, "DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_DMSC_CLK", "Input clock"},
+       [147] = {17, 4, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK4_CLK_CLK", "Input clock"},
+       [148] = {19, 0, "DEV_CPSW0_MDIO_MDCLK_O", "Output clock"},
+       [149] = {19, 1, "DEV_CPSW0_GMII3_MT_CLK", "Input clock"},
+       [150] = {19, 2, "DEV_CPSW0_GMII2_MR_CLK", "Input clock"},
+       [151] = {19, 3, "DEV_CPSW0_SERDES4_RXCLK", "Input clock"},
+       [152] = {19, 4, "DEV_CPSW0_CPTS_GENF0", "Output clock"},
+       [153] = {19, 5, "DEV_CPSW0_PRE_RGMII4_TCLK", "Output clock"},
+       [154] = {19, 6, "DEV_CPSW0_RGMII3_RXC_I", "Input clock"},
+       [155] = {19, 7, "DEV_CPSW0_RGMII4_RXC_I", "Input clock"},
+       [156] = {19, 8, "DEV_CPSW0_PRE_RGMII3_TCLK", "Output clock"},
+       [157] = {19, 9, "DEV_CPSW0_RGMII1_RXC_I", "Input clock"},
+       [158] = {19, 10, "DEV_CPSW0_RGMII_MHZ_250_CLK", "Input clock"},
+       [159] = {19, 11, "DEV_CPSW0_GMII4_MT_CLK", "Input clock"},
+       [160] = {19, 13, "DEV_CPSW0_GMII3_MR_CLK", "Input clock"},
+       [161] = {19, 14, "DEV_CPSW0_SERDES4_RXFCLK", "Input clock"},
+       [162] = {19, 15, "DEV_CPSW0_CPTS_RFT_CLK", "Input muxed clock"},
+       [163] = {19, 16, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [164] = {19, 17, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [165] = {19, 18, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [166] = {19, 19, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [167] = {19, 20, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [168] = {19, 21, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [169] = {19, 22, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [170] = {19, 23, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [171] = {19, 24, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [172] = {19, 25, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [173] = {19, 30, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [174] = {19, 31, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+       [175] = {19, 32, "DEV_CPSW0_SERDES1_TXCLK", "Output clock"},
+       [176] = {19, 33, "DEV_CPSW0_CPPI_CLK_CLK", "Input clock"},
+       [177] = {19, 34, "DEV_CPSW0_SERDES2_RXCLK", "Input clock"},
+       [178] = {19, 35, "DEV_CPSW0_SERDES1_RXFCLK", "Input clock"},
+       [179] = {19, 36, "DEV_CPSW0_GMII_RFT_CLK", "Input clock"},
+       [180] = {19, 37, "DEV_CPSW0_SERDES1_TXMCLK", "Input clock"},
+       [181] = {19, 38, "DEV_CPSW0_SERDES1_REFCLK", "Input clock"},
+       [182] = {19, 39, "DEV_CPSW0_RMII_MHZ_50_CLK", "Input clock"},
+       [183] = {19, 40, "DEV_CPSW0_GMII4_MR_CLK", "Input clock"},
+       [184] = {19, 41, "DEV_CPSW0_RGMII_MHZ_50_CLK", "Input clock"},
+       [185] = {19, 42, "DEV_CPSW0_SERDES3_TXFCLK", "Input clock"},
+       [186] = {19, 43, "DEV_CPSW0_SERDES3_RXFCLK", "Input clock"},
+       [187] = {19, 45, "DEV_CPSW0_PRE_RGMII2_TCLK", "Output clock"},
+       [188] = {19, 46, "DEV_CPSW0_SERDES2_TXCLK", "Output clock"},
+       [189] = {19, 47, "DEV_CPSW0_SERDES1_RXCLK", "Input clock"},
+       [190] = {19, 48, "DEV_CPSW0_SERDES1_TXFCLK", "Input clock"},
+       [191] = {19, 49, "DEV_CPSW0_RGMII2_RXC_I", "Input clock"},
+       [192] = {19, 50, "DEV_CPSW0_SERDES2_TXFCLK", "Input clock"},
+       [193] = {19, 51, "DEV_CPSW0_PRE_RGMII1_TCLK", "Output clock"},
+       [194] = {19, 52, "DEV_CPSW0_RGMII_MHZ_5_CLK", "Input clock"},
+       [195] = {19, 53, "DEV_CPSW0_GMII2_MT_CLK", "Input clock"},
+       [196] = {19, 54, "DEV_CPSW0_SERDES4_TXMCLK", "Input clock"},
+       [197] = {19, 55, "DEV_CPSW0_SERDES3_TXCLK", "Output clock"},
+       [198] = {19, 56, "DEV_CPSW0_SERDES2_TXMCLK", "Input clock"},
+       [199] = {19, 57, "DEV_CPSW0_GMII1_MR_CLK", "Input clock"},
+       [200] = {19, 58, "DEV_CPSW0_SERDES4_REFCLK", "Input clock"},
+       [201] = {19, 59, "DEV_CPSW0_SERDES3_TXMCLK", "Input clock"},
+       [202] = {19, 60, "DEV_CPSW0_SERDES2_REFCLK", "Input clock"},
+       [203] = {19, 61, "DEV_CPSW0_SERDES3_REFCLK", "Input clock"},
+       [204] = {19, 62, "DEV_CPSW0_SERDES3_RXCLK", "Input clock"},
+       [205] = {19, 63, "DEV_CPSW0_GMII1_MT_CLK", "Input clock"},
+       [206] = {19, 64, "DEV_CPSW0_SERDES2_RXFCLK", "Input clock"},
+       [207] = {19, 66, "DEV_CPSW0_SERDES4_TXCLK", "Output clock"},
+       [208] = {19, 67, "DEV_CPSW0_SERDES4_TXFCLK", "Input clock"},
+       [209] = {26, 0, "DEV_CPSW_TX_RGMII0_IO__RGMII4_TXC__A", "Output clock"},
+       [210] = {26, 1, "DEV_CPSW_TX_RGMII0_IO__RGMII3_TXC__A", "Output clock"},
+       [211] = {26, 2, "DEV_CPSW_TX_RGMII0_IO__RGMII2_TXC__A", "Output clock"},
+       [212] = {26, 3, "DEV_CPSW_TX_RGMII0_IO__RGMII1_TXC__A", "Output clock"},
+       [213] = {26, 4, "DEV_CPSW_TX_RGMII0_PRE_RGMII2_TCLK", "Input clock"},
+       [214] = {26, 5, "DEV_CPSW_TX_RGMII0_PRE_RGMII4_TCLK", "Input clock"},
+       [215] = {26, 6, "DEV_CPSW_TX_RGMII0_PRE_RGMII3_TCLK", "Input clock"},
+       [216] = {26, 7, "DEV_CPSW_TX_RGMII0_PRE_RGMII1_TCLK", "Input clock"},
+       [217] = {20, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"},
+       [218] = {21, 0, "DEV_CPT2_AGGR1_VCLK_CLK", "Input clock"},
+       [219] = {23, 0, "DEV_CPT2_AGGR2_VCLK_CLK", "Input clock"},
+       [220] = {25, 0, "DEV_CPT2_AGGR3_VCLK_CLK", "Input clock"},
+       [221] = {30, 0, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"},
+       [222] = {30, 1, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"},
+       [223] = {30, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"},
+       [224] = {30, 4, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"},
+       [225] = {30, 5, "DEV_DCC0_VBUS_CLK", "Input clock"},
+       [226] = {30, 6, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"},
+       [227] = {30, 7, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"},
+       [228] = {30, 8, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"},
+       [229] = {30, 9, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"},
+       [230] = {30, 10, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"},
+       [231] = {30, 11, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"},
+       [232] = {30, 12, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"},
+       [233] = {31, 0, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"},
+       [234] = {31, 1, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"},
+       [235] = {31, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"},
+       [236] = {31, 4, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"},
+       [237] = {31, 5, "DEV_DCC1_VBUS_CLK", "Input clock"},
+       [238] = {31, 6, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"},
+       [239] = {31, 7, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"},
+       [240] = {31, 8, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"},
+       [241] = {31, 9, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"},
+       [242] = {31, 10, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"},
+       [243] = {31, 11, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"},
+       [244] = {31, 12, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"},
+       [245] = {32, 0, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"},
+       [246] = {32, 1, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"},
+       [247] = {32, 2, "DEV_DCC2_DCC_CLKSRC2_CLK", "Input clock"},
+       [248] = {32, 3, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"},
+       [249] = {32, 4, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"},
+       [250] = {32, 5, "DEV_DCC2_VBUS_CLK", "Input clock"},
+       [251] = {32, 6, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"},
+       [252] = {32, 8, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"},
+       [253] = {32, 9, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"},
+       [254] = {32, 10, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"},
+       [255] = {32, 11, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"},
+       [256] = {32, 12, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"},
+       [257] = {33, 0, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"},
+       [258] = {33, 1, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"},
+       [259] = {33, 2, "DEV_DCC3_DCC_CLKSRC2_CLK", "Input clock"},
+       [260] = {33, 3, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"},
+       [261] = {33, 4, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"},
+       [262] = {33, 5, "DEV_DCC3_VBUS_CLK", "Input clock"},
+       [263] = {33, 6, "DEV_DCC3_DCC_CLKSRC4_CLK", "Input clock"},
+       [264] = {33, 8, "DEV_DCC3_DCC_CLKSRC3_CLK", "Input clock"},
+       [265] = {33, 9, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"},
+       [266] = {33, 10, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"},
+       [267] = {33, 11, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"},
+       [268] = {33, 12, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"},
+       [269] = {34, 0, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"},
+       [270] = {34, 1, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"},
+       [271] = {34, 2, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"},
+       [272] = {34, 3, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"},
+       [273] = {34, 4, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input clock"},
+       [274] = {34, 5, "DEV_DCC4_VBUS_CLK", "Input clock"},
+       [275] = {34, 6, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"},
+       [276] = {34, 7, "DEV_DCC4_DCC_CLKSRC1_CLK", "Input clock"},
+       [277] = {34, 8, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"},
+       [278] = {34, 9, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"},
+       [279] = {34, 10, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"},
+       [280] = {34, 11, "DEV_DCC4_DCC_CLKSRC6_CLK", "Input clock"},
+       [281] = {34, 12, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"},
+       [282] = {36, 0, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"},
+       [283] = {36, 1, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"},
+       [284] = {36, 4, "DEV_DCC5_DCC_CLKSRC0_CLK", "Input clock"},
+       [285] = {36, 5, "DEV_DCC5_VBUS_CLK", "Input clock"},
+       [286] = {36, 6, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"},
+       [287] = {36, 7, "DEV_DCC5_DCC_CLKSRC1_CLK", "Input clock"},
+       [288] = {36, 9, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"},
+       [289] = {36, 11, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"},
+       [290] = {36, 12, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"},
+       [291] = {37, 0, "DEV_DCC6_DCC_INPUT10_CLK", "Input clock"},
+       [292] = {37, 1, "DEV_DCC6_DCC_INPUT01_CLK", "Input clock"},
+       [293] = {37, 2, "DEV_DCC6_DCC_CLKSRC2_CLK", "Input clock"},
+       [294] = {37, 3, "DEV_DCC6_DCC_CLKSRC7_CLK", "Input clock"},
+       [295] = {37, 4, "DEV_DCC6_DCC_CLKSRC0_CLK", "Input clock"},
+       [296] = {37, 5, "DEV_DCC6_VBUS_CLK", "Input clock"},
+       [297] = {37, 6, "DEV_DCC6_DCC_CLKSRC4_CLK", "Input clock"},
+       [298] = {37, 7, "DEV_DCC6_DCC_CLKSRC1_CLK", "Input clock"},
+       [299] = {37, 8, "DEV_DCC6_DCC_CLKSRC3_CLK", "Input clock"},
+       [300] = {37, 9, "DEV_DCC6_DCC_INPUT00_CLK", "Input clock"},
+       [301] = {37, 10, "DEV_DCC6_DCC_CLKSRC5_CLK", "Input clock"},
+       [302] = {37, 11, "DEV_DCC6_DCC_CLKSRC6_CLK", "Input clock"},
+       [303] = {37, 12, "DEV_DCC6_DCC_INPUT02_CLK", "Input clock"},
+       [304] = {8, 0, "DEV_DDR0_PLL_CTRL_CLK", "Input clock"},
+       [305] = {8, 5, "DEV_DDR0_DDRSS_DDR_PLL_CLK", "Input clock"},
+       [306] = {304, 5, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"},
+       [307] = {304, 9, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"},
+       [308] = {304, 25, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"},
+       [309] = {304, 34, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"},
+       [310] = {304, 49, "DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK", "Output clock"},
+       [311] = {80, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"},
+       [312] = {81, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"},
+       [313] = {82, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"},
+       [314] = {83, 0, "DEV_EHRPWM0_VBUSP_CLK", "Input clock"},
+       [315] = {84, 0, "DEV_EHRPWM1_VBUSP_CLK", "Input clock"},
+       [316] = {85, 0, "DEV_EHRPWM2_VBUSP_CLK", "Input clock"},
+       [317] = {86, 0, "DEV_EHRPWM3_VBUSP_CLK", "Input clock"},
+       [318] = {87, 0, "DEV_EHRPWM4_VBUSP_CLK", "Input clock"},
+       [319] = {88, 0, "DEV_EHRPWM5_VBUSP_CLK", "Input clock"},
+       [320] = {89, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"},
+       [321] = {94, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"},
+       [322] = {95, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"},
+       [323] = {96, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"},
+       [324] = {97, 0, "DEV_ESM0_CLK", "Input clock"},
+       [325] = {105, 0, "DEV_GPIO0_MMR_CLK", "Input clock"},
+       [326] = {107, 0, "DEV_GPIO2_MMR_CLK", "Input clock"},
+       [327] = {109, 0, "DEV_GPIO4_MMR_CLK", "Input clock"},
+       [328] = {111, 0, "DEV_GPIO6_MMR_CLK", "Input clock"},
+       [329] = {131, 0, "DEV_GPIOMUX_INTRTR0_INTR_CLK", "Input clock"},
+       [330] = {115, 0, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"},
+       [331] = {115, 1, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
+       [332] = {115, 2, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
+       [333] = {115, 3, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
+       [334] = {115, 4, "DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
+       [335] = {115, 5, "DEV_GPMC0_VBUSP_CLK", "Input clock"},
+       [336] = {115, 6, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"},
+       [337] = {115, 7, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"},
+       [338] = {61, 0, "DEV_GTC0_VBUSP_CLK", "Input clock"},
+       [339] = {61, 1, "DEV_GTC0_GTC_CLK", "Input muxed clock"},
+       [340] = {61, 2, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [341] = {61, 3, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [342] = {61, 4, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [343] = {61, 5, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [344] = {61, 6, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [345] = {61, 7, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [346] = {61, 8, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [347] = {61, 9, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [348] = {61, 10, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [349] = {61, 11, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [350] = {61, 16, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [351] = {61, 17, "DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+       [352] = {187, 0, "DEV_I2C0_PISCL", "Input clock"},
+       [353] = {187, 1, "DEV_I2C0_PISYS_CLK", "Input clock"},
+       [354] = {187, 2, "DEV_I2C0_CLK", "Input clock"},
+       [355] = {187, 3, "DEV_I2C0_PORSCL", "Output clock"},
+       [356] = {188, 0, "DEV_I2C1_PISCL", "Input clock"},
+       [357] = {188, 1, "DEV_I2C1_PISYS_CLK", "Input clock"},
+       [358] = {188, 2, "DEV_I2C1_CLK", "Input clock"},
+       [359] = {188, 3, "DEV_I2C1_PORSCL", "Output clock"},
+       [360] = {189, 0, "DEV_I2C2_PISCL", "Input clock"},
+       [361] = {189, 1, "DEV_I2C2_PISYS_CLK", "Input clock"},
+       [362] = {189, 2, "DEV_I2C2_CLK", "Input clock"},
+       [363] = {189, 3, "DEV_I2C2_PORSCL", "Output clock"},
+       [364] = {190, 0, "DEV_I2C3_PISCL", "Input clock"},
+       [365] = {190, 1, "DEV_I2C3_PISYS_CLK", "Input clock"},
+       [366] = {190, 2, "DEV_I2C3_CLK", "Input clock"},
+       [367] = {190, 3, "DEV_I2C3_PORSCL", "Output clock"},
+       [368] = {191, 0, "DEV_I2C4_PISCL", "Input clock"},
+       [369] = {191, 1, "DEV_I2C4_PISYS_CLK", "Input clock"},
+       [370] = {191, 2, "DEV_I2C4_CLK", "Input clock"},
+       [371] = {191, 3, "DEV_I2C4_PORSCL", "Output clock"},
+       [372] = {192, 0, "DEV_I2C5_PISCL", "Input clock"},
+       [373] = {192, 1, "DEV_I2C5_PISYS_CLK", "Input clock"},
+       [374] = {192, 2, "DEV_I2C5_CLK", "Input clock"},
+       [375] = {192, 3, "DEV_I2C5_PORSCL", "Output clock"},
+       [376] = {193, 0, "DEV_I2C6_PISCL", "Input clock"},
+       [377] = {193, 1, "DEV_I2C6_PISYS_CLK", "Input clock"},
+       [378] = {193, 2, "DEV_I2C6_CLK", "Input clock"},
+       [379] = {193, 3, "DEV_I2C6_PORSCL", "Output clock"},
+       [380] = {116, 0, "DEV_I3C0_I3C_SCL_DI", "Input clock"},
+       [381] = {116, 1, "DEV_I3C0_I3C_SCL_DO", "Output clock"},
+       [382] = {116, 2, "DEV_I3C0_I3C_PCLK_CLK", "Input clock"},
+       [383] = {116, 4, "DEV_I3C0_I3C_SCLK_CLK", "Input clock"},
+       [384] = {127, 0, "DEV_LED0_LED_CLK", "Input clock"},
+       [385] = {127, 1, "DEV_LED0_VBUS_CLK", "Input clock"},
+       [386] = {156, 0, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"},
+       [387] = {156, 2, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [388] = {156, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+       [389] = {156, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+       [390] = {156, 5, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+       [391] = {156, 6, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+       [392] = {158, 0, "DEV_MCAN1_MCANSS_HCLK_CLK", "Input clock"},
+       [393] = {158, 2, "DEV_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [394] = {158, 3, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
+       [395] = {158, 4, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
+       [396] = {158, 5, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
+       [397] = {158, 6, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
+       [398] = {168, 0, "DEV_MCAN10_MCANSS_HCLK_CLK", "Input clock"},
+       [399] = {168, 2, "DEV_MCAN10_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [400] = {168, 3, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
+       [401] = {168, 4, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
+       [402] = {168, 5, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
+       [403] = {168, 6, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
+       [404] = {169, 0, "DEV_MCAN11_MCANSS_HCLK_CLK", "Input clock"},
+       [405] = {169, 2, "DEV_MCAN11_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [406] = {169, 3, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
+       [407] = {169, 4, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
+       [408] = {169, 5, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
+       [409] = {169, 6, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
+       [410] = {170, 0, "DEV_MCAN12_MCANSS_HCLK_CLK", "Input clock"},
+       [411] = {170, 2, "DEV_MCAN12_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [412] = {170, 3, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
+       [413] = {170, 4, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
+       [414] = {170, 5, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
+       [415] = {170, 6, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
+       [416] = {171, 0, "DEV_MCAN13_MCANSS_HCLK_CLK", "Input clock"},
+       [417] = {171, 2, "DEV_MCAN13_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [418] = {171, 3, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
+       [419] = {171, 4, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
+       [420] = {171, 5, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
+       [421] = {171, 6, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
+       [422] = {150, 0, "DEV_MCAN14_MCANSS_HCLK_CLK", "Input clock"},
+       [423] = {150, 2, "DEV_MCAN14_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [424] = {150, 3, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"},
+       [425] = {150, 4, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"},
+       [426] = {150, 5, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"},
+       [427] = {150, 6, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"},
+       [428] = {151, 0, "DEV_MCAN15_MCANSS_HCLK_CLK", "Input clock"},
+       [429] = {151, 2, "DEV_MCAN15_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [430] = {151, 3, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"},
+       [431] = {151, 4, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"},
+       [432] = {151, 5, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"},
+       [433] = {151, 6, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"},
+       [434] = {152, 0, "DEV_MCAN16_MCANSS_HCLK_CLK", "Input clock"},
+       [435] = {152, 2, "DEV_MCAN16_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [436] = {152, 3, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"},
+       [437] = {152, 4, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"},
+       [438] = {152, 5, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"},
+       [439] = {152, 6, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"},
+       [440] = {153, 0, "DEV_MCAN17_MCANSS_HCLK_CLK", "Input clock"},
+       [441] = {153, 2, "DEV_MCAN17_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [442] = {153, 3, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"},
+       [443] = {153, 4, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"},
+       [444] = {153, 5, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"},
+       [445] = {153, 6, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"},
+       [446] = {160, 0, "DEV_MCAN2_MCANSS_HCLK_CLK", "Input clock"},
+       [447] = {160, 2, "DEV_MCAN2_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [448] = {160, 3, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
+       [449] = {160, 4, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
+       [450] = {160, 5, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
+       [451] = {160, 6, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
+       [452] = {161, 0, "DEV_MCAN3_MCANSS_HCLK_CLK", "Input clock"},
+       [453] = {161, 2, "DEV_MCAN3_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [454] = {161, 3, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
+       [455] = {161, 4, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
+       [456] = {161, 5, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
+       [457] = {161, 6, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
+       [458] = {162, 0, "DEV_MCAN4_MCANSS_HCLK_CLK", "Input clock"},
+       [459] = {162, 2, "DEV_MCAN4_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [460] = {162, 3, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
+       [461] = {162, 4, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
+       [462] = {162, 5, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
+       [463] = {162, 6, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
+       [464] = {163, 0, "DEV_MCAN5_MCANSS_HCLK_CLK", "Input clock"},
+       [465] = {163, 2, "DEV_MCAN5_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [466] = {163, 3, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
+       [467] = {163, 4, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
+       [468] = {163, 5, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
+       [469] = {163, 6, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
+       [470] = {164, 0, "DEV_MCAN6_MCANSS_HCLK_CLK", "Input clock"},
+       [471] = {164, 2, "DEV_MCAN6_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [472] = {164, 3, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
+       [473] = {164, 4, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
+       [474] = {164, 5, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
+       [475] = {164, 6, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
+       [476] = {165, 0, "DEV_MCAN7_MCANSS_HCLK_CLK", "Input clock"},
+       [477] = {165, 2, "DEV_MCAN7_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [478] = {165, 3, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
+       [479] = {165, 4, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
+       [480] = {165, 5, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
+       [481] = {165, 6, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
+       [482] = {166, 0, "DEV_MCAN8_MCANSS_HCLK_CLK", "Input clock"},
+       [483] = {166, 2, "DEV_MCAN8_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [484] = {166, 3, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
+       [485] = {166, 4, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
+       [486] = {166, 5, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
+       [487] = {166, 6, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
+       [488] = {167, 0, "DEV_MCAN9_MCANSS_HCLK_CLK", "Input clock"},
+       [489] = {167, 2, "DEV_MCAN9_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [490] = {167, 3, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
+       [491] = {167, 4, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
+       [492] = {167, 5, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
+       [493] = {167, 6, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
+       [494] = {174, 0, "DEV_MCASP0_MCASP_AHCLKX_POUT", "Output clock"},
+       [495] = {174, 2, "DEV_MCASP0_MCASP_AHCLKR_PIN", "Input muxed clock"},
+       [496] = {174, 3, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+       [497] = {174, 4, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+       [498] = {174, 5, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+       [499] = {174, 6, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+       [500] = {174, 11, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+       [501] = {174, 12, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+       [502] = {174, 13, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+       [503] = {174, 14, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
+       [504] = {174, 19, "DEV_MCASP0_MCASP_ACLKR_PIN", "Input clock"},
+       [505] = {174, 21, "DEV_MCASP0_MCASP_AHCLKX_PIN", "Input muxed clock"},
+       [506] = {174, 22, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+       [507] = {174, 23, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+       [508] = {174, 24, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+       [509] = {174, 25, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+       [510] = {174, 30, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+       [511] = {174, 31, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+       [512] = {174, 32, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+       [513] = {174, 33, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
+       [514] = {174, 38, "DEV_MCASP0_MCASP_AHCLKR_POUT", "Output clock"},
+       [515] = {174, 39, "DEV_MCASP0_MCASP_ACLKX_PIN", "Input clock"},
+       [516] = {174, 40, "DEV_MCASP0_AUX_CLK", "Input muxed clock"},
+       [517] = {174, 41, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+       [518] = {174, 42, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+       [519] = {174, 45, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+       [520] = {174, 46, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+       [521] = {174, 47, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+       [522] = {174, 48, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+       [523] = {174, 49, "DEV_MCASP0_VBUSP_CLK", "Input clock"},
+       [524] = {174, 50, "DEV_MCASP0_MCASP_ACLKR_POUT", "Output clock"},
+       [525] = {174, 51, "DEV_MCASP0_MCASP_ACLKX_POUT", "Output clock"},
+       [526] = {175, 0, "DEV_MCASP1_MCASP_AHCLKX_POUT", "Output clock"},
+       [527] = {175, 2, "DEV_MCASP1_MCASP_AHCLKR_PIN", "Input muxed clock"},
+       [528] = {175, 3, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+       [529] = {175, 4, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+       [530] = {175, 5, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+       [531] = {175, 6, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+       [532] = {175, 11, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+       [533] = {175, 12, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+       [534] = {175, 13, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+       [535] = {175, 14, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
+       [536] = {175, 19, "DEV_MCASP1_MCASP_ACLKR_PIN", "Input clock"},
+       [537] = {175, 21, "DEV_MCASP1_MCASP_AHCLKX_PIN", "Input muxed clock"},
+       [538] = {175, 22, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+       [539] = {175, 23, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+       [540] = {175, 24, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+       [541] = {175, 25, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+       [542] = {175, 30, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+       [543] = {175, 31, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+       [544] = {175, 32, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+       [545] = {175, 33, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
+       [546] = {175, 38, "DEV_MCASP1_MCASP_AHCLKR_POUT", "Output clock"},
+       [547] = {175, 39, "DEV_MCASP1_MCASP_ACLKX_PIN", "Input clock"},
+       [548] = {175, 40, "DEV_MCASP1_AUX_CLK", "Input muxed clock"},
+       [549] = {175, 41, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+       [550] = {175, 42, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+       [551] = {175, 45, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+       [552] = {175, 46, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+       [553] = {175, 47, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+       [554] = {175, 48, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+       [555] = {175, 49, "DEV_MCASP1_VBUSP_CLK", "Input clock"},
+       [556] = {175, 50, "DEV_MCASP1_MCASP_ACLKR_POUT", "Output clock"},
+       [557] = {175, 51, "DEV_MCASP1_MCASP_ACLKX_POUT", "Output clock"},
+       [558] = {176, 0, "DEV_MCASP2_MCASP_AHCLKX_POUT", "Output clock"},
+       [559] = {176, 2, "DEV_MCASP2_MCASP_AHCLKR_PIN", "Input muxed clock"},
+       [560] = {176, 3, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+       [561] = {176, 4, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+       [562] = {176, 5, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+       [563] = {176, 6, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+       [564] = {176, 11, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+       [565] = {176, 12, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+       [566] = {176, 13, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+       [567] = {176, 14, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
+       [568] = {176, 19, "DEV_MCASP2_MCASP_ACLKR_PIN", "Input clock"},
+       [569] = {176, 21, "DEV_MCASP2_MCASP_AHCLKX_PIN", "Input muxed clock"},
+       [570] = {176, 22, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+       [571] = {176, 23, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+       [572] = {176, 24, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+       [573] = {176, 25, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+       [574] = {176, 30, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+       [575] = {176, 31, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+       [576] = {176, 32, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+       [577] = {176, 33, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
+       [578] = {176, 38, "DEV_MCASP2_MCASP_AHCLKR_POUT", "Output clock"},
+       [579] = {176, 39, "DEV_MCASP2_MCASP_ACLKX_PIN", "Input clock"},
+       [580] = {176, 40, "DEV_MCASP2_AUX_CLK", "Input muxed clock"},
+       [581] = {176, 41, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+       [582] = {176, 42, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+       [583] = {176, 45, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+       [584] = {176, 46, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+       [585] = {176, 47, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+       [586] = {176, 48, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+       [587] = {176, 49, "DEV_MCASP2_VBUSP_CLK", "Input clock"},
+       [588] = {176, 50, "DEV_MCASP2_MCASP_ACLKR_POUT", "Output clock"},
+       [589] = {176, 51, "DEV_MCASP2_MCASP_ACLKX_POUT", "Output clock"},
+       [590] = {266, 3, "DEV_MCSPI0_VBUSP_CLK", "Input clock"},
+       [591] = {266, 4, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"},
+       [592] = {266, 5, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"},
+       [593] = {267, 3, "DEV_MCSPI1_VBUSP_CLK", "Input clock"},
+       [594] = {267, 4, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"},
+       [595] = {267, 5, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"},
+       [596] = {268, 3, "DEV_MCSPI2_VBUSP_CLK", "Input clock"},
+       [597] = {268, 4, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"},
+       [598] = {268, 5, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"},
+       [599] = {269, 0, "DEV_MCSPI3_IO_CLKSPII_CLK", "Input muxed clock"},
+       [600] = {269, 1, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"},
+       [601] = {269, 3, "DEV_MCSPI3_VBUSP_CLK", "Input clock"},
+       [602] = {269, 4, "DEV_MCSPI3_CLKSPIREF_CLK", "Input clock"},
+       [603] = {269, 5, "DEV_MCSPI3_IO_CLKSPIO_CLK", "Output clock"},
+       [604] = {270, 0, "DEV_MCSPI4_IO_CLKSPII_CLK", "Input clock"},
+       [605] = {270, 1, "DEV_MCSPI4_VBUSP_CLK", "Input clock"},
+       [606] = {270, 2, "DEV_MCSPI4_CLKSPIREF_CLK", "Input clock"},
+       [607] = {270, 3, "DEV_MCSPI4_IO_CLKSPIO_CLK", "Output clock"},
+       [608] = {271, 3, "DEV_MCSPI5_VBUSP_CLK", "Input clock"},
+       [609] = {271, 4, "DEV_MCSPI5_CLKSPIREF_CLK", "Input clock"},
+       [610] = {271, 5, "DEV_MCSPI5_IO_CLKSPIO_CLK", "Output clock"},
+       [611] = {272, 3, "DEV_MCSPI6_VBUSP_CLK", "Input clock"},
+       [612] = {272, 4, "DEV_MCSPI6_CLKSPIREF_CLK", "Input clock"},
+       [613] = {272, 5, "DEV_MCSPI6_IO_CLKSPIO_CLK", "Output clock"},
+       [614] = {273, 3, "DEV_MCSPI7_VBUSP_CLK", "Input clock"},
+       [615] = {273, 4, "DEV_MCSPI7_CLKSPIREF_CLK", "Input clock"},
+       [616] = {273, 5, "DEV_MCSPI7_IO_CLKSPIO_CLK", "Output clock"},
+       [617] = {0, 0, "DEV_MCU_ADC0_SYS_CLK", "Input clock"},
+       [618] = {0, 1, "DEV_MCU_ADC0_ADC_CLK", "Input muxed clock"},
+       [619] = {0, 2, "DEV_MCU_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"},
+       [620] = {0, 3, "DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"},
+       [621] = {0, 4, "DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"},
+       [622] = {0, 5, "DEV_MCU_ADC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"},
+       [623] = {0, 6, "DEV_MCU_ADC0_VBUS_CLK", "Input clock"},
+       [624] = {1, 0, "DEV_MCU_ADC1_SYS_CLK", "Input clock"},
+       [625] = {1, 1, "DEV_MCU_ADC1_ADC_CLK", "Input muxed clock"},
+       [626] = {1, 2, "DEV_MCU_ADC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"},
+       [627] = {1, 3, "DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"},
+       [628] = {1, 4, "DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"},
+       [629] = {1, 5, "DEV_MCU_ADC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"},
+       [630] = {1, 6, "DEV_MCU_ADC1_VBUS_CLK", "Input clock"},
+       [631] = {18, 0, "DEV_MCU_CPSW0_MDIO_MDCLK_O", "Output clock"},
+       [632] = {18, 2, "DEV_MCU_CPSW0_CPTS_RFT_CLK", "Input muxed clock"},
+       [633] = {18, 3, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+       [634] = {18, 4, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+       [635] = {18, 5, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+       [636] = {18, 6, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+       [637] = {18, 7, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+       [638] = {18, 8, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+       [639] = {18, 9, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+       [640] = {18, 10, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+       [641] = {18, 11, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+       [642] = {18, 12, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+       [643] = {18, 17, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+       [644] = {18, 18, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+       [645] = {18, 20, "DEV_MCU_CPSW0_GMII1_MR_CLK", "Input clock"},
+       [646] = {18, 21, "DEV_MCU_CPSW0_CPPI_CLK_CLK", "Input clock"},
+       [647] = {18, 22, "DEV_MCU_CPSW0_CPTS_GENF0", "Output clock"},
+       [648] = {18, 24, "DEV_MCU_CPSW0_GMII_RFT_CLK", "Input clock"},
+       [649] = {18, 27, "DEV_MCU_CPSW0_GMII1_MT_CLK", "Input clock"},
+       [650] = {18, 28, "DEV_MCU_CPSW0_RGMII1_TXC_O", "Output clock"},
+       [651] = {18, 29, "DEV_MCU_CPSW0_RMII_MHZ_50_CLK", "Input clock"},
+       [652] = {18, 30, "DEV_MCU_CPSW0_RGMII_MHZ_5_CLK", "Input clock"},
+       [653] = {18, 31, "DEV_MCU_CPSW0_RGMII1_RXC_I", "Input clock"},
+       [654] = {18, 32, "DEV_MCU_CPSW0_RGMII_MHZ_250_CLK", "Input clock"},
+       [655] = {18, 33, "DEV_MCU_CPSW0_RGMII_MHZ_50_CLK", "Input clock"},
+       [656] = {24, 0, "DEV_MCU_CPT2_AGGR0_VCLK_CLK", "Input clock"},
+       [657] = {44, 0, "DEV_MCU_DCC0_DCC_INPUT10_CLK", "Input clock"},
+       [658] = {44, 1, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"},
+       [659] = {44, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"},
+       [660] = {44, 3, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"},
+       [661] = {44, 4, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"},
+       [662] = {44, 5, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"},
+       [663] = {44, 6, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"},
+       [664] = {44, 7, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"},
+       [665] = {44, 8, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"},
+       [666] = {44, 9, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"},
+       [667] = {44, 10, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"},
+       [668] = {44, 11, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"},
+       [669] = {44, 12, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"},
+       [670] = {45, 0, "DEV_MCU_DCC1_DCC_INPUT10_CLK", "Input clock"},
+       [671] = {45, 1, "DEV_MCU_DCC1_DCC_INPUT01_CLK", "Input clock"},
+       [672] = {45, 2, "DEV_MCU_DCC1_DCC_CLKSRC2_CLK", "Input clock"},
+       [673] = {45, 3, "DEV_MCU_DCC1_DCC_CLKSRC7_CLK", "Input clock"},
+       [674] = {45, 4, "DEV_MCU_DCC1_DCC_CLKSRC0_CLK", "Input clock"},
+       [675] = {45, 5, "DEV_MCU_DCC1_VBUS_CLK", "Input clock"},
+       [676] = {45, 6, "DEV_MCU_DCC1_DCC_CLKSRC4_CLK", "Input clock"},
+       [677] = {45, 7, "DEV_MCU_DCC1_DCC_CLKSRC1_CLK", "Input clock"},
+       [678] = {45, 8, "DEV_MCU_DCC1_DCC_CLKSRC3_CLK", "Input clock"},
+       [679] = {45, 9, "DEV_MCU_DCC1_DCC_INPUT00_CLK", "Input clock"},
+       [680] = {45, 10, "DEV_MCU_DCC1_DCC_CLKSRC5_CLK", "Input clock"},
+       [681] = {45, 11, "DEV_MCU_DCC1_DCC_CLKSRC6_CLK", "Input clock"},
+       [682] = {45, 12, "DEV_MCU_DCC1_DCC_INPUT02_CLK", "Input clock"},
+       [683] = {46, 0, "DEV_MCU_DCC2_DCC_INPUT10_CLK", "Input clock"},
+       [684] = {46, 1, "DEV_MCU_DCC2_DCC_INPUT01_CLK", "Input clock"},
+       [685] = {46, 3, "DEV_MCU_DCC2_DCC_CLKSRC7_CLK", "Input clock"},
+       [686] = {46, 4, "DEV_MCU_DCC2_DCC_CLKSRC0_CLK", "Input clock"},
+       [687] = {46, 5, "DEV_MCU_DCC2_VBUS_CLK", "Input clock"},
+       [688] = {46, 7, "DEV_MCU_DCC2_DCC_CLKSRC1_CLK", "Input clock"},
+       [689] = {46, 8, "DEV_MCU_DCC2_DCC_CLKSRC3_CLK", "Input clock"},
+       [690] = {46, 9, "DEV_MCU_DCC2_DCC_INPUT00_CLK", "Input clock"},
+       [691] = {46, 11, "DEV_MCU_DCC2_DCC_CLKSRC6_CLK", "Input clock"},
+       [692] = {46, 12, "DEV_MCU_DCC2_DCC_INPUT02_CLK", "Input clock"},
+       [693] = {98, 0, "DEV_MCU_ESM0_CLK", "Input clock"},
+       [694] = {101, 0, "DEV_MCU_FSS0_FSAS_0_GCLK", "Input clock"},
+       [695] = {102, 0, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N", "Output clock"},
+       [696] = {102, 1, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK", "Input clock"},
+       [697] = {102, 2, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK", "Input clock"},
+       [698] = {102, 4, "DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK", "Input clock"},
+       [699] = {102, 5, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK", "Input clock"},
+       [700] = {102, 7, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK", "Input clock"},
+       [701] = {102, 10, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P", "Output clock"},
+       [702] = {103, 0, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK", "Input muxed clock"},
+       [703] = {103, 1, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"},
+       [704] = {103, 2, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"},
+       [705] = {103, 3, "DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"},
+       [706] = {103, 4, "DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"},
+       [707] = {103, 5, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"},
+       [708] = {103, 6, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"},
+       [709] = {103, 7, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"},
+       [710] = {103, 8, "DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"},
+       [711] = {103, 9, "DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"},
+       [712] = {104, 0, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK", "Input clock"},
+       [713] = {104, 1, "DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK", "Input clock"},
+       [714] = {104, 7, "DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK", "Input clock"},
+       [715] = {194, 0, "DEV_MCU_I2C0_PISCL", "Input clock"},
+       [716] = {194, 1, "DEV_MCU_I2C0_PISYS_CLK", "Input clock"},
+       [717] = {194, 2, "DEV_MCU_I2C0_CLK", "Input clock"},
+       [718] = {195, 0, "DEV_MCU_I2C1_PISCL", "Input clock"},
+       [719] = {195, 1, "DEV_MCU_I2C1_PISYS_CLK", "Input clock"},
+       [720] = {195, 2, "DEV_MCU_I2C1_CLK", "Input clock"},
+       [721] = {195, 3, "DEV_MCU_I2C1_PORSCL", "Output clock"},
+       [722] = {117, 0, "DEV_MCU_I3C0_I3C_SCL_DI", "Input clock"},
+       [723] = {117, 1, "DEV_MCU_I3C0_I3C_SCL_DO", "Output clock"},
+       [724] = {117, 2, "DEV_MCU_I3C0_I3C_PCLK_CLK", "Input clock"},
+       [725] = {117, 4, "DEV_MCU_I3C0_I3C_SCLK_CLK", "Input clock"},
+       [726] = {118, 2, "DEV_MCU_I3C1_I3C_PCLK_CLK", "Input clock"},
+       [727] = {118, 4, "DEV_MCU_I3C1_I3C_SCLK_CLK", "Input clock"},
+       [728] = {172, 0, "DEV_MCU_MCAN0_MCANSS_HCLK_CLK", "Input clock"},
+       [729] = {172, 2, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [730] = {172, 3, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
+       [731] = {172, 4, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
+       [732] = {172, 5, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
+       [733] = {172, 6, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
+       [734] = {173, 0, "DEV_MCU_MCAN1_MCANSS_HCLK_CLK", "Input clock"},
+       [735] = {173, 2, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [736] = {173, 3, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
+       [737] = {173, 4, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
+       [738] = {173, 5, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
+       [739] = {173, 6, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
+       [740] = {274, 3, "DEV_MCU_MCSPI0_VBUSP_CLK", "Input clock"},
+       [741] = {274, 4, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"},
+       [742] = {274, 5, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"},
+       [743] = {275, 0, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"},
+       [744] = {275, 1, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"},
+       [745] = {275, 3, "DEV_MCU_MCSPI1_VBUSP_CLK", "Input clock"},
+       [746] = {275, 4, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"},
+       [747] = {275, 5, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"},
+       [748] = {276, 0, "DEV_MCU_MCSPI2_IO_CLKSPII_CLK", "Input clock"},
+       [749] = {276, 1, "DEV_MCU_MCSPI2_VBUSP_CLK", "Input clock"},
+       [750] = {276, 2, "DEV_MCU_MCSPI2_CLKSPIREF_CLK", "Input clock"},
+       [751] = {276, 3, "DEV_MCU_MCSPI2_IO_CLKSPIO_CLK", "Output clock"},
+       [752] = {237, 0, "DEV_MCU_NAVSS0_INTR_0_INTR_CLK", "Input clock"},
+       [753] = {238, 0, "DEV_MCU_NAVSS0_MCRC_0_CLK", "Input clock"},
+       [754] = {302, 0, "DEV_MCU_NAVSS0_MODSS_VD2CLK", "Input clock"},
+       [755] = {234, 0, "DEV_MCU_NAVSS0_PROXY0_CLK_CLK", "Input clock"},
+       [756] = {235, 0, "DEV_MCU_NAVSS0_RINGACC0_SYS_CLK", "Input clock"},
+       [757] = {236, 0, "DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"},
+       [758] = {303, 0, "DEV_MCU_NAVSS0_UDMASS_VD2CLK", "Input clock"},
+       [759] = {233, 0, "DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK", "Input clock"},
+       [760] = {142, 1, "DEV_MCU_PBIST0_CLK7_CLK", "Input clock"},
+       [761] = {142, 2, "DEV_MCU_PBIST0_CLK3_CLK", "Input clock"},
+       [762] = {142, 3, "DEV_MCU_PBIST0_CLK5_CLK", "Input clock"},
+       [763] = {142, 4, "DEV_MCU_PBIST0_CLK1_CLK", "Input clock"},
+       [764] = {142, 5, "DEV_MCU_PBIST0_CLK8_CLK", "Input clock"},
+       [765] = {142, 6, "DEV_MCU_PBIST0_CLK6_CLK", "Input clock"},
+       [766] = {142, 8, "DEV_MCU_PBIST0_CLK4_CLK", "Input clock"},
+       [767] = {142, 9, "DEV_MCU_PBIST0_CLK2_CLK", "Input clock"},
+       [768] = {143, 1, "DEV_MCU_PBIST1_CLK7_CLK", "Input clock"},
+       [769] = {143, 2, "DEV_MCU_PBIST1_CLK3_CLK", "Input clock"},
+       [770] = {143, 3, "DEV_MCU_PBIST1_CLK5_CLK", "Input clock"},
+       [771] = {143, 4, "DEV_MCU_PBIST1_CLK1_CLK", "Input clock"},
+       [772] = {143, 5, "DEV_MCU_PBIST1_CLK8_CLK", "Input clock"},
+       [773] = {143, 6, "DEV_MCU_PBIST1_CLK6_CLK", "Input clock"},
+       [774] = {143, 8, "DEV_MCU_PBIST1_CLK4_CLK", "Input clock"},
+       [775] = {143, 9, "DEV_MCU_PBIST1_CLK2_CLK", "Input clock"},
+       [776] = {144, 1, "DEV_MCU_PBIST2_CLK7_CLK", "Input clock"},
+       [777] = {144, 2, "DEV_MCU_PBIST2_CLK3_CLK", "Input clock"},
+       [778] = {144, 3, "DEV_MCU_PBIST2_CLK5_CLK", "Input clock"},
+       [779] = {144, 4, "DEV_MCU_PBIST2_CLK1_CLK", "Input clock"},
+       [780] = {144, 5, "DEV_MCU_PBIST2_CLK8_CLK", "Input clock"},
+       [781] = {144, 6, "DEV_MCU_PBIST2_CLK6_CLK", "Input clock"},
+       [782] = {144, 8, "DEV_MCU_PBIST2_CLK4_CLK", "Input clock"},
+       [783] = {144, 9, "DEV_MCU_PBIST2_CLK2_CLK", "Input clock"},
+       [784] = {250, 0, "DEV_MCU_R5FSS0_CORE0_CPU_CLK", "Input muxed clock"},
+       [785] = {250, 1, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"},
+       [786] = {250, 2, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"},
+       [787] = {250, 3, "DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"},
+       [788] = {250, 4, "DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE", "Input clock"},
+       [789] = {251, 0, "DEV_MCU_R5FSS0_CORE1_CPU_CLK", "Input muxed clock"},
+       [790] = {251, 1, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"},
+       [791] = {251, 2, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"},
+       [792] = {251, 3, "DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"},
+       [793] = {251, 4, "DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE", "Input clock"},
+       [794] = {262, 0, "DEV_MCU_RTI0_VBUSP_CLK", "Input clock"},
+       [795] = {262, 1, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"},
+       [796] = {262, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
+       [797] = {262, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
+       [798] = {262, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
+       [799] = {262, 5, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
+       [800] = {263, 0, "DEV_MCU_RTI1_VBUSP_CLK", "Input clock"},
+       [801] = {263, 1, "DEV_MCU_RTI1_RTI_CLK", "Input muxed clock"},
+       [802] = {263, 2, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
+       [803] = {263, 3, "DEV_MCU_RTI1_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
+       [804] = {263, 4, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
+       [805] = {263, 5, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
+       [806] = {265, 0, "DEV_MCU_SA2_UL0_X2_CLK", "Input clock"},
+       [807] = {265, 1, "DEV_MCU_SA2_UL0_PKA_IN_CLK", "Input clock"},
+       [808] = {265, 2, "DEV_MCU_SA2_UL0_X1_CLK", "Input clock"},
+       [809] = {35, 0, "DEV_MCU_TIMER0_TIMER_HCLK_CLK", "Input clock"},
+       [810] = {35, 1, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"},
+       [811] = {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+       [812] = {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+       [813] = {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+       [814] = {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+       [815] = {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+       [816] = {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+       [817] = {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+       [818] = {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+       [819] = {35, 11, "DEV_MCU_TIMER0_TIMER_PWM", "Output clock"},
+       [820] = {71, 0, "DEV_MCU_TIMER1_TIMER_HCLK_CLK", "Input clock"},
+       [821] = {71, 1, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"},
+       [822] = {71, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
+       [823] = {71, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
+       [824] = {72, 0, "DEV_MCU_TIMER2_TIMER_HCLK_CLK", "Input clock"},
+       [825] = {72, 1, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"},
+       [826] = {72, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+       [827] = {72, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+       [828] = {72, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+       [829] = {72, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+       [830] = {72, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+       [831] = {72, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+       [832] = {72, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+       [833] = {72, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+       [834] = {72, 11, "DEV_MCU_TIMER2_TIMER_PWM", "Output clock"},
+       [835] = {73, 0, "DEV_MCU_TIMER3_TIMER_HCLK_CLK", "Input clock"},
+       [836] = {73, 1, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"},
+       [837] = {73, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
+       [838] = {73, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
+       [839] = {74, 0, "DEV_MCU_TIMER4_TIMER_HCLK_CLK", "Input clock"},
+       [840] = {74, 1, "DEV_MCU_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"},
+       [841] = {74, 2, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+       [842] = {74, 3, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+       [843] = {74, 4, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+       [844] = {74, 5, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+       [845] = {74, 6, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+       [846] = {74, 7, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+       [847] = {74, 8, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+       [848] = {74, 9, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+       [849] = {74, 11, "DEV_MCU_TIMER4_TIMER_PWM", "Output clock"},
+       [850] = {75, 0, "DEV_MCU_TIMER5_TIMER_HCLK_CLK", "Input clock"},
+       [851] = {75, 1, "DEV_MCU_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"},
+       [852] = {75, 2, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"},
+       [853] = {75, 3, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"},
+       [854] = {76, 0, "DEV_MCU_TIMER6_TIMER_HCLK_CLK", "Input clock"},
+       [855] = {76, 1, "DEV_MCU_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"},
+       [856] = {76, 2, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+       [857] = {76, 3, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+       [858] = {76, 4, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+       [859] = {76, 5, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+       [860] = {76, 6, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+       [861] = {76, 7, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+       [862] = {76, 8, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+       [863] = {76, 9, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+       [864] = {76, 11, "DEV_MCU_TIMER6_TIMER_PWM", "Output clock"},
+       [865] = {77, 0, "DEV_MCU_TIMER7_TIMER_HCLK_CLK", "Input clock"},
+       [866] = {77, 1, "DEV_MCU_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"},
+       [867] = {77, 2, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"},
+       [868] = {77, 3, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"},
+       [869] = {78, 0, "DEV_MCU_TIMER8_TIMER_HCLK_CLK", "Input clock"},
+       [870] = {78, 1, "DEV_MCU_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"},
+       [871] = {78, 2, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+       [872] = {78, 3, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+       [873] = {78, 4, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+       [874] = {78, 5, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+       [875] = {78, 6, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+       [876] = {78, 7, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+       [877] = {78, 8, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+       [878] = {78, 9, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+       [879] = {78, 11, "DEV_MCU_TIMER8_TIMER_PWM", "Output clock"},
+       [880] = {79, 0, "DEV_MCU_TIMER9_TIMER_HCLK_CLK", "Input clock"},
+       [881] = {79, 1, "DEV_MCU_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"},
+       [882] = {79, 2, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"},
+       [883] = {79, 3, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"},
+       [884] = {149, 2, "DEV_MCU_UART0_FCLK_CLK", "Input muxed clock"},
+       [885] = {149, 3, "DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"},
+       [886] = {149, 4, "DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"},
+       [887] = {149, 5, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"},
+       [888] = {91, 0, "DEV_MMCSD0_EMMCSS_VBUS_CLK", "Input clock"},
+       [889] = {91, 3, "DEV_MMCSD0_EMMCSS_XIN_CLK", "Input muxed clock"},
+       [890] = {91, 4, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
+       [891] = {91, 5, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
+       [892] = {91, 6, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
+       [893] = {91, 7, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK_DUP0", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
+       [894] = {92, 0, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I", "Input clock"},
+       [895] = {92, 1, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"},
+       [896] = {92, 2, "DEV_MMCSD1_EMMCSDSS_XIN_CLK", "Input muxed clock"},
+       [897] = {92, 3, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
+       [898] = {92, 4, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
+       [899] = {92, 5, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
+       [900] = {92, 6, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK_DUP0", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
+       [901] = {92, 7, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O", "Output clock"},
+       [902] = {199, 0, "DEV_NAVSS0_CPTS0_GENF2", "Output clock"},
+       [903] = {199, 1, "DEV_NAVSS0_CPTS0_GENF3", "Output clock"},
+       [904] = {199, 2, "DEV_NAVSS0_CPTS0_GENF4", "Output clock"},
+       [905] = {201, 0, "DEV_NAVSS0_CPTS_0_VBUSP_GCLK", "Input clock"},
+       [906] = {201, 1, "DEV_NAVSS0_CPTS_0_RCLK", "Input muxed clock"},
+       [907] = {201, 2, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+       [908] = {201, 3, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+       [909] = {201, 4, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+       [910] = {201, 5, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+       [911] = {201, 6, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+       [912] = {201, 7, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+       [913] = {201, 8, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+       [914] = {201, 9, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+       [915] = {201, 10, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+       [916] = {201, 11, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+       [917] = {201, 16, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+       [918] = {201, 17, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+       [919] = {201, 20, "DEV_NAVSS0_CPTS_0_TS_GENF0", "Output clock"},
+       [920] = {201, 21, "DEV_NAVSS0_CPTS_0_TS_GENF1", "Output clock"},
+       [921] = {206, 0, "DEV_NAVSS0_DTI_0_CLK_CLK", "Input clock"},
+       [922] = {213, 0, "DEV_NAVSS0_INTR_ROUTER_0_INTR_CLK", "Input clock"},
+       [923] = {214, 0, "DEV_NAVSS0_MAILBOX_0_VCLK_CLK", "Input clock"},
+       [924] = {215, 0, "DEV_NAVSS0_MAILBOX_1_VCLK_CLK", "Input clock"},
+       [925] = {224, 0, "DEV_NAVSS0_MAILBOX_10_VCLK_CLK", "Input clock"},
+       [926] = {225, 0, "DEV_NAVSS0_MAILBOX_11_VCLK_CLK", "Input clock"},
+       [927] = {216, 0, "DEV_NAVSS0_MAILBOX_2_VCLK_CLK", "Input clock"},
+       [928] = {217, 0, "DEV_NAVSS0_MAILBOX_3_VCLK_CLK", "Input clock"},
+       [929] = {218, 0, "DEV_NAVSS0_MAILBOX_4_VCLK_CLK", "Input clock"},
+       [930] = {219, 0, "DEV_NAVSS0_MAILBOX_5_VCLK_CLK", "Input clock"},
+       [931] = {220, 0, "DEV_NAVSS0_MAILBOX_6_VCLK_CLK", "Input clock"},
+       [932] = {221, 0, "DEV_NAVSS0_MAILBOX_7_VCLK_CLK", "Input clock"},
+       [933] = {222, 0, "DEV_NAVSS0_MAILBOX_8_VCLK_CLK", "Input clock"},
+       [934] = {223, 0, "DEV_NAVSS0_MAILBOX_9_VCLK_CLK", "Input clock"},
+       [935] = {227, 0, "DEV_NAVSS0_MCRC_0_CLK", "Input clock"},
+       [936] = {299, 0, "DEV_NAVSS0_MODSS_VD2CLK", "Input clock"},
+       [937] = {207, 0, "DEV_NAVSS0_MODSS_INTA_0_SYS_CLK", "Input clock"},
+       [938] = {208, 0, "DEV_NAVSS0_MODSS_INTA_1_SYS_CLK", "Input clock"},
+       [939] = {210, 0, "DEV_NAVSS0_PROXY_0_CLK_CLK", "Input clock"},
+       [940] = {211, 0, "DEV_NAVSS0_RINGACC_0_SYS_CLK", "Input clock"},
+       [941] = {226, 0, "DEV_NAVSS0_SPINLOCK_0_CLK", "Input clock"},
+       [942] = {228, 0, "DEV_NAVSS0_TBU_0_CLK_CLK", "Input clock"},
+       [943] = {230, 0, "DEV_NAVSS0_TIMERMGR_0_VCLK_CLK", "Input clock"},
+       [944] = {230, 1, "DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT", "Input clock"},
+       [945] = {231, 0, "DEV_NAVSS0_TIMERMGR_1_VCLK_CLK", "Input clock"},
+       [946] = {231, 1, "DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT", "Input clock"},
+       [947] = {212, 0, "DEV_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"},
+       [948] = {300, 0, "DEV_NAVSS0_UDMASS_VD2CLK", "Input clock"},
+       [949] = {209, 0, "DEV_NAVSS0_UDMASS_INTA_0_SYS_CLK", "Input clock"},
+       [950] = {301, 0, "DEV_NAVSS0_VIRTSS_VD2CLK", "Input clock"},
+       [951] = {139, 1, "DEV_PBIST0_CLK7_CLK", "Input clock"},
+       [952] = {139, 2, "DEV_PBIST0_CLK3_CLK", "Input clock"},
+       [953] = {139, 3, "DEV_PBIST0_CLK5_CLK", "Input clock"},
+       [954] = {139, 4, "DEV_PBIST0_CLK1_CLK", "Input clock"},
+       [955] = {139, 5, "DEV_PBIST0_CLK8_CLK", "Input clock"},
+       [956] = {139, 6, "DEV_PBIST0_CLK6_CLK", "Input clock"},
+       [957] = {139, 8, "DEV_PBIST0_CLK4_CLK", "Input clock"},
+       [958] = {139, 9, "DEV_PBIST0_CLK2_CLK", "Input clock"},
+       [959] = {140, 1, "DEV_PBIST1_CLK7_CLK", "Input clock"},
+       [960] = {140, 2, "DEV_PBIST1_CLK3_CLK", "Input clock"},
+       [961] = {140, 3, "DEV_PBIST1_CLK5_CLK", "Input clock"},
+       [962] = {140, 4, "DEV_PBIST1_CLK1_CLK", "Input clock"},
+       [963] = {140, 5, "DEV_PBIST1_CLK8_CLK", "Input clock"},
+       [964] = {140, 6, "DEV_PBIST1_CLK6_CLK", "Input clock"},
+       [965] = {140, 8, "DEV_PBIST1_CLK4_CLK", "Input clock"},
+       [966] = {140, 9, "DEV_PBIST1_CLK2_CLK", "Input clock"},
+       [967] = {141, 1, "DEV_PBIST2_CLK7_CLK", "Input clock"},
+       [968] = {141, 2, "DEV_PBIST2_CLK3_CLK", "Input clock"},
+       [969] = {141, 3, "DEV_PBIST2_CLK5_CLK", "Input clock"},
+       [970] = {141, 4, "DEV_PBIST2_CLK1_CLK", "Input clock"},
+       [971] = {141, 5, "DEV_PBIST2_CLK8_CLK", "Input clock"},
+       [972] = {141, 6, "DEV_PBIST2_CLK6_CLK", "Input clock"},
+       [973] = {141, 8, "DEV_PBIST2_CLK4_CLK", "Input clock"},
+       [974] = {141, 9, "DEV_PBIST2_CLK2_CLK", "Input clock"},
+       [975] = {240, 0, "DEV_PCIE1_PCIE_LANE0_TXCLK", "Output clock"},
+       [976] = {240, 1, "DEV_PCIE1_PCIE_LANE1_TXMCLK", "Input clock"},
+       [977] = {240, 2, "DEV_PCIE1_PCIE_LANE0_TXMCLK", "Input clock"},
+       [978] = {240, 3, "DEV_PCIE1_PCIE_LANE0_TXFCLK", "Input clock"},
+       [979] = {240, 4, "DEV_PCIE1_PCIE_PM_CLK", "Input clock"},
+       [980] = {240, 5, "DEV_PCIE1_PCIE_LANE3_TXMCLK", "Input clock"},
+       [981] = {240, 6, "DEV_PCIE1_PCIE_CBA_CLK", "Input clock"},
+       [982] = {240, 7, "DEV_PCIE1_PCIE_LANE1_REFCLK", "Input clock"},
+       [983] = {240, 8, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
+       [984] = {240, 9, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+       [985] = {240, 10, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+       [986] = {240, 11, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+       [987] = {240, 12, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+       [988] = {240, 13, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+       [989] = {240, 14, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+       [990] = {240, 15, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+       [991] = {240, 16, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+       [992] = {240, 17, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+       [993] = {240, 18, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+       [994] = {240, 23, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+       [995] = {240, 24, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+       [996] = {240, 25, "DEV_PCIE1_PCIE_LANE1_RXFCLK", "Input clock"},
+       [997] = {240, 27, "DEV_PCIE1_PCIE_LANE2_RXCLK", "Input clock"},
+       [998] = {240, 28, "DEV_PCIE1_PCIE_LANE2_TXMCLK", "Input clock"},
+       [999] = {240, 29, "DEV_PCIE1_PCIE_LANE1_TXCLK", "Output clock"},
+       [1000] = {240, 30, "DEV_PCIE1_PCIE_LANE3_TXFCLK", "Input clock"},
+       [1001] = {240, 31, "DEV_PCIE1_PCIE_LANE2_TXFCLK", "Input clock"},
+       [1002] = {240, 32, "DEV_PCIE1_PCIE_LANE1_RXCLK", "Input clock"},
+       [1003] = {240, 33, "DEV_PCIE1_PCIE_LANE2_TXCLK", "Output clock"},
+       [1004] = {240, 34, "DEV_PCIE1_PCIE_LANE1_TXFCLK", "Input clock"},
+       [1005] = {240, 35, "DEV_PCIE1_PCIE_LANE0_REFCLK", "Input clock"},
+       [1006] = {240, 36, "DEV_PCIE1_PCIE_LANE3_RXFCLK", "Input clock"},
+       [1007] = {240, 37, "DEV_PCIE1_PCIE_LANE2_RXFCLK", "Input clock"},
+       [1008] = {240, 38, "DEV_PCIE1_PCIE_LANE3_RXCLK", "Input clock"},
+       [1009] = {240, 39, "DEV_PCIE1_PCIE_LANE3_REFCLK", "Input clock"},
+       [1010] = {240, 40, "DEV_PCIE1_PCIE_LANE2_REFCLK", "Input clock"},
+       [1011] = {240, 41, "DEV_PCIE1_PCIE_LANE0_RXFCLK", "Input clock"},
+       [1012] = {240, 42, "DEV_PCIE1_PCIE_LANE3_TXCLK", "Output clock"},
+       [1013] = {240, 43, "DEV_PCIE1_PCIE_LANE0_RXCLK", "Input clock"},
+       [1014] = {133, 0, "DEV_PSC0_SLOW_CLK", "Input clock"},
+       [1015] = {133, 1, "DEV_PSC0_CLK", "Input clock"},
+       [1016] = {245, 0, "DEV_R5FSS0_CORE0_CPU_CLK", "Input clock"},
+       [1017] = {245, 1, "DEV_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"},
+       [1018] = {245, 2, "DEV_R5FSS0_CORE0_INTERFACE_PHASE", "Input clock"},
+       [1019] = {246, 0, "DEV_R5FSS0_CORE1_CPU_CLK", "Input clock"},
+       [1020] = {246, 1, "DEV_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"},
+       [1021] = {246, 2, "DEV_R5FSS0_CORE1_INTERFACE_PHASE", "Input clock"},
+       [1022] = {252, 0, "DEV_RTI0_VBUSP_CLK", "Input clock"},
+       [1023] = {252, 1, "DEV_RTI0_RTI_CLK", "Input muxed clock"},
+       [1024] = {252, 2, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+       [1025] = {252, 3, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+       [1026] = {252, 4, "DEV_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+       [1027] = {252, 5, "DEV_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+       [1028] = {252, 6, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+       [1029] = {252, 7, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+       [1030] = {252, 8, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+       [1031] = {252, 9, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+       [1032] = {253, 0, "DEV_RTI1_VBUSP_CLK", "Input clock"},
+       [1033] = {253, 1, "DEV_RTI1_RTI_CLK", "Input muxed clock"},
+       [1034] = {253, 2, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+       [1035] = {253, 3, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+       [1036] = {253, 4, "DEV_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+       [1037] = {253, 5, "DEV_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+       [1038] = {253, 6, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+       [1039] = {253, 7, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+       [1040] = {253, 8, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+       [1041] = {253, 9, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+       [1042] = {258, 0, "DEV_RTI28_VBUSP_CLK", "Input clock"},
+       [1043] = {258, 1, "DEV_RTI28_RTI_CLK", "Input muxed clock"},
+       [1044] = {258, 2, "DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+       [1045] = {258, 3, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+       [1046] = {258, 4, "DEV_RTI28_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+       [1047] = {258, 5, "DEV_RTI28_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+       [1048] = {258, 6, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+       [1049] = {258, 7, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+       [1050] = {258, 8, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+       [1051] = {258, 9, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+       [1052] = {259, 0, "DEV_RTI29_VBUSP_CLK", "Input clock"},
+       [1053] = {259, 1, "DEV_RTI29_RTI_CLK", "Input muxed clock"},
+       [1054] = {259, 2, "DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+       [1055] = {259, 3, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+       [1056] = {259, 4, "DEV_RTI29_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+       [1057] = {259, 5, "DEV_RTI29_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+       [1058] = {259, 6, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+       [1059] = {259, 7, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+       [1060] = {259, 8, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+       [1061] = {259, 9, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+       [1062] = {292, 1, "DEV_SERDES_10G1_IP3_LN1_TXFCLK", "Output clock"},
+       [1063] = {292, 3, "DEV_SERDES_10G1_IP2_LN2_REFCLK", "Output clock"},
+       [1064] = {292, 4, "DEV_SERDES_10G1_IP1_LN0_TXMCLK", "Output clock"},
+       [1065] = {292, 6, "DEV_SERDES_10G1_IP3_LN3_RXCLK", "Output clock"},
+       [1066] = {292, 9, "DEV_SERDES_10G1_IP2_LN2_RXCLK", "Output clock"},
+       [1067] = {292, 10, "DEV_SERDES_10G1_IP1_LN0_TXFCLK", "Output clock"},
+       [1068] = {292, 11, "DEV_SERDES_10G1_CLK", "Input clock"},
+       [1069] = {292, 13, "DEV_SERDES_10G1_IP1_LN3_RXCLK", "Output clock"},
+       [1070] = {292, 14, "DEV_SERDES_10G1_IP1_LN1_TXMCLK", "Output clock"},
+       [1071] = {292, 15, "DEV_SERDES_10G1_IP2_LN0_TXFCLK", "Output clock"},
+       [1072] = {292, 16, "DEV_SERDES_10G1_IP2_LN2_TXMCLK", "Output clock"},
+       [1073] = {292, 19, "DEV_SERDES_10G1_IP3_LN1_TXCLK", "Input clock"},
+       [1074] = {292, 21, "DEV_SERDES_10G1_IP2_LN3_RXFCLK", "Output clock"},
+       [1075] = {292, 22, "DEV_SERDES_10G1_IP1_LN2_TXCLK", "Input clock"},
+       [1076] = {292, 24, "DEV_SERDES_10G1_IP2_LN1_RXCLK", "Output clock"},
+       [1077] = {292, 25, "DEV_SERDES_10G1_IP2_LN1_TXCLK", "Input clock"},
+       [1078] = {292, 29, "DEV_SERDES_10G1_IP1_LN2_TXMCLK", "Output clock"},
+       [1079] = {292, 32, "DEV_SERDES_10G1_IP2_LN1_TXMCLK", "Output clock"},
+       [1080] = {292, 33, "DEV_SERDES_10G1_IP2_LN1_TXFCLK", "Output clock"},
+       [1081] = {292, 34, "DEV_SERDES_10G1_IP1_LN1_TXFCLK", "Output clock"},
+       [1082] = {292, 38, "DEV_SERDES_10G1_IP1_LN2_RXCLK", "Output clock"},
+       [1083] = {292, 40, "DEV_SERDES_10G1_IP2_LN1_REFCLK", "Output clock"},
+       [1084] = {292, 41, "DEV_SERDES_10G1_IP2_LN0_TXMCLK", "Output clock"},
+       [1085] = {292, 42, "DEV_SERDES_10G1_IP2_LN3_RXCLK", "Output clock"},
+       [1086] = {292, 43, "DEV_SERDES_10G1_IP2_LN2_TXCLK", "Input clock"},
+       [1087] = {292, 44, "DEV_SERDES_10G1_IP2_LN2_RXFCLK", "Output clock"},
+       [1088] = {292, 45, "DEV_SERDES_10G1_IP1_LN1_RXFCLK", "Output clock"},
+       [1089] = {292, 49, "DEV_SERDES_10G1_IP1_LN0_RXCLK", "Output clock"},
+       [1090] = {292, 52, "DEV_SERDES_10G1_IP1_LN1_RXCLK", "Output clock"},
+       [1091] = {292, 55, "DEV_SERDES_10G1_IP1_LN0_RXFCLK", "Output clock"},
+       [1092] = {292, 56, "DEV_SERDES_10G1_IP3_LN3_TXCLK", "Input clock"},
+       [1093] = {292, 59, "DEV_SERDES_10G1_IP2_LN3_REFCLK", "Output clock"},
+       [1094] = {292, 61, "DEV_SERDES_10G1_IP2_LN0_TXCLK", "Input clock"},
+       [1095] = {292, 62, "DEV_SERDES_10G1_IP2_LN3_TXMCLK", "Output clock"},
+       [1096] = {292, 63, "DEV_SERDES_10G1_IP1_LN1_REFCLK", "Output clock"},
+       [1097] = {292, 65, "DEV_SERDES_10G1_IP1_LN3_TXCLK", "Input clock"},
+       [1098] = {292, 66, "DEV_SERDES_10G1_IP3_LN1_TXMCLK", "Output clock"},
+       [1099] = {292, 67, "DEV_SERDES_10G1_IP2_LN2_TXFCLK", "Output clock"},
+       [1100] = {292, 73, "DEV_SERDES_10G1_IP3_LN1_RXCLK", "Output clock"},
+       [1101] = {292, 74, "DEV_SERDES_10G1_IP3_LN1_REFCLK", "Output clock"},
+       [1102] = {292, 75, "DEV_SERDES_10G1_IP1_LN3_REFCLK", "Output clock"},
+       [1103] = {292, 77, "DEV_SERDES_10G1_IP1_LN0_REFCLK", "Output clock"},
+       [1104] = {292, 80, "DEV_SERDES_10G1_IP1_LN2_REFCLK", "Output clock"},
+       [1105] = {292, 81, "DEV_SERDES_10G1_IP2_LN0_REFCLK", "Output clock"},
+       [1106] = {292, 82, "DEV_SERDES_10G1_IP2_LN0_RXCLK", "Output clock"},
+       [1107] = {292, 85, "DEV_SERDES_10G1_CORE_REF_CLK", "Input muxed clock"},
+       [1108] = {292, 86, "DEV_SERDES_10G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK"},
+       [1109] = {292, 87, "DEV_SERDES_10G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK"},
+       [1110] = {292, 88, "DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK"},
+       [1111] = {292, 89, "DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK"},
+       [1112] = {292, 92, "DEV_SERDES_10G1_IP1_LN3_TXMCLK", "Output clock"},
+       [1113] = {292, 95, "DEV_SERDES_10G1_IP2_LN3_TXCLK", "Input clock"},
+       [1114] = {292, 96, "DEV_SERDES_10G1_IP3_LN3_RXFCLK", "Output clock"},
+       [1115] = {292, 98, "DEV_SERDES_10G1_IP3_LN3_REFCLK", "Output clock"},
+       [1116] = {292, 100, "DEV_SERDES_10G1_IP2_LN1_RXFCLK", "Output clock"},
+       [1117] = {292, 102, "DEV_SERDES_10G1_IP3_LN1_RXFCLK", "Output clock"},
+       [1118] = {292, 104, "DEV_SERDES_10G1_IP1_LN1_TXCLK", "Input clock"},
+       [1119] = {292, 107, "DEV_SERDES_10G1_IP3_LN3_TXFCLK", "Output clock"},
+       [1120] = {292, 108, "DEV_SERDES_10G1_IP1_LN3_TXFCLK", "Output clock"},
+       [1121] = {292, 109, "DEV_SERDES_10G1_IP2_LN3_TXFCLK", "Output clock"},
+       [1122] = {292, 111, "DEV_SERDES_10G1_IP1_LN0_TXCLK", "Input clock"},
+       [1123] = {292, 112, "DEV_SERDES_10G1_IP2_LN0_RXFCLK", "Output clock"},
+       [1124] = {292, 113, "DEV_SERDES_10G1_IP1_LN2_RXFCLK", "Output clock"},
+       [1125] = {292, 118, "DEV_SERDES_10G1_IP1_LN2_TXFCLK", "Output clock"},
+       [1126] = {292, 124, "DEV_SERDES_10G1_IP1_LN3_RXFCLK", "Output clock"},
+       [1127] = {292, 126, "DEV_SERDES_10G1_IP3_LN3_TXMCLK", "Output clock"},
+       [1128] = {29, 0, "DEV_STM0_CORE_CLK", "Input clock"},
+       [1129] = {29, 1, "DEV_STM0_VBUSP_CLK", "Input clock"},
+       [1130] = {29, 2, "DEV_STM0_ATB_CLK", "Input clock"},
+       [1131] = {49, 0, "DEV_TIMER0_TIMER_HCLK_CLK", "Input clock"},
+       [1132] = {49, 1, "DEV_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1133] = {49, 2, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+       [1134] = {49, 3, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+       [1135] = {49, 4, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+       [1136] = {49, 5, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+       [1137] = {49, 6, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+       [1138] = {49, 7, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+       [1139] = {49, 8, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+       [1140] = {49, 9, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+       [1141] = {49, 10, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+       [1142] = {49, 11, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+       [1143] = {49, 12, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+       [1144] = {49, 13, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+       [1145] = {49, 14, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+       [1146] = {49, 15, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+       [1147] = {49, 16, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+       [1148] = {49, 17, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+       [1149] = {49, 26, "DEV_TIMER0_TIMER_PWM", "Output clock"},
+       [1150] = {50, 0, "DEV_TIMER1_TIMER_HCLK_CLK", "Input clock"},
+       [1151] = {50, 1, "DEV_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1152] = {50, 2, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
+       [1153] = {50, 3, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
+       [1154] = {60, 0, "DEV_TIMER10_TIMER_HCLK_CLK", "Input clock"},
+       [1155] = {60, 1, "DEV_TIMER10_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1156] = {60, 2, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+       [1157] = {60, 3, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+       [1158] = {60, 4, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+       [1159] = {60, 5, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+       [1160] = {60, 6, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+       [1161] = {60, 7, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+       [1162] = {60, 8, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+       [1163] = {60, 9, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+       [1164] = {60, 10, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+       [1165] = {60, 11, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+       [1166] = {60, 12, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+       [1167] = {60, 13, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+       [1168] = {60, 14, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+       [1169] = {60, 15, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+       [1170] = {60, 16, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+       [1171] = {60, 17, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+       [1172] = {60, 26, "DEV_TIMER10_TIMER_PWM", "Output clock"},
+       [1173] = {62, 0, "DEV_TIMER11_TIMER_HCLK_CLK", "Input clock"},
+       [1174] = {62, 1, "DEV_TIMER11_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1175] = {62, 2, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
+       [1176] = {62, 3, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
+       [1177] = {63, 0, "DEV_TIMER12_TIMER_HCLK_CLK", "Input clock"},
+       [1178] = {63, 1, "DEV_TIMER12_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1179] = {63, 2, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+       [1180] = {63, 3, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+       [1181] = {63, 4, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+       [1182] = {63, 5, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+       [1183] = {63, 6, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+       [1184] = {63, 7, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+       [1185] = {63, 8, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+       [1186] = {63, 9, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+       [1187] = {63, 10, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+       [1188] = {63, 11, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+       [1189] = {63, 12, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+       [1190] = {63, 13, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+       [1191] = {63, 14, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+       [1192] = {63, 15, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+       [1193] = {63, 16, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+       [1194] = {63, 17, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+       [1195] = {63, 26, "DEV_TIMER12_TIMER_PWM", "Output clock"},
+       [1196] = {64, 0, "DEV_TIMER13_TIMER_HCLK_CLK", "Input clock"},
+       [1197] = {64, 1, "DEV_TIMER13_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1198] = {64, 2, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"},
+       [1199] = {64, 3, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"},
+       [1200] = {65, 0, "DEV_TIMER14_TIMER_HCLK_CLK", "Input clock"},
+       [1201] = {65, 1, "DEV_TIMER14_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1202] = {65, 2, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+       [1203] = {65, 3, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+       [1204] = {65, 4, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+       [1205] = {65, 5, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+       [1206] = {65, 6, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+       [1207] = {65, 7, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+       [1208] = {65, 8, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+       [1209] = {65, 9, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+       [1210] = {65, 10, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+       [1211] = {65, 11, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+       [1212] = {65, 12, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+       [1213] = {65, 13, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+       [1214] = {65, 14, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+       [1215] = {65, 15, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+       [1216] = {65, 16, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+       [1217] = {65, 17, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+       [1218] = {65, 26, "DEV_TIMER14_TIMER_PWM", "Output clock"},
+       [1219] = {66, 0, "DEV_TIMER15_TIMER_HCLK_CLK", "Input clock"},
+       [1220] = {66, 1, "DEV_TIMER15_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1221] = {66, 2, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"},
+       [1222] = {66, 3, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"},
+       [1223] = {67, 0, "DEV_TIMER16_TIMER_HCLK_CLK", "Input clock"},
+       [1224] = {67, 1, "DEV_TIMER16_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1225] = {67, 2, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+       [1226] = {67, 3, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+       [1227] = {67, 4, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+       [1228] = {67, 5, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+       [1229] = {67, 6, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+       [1230] = {67, 7, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+       [1231] = {67, 8, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+       [1232] = {67, 9, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+       [1233] = {67, 10, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+       [1234] = {67, 11, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+       [1235] = {67, 12, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+       [1236] = {67, 13, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+       [1237] = {67, 14, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+       [1238] = {67, 15, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+       [1239] = {67, 16, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+       [1240] = {67, 17, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+       [1241] = {67, 26, "DEV_TIMER16_TIMER_PWM", "Output clock"},
+       [1242] = {68, 0, "DEV_TIMER17_TIMER_HCLK_CLK", "Input clock"},
+       [1243] = {68, 1, "DEV_TIMER17_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1244] = {68, 2, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT17", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"},
+       [1245] = {68, 3, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"},
+       [1246] = {69, 0, "DEV_TIMER18_TIMER_HCLK_CLK", "Input clock"},
+       [1247] = {69, 1, "DEV_TIMER18_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1248] = {69, 2, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+       [1249] = {69, 3, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+       [1250] = {69, 4, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+       [1251] = {69, 5, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+       [1252] = {69, 6, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+       [1253] = {69, 7, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+       [1254] = {69, 8, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+       [1255] = {69, 9, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+       [1256] = {69, 10, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+       [1257] = {69, 11, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+       [1258] = {69, 12, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+       [1259] = {69, 13, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+       [1260] = {69, 14, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+       [1261] = {69, 15, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+       [1262] = {69, 16, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+       [1263] = {69, 17, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+       [1264] = {69, 26, "DEV_TIMER18_TIMER_PWM", "Output clock"},
+       [1265] = {70, 0, "DEV_TIMER19_TIMER_HCLK_CLK", "Input clock"},
+       [1266] = {70, 1, "DEV_TIMER19_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1267] = {70, 2, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT19", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"},
+       [1268] = {70, 3, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"},
+       [1269] = {51, 0, "DEV_TIMER2_TIMER_HCLK_CLK", "Input clock"},
+       [1270] = {51, 1, "DEV_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1271] = {51, 2, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+       [1272] = {51, 3, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+       [1273] = {51, 4, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+       [1274] = {51, 5, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+       [1275] = {51, 6, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+       [1276] = {51, 7, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+       [1277] = {51, 8, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+       [1278] = {51, 9, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+       [1279] = {51, 10, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+       [1280] = {51, 11, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+       [1281] = {51, 12, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+       [1282] = {51, 13, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+       [1283] = {51, 14, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+       [1284] = {51, 15, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+       [1285] = {51, 16, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+       [1286] = {51, 17, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+       [1287] = {51, 26, "DEV_TIMER2_TIMER_PWM", "Output clock"},
+       [1288] = {52, 0, "DEV_TIMER3_TIMER_HCLK_CLK", "Input clock"},
+       [1289] = {52, 1, "DEV_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1290] = {52, 2, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
+       [1291] = {52, 3, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
+       [1292] = {53, 0, "DEV_TIMER4_TIMER_HCLK_CLK", "Input clock"},
+       [1293] = {53, 1, "DEV_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1294] = {53, 2, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+       [1295] = {53, 3, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+       [1296] = {53, 4, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+       [1297] = {53, 5, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+       [1298] = {53, 6, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+       [1299] = {53, 7, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+       [1300] = {53, 8, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+       [1301] = {53, 9, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+       [1302] = {53, 10, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+       [1303] = {53, 11, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+       [1304] = {53, 12, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+       [1305] = {53, 13, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+       [1306] = {53, 14, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+       [1307] = {53, 15, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+       [1308] = {53, 16, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+       [1309] = {53, 17, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+       [1310] = {53, 26, "DEV_TIMER4_TIMER_PWM", "Output clock"},
+       [1311] = {54, 0, "DEV_TIMER5_TIMER_HCLK_CLK", "Input clock"},
+       [1312] = {54, 1, "DEV_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1313] = {54, 2, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
+       [1314] = {54, 3, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
+       [1315] = {55, 0, "DEV_TIMER6_TIMER_HCLK_CLK", "Input clock"},
+       [1316] = {55, 1, "DEV_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1317] = {55, 2, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+       [1318] = {55, 3, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+       [1319] = {55, 4, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+       [1320] = {55, 5, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+       [1321] = {55, 6, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+       [1322] = {55, 7, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+       [1323] = {55, 8, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+       [1324] = {55, 9, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+       [1325] = {55, 10, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+       [1326] = {55, 11, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+       [1327] = {55, 12, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+       [1328] = {55, 13, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+       [1329] = {55, 14, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+       [1330] = {55, 15, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+       [1331] = {55, 16, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+       [1332] = {55, 17, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+       [1333] = {55, 26, "DEV_TIMER6_TIMER_PWM", "Output clock"},
+       [1334] = {57, 0, "DEV_TIMER7_TIMER_HCLK_CLK", "Input clock"},
+       [1335] = {57, 1, "DEV_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1336] = {57, 2, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
+       [1337] = {57, 3, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
+       [1338] = {58, 0, "DEV_TIMER8_TIMER_HCLK_CLK", "Input clock"},
+       [1339] = {58, 1, "DEV_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1340] = {58, 2, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+       [1341] = {58, 3, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+       [1342] = {58, 4, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+       [1343] = {58, 5, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+       [1344] = {58, 6, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+       [1345] = {58, 7, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+       [1346] = {58, 8, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+       [1347] = {58, 9, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+       [1348] = {58, 10, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+       [1349] = {58, 11, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+       [1350] = {58, 12, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+       [1351] = {58, 13, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+       [1352] = {58, 14, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+       [1353] = {58, 15, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+       [1354] = {58, 16, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+       [1355] = {58, 17, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+       [1356] = {58, 26, "DEV_TIMER8_TIMER_PWM", "Output clock"},
+       [1357] = {59, 0, "DEV_TIMER9_TIMER_HCLK_CLK", "Input clock"},
+       [1358] = {59, 1, "DEV_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1359] = {59, 2, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
+       [1360] = {59, 3, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
+       [1361] = {146, 2, "DEV_UART0_FCLK_CLK", "Input clock"},
+       [1362] = {146, 3, "DEV_UART0_VBUSP_CLK", "Input clock"},
+       [1363] = {278, 2, "DEV_UART1_FCLK_CLK", "Input clock"},
+       [1364] = {278, 3, "DEV_UART1_VBUSP_CLK", "Input clock"},
+       [1365] = {279, 2, "DEV_UART2_FCLK_CLK", "Input clock"},
+       [1366] = {279, 3, "DEV_UART2_VBUSP_CLK", "Input clock"},
+       [1367] = {280, 2, "DEV_UART3_FCLK_CLK", "Input clock"},
+       [1368] = {280, 3, "DEV_UART3_VBUSP_CLK", "Input clock"},
+       [1369] = {281, 2, "DEV_UART4_FCLK_CLK", "Input clock"},
+       [1370] = {281, 3, "DEV_UART4_VBUSP_CLK", "Input clock"},
+       [1371] = {282, 2, "DEV_UART5_FCLK_CLK", "Input clock"},
+       [1372] = {282, 3, "DEV_UART5_VBUSP_CLK", "Input clock"},
+       [1373] = {283, 2, "DEV_UART6_FCLK_CLK", "Input clock"},
+       [1374] = {283, 3, "DEV_UART6_VBUSP_CLK", "Input clock"},
+       [1375] = {284, 2, "DEV_UART7_FCLK_CLK", "Input clock"},
+       [1376] = {284, 3, "DEV_UART7_VBUSP_CLK", "Input clock"},
+       [1377] = {285, 2, "DEV_UART8_FCLK_CLK", "Input clock"},
+       [1378] = {285, 3, "DEV_UART8_VBUSP_CLK", "Input clock"},
+       [1379] = {286, 2, "DEV_UART9_FCLK_CLK", "Input clock"},
+       [1380] = {286, 3, "DEV_UART9_VBUSP_CLK", "Input clock"},
+       [1381] = {288, 0, "DEV_USB0_PIPE_REFCLK", "Input muxed clock"},
+       [1382] = {288, 1, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"},
+       [1383] = {288, 2, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP3_LN3_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"},
+       [1384] = {288, 3, "DEV_USB0_CLK_LPM_CLK", "Input clock"},
+       [1385] = {288, 4, "DEV_USB0_BUF_CLK", "Input clock"},
+       [1386] = {288, 5, "DEV_USB0_PIPE_TXFCLK", "Input clock"},
+       [1387] = {288, 6, "DEV_USB0_USB2_APB_PCLK_CLK", "Input clock"},
+       [1388] = {288, 7, "DEV_USB0_PIPE_RXCLK", "Input clock"},
+       [1389] = {288, 8, "DEV_USB0_PIPE_TXMCLK", "Input clock"},
+       [1390] = {288, 9, "DEV_USB0_PIPE_RXFCLK", "Input clock"},
+       [1391] = {288, 11, "DEV_USB0_PIPE_TXCLK", "Output clock"},
+       [1392] = {288, 12, "DEV_USB0_USB2_REFCLOCK_CLK", "Input muxed clock"},
+       [1393] = {288, 13, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"},
+       [1394] = {288, 14, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"},
+       [1395] = {288, 15, "DEV_USB0_PCLK_CLK", "Input clock"},
+       [1396] = {288, 17, "DEV_USB0_ACLK_CLK", "Input clock"},
+       [1397] = {145, 0, "DEV_WKUP_DDPA0_DDPA_CLK", "Input clock"},
+       [1398] = {99, 0, "DEV_WKUP_ESM0_CLK", "Input clock"},
+       [1399] = {113, 0, "DEV_WKUP_GPIO0_MMR_CLK", "Input muxed clock"},
+       [1400] = {113, 1, "DEV_WKUP_GPIO0_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_WKUP_GPIO0_MMR_CLK"},
+       [1401] = {113, 2, "DEV_WKUP_GPIO0_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6_DUP0", "Parent input clock option to DEV_WKUP_GPIO0_MMR_CLK"},
+       [1402] = {113, 3, "DEV_WKUP_GPIO0_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_WKUP_GPIO0_MMR_CLK"},
+       [1403] = {113, 4, "DEV_WKUP_GPIO0_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_WKUP_GPIO0_MMR_CLK"},
+       [1404] = {114, 0, "DEV_WKUP_GPIO1_MMR_CLK", "Input muxed clock"},
+       [1405] = {114, 1, "DEV_WKUP_GPIO1_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_WKUP_GPIO1_MMR_CLK"},
+       [1406] = {114, 2, "DEV_WKUP_GPIO1_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6_DUP0", "Parent input clock option to DEV_WKUP_GPIO1_MMR_CLK"},
+       [1407] = {114, 3, "DEV_WKUP_GPIO1_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_WKUP_GPIO1_MMR_CLK"},
+       [1408] = {114, 4, "DEV_WKUP_GPIO1_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_WKUP_GPIO1_MMR_CLK"},
+       [1409] = {197, 0, "DEV_WKUP_I2C0_PISCL", "Input clock"},
+       [1410] = {197, 1, "DEV_WKUP_I2C0_PISYS_CLK", "Input clock"},
+       [1411] = {197, 2, "DEV_WKUP_I2C0_CLK", "Input clock"},
+       [1412] = {197, 3, "DEV_WKUP_I2C0_PORSCL", "Output clock"},
+       [1413] = {132, 0, "DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK", "Input clock"},
+       [1414] = {138, 0, "DEV_WKUP_PSC0_SLOW_CLK", "Input clock"},
+       [1415] = {138, 1, "DEV_WKUP_PSC0_CLK", "Input clock"},
+       [1416] = {287, 2, "DEV_WKUP_UART0_FCLK_CLK", "Input muxed clock"},
+       [1417] = {287, 3, "DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_OUT0", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"},
+       [1418] = {287, 4, "DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"},
+       [1419] = {287, 5, "DEV_WKUP_UART0_VBUSP_CLK", "Input clock"},
+       [1420] = {154, 0, "DEV_WKUP_VTM0_FIX_REF2_CLK", "Input clock"},
+       [1421] = {154, 1, "DEV_WKUP_VTM0_VBUSP_CLK", "Input clock"},
+       [1422] = {154, 2, "DEV_WKUP_VTM0_FIX_REF_CLK", "Input clock"},
+       [1423] = {40, 0, "DEV_WKUP_WAKEUP0_PLL_CTRL_WKUP_CLK24_CLK", "Input clock"},
+       [1424] = {40, 1, "DEV_WKUP_WAKEUP0_WKUP_RCOSC_32K_CLK", "Output clock"},
+       [1425] = {40, 2, "DEV_WKUP_WAKEUP0_WKUP_RCOSC_12P5M_CLK", "Output clock"},
+};
diff --git a/soc/j7200/j7200_clocks_info.h b/soc/j7200/j7200_clocks_info.h
new file mode 100644 (file)
index 0000000..e9e5ad2
--- /dev/null
@@ -0,0 +1,42 @@
+/*
+ * J7200 Clocks Info
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __J7200_CLOCKS_INFO_H
+#define __J7200_CLOCKS_INFO_H
+
+#define J7200_MAX_CLOCKS       1426
+
+extern struct ti_sci_clocks_info j7200_clocks_info[];
+
+#endif /* __J7200_CLOCKS_INFO_H */