soc: am65x: Add the missing clock ids for each device
authorLokesh Vutla <lokeshvutla@ti.com>
Tue, 14 Apr 2020 05:41:22 +0000 (11:11 +0530)
committerLokesh Vutla <lokeshvutla@ti.com>
Tue, 14 Apr 2020 05:45:36 +0000 (11:15 +0530)
First clock for each device is missed by auto generation. Add the first
clock id and update the clock names to latest sysfw documentation.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
soc/am65x/am65x_clocks_info.c
soc/am65x/am65x_clocks_info.h

index cf45a9c210012605664e2a788a0c375b88641b55..b169e9f3ffe9893bd515c8f883b2ebbbaa316d04 100644 (file)
 #include <socinfo.h>
 
 struct ti_sci_clocks_info am65x_clocks_info[] = {
-       [0] = {157, 1, "DEV_BOARD0_BUS_SCL2_IN", "Input clock"},
-       [1] = {157, 2, "DEV_BOARD0_BUS_SCL1_IN", "Input clock"},
-       [2] = {157, 3, "DEV_BOARD0_BUS_SCL0_IN", "Input clock"},
-       [3] = {157, 4, "DEV_BOARD0_BUS_PRG2_RGMII2_TCLK_IN", "Input clock"},
-       [4] = {157, 5, "DEV_BOARD0_BUS_MCU_OSPI1CLK_IN", "Input clock"},
-       [5] = {157, 6, "DEV_BOARD0_BUS_PRG1_RGMII1_TCLK_IN", "Input clock"},
-       [6] = {157, 7, "DEV_BOARD0_BUS_REFCLK1P_IN", "Input muxed clock"},
-       [7] = {157, 8, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
-       [8] = {157, 9, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
-       [9] = {157, 10, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
-       [10] = {157, 11, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
-       [11] = {157, 12, "DEV_BOARD0_BUS_MCU_OSPI1LBCLKO_IN", "Input clock"},
-       [12] = {157, 13, "DEV_BOARD0_BUS_MCU_OBSCLK_IN", "Input clock"},
-       [13] = {157, 14, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [14] = {157, 15, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [15] = {157, 16, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [16] = {157, 17, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [17] = {157, 18, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [18] = {157, 19, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [19] = {157, 20, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [20] = {157, 21, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [21] = {157, 22, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [22] = {157, 23, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [23] = {157, 24, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [24] = {157, 25, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [25] = {157, 26, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [26] = {157, 27, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [27] = {157, 28, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [28] = {157, 29, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [29] = {157, 30, "DEV_BOARD0_BUS_PRG2_RGMII1_TCLK_IN", "Input clock"},
-       [30] = {157, 31, "DEV_BOARD0_BUS_REFCLK1M_IN", "Input muxed clock"},
-       [31] = {157, 32, "DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M_IN"},
-       [32] = {157, 33, "DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M_IN"},
-       [33] = {157, 34, "DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M_IN"},
-       [34] = {157, 35, "DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M_IN"},
-       [35] = {157, 36, "DEV_BOARD0_BUS_OBSCLK_IN", "Input clock"},
-       [36] = {157, 37, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [37] = {157, 38, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [38] = {157, 39, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [39] = {157, 40, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [40] = {157, 41, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [41] = {157, 42, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [42] = {157, 43, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_4_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [43] = {157, 44, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_6_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [44] = {157, 45, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [45] = {157, 46, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [46] = {157, 47, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [47] = {157, 48, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_7_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [48] = {157, 49, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [49] = {157, 50, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [50] = {157, 51, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [51] = {157, 52, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [52] = {157, 53, "DEV_BOARD0_BUS_PRG0_RGMII1_TCLK_IN", "Input clock"},
-       [53] = {157, 54, "DEV_BOARD0_BUS_MCU_OSPI0CLK_IN", "Input clock"},
-       [54] = {157, 55, "DEV_BOARD0_BUS_DSS0PCLK_IN", "Input clock"},
-       [55] = {157, 56, "DEV_BOARD0_BUS_PRG0_RGMII2_TCLK_IN", "Input clock"},
-       [56] = {157, 57, "DEV_BOARD0_BUS_WKUP_SCL0_IN", "Input clock"},
-       [57] = {157, 58, "DEV_BOARD0_BUS_REFCLK0P_IN", "Input muxed clock"},
-       [58] = {157, 59, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
-       [59] = {157, 60, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
-       [60] = {157, 61, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
-       [61] = {157, 62, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
-       [62] = {157, 63, "DEV_BOARD0_BUS_REFCLK0M_IN", "Input muxed clock"},
-       [63] = {157, 64, "DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M_IN"},
-       [64] = {157, 65, "DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M_IN"},
-       [65] = {157, 66, "DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M_IN"},
-       [66] = {157, 67, "DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M_IN"},
-       [67] = {157, 68, "DEV_BOARD0_BUS_MCU_OSPI0LBCLKO_IN", "Input clock"},
-       [68] = {157, 69, "DEV_BOARD0_BUS_MCU_CLKOUT_IN", "Input muxed clock"},
-       [69] = {157, 70, "DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN"},
-       [70] = {157, 71, "DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK10", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN"},
-       [71] = {157, 72, "DEV_BOARD0_BUS_MCU_SCL0_IN", "Input clock"},
-       [72] = {157, 73, "DEV_BOARD0_BUS_SYSCLKOUT_IN", "Input clock"},
-       [73] = {157, 74, "DEV_BOARD0_BUS_MCU_SYSCLKOUT_IN", "Input clock"},
-       [74] = {157, 75, "DEV_BOARD0_BUS_PRG1_RGMII1_RCLK_OUT", "Output clock"},
-       [75] = {157, 76, "DEV_BOARD0_BUS_PRG1_RGMII2_RCLK_OUT", "Output clock"},
-       [76] = {157, 77, "DEV_BOARD0_BUS_GPMCCLK_OUT", "Output clock"},
-       [77] = {157, 78, "DEV_BOARD0_BUS_MCASP2AHCLKX_OUT", "Output clock"},
-       [78] = {157, 79, "DEV_BOARD0_BUS_MCASP2AHCLKR_OUT", "Output clock"},
-       [79] = {157, 80, "DEV_BOARD0_BUS_PRG2_RGMII2_RCLK_OUT", "Output clock"},
-       [80] = {157, 81, "DEV_BOARD0_BUS_CPTS_RFT_CLK_OUT", "Output clock"},
-       [81] = {157, 82, "DEV_BOARD0_BUS_MCASP0ACLKR_OUT", "Output clock"},
-       [82] = {157, 83, "DEV_BOARD0_BUS_MCASP0ACLKX_OUT", "Output clock"},
-       [83] = {157, 84, "DEV_BOARD0_BUS_EXT_REFCLK1_OUT", "Output clock"},
-       [84] = {157, 85, "DEV_BOARD0_BUS_PRG0_RGMII2_RCLK_OUT", "Output clock"},
-       [85] = {157, 86, "DEV_BOARD0_BUS_MCU_OSPI0DQS_OUT", "Output clock"},
-       [86] = {157, 87, "DEV_BOARD0_BUS_USB0REFCLKP_OUT", "Output clock"},
-       [87] = {157, 88, "DEV_BOARD0_BUS_DSS0EXTPCLKIN_OUT", "Output clock"},
-       [88] = {157, 89, "DEV_BOARD0_BUS_SPI1CLK_OUT", "Output clock"},
-       [89] = {157, 90, "DEV_BOARD0_BUS_MCASP2ACLKR_OUT", "Output clock"},
-       [90] = {157, 91, "DEV_BOARD0_BUS_MCASP1ACLKX_OUT", "Output clock"},
-       [91] = {157, 92, "DEV_BOARD0_BUS_MCASP1ACLKR_OUT", "Output clock"},
-       [92] = {157, 93, "DEV_BOARD0_BUS_MCASP2ACLKX_OUT", "Output clock"},
-       [93] = {157, 94, "DEV_BOARD0_BUS_MCU_RMII1_REFCLK_OUT", "Output clock"},
-       [94] = {157, 95, "DEV_BOARD0_BUS_MCU_CPTS_RFT_CLK_OUT", "Output clock"},
-       [95] = {157, 96, "DEV_BOARD0_BUS_MCU_RGMII1_TCLK_OUT", "Output clock"},
-       [96] = {157, 97, "DEV_BOARD0_BUS_MCU_SPI0CLK_OUT", "Output clock"},
-       [97] = {157, 98, "DEV_BOARD0_BUS_MCU_SPI1CLK_OUT", "Output clock"},
-       [98] = {157, 99, "DEV_BOARD0_BUS_PRG0_RGMII1_RCLK_OUT", "Output clock"},
-       [99] = {157, 100, "DEV_BOARD0_BUS_SPI2CLK_OUT", "Output clock"},
-       [100] = {157, 101, "DEV_BOARD0_BUS_WKUP_TCK_OUT", "Output clock"},
-       [101] = {157, 102, "DEV_BOARD0_BUS_SPI3CLK_OUT", "Output clock"},
-       [102] = {157, 103, "DEV_BOARD0_BUS_USB0REFCLKM_OUT", "Output clock"},
-       [103] = {157, 104, "DEV_BOARD0_BUS_MCU_RGMII1_RCLK_OUT", "Output clock"},
-       [104] = {157, 105, "DEV_BOARD0_BUS_MCASP0AHCLKR_OUT", "Output clock"},
-       [105] = {157, 106, "DEV_BOARD0_BUS_MCU_EXT_REFCLK0_OUT", "Output clock"},
-       [106] = {157, 107, "DEV_BOARD0_BUS_MCASP0AHCLKX_OUT", "Output clock"},
-       [107] = {157, 108, "DEV_BOARD0_BUS_CCDC0_PCLK_OUT", "Output clock"},
-       [108] = {157, 109, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"},
-       [109] = {157, 110, "DEV_BOARD0_BUS_MCU_OSPI1DQS_OUT", "Output clock"},
-       [110] = {157, 111, "DEV_BOARD0_BUS_MCASP1AHCLKX_OUT", "Output clock"},
-       [111] = {157, 112, "DEV_BOARD0_BUS_PCIE1REFCLKM_OUT", "Output clock"},
-       [112] = {157, 113, "DEV_BOARD0_BUS_MCASP1AHCLKR_OUT", "Output clock"},
-       [113] = {157, 114, "DEV_BOARD0_BUS_PCIE1REFCLKP_OUT", "Output clock"},
-       [114] = {157, 115, "DEV_BOARD0_BUS_PRG2_RGMII1_RCLK_OUT", "Output clock"},
-       [115] = {157, 116, "DEV_BOARD0_BUS_SPI0CLK_OUT", "Output clock"},
-       [116] = {157, 117, "DEV_BOARD0_BUS_MCU_HYPERBUS_CLK_IN", "Input clock"},
-       [117] = {157, 118, "DEV_BOARD0_BUS_MCU_HYPERBUS_NCLK_IN", "Input clock"},
-       [118] = {2, 1, "DEV_CAL0_BUS_CP_C_CLK", "Input clock"},
-       [119] = {82, 1, "DEV_CBASS0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
-       [120] = {83, 1, "DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
-       [121] = {84, 1, "DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
-       [122] = {85, 1, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
-       [123] = {85, 2, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
-       [124] = {85, 3, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
-       [125] = {85, 4, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
-       [126] = {85, 5, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
-       [127] = {85, 6, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
-       [128] = {85, 7, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
-       [129] = {85, 8, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
-       [130] = {85, 9, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
-       [131] = {85, 10, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
-       [132] = {66, 1, "DEV_CCDEBUGSS0_BUS_ATB0_CLK", "Input clock"},
-       [133] = {66, 2, "DEV_CCDEBUGSS0_BUS_SYS_CLK", "Input clock"},
-       [134] = {66, 3, "DEV_CCDEBUGSS0_BUS_DBG_CLK", "Input clock"},
-       [135] = {66, 4, "DEV_CCDEBUGSS0_BUS_CFG_CLK", "Input clock"},
-       [136] = {196, 1, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_DBG_CLK", "Input clock"},
-       [137] = {196, 2, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_MSMC_CLK", "Input clock"},
-       [138] = {196, 3, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_CFG_CLK", "Input clock"},
-       [139] = {196, 4, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_GIC_CLK", "Input clock"},
-       [140] = {213, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_PROBE_CLK", "Input clock"},
-       [141] = {214, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_PROBE_CLK", "Input clock"},
-       [142] = {211, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_PROBE_CLK", "Input clock"},
-       [143] = {212, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_PROBE_CLK", "Input clock"},
-       [144] = {209, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_PROBE_CLK", "Input clock"},
-       [145] = {206, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_PROBE_CLK", "Input clock"},
-       [146] = {208, 1, "DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_PROBE_CLK", "Input clock"},
-       [147] = {215, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_PROBE_CLK", "Input clock"},
-       [148] = {207, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_PROBE_CLK", "Input clock"},
-       [149] = {210, 1, "DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_PROBE_CLK", "Input clock"},
-       [150] = {9, 1, "DEV_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [151] = {9, 2, "DEV_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [152] = {9, 3, "DEV_DCC0_BUS_VBUS_CLK", "Input clock"},
-       [153] = {9, 4, "DEV_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [154] = {9, 5, "DEV_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [155] = {9, 6, "DEV_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [156] = {9, 7, "DEV_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [157] = {9, 8, "DEV_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [158] = {9, 9, "DEV_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [159] = {9, 10, "DEV_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [160] = {9, 11, "DEV_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [161] = {10, 1, "DEV_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [162] = {10, 2, "DEV_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [163] = {10, 3, "DEV_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [164] = {10, 4, "DEV_DCC1_BUS_VBUS_CLK", "Input clock"},
-       [165] = {10, 5, "DEV_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [166] = {10, 6, "DEV_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [167] = {10, 7, "DEV_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [168] = {10, 8, "DEV_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [169] = {10, 9, "DEV_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [170] = {10, 10, "DEV_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [171] = {10, 11, "DEV_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [172] = {10, 12, "DEV_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [173] = {11, 1, "DEV_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [174] = {11, 2, "DEV_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [175] = {11, 3, "DEV_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [176] = {11, 4, "DEV_DCC2_BUS_VBUS_CLK", "Input clock"},
-       [177] = {11, 5, "DEV_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [178] = {11, 6, "DEV_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [179] = {11, 7, "DEV_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [180] = {11, 8, "DEV_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [181] = {11, 9, "DEV_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [182] = {11, 10, "DEV_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [183] = {11, 11, "DEV_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [184] = {11, 12, "DEV_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [185] = {12, 1, "DEV_DCC3_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [186] = {12, 2, "DEV_DCC3_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [187] = {12, 3, "DEV_DCC3_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [188] = {12, 4, "DEV_DCC3_BUS_VBUS_CLK", "Input clock"},
-       [189] = {12, 5, "DEV_DCC3_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [190] = {12, 6, "DEV_DCC3_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [191] = {12, 7, "DEV_DCC3_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [192] = {12, 8, "DEV_DCC3_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [193] = {12, 9, "DEV_DCC3_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [194] = {12, 10, "DEV_DCC3_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [195] = {12, 11, "DEV_DCC3_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [196] = {13, 1, "DEV_DCC4_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [197] = {13, 2, "DEV_DCC4_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [198] = {13, 3, "DEV_DCC4_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [199] = {13, 4, "DEV_DCC4_BUS_VBUS_CLK", "Input clock"},
-       [200] = {13, 5, "DEV_DCC4_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [201] = {13, 6, "DEV_DCC4_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [202] = {13, 7, "DEV_DCC4_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [203] = {13, 8, "DEV_DCC4_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [204] = {13, 9, "DEV_DCC4_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [205] = {13, 10, "DEV_DCC4_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [206] = {13, 11, "DEV_DCC4_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [207] = {14, 1, "DEV_DCC5_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [208] = {14, 2, "DEV_DCC5_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [209] = {14, 3, "DEV_DCC5_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [210] = {14, 4, "DEV_DCC5_BUS_VBUS_CLK", "Input clock"},
-       [211] = {14, 5, "DEV_DCC5_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [212] = {14, 6, "DEV_DCC5_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [213] = {14, 7, "DEV_DCC5_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [214] = {14, 8, "DEV_DCC5_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [215] = {14, 9, "DEV_DCC5_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [216] = {14, 10, "DEV_DCC5_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [217] = {14, 11, "DEV_DCC5_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [218] = {14, 12, "DEV_DCC5_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [219] = {15, 1, "DEV_DCC6_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [220] = {15, 2, "DEV_DCC6_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [221] = {15, 3, "DEV_DCC6_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [222] = {15, 4, "DEV_DCC6_BUS_VBUS_CLK", "Input clock"},
-       [223] = {15, 5, "DEV_DCC6_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [224] = {15, 6, "DEV_DCC6_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [225] = {15, 7, "DEV_DCC6_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [226] = {15, 8, "DEV_DCC6_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [227] = {15, 9, "DEV_DCC6_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [228] = {15, 10, "DEV_DCC6_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [229] = {15, 11, "DEV_DCC6_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [230] = {15, 12, "DEV_DCC6_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [231] = {16, 1, "DEV_DCC7_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [232] = {16, 2, "DEV_DCC7_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [233] = {16, 3, "DEV_DCC7_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [234] = {16, 4, "DEV_DCC7_BUS_VBUS_CLK", "Input clock"},
-       [235] = {16, 5, "DEV_DCC7_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [236] = {16, 6, "DEV_DCC7_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [237] = {16, 7, "DEV_DCC7_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [238] = {16, 8, "DEV_DCC7_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [239] = {16, 9, "DEV_DCC7_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [240] = {16, 10, "DEV_DCC7_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [241] = {16, 11, "DEV_DCC7_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [242] = {16, 12, "DEV_DCC7_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [243] = {20, 1, "DEV_DDRSS0_BUS_DDRSS_BYP_4X_CLK", "Input clock"},
-       [244] = {20, 2, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
-       [245] = {20, 3, "DEV_DDRSS0_BUS_DDRSS_TCLK", "Input clock"},
-       [246] = {20, 4, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
-       [247] = {20, 5, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
-       [248] = {20, 6, "DEV_DDRSS0_BUS_DDRSS_CFG_CLK", "Input clock"},
-       [249] = {20, 7, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
-       [250] = {20, 8, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
-       [251] = {20, 9, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
-       [252] = {68, 1, "DEV_DEBUGSS0_BUS_ATB5_CLK", "Input clock"},
-       [253] = {68, 2, "DEV_DEBUGSS0_BUS_ATB0_CLK", "Input clock"},
-       [254] = {68, 3, "DEV_DEBUGSS0_BUS_SYS_CLK", "Input clock"},
-       [255] = {68, 4, "DEV_DEBUGSS0_BUS_ATB4_CLK", "Input clock"},
-       [256] = {68, 5, "DEV_DEBUGSS0_BUS_CFG_CLK", "Input clock"},
-       [257] = {68, 6, "DEV_DEBUGSS0_BUS_ATB2_CLK", "Input clock"},
-       [258] = {68, 7, "DEV_DEBUGSS0_BUS_DBG_CLK", "Input clock"},
-       [259] = {68, 8, "DEV_DEBUGSS0_BUS_ATB3_CLK", "Input clock"},
-       [260] = {21, 1, "DEV_DEBUGSS_WRAP0_BUS_ATB_CLK", "Input clock"},
-       [261] = {21, 2, "DEV_DEBUGSS_WRAP0_BUS_TREXPT_CLK", "Input clock"},
-       [262] = {21, 3, "DEV_DEBUGSS_WRAP0_BUS_CORE_CLK", "Input clock"},
-       [263] = {67, 1, "DEV_DSS0_BUS_DSS_FUNC_CLK", "Input clock"},
-       [264] = {67, 2, "DEV_DSS0_BUS_DPI_1_IN_CLK", "Input muxed clock"},
-       [265] = {67, 3, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_CLOCKDIVIDER_DSS_BUS_OUT07", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"},
-       [266] = {67, 4, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_BOARD_0_BUS_DSS0EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"},
-       [267] = {67, 5, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_CLOCKDIVIDER_DSS_BUS_OUT1", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"},
-       [268] = {67, 6, "DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN0_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"},
-       [269] = {67, 7, "DEV_DSS0_BUS_DPI_1_OUT_CLK", "Output clock"},
-       [270] = {69, 1, "DEV_EFUSE0_BUS_EFC1_CTL_FCLK", "Output clock"},
-       [271] = {69, 2, "DEV_EFUSE0_BUS_EFC0_CTL_FCLK", "Output clock"},
-       [272] = {60, 1, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
-       [273] = {60, 2, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK3", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
-       [274] = {60, 3, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK2", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
-       [275] = {60, 4, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
-       [276] = {60, 5, "DEV_GPMC0_BUS_PI_GPMC_RET_CLK", "Input clock"},
-       [277] = {60, 6, "DEV_GPMC0_BUS_VBUSP_CLK", "Input clock"},
-       [278] = {60, 7, "DEV_GPMC0_BUS_PO_GPMC_DEV_CLK", "Output clock"},
-       [279] = {65, 1, "DEV_GPU0_BUS_HYD_CORE_CLK", "Input clock"},
-       [280] = {65, 2, "DEV_GPU0_BUS_SGX_CORE_CLK", "Input clock"},
-       [281] = {65, 3, "DEV_GPU0_BUS_SYS_CLK", "Input clock"},
-       [282] = {232, 1, "DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_CLK", "Input clock"},
-       [283] = {231, 1, "DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_CLK", "Input clock"},
-       [284] = {61, 1, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
-       [285] = {61, 2, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
-       [286] = {61, 3, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
-       [287] = {61, 4, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
-       [288] = {61, 5, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
-       [289] = {61, 6, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
-       [290] = {61, 7, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
-       [291] = {61, 8, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
-       [292] = {110, 1, "DEV_I2C0_BUS_PISYS_CLK", "Input clock"},
-       [293] = {110, 2, "DEV_I2C0_BUS_PISCL", "Output clock"},
-       [294] = {111, 1, "DEV_I2C1_BUS_PISYS_CLK", "Input clock"},
-       [295] = {111, 2, "DEV_I2C1_BUS_PISCL", "Output clock"},
-       [296] = {112, 1, "DEV_I2C2_BUS_PISYS_CLK", "Input clock"},
-       [297] = {112, 2, "DEV_I2C2_BUS_PISCL", "Output clock"},
-       [298] = {113, 1, "DEV_I2C3_BUS_PISYS_CLK", "Input clock"},
-       [299] = {113, 2, "DEV_I2C3_BUS_PISCL", "Output clock"},
-       [300] = {104, 1, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
-       [301] = {104, 2, "DEV_MCASP0_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
-       [302] = {104, 3, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
-       [303] = {104, 4, "DEV_MCASP0_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
-       [304] = {104, 5, "DEV_MCASP0_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
-       [305] = {104, 6, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
-       [306] = {104, 7, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
-       [307] = {104, 8, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
-       [308] = {104, 9, "DEV_MCASP0_BUS_VBUSP_CLK", "Input clock"},
-       [309] = {104, 10, "DEV_MCASP0_BUS_MCASP_AHCLKX_PIN", "Input clock"},
-       [310] = {104, 11, "DEV_MCASP0_BUS_MCASP_AHCLKR_PIN", "Input clock"},
-       [311] = {105, 1, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
-       [312] = {105, 2, "DEV_MCASP1_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
-       [313] = {105, 3, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
-       [314] = {105, 4, "DEV_MCASP1_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
-       [315] = {105, 5, "DEV_MCASP1_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
-       [316] = {105, 6, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
-       [317] = {105, 7, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
-       [318] = {105, 8, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
-       [319] = {105, 9, "DEV_MCASP1_BUS_VBUSP_CLK", "Input clock"},
-       [320] = {105, 10, "DEV_MCASP1_BUS_MCASP_AHCLKX_PIN", "Input clock"},
-       [321] = {105, 11, "DEV_MCASP1_BUS_MCASP_AHCLKR_PIN", "Input clock"},
-       [322] = {106, 1, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
-       [323] = {106, 2, "DEV_MCASP2_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
-       [324] = {106, 3, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
-       [325] = {106, 4, "DEV_MCASP2_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
-       [326] = {106, 5, "DEV_MCASP2_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT2", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
-       [327] = {106, 6, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
-       [328] = {106, 7, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
-       [329] = {106, 8, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
-       [330] = {106, 9, "DEV_MCASP2_BUS_VBUSP_CLK", "Input clock"},
-       [331] = {106, 10, "DEV_MCASP2_BUS_MCASP_AHCLKX_PIN", "Input clock"},
-       [332] = {106, 11, "DEV_MCASP2_BUS_MCASP_AHCLKR_PIN", "Input clock"},
-       [333] = {137, 1, "DEV_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"},
-       [334] = {137, 2, "DEV_MCSPI0_BUS_VBUSP_CLK", "Input clock"},
-       [335] = {137, 3, "DEV_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"},
-       [336] = {138, 1, "DEV_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"},
-       [337] = {138, 2, "DEV_MCSPI1_BUS_VBUSP_CLK", "Input clock"},
-       [338] = {138, 3, "DEV_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"},
-       [339] = {139, 1, "DEV_MCSPI2_BUS_CLKSPIREF_CLK", "Input clock"},
-       [340] = {139, 2, "DEV_MCSPI2_BUS_VBUSP_CLK", "Input clock"},
-       [341] = {139, 3, "DEV_MCSPI2_BUS_IO_CLKSPIO_CLK", "Output clock"},
-       [342] = {140, 1, "DEV_MCSPI3_BUS_CLKSPIREF_CLK", "Input clock"},
-       [343] = {140, 2, "DEV_MCSPI3_BUS_VBUSP_CLK", "Input clock"},
-       [344] = {140, 3, "DEV_MCSPI3_BUS_IO_CLKSPIO_CLK", "Output clock"},
-       [345] = {141, 1, "DEV_MCSPI4_BUS_VBUSP_CLK", "Input clock"},
-       [346] = {0, 1, "DEV_MCU_ADC0_BUS_SYS_CLK", "Input clock"},
-       [347] = {0, 2, "DEV_MCU_ADC0_BUS_ADC_CLK", "Input muxed clock"},
-       [348] = {0, 3, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
-       [349] = {0, 4, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
-       [350] = {0, 5, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
-       [351] = {0, 6, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
-       [352] = {1, 1, "DEV_MCU_ADC1_BUS_SYS_CLK", "Input clock"},
-       [353] = {1, 2, "DEV_MCU_ADC1_BUS_ADC_CLK", "Input muxed clock"},
-       [354] = {1, 3, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
-       [355] = {1, 4, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
-       [356] = {1, 5, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
-       [357] = {1, 6, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
-       [358] = {159, 1, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE", "Input muxed clock"},
-       [359] = {159, 2, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE"},
-       [360] = {159, 3, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK", "Input muxed clock"},
-       [361] = {159, 4, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"},
-       [362] = {159, 5, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"},
-       [363] = {245, 1, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE", "Input muxed clock"},
-       [364] = {245, 2, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE"},
-       [365] = {245, 3, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK", "Input muxed clock"},
-       [366] = {245, 4, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"},
-       [367] = {245, 5, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"},
-       [368] = {89, 1, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_4_CLK", "Input clock"},
-       [369] = {89, 2, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"},
-       [370] = {91, 1, "DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"},
-       [371] = {5, 1, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_250_CLK", "Input clock"},
-       [372] = {5, 2, "DEV_MCU_CPSW0_BUS_CPTS_RFT_CLK", "Input clock"},
-       [373] = {5, 3, "DEV_MCU_CPSW0_BUS_GMII1_MT_CLK", "Input clock"},
-       [374] = {5, 4, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_5_CLK", "Input clock"},
-       [375] = {5, 5, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_50_CLK", "Input clock"},
-       [376] = {5, 6, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK", "Input muxed clock"},
-       [377] = {5, 7, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"},
-       [378] = {5, 8, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_BOARD_0_BUS_MCU_RMII1_REFCLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"},
-       [379] = {5, 9, "DEV_MCU_CPSW0_BUS_GMII_RFT_CLK", "Input clock"},
-       [380] = {5, 10, "DEV_MCU_CPSW0_BUS_CPPI_CLK_CLK", "Input clock"},
-       [381] = {5, 11, "DEV_MCU_CPSW0_BUS_CPTS_GENF0_0", "Output clock"},
-       [382] = {17, 1, "DEV_MCU_DCC0_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [383] = {17, 2, "DEV_MCU_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [384] = {17, 3, "DEV_MCU_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [385] = {17, 4, "DEV_MCU_DCC0_BUS_VBUS_CLK", "Input clock"},
-       [386] = {17, 5, "DEV_MCU_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [387] = {17, 6, "DEV_MCU_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [388] = {17, 7, "DEV_MCU_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [389] = {17, 8, "DEV_MCU_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [390] = {17, 9, "DEV_MCU_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [391] = {17, 10, "DEV_MCU_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [392] = {17, 11, "DEV_MCU_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [393] = {17, 12, "DEV_MCU_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [394] = {18, 1, "DEV_MCU_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [395] = {18, 2, "DEV_MCU_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [396] = {18, 3, "DEV_MCU_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [397] = {18, 4, "DEV_MCU_DCC1_BUS_VBUS_CLK", "Input clock"},
-       [398] = {18, 5, "DEV_MCU_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [399] = {18, 6, "DEV_MCU_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [400] = {18, 7, "DEV_MCU_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [401] = {18, 8, "DEV_MCU_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [402] = {18, 9, "DEV_MCU_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [403] = {18, 10, "DEV_MCU_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [404] = {18, 11, "DEV_MCU_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [405] = {18, 12, "DEV_MCU_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [406] = {19, 1, "DEV_MCU_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [407] = {19, 2, "DEV_MCU_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [408] = {19, 3, "DEV_MCU_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [409] = {19, 4, "DEV_MCU_DCC2_BUS_VBUS_CLK", "Input clock"},
-       [410] = {19, 5, "DEV_MCU_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [411] = {19, 6, "DEV_MCU_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [412] = {19, 7, "DEV_MCU_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [413] = {19, 8, "DEV_MCU_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [414] = {19, 9, "DEV_MCU_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [415] = {19, 10, "DEV_MCU_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [416] = {19, 11, "DEV_MCU_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [417] = {19, 12, "DEV_MCU_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [418] = {71, 1, "DEV_MCU_DEBUGSS0_BUS_ATB0_CLK", "Input clock"},
-       [419] = {71, 2, "DEV_MCU_DEBUGSS0_BUS_SYS_CLK", "Input clock"},
-       [420] = {71, 3, "DEV_MCU_DEBUGSS0_BUS_CFG_CLK", "Input clock"},
-       [421] = {71, 4, "DEV_MCU_DEBUGSS0_BUS_ATB2_CLK", "Input clock"},
-       [422] = {71, 5, "DEV_MCU_DEBUGSS0_BUS_DBG_CLK", "Input clock"},
-       [423] = {71, 6, "DEV_MCU_DEBUGSS0_BUS_ATB3_CLK", "Input clock"},
-       [424] = {72, 1, "DEV_MCU_EFUSE0_BUS_EFC3_CTL_FCLK", "Output clock"},
-       [425] = {72, 2, "DEV_MCU_EFUSE0_BUS_EFC0_CTL_FCLK", "Output clock"},
-       [426] = {72, 3, "DEV_MCU_EFUSE0_BUS_EFC1_CTL_FCLK", "Output clock"},
-       [427] = {72, 4, "DEV_MCU_EFUSE0_BUS_EFC2_CTL_FCLK", "Output clock"},
-       [428] = {247, 1, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_CLK", "Input clock"},
-       [429] = {247, 2, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX2_CLK", "Input clock"},
-       [430] = {247, 3, "DEV_MCU_FSS0_HYPERBUS0_BUS_CBA_CLK", "Input clock"},
-       [431] = {247, 4, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX2_INV_CLK", "Input clock"},
-       [432] = {247, 5, "DEV_MCU_FSS0_HYPERBUS0_HPB_OUT_CLK_N", "Output clock"},
-       [433] = {247, 6, "DEV_MCU_FSS0_HYPERBUS0_HPB_OUT_CLK_P", "Output clock"},
-       [434] = {248, 1, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK"},
-       [435] = {248, 2, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK"},
-       [436] = {248, 3, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK", "Input muxed clock"},
-       [437] = {248, 4, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI0DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK"},
-       [438] = {248, 5, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_BUS_OSPI0_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK"},
-       [439] = {248, 6, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_PCLK_CLK", "Input clock"},
-       [440] = {248, 7, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_DQS_CLK", "Input clock"},
-       [441] = {248, 8, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_HCLK_CLK", "Input clock"},
-       [442] = {248, 9, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_OCLK_CLK", "Output clock"},
-       [443] = {249, 1, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK", "Input muxed clock"},
-       [444] = {249, 2, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI1DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK"},
-       [445] = {249, 3, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_BUS_OSPI1_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK"},
-       [446] = {249, 4, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_HCLK_CLK", "Input clock"},
-       [447] = {249, 5, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_DQS_CLK", "Input clock"},
-       [448] = {249, 6, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK", "Input muxed clock"},
-       [449] = {249, 7, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK"},
-       [450] = {249, 8, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK"},
-       [451] = {249, 9, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_OCLK_CLK", "Output clock"},
-       [452] = {114, 1, "DEV_MCU_I2C0_BUS_PISYS_CLK", "Input clock"},
-       [453] = {114, 2, "DEV_MCU_I2C0_BUS_PISCL", "Output clock"},
-       [454] = {102, 1, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
-       [455] = {102, 2, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
-       [456] = {102, 3, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
-       [457] = {102, 4, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
-       [458] = {102, 5, "DEV_MCU_MCAN0_BUS_MCANSS_HCLK_CLK", "Input clock"},
-       [459] = {103, 1, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
-       [460] = {103, 2, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
-       [461] = {103, 3, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
-       [462] = {103, 4, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
-       [463] = {103, 5, "DEV_MCU_MCAN1_BUS_MCANSS_HCLK_CLK", "Input clock"},
-       [464] = {142, 1, "DEV_MCU_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"},
-       [465] = {142, 2, "DEV_MCU_MCSPI0_BUS_VBUSP_CLK", "Input clock"},
-       [466] = {142, 3, "DEV_MCU_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"},
-       [467] = {143, 1, "DEV_MCU_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"},
-       [468] = {143, 2, "DEV_MCU_MCSPI1_BUS_VBUSP_CLK", "Input clock"},
-       [469] = {143, 3, "DEV_MCU_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"},
-       [470] = {144, 1, "DEV_MCU_MCSPI2_BUS_VBUSP_CLK", "Input clock"},
-       [471] = {116, 1, "DEV_MCU_MSRAM0_BUS_VCLK_CLK", "Input clock"},
-       [472] = {119, 1, "DEV_MCU_NAVSS0_BUS_CPSW0CLK", "Input clock"},
-       [473] = {119, 2, "DEV_MCU_NAVSS0_BUS_MODSS_VD2CLK", "Input clock"},
-       [474] = {119, 3, "DEV_MCU_NAVSS0_BUS_PDMA_MCU1CLK", "Input clock"},
-       [475] = {75, 1, "DEV_MCU_PBIST0_BUS_CLK4_CLK", "Input clock"},
-       [476] = {75, 2, "DEV_MCU_PBIST0_BUS_CLK2_CLK", "Input clock"},
-       [477] = {134, 1, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
-       [478] = {134, 2, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
-       [479] = {134, 3, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
-       [480] = {134, 4, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
-       [481] = {134, 5, "DEV_MCU_RTI0_BUS_VBUSP_CLK", "Input clock"},
-       [482] = {135, 1, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
-       [483] = {135, 2, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
-       [484] = {135, 3, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
-       [485] = {135, 4, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
-       [486] = {135, 5, "DEV_MCU_RTI1_BUS_VBUSP_CLK", "Input clock"},
-       [487] = {35, 1, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [488] = {35, 2, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [489] = {35, 3, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [490] = {35, 4, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [491] = {35, 5, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [492] = {35, 6, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [493] = {35, 7, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [494] = {35, 8, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [495] = {35, 9, "DEV_MCU_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [496] = {36, 1, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [497] = {36, 2, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [498] = {36, 3, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [499] = {36, 4, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [500] = {36, 5, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [501] = {36, 6, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [502] = {36, 7, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [503] = {36, 8, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [504] = {36, 9, "DEV_MCU_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [505] = {37, 1, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [506] = {37, 2, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [507] = {37, 3, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [508] = {37, 4, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [509] = {37, 5, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [510] = {37, 6, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [511] = {37, 7, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [512] = {37, 8, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [513] = {37, 9, "DEV_MCU_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [514] = {38, 1, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [515] = {38, 2, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [516] = {38, 3, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [517] = {38, 4, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [518] = {38, 5, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [519] = {38, 6, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [520] = {38, 7, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [521] = {38, 8, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [522] = {38, 9, "DEV_MCU_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [523] = {149, 1, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"},
-       [524] = {149, 2, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"},
-       [525] = {149, 3, "DEV_MCU_UART0_BUS_VBUSP_CLK", "Input clock"},
-       [526] = {47, 1, "DEV_MMCSD0_BUS_EMMCSDSS_XIN_CLK", "Input clock"},
-       [527] = {48, 1, "DEV_MMCSD1_BUS_EMMCSDSS_XIN_CLK", "Input clock"},
-       [528] = {234, 1, "DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0_BUS_UNDEFINEDCHAIN0_FCLK", "Input clock"},
-       [529] = {235, 1, "DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN0_FCLK", "Input clock"},
-       [530] = {235, 2, "DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN2_FCLK", "Input clock"},
-       [531] = {118, 1, "DEV_NAVSS0_BUS_ICSS_G2CLK", "Input clock"},
-       [532] = {118, 2, "DEV_NAVSS0_BUS_ICSS_G0CLK", "Input clock"},
-       [533] = {118, 3, "DEV_NAVSS0_BUS_RCLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"},
-       [534] = {118, 4, "DEV_NAVSS0_BUS_MSMC0CLK", "Input clock"},
-       [535] = {118, 5, "DEV_NAVSS0_BUS_RCLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"},
-       [536] = {118, 6, "DEV_NAVSS0_BUS_RCLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"},
-       [537] = {118, 7, "DEV_NAVSS0_BUS_MODSS_VD2CLK", "Input clock"},
-       [538] = {118, 8, "DEV_NAVSS0_BUS_RCLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"},
-       [539] = {118, 9, "DEV_NAVSS0_BUS_PDMA_MAIN1CLK", "Input clock"},
-       [540] = {118, 10, "DEV_NAVSS0_BUS_NBSS_VCLK", "Input clock"},
-       [541] = {118, 11, "DEV_NAVSS0_BUS_RCLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"},
-       [542] = {118, 12, "DEV_NAVSS0_BUS_NBSS_VD2CLK", "Input clock"},
-       [543] = {118, 13, "DEV_NAVSS0_BUS_ICSS_G1CLK", "Input clock"},
-       [544] = {118, 14, "DEV_NAVSS0_BUS_RCLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"},
-       [545] = {118, 15, "DEV_NAVSS0_BUS_CPTS0_GENF4_0", "Output clock"},
-       [546] = {118, 16, "DEV_NAVSS0_BUS_CPTS0_GENF5_0", "Output clock"},
-       [547] = {118, 17, "DEV_NAVSS0_BUS_CPTS0_GENF2_0", "Output clock"},
-       [548] = {118, 18, "DEV_NAVSS0_BUS_CPTS0_GENF3_0", "Output clock"},
-       [549] = {216, 1, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN1_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"},
-       [550] = {216, 2, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN0_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"},
-       [551] = {73, 1, "DEV_PBIST0_BUS_CLK4_CLK", "Input clock"},
-       [552] = {73, 2, "DEV_PBIST0_BUS_CLK2_CLK", "Input clock"},
-       [553] = {74, 1, "DEV_PBIST1_BUS_CLK4_CLK", "Input clock"},
-       [554] = {74, 2, "DEV_PBIST1_BUS_CLK2_CLK", "Input clock"},
-       [555] = {120, 1, "DEV_PCIE0_BUS_PCIE_CBA_CLK", "Input clock"},
-       [556] = {120, 2, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"},
-       [557] = {120, 3, "DEV_PCIE0_BUS_PCIE_TXI0_CLK", "Input clock"},
-       [558] = {120, 4, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"},
-       [559] = {120, 5, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"},
-       [560] = {120, 6, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"},
-       [561] = {120, 7, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"},
-       [562] = {120, 8, "DEV_PCIE0_BUS_PCIE_TXR1_CLK", "Output clock"},
-       [563] = {120, 9, "DEV_PCIE0_BUS_PCIE_TXR0_CLK", "Output clock"},
-       [564] = {121, 1, "DEV_PCIE1_BUS_PCIE_CBA_CLK", "Input clock"},
-       [565] = {121, 2, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"},
-       [566] = {121, 3, "DEV_PCIE1_BUS_PCIE_TXI0_CLK", "Input clock"},
-       [567] = {121, 4, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"},
-       [568] = {121, 5, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"},
-       [569] = {121, 6, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"},
-       [570] = {121, 7, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"},
-       [571] = {121, 8, "DEV_PCIE1_BUS_PCIE_TXR0_CLK", "Output clock"},
-       [572] = {76, 1, "DEV_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"},
-       [573] = {76, 2, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input muxed clock"},
-       [574] = {76, 3, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"},
-       [575] = {76, 4, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"},
-       [576] = {62, 1, "DEV_PRU_ICSSG0_BUS_WIZ1_TX_SLV_CLK", "Input clock"},
-       [577] = {62, 2, "DEV_PRU_ICSSG0_BUS_WIZ0_RX_SLV_CLK", "Input clock"},
-       [578] = {62, 3, "DEV_PRU_ICSSG0_BUS_VCLK_CLK", "Input clock"},
-       [579] = {62, 4, "DEV_PRU_ICSSG0_BUS_UCLK_CLK", "Input clock"},
-       [580] = {62, 5, "DEV_PRU_ICSSG0_BUS_WIZ0_TX_SLV_CLK", "Input clock"},
-       [581] = {62, 6, "DEV_PRU_ICSSG0_BUS_WIZ1_RX_SLV_CLK", "Input clock"},
-       [582] = {62, 7, "DEV_PRU_ICSSG0_BUS_PR1_RGMII1_RXC_I", "Input clock"},
-       [583] = {62, 8, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_250_CLK", "Input clock"},
-       [584] = {62, 9, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_50_CLK", "Input clock"},
-       [585] = {62, 10, "DEV_PRU_ICSSG0_BUS_IEP_CLK", "Input muxed clock"},
-       [586] = {62, 11, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
-       [587] = {62, 12, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
-       [588] = {62, 13, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
-       [589] = {62, 14, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
-       [590] = {62, 15, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
-       [591] = {62, 16, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
-       [592] = {62, 17, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
-       [593] = {62, 18, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
-       [594] = {62, 19, "DEV_PRU_ICSSG0_BUS_CORE_CLK", "Input muxed clock"},
-       [595] = {62, 20, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"},
-       [596] = {62, 21, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"},
-       [597] = {62, 22, "DEV_PRU_ICSSG0_BUS_PR1_RGMII0_RXC_I", "Input clock"},
-       [598] = {62, 23, "DEV_PRU_ICSSG0_BUS_PR1_RGMII1_TXC_I", "Output clock"},
-       [599] = {62, 24, "DEV_PRU_ICSSG0_BUS_PR1_RGMII0_TXC_I", "Output clock"},
-       [600] = {63, 1, "DEV_PRU_ICSSG1_BUS_WIZ1_TX_SLV_CLK", "Input clock"},
-       [601] = {63, 2, "DEV_PRU_ICSSG1_BUS_WIZ0_RX_SLV_CLK", "Input clock"},
-       [602] = {63, 3, "DEV_PRU_ICSSG1_BUS_VCLK_CLK", "Input clock"},
-       [603] = {63, 4, "DEV_PRU_ICSSG1_BUS_UCLK_CLK", "Input clock"},
-       [604] = {63, 5, "DEV_PRU_ICSSG1_BUS_WIZ0_TX_SLV_CLK", "Input clock"},
-       [605] = {63, 6, "DEV_PRU_ICSSG1_BUS_WIZ1_RX_SLV_CLK", "Input clock"},
-       [606] = {63, 7, "DEV_PRU_ICSSG1_BUS_PR1_RGMII1_RXC_I", "Input clock"},
-       [607] = {63, 8, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_250_CLK", "Input clock"},
-       [608] = {63, 9, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_50_CLK", "Input clock"},
-       [609] = {63, 10, "DEV_PRU_ICSSG1_BUS_IEP_CLK", "Input muxed clock"},
-       [610] = {63, 11, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
-       [611] = {63, 12, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
-       [612] = {63, 13, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
-       [613] = {63, 14, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
-       [614] = {63, 15, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
-       [615] = {63, 16, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
-       [616] = {63, 17, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
-       [617] = {63, 18, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
-       [618] = {63, 19, "DEV_PRU_ICSSG1_BUS_CORE_CLK", "Input muxed clock"},
-       [619] = {63, 20, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"},
-       [620] = {63, 21, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"},
-       [621] = {63, 22, "DEV_PRU_ICSSG1_BUS_PR1_RGMII0_RXC_I", "Input clock"},
-       [622] = {63, 23, "DEV_PRU_ICSSG1_BUS_PR1_RGMII1_TXC_I", "Output clock"},
-       [623] = {63, 24, "DEV_PRU_ICSSG1_BUS_PR1_RGMII0_TXC_I", "Output clock"},
-       [624] = {64, 1, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_SLV_CLK", "Input clock"},
-       [625] = {64, 2, "DEV_PRU_ICSSG2_BUS_WIZ0_RX_SLV_CLK", "Input clock"},
-       [626] = {64, 3, "DEV_PRU_ICSSG2_BUS_VCLK_CLK", "Input clock"},
-       [627] = {64, 4, "DEV_PRU_ICSSG2_BUS_UCLK_CLK", "Input clock"},
-       [628] = {64, 5, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_SLV_CLK", "Input clock"},
-       [629] = {64, 6, "DEV_PRU_ICSSG2_BUS_WIZ1_RX_SLV_CLK", "Input clock"},
-       [630] = {64, 7, "DEV_PRU_ICSSG2_BUS_PR1_RGMII1_RXC_I", "Input clock"},
-       [631] = {64, 8, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_250_CLK", "Input clock"},
-       [632] = {64, 9, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_50_CLK", "Input clock"},
-       [633] = {64, 10, "DEV_PRU_ICSSG2_BUS_IEP_CLK", "Input muxed clock"},
-       [634] = {64, 11, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
-       [635] = {64, 12, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
-       [636] = {64, 13, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
-       [637] = {64, 14, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
-       [638] = {64, 15, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
-       [639] = {64, 16, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
-       [640] = {64, 17, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
-       [641] = {64, 18, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
-       [642] = {64, 19, "DEV_PRU_ICSSG2_BUS_CORE_CLK", "Input muxed clock"},
-       [643] = {64, 20, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"},
-       [644] = {64, 21, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"},
-       [645] = {64, 22, "DEV_PRU_ICSSG2_BUS_PR1_RGMII0_RXC_I", "Input clock"},
-       [646] = {64, 23, "DEV_PRU_ICSSG2_BUS_PR1_RGMII1_TXC_I", "Output clock"},
-       [647] = {64, 24, "DEV_PRU_ICSSG2_BUS_PR1_RGMII0_TXC_I", "Output clock"},
-       [648] = {64, 25, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_MST_CLK", "Output clock"},
-       [649] = {64, 26, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_MST_CLK", "Output clock"},
-       [650] = {70, 1, "DEV_PSC0_BUS_SLOW_CLK", "Input clock"},
-       [651] = {130, 1, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
-       [652] = {130, 2, "DEV_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
-       [653] = {130, 3, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
-       [654] = {130, 4, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
-       [655] = {130, 5, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
-       [656] = {130, 6, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
-       [657] = {130, 7, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
-       [658] = {130, 8, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
-       [659] = {130, 9, "DEV_RTI0_BUS_VBUSP_CLK", "Input clock"},
-       [660] = {131, 1, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
-       [661] = {131, 2, "DEV_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
-       [662] = {131, 3, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
-       [663] = {131, 4, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
-       [664] = {131, 5, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
-       [665] = {131, 6, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
-       [666] = {131, 7, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
-       [667] = {131, 8, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
-       [668] = {131, 9, "DEV_RTI1_BUS_VBUSP_CLK", "Input clock"},
-       [669] = {132, 1, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
-       [670] = {132, 2, "DEV_RTI2_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
-       [671] = {132, 3, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
-       [672] = {132, 4, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
-       [673] = {132, 5, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
-       [674] = {132, 6, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
-       [675] = {132, 7, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
-       [676] = {132, 8, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
-       [677] = {132, 9, "DEV_RTI2_BUS_VBUSP_CLK", "Input clock"},
-       [678] = {133, 1, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
-       [679] = {133, 2, "DEV_RTI3_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
-       [680] = {133, 3, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
-       [681] = {133, 4, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
-       [682] = {133, 5, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
-       [683] = {133, 6, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
-       [684] = {133, 7, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
-       [685] = {133, 8, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
-       [686] = {133, 9, "DEV_RTI3_BUS_VBUSP_CLK", "Input clock"},
-       [687] = {136, 1, "DEV_SA2_UL0_BUS_X1_CLK", "Input clock"},
-       [688] = {136, 2, "DEV_SA2_UL0_BUS_X2_CLK", "Input clock"},
-       [689] = {153, 1, "DEV_SERDES0_BUS_REFCLKPP", "Input clock"},
-       [690] = {153, 2, "DEV_SERDES0_BUS_CLK", "Input clock"},
-       [691] = {153, 3, "DEV_SERDES0_BUS_IP2_LN0_TXRCLK", "Input clock"},
-       [692] = {153, 4, "DEV_SERDES0_BUS_LI_REFCLK", "Input muxed clock"},
-       [693] = {153, 5, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
-       [694] = {153, 6, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
-       [695] = {153, 7, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
-       [696] = {153, 8, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
-       [697] = {153, 9, "DEV_SERDES0_BUS_REFCLKPN", "Input clock"},
-       [698] = {153, 10, "DEV_SERDES0_BUS_LN0_TXCLK", "Output clock"},
-       [699] = {153, 11, "DEV_SERDES0_BUS_LN0_RXCLK", "Output clock"},
-       [700] = {154, 1, "DEV_SERDES1_BUS_REFCLKPP", "Input clock"},
-       [701] = {154, 2, "DEV_SERDES1_BUS_CLK", "Input clock"},
-       [702] = {154, 3, "DEV_SERDES1_BUS_IP1_LN0_TXRCLK", "Input clock"},
-       [703] = {154, 4, "DEV_SERDES1_BUS_IP2_LN0_TXRCLK", "Input clock"},
-       [704] = {154, 5, "DEV_SERDES1_BUS_RI_REFCLK", "Input muxed clock"},
-       [705] = {154, 6, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
-       [706] = {154, 7, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
-       [707] = {154, 8, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
-       [708] = {154, 9, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
-       [709] = {154, 10, "DEV_SERDES1_BUS_REFCLKPN", "Input clock"},
-       [710] = {154, 11, "DEV_SERDES1_BUS_LN0_TXCLK", "Output clock"},
-       [711] = {154, 12, "DEV_SERDES1_BUS_LN0_RXCLK", "Output clock"},
-       [712] = {8, 1, "DEV_STM0_BUS_ATB_CLK", "Input clock"},
-       [713] = {8, 2, "DEV_STM0_BUS_VBUSP_CLK", "Input clock"},
-       [714] = {23, 1, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [715] = {23, 2, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [716] = {23, 3, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [717] = {23, 4, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [718] = {23, 5, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [719] = {23, 6, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [720] = {23, 7, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [721] = {23, 8, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [722] = {23, 9, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [723] = {23, 10, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [724] = {23, 11, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [725] = {23, 12, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [726] = {23, 13, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [727] = {23, 14, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [728] = {23, 15, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [729] = {23, 16, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [730] = {23, 17, "DEV_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [731] = {24, 1, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [732] = {24, 2, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [733] = {24, 3, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [734] = {24, 4, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [735] = {24, 5, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [736] = {24, 6, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [737] = {24, 7, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [738] = {24, 8, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [739] = {24, 9, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [740] = {24, 10, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [741] = {24, 11, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [742] = {24, 12, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [743] = {24, 13, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [744] = {24, 14, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [745] = {24, 15, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [746] = {24, 16, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [747] = {24, 17, "DEV_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [748] = {25, 1, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [749] = {25, 2, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [750] = {25, 3, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [751] = {25, 4, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [752] = {25, 5, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [753] = {25, 6, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [754] = {25, 7, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [755] = {25, 8, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [756] = {25, 9, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [757] = {25, 10, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [758] = {25, 11, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [759] = {25, 12, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [760] = {25, 13, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [761] = {25, 14, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [762] = {25, 15, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [763] = {25, 16, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [764] = {25, 17, "DEV_TIMER10_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [765] = {26, 1, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [766] = {26, 2, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [767] = {26, 3, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [768] = {26, 4, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [769] = {26, 5, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [770] = {26, 6, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [771] = {26, 7, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [772] = {26, 8, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [773] = {26, 9, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [774] = {26, 10, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [775] = {26, 11, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [776] = {26, 12, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [777] = {26, 13, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [778] = {26, 14, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [779] = {26, 15, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [780] = {26, 16, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [781] = {26, 17, "DEV_TIMER11_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [782] = {27, 1, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [783] = {27, 2, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [784] = {27, 3, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [785] = {27, 4, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [786] = {27, 5, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [787] = {27, 6, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [788] = {27, 7, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [789] = {27, 8, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [790] = {27, 9, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [791] = {27, 10, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [792] = {27, 11, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [793] = {27, 12, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [794] = {27, 13, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [795] = {27, 14, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [796] = {27, 15, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [797] = {27, 16, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [798] = {27, 17, "DEV_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [799] = {28, 1, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [800] = {28, 2, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [801] = {28, 3, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [802] = {28, 4, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [803] = {28, 5, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [804] = {28, 6, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [805] = {28, 7, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [806] = {28, 8, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [807] = {28, 9, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [808] = {28, 10, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [809] = {28, 11, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [810] = {28, 12, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [811] = {28, 13, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [812] = {28, 14, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [813] = {28, 15, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [814] = {28, 16, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [815] = {28, 17, "DEV_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [816] = {29, 1, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [817] = {29, 2, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [818] = {29, 3, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [819] = {29, 4, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [820] = {29, 5, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [821] = {29, 6, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [822] = {29, 7, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [823] = {29, 8, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [824] = {29, 9, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [825] = {29, 10, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [826] = {29, 11, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [827] = {29, 12, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [828] = {29, 13, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [829] = {29, 14, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [830] = {29, 15, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [831] = {29, 16, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [832] = {29, 17, "DEV_TIMER4_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [833] = {30, 1, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [834] = {30, 2, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [835] = {30, 3, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [836] = {30, 4, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [837] = {30, 5, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [838] = {30, 6, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [839] = {30, 7, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [840] = {30, 8, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [841] = {30, 9, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [842] = {30, 10, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [843] = {30, 11, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [844] = {30, 12, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [845] = {30, 13, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [846] = {30, 14, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [847] = {30, 15, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [848] = {30, 16, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [849] = {30, 17, "DEV_TIMER5_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [850] = {31, 1, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [851] = {31, 2, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [852] = {31, 3, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [853] = {31, 4, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [854] = {31, 5, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [855] = {31, 6, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [856] = {31, 7, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [857] = {31, 8, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [858] = {31, 9, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [859] = {31, 10, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [860] = {31, 11, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [861] = {31, 12, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [862] = {31, 13, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [863] = {31, 14, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [864] = {31, 15, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [865] = {31, 16, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [866] = {31, 17, "DEV_TIMER6_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [867] = {32, 1, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [868] = {32, 2, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [869] = {32, 3, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [870] = {32, 4, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [871] = {32, 5, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [872] = {32, 6, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [873] = {32, 7, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [874] = {32, 8, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [875] = {32, 9, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [876] = {32, 10, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [877] = {32, 11, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [878] = {32, 12, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [879] = {32, 13, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [880] = {32, 14, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [881] = {32, 15, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [882] = {32, 16, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [883] = {32, 17, "DEV_TIMER7_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [884] = {33, 1, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [885] = {33, 2, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [886] = {33, 3, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [887] = {33, 4, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [888] = {33, 5, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [889] = {33, 6, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [890] = {33, 7, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [891] = {33, 8, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [892] = {33, 9, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [893] = {33, 10, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [894] = {33, 11, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [895] = {33, 12, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [896] = {33, 13, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [897] = {33, 14, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [898] = {33, 15, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [899] = {33, 16, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [900] = {33, 17, "DEV_TIMER8_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [901] = {34, 1, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [902] = {34, 2, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [903] = {34, 3, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [904] = {34, 4, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [905] = {34, 5, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [906] = {34, 6, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [907] = {34, 7, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [908] = {34, 8, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [909] = {34, 9, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [910] = {34, 10, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [911] = {34, 11, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [912] = {34, 12, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [913] = {34, 13, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [914] = {34, 14, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [915] = {34, 15, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [916] = {34, 16, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [917] = {34, 17, "DEV_TIMER9_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [918] = {146, 1, "DEV_UART0_BUS_VBUSP_CLK", "Input clock"},
-       [919] = {147, 1, "DEV_UART1_BUS_VBUSP_CLK", "Input clock"},
-       [920] = {148, 1, "DEV_UART2_BUS_VBUSP_CLK", "Input clock"},
-       [921] = {151, 1, "DEV_USB3SS0_BUS_PHY2_REFCLK960M_CLK", "Input clock"},
-       [922] = {151, 2, "DEV_USB3SS0_BUS_REF_CLK", "Input muxed clock"},
-       [923] = {151, 3, "DEV_USB3SS0_BUS_REF_CLK_PARENT_CLOCKMUX_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"},
-       [924] = {151, 4, "DEV_USB3SS0_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"},
-       [925] = {151, 5, "DEV_USB3SS0_BUS_HSIC_CLK_CLK", "Input clock"},
-       [926] = {151, 6, "DEV_USB3SS0_BUS_BUS_CLK", "Input clock"},
-       [927] = {151, 7, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK", "Input muxed clock"},
-       [928] = {151, 8, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"},
-       [929] = {151, 9, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_CLOCKMUX_USB0_PIPE3_CLK_SEL_DIV_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"},
-       [930] = {151, 10, "DEV_USB3SS0_BUS_UTMI_CLK_CLK", "Input clock"},
-       [931] = {152, 1, "DEV_USB3SS1_BUS_PHY2_REFCLK960M_CLK", "Input clock"},
-       [932] = {152, 2, "DEV_USB3SS1_BUS_REF_CLK", "Input muxed clock"},
-       [933] = {152, 3, "DEV_USB3SS1_BUS_REF_CLK_PARENT_CLOCKMUX_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"},
-       [934] = {152, 4, "DEV_USB3SS1_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"},
-       [935] = {152, 5, "DEV_USB3SS1_BUS_HSIC_CLK_CLK", "Input clock"},
-       [936] = {152, 6, "DEV_USB3SS1_BUS_BUS_CLK", "Input clock"},
-       [937] = {152, 7, "DEV_USB3SS1_BUS_PIPE3_TXB_CLK", "Input clock"},
-       [938] = {152, 8, "DEV_USB3SS1_BUS_UTMI_CLK_CLK", "Input clock"},
-       [939] = {94, 1, "DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_4_CLK", "Input clock"},
-       [940] = {22, 1, "DEV_WKUP_DMSC0_BUS_FUNC_MOSC_CLK", "Input clock"},
-       [941] = {22, 2, "DEV_WKUP_DMSC0_BUS_VBUS_CLK", "Input clock"},
-       [942] = {22, 3, "DEV_WKUP_DMSC0_BUS_FUNC_32K_RC_CLK", "Input clock"},
-       [943] = {22, 4, "DEV_WKUP_DMSC0_BUS_SEC_EFC_FCLK", "Input clock"},
-       [944] = {22, 5, "DEV_WKUP_DMSC0_BUS_DAP_CLK", "Input clock"},
-       [945] = {22, 6, "DEV_WKUP_DMSC0_BUS_EXT_CLK", "Input clock"},
-       [946] = {59, 1, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
-       [947] = {59, 2, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4_DUP0", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
-       [948] = {59, 3, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
-       [949] = {59, 4, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
-       [950] = {115, 1, "DEV_WKUP_I2C0_BUS_PISYS_CLK", "Input muxed clock"},
-       [951] = {115, 2, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"},
-       [952] = {115, 3, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"},
-       [953] = {115, 4, "DEV_WKUP_I2C0_BUS_PISCL", "Output clock"},
-       [954] = {77, 1, "DEV_WKUP_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"},
-       [955] = {77, 2, "DEV_WKUP_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input clock"},
-       [956] = {79, 1, "DEV_WKUP_PSC0_BUS_SLOW_CLK", "Input clock"},
-       [957] = {150, 1, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_CLOCKMUX_WKUPUSART_CLK_SEL_BUS_OUT0", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"},
-       [958] = {150, 2, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"},
-       [959] = {150, 3, "DEV_WKUP_UART0_BUS_VBUSP_CLK", "Input clock"},
-       [960] = {80, 1, "DEV_WKUP_VTM0_BUS_VBUSP_CLK", "Input clock"},
+       [0] = {157, 0, "DEV_BOARD0_BUS_SCL3_IN", "Input clock"},
+       [1] = {157, 1, "DEV_BOARD0_BUS_SCL2_IN", "Input clock"},
+       [2] = {157, 2, "DEV_BOARD0_BUS_SCL1_IN", "Input clock"},
+       [3] = {157, 3, "DEV_BOARD0_BUS_SCL0_IN", "Input clock"},
+       [4] = {157, 4, "DEV_BOARD0_BUS_PRG2_RGMII2_TCLK_IN", "Input clock"},
+       [5] = {157, 5, "DEV_BOARD0_BUS_MCU_OSPI1CLK_IN", "Input clock"},
+       [6] = {157, 6, "DEV_BOARD0_BUS_PRG1_RGMII1_TCLK_IN", "Input clock"},
+       [7] = {157, 7, "DEV_BOARD0_BUS_REFCLK1P_IN", "Input muxed clock"},
+       [8] = {157, 8, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
+       [9] = {157, 9, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
+       [10] = {157, 10, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
+       [11] = {157, 11, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
+       [12] = {157, 12, "DEV_BOARD0_BUS_MCU_OSPI1LBCLKO_IN", "Input clock"},
+       [13] = {157, 13, "DEV_BOARD0_BUS_MCU_OBSCLK_IN", "Input clock"},
+       [14] = {157, 14, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       [15] = {157, 15, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       [16] = {157, 16, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       [17] = {157, 17, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       [18] = {157, 18, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       [19] = {157, 19, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       [20] = {157, 20, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       [21] = {157, 21, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       [22] = {157, 22, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       [23] = {157, 23, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       [24] = {157, 24, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       [25] = {157, 25, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       [26] = {157, 26, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       [27] = {157, 27, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       [28] = {157, 28, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       [29] = {157, 29, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       [30] = {157, 30, "DEV_BOARD0_BUS_PRG2_RGMII1_TCLK_IN", "Input clock"},
+       [31] = {157, 31, "DEV_BOARD0_BUS_REFCLK1M_IN", "Input muxed clock"},
+       [32] = {157, 32, "DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M_IN"},
+       [33] = {157, 33, "DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M_IN"},
+       [34] = {157, 34, "DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M_IN"},
+       [35] = {157, 35, "DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M_IN"},
+       [36] = {157, 36, "DEV_BOARD0_BUS_OBSCLK_IN", "Input clock"},
+       [37] = {157, 37, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       [38] = {157, 38, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       [39] = {157, 39, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       [40] = {157, 40, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       [41] = {157, 41, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       [42] = {157, 42, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       [43] = {157, 43, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_4_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       [44] = {157, 44, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_6_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       [45] = {157, 45, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       [46] = {157, 46, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       [47] = {157, 47, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       [48] = {157, 48, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_7_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       [49] = {157, 49, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       [50] = {157, 50, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       [51] = {157, 51, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       [52] = {157, 52, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       [53] = {157, 53, "DEV_BOARD0_BUS_PRG0_RGMII1_TCLK_IN", "Input clock"},
+       [54] = {157, 54, "DEV_BOARD0_BUS_MCU_OSPI0CLK_IN", "Input clock"},
+       [55] = {157, 55, "DEV_BOARD0_BUS_DSS0PCLK_IN", "Input clock"},
+       [56] = {157, 56, "DEV_BOARD0_BUS_PRG0_RGMII2_TCLK_IN", "Input clock"},
+       [57] = {157, 57, "DEV_BOARD0_BUS_WKUP_SCL0_IN", "Input clock"},
+       [58] = {157, 58, "DEV_BOARD0_BUS_REFCLK0P_IN", "Input muxed clock"},
+       [59] = {157, 59, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
+       [60] = {157, 60, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
+       [61] = {157, 61, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
+       [62] = {157, 62, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
+       [63] = {157, 63, "DEV_BOARD0_BUS_REFCLK0M_IN", "Input muxed clock"},
+       [64] = {157, 64, "DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M_IN"},
+       [65] = {157, 65, "DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M_IN"},
+       [66] = {157, 66, "DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M_IN"},
+       [67] = {157, 67, "DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M_IN"},
+       [68] = {157, 68, "DEV_BOARD0_BUS_MCU_OSPI0LBCLKO_IN", "Input clock"},
+       [69] = {157, 69, "DEV_BOARD0_BUS_MCU_CLKOUT_IN", "Input muxed clock"},
+       [70] = {157, 70, "DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN"},
+       [71] = {157, 71, "DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK10", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN"},
+       [72] = {157, 72, "DEV_BOARD0_BUS_MCU_SCL0_IN", "Input clock"},
+       [73] = {157, 73, "DEV_BOARD0_BUS_SYSCLKOUT_IN", "Input clock"},
+       [74] = {157, 74, "DEV_BOARD0_BUS_MCU_SYSCLKOUT_IN", "Input clock"},
+       [75] = {157, 75, "DEV_BOARD0_BUS_PRG1_RGMII1_RCLK_OUT", "Output clock"},
+       [76] = {157, 76, "DEV_BOARD0_BUS_PRG1_RGMII2_RCLK_OUT", "Output clock"},
+       [77] = {157, 77, "DEV_BOARD0_BUS_GPMCCLK_OUT", "Output clock"},
+       [78] = {157, 78, "DEV_BOARD0_BUS_MCASP2AHCLKX_OUT", "Output clock"},
+       [79] = {157, 79, "DEV_BOARD0_BUS_MCASP2AHCLKR_OUT", "Output clock"},
+       [80] = {157, 80, "DEV_BOARD0_BUS_PRG2_RGMII2_RCLK_OUT", "Output clock"},
+       [81] = {157, 81, "DEV_BOARD0_BUS_CPTS_RFT_CLK_OUT", "Output clock"},
+       [82] = {157, 82, "DEV_BOARD0_BUS_MCASP0ACLKR_OUT", "Output clock"},
+       [83] = {157, 83, "DEV_BOARD0_BUS_MCASP0ACLKX_OUT", "Output clock"},
+       [84] = {157, 84, "DEV_BOARD0_BUS_EXT_REFCLK1_OUT", "Output clock"},
+       [85] = {157, 85, "DEV_BOARD0_BUS_PRG0_RGMII2_RCLK_OUT", "Output clock"},
+       [86] = {157, 86, "DEV_BOARD0_BUS_MCU_OSPI0DQS_OUT", "Output clock"},
+       [87] = {157, 87, "DEV_BOARD0_BUS_USB0REFCLKP_OUT", "Output clock"},
+       [88] = {157, 88, "DEV_BOARD0_BUS_DSS0EXTPCLKIN_OUT", "Output clock"},
+       [89] = {157, 89, "DEV_BOARD0_BUS_SPI1CLK_OUT", "Output clock"},
+       [90] = {157, 90, "DEV_BOARD0_BUS_MCASP2ACLKR_OUT", "Output clock"},
+       [91] = {157, 91, "DEV_BOARD0_BUS_MCASP1ACLKX_OUT", "Output clock"},
+       [92] = {157, 92, "DEV_BOARD0_BUS_MCASP1ACLKR_OUT", "Output clock"},
+       [93] = {157, 93, "DEV_BOARD0_BUS_MCASP2ACLKX_OUT", "Output clock"},
+       [94] = {157, 94, "DEV_BOARD0_BUS_MCU_RMII1_REFCLK_OUT", "Output clock"},
+       [95] = {157, 95, "DEV_BOARD0_BUS_MCU_CPTS_RFT_CLK_OUT", "Output clock"},
+       [96] = {157, 96, "DEV_BOARD0_BUS_MCU_RGMII1_TCLK_OUT", "Output clock"},
+       [97] = {157, 97, "DEV_BOARD0_BUS_MCU_SPI0CLK_OUT", "Output clock"},
+       [98] = {157, 98, "DEV_BOARD0_BUS_MCU_SPI1CLK_OUT", "Output clock"},
+       [99] = {157, 99, "DEV_BOARD0_BUS_PRG0_RGMII1_RCLK_OUT", "Output clock"},
+       [100] = {157, 100, "DEV_BOARD0_BUS_SPI2CLK_OUT", "Output clock"},
+       [101] = {157, 101, "DEV_BOARD0_BUS_WKUP_TCK_OUT", "Output clock"},
+       [102] = {157, 102, "DEV_BOARD0_BUS_SPI3CLK_OUT", "Output clock"},
+       [103] = {157, 103, "DEV_BOARD0_BUS_USB0REFCLKM_OUT", "Output clock"},
+       [104] = {157, 104, "DEV_BOARD0_BUS_MCU_RGMII1_RCLK_OUT", "Output clock"},
+       [105] = {157, 105, "DEV_BOARD0_BUS_MCASP0AHCLKR_OUT", "Output clock"},
+       [106] = {157, 106, "DEV_BOARD0_BUS_MCU_EXT_REFCLK0_OUT", "Output clock"},
+       [107] = {157, 107, "DEV_BOARD0_BUS_MCASP0AHCLKX_OUT", "Output clock"},
+       [108] = {157, 108, "DEV_BOARD0_BUS_CCDC0_PCLK_OUT", "Output clock"},
+       [109] = {157, 109, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"},
+       [110] = {157, 110, "DEV_BOARD0_BUS_MCU_OSPI1DQS_OUT", "Output clock"},
+       [111] = {157, 111, "DEV_BOARD0_BUS_MCASP1AHCLKX_OUT", "Output clock"},
+       [112] = {157, 112, "DEV_BOARD0_BUS_PCIE1REFCLKM_OUT", "Output clock"},
+       [113] = {157, 113, "DEV_BOARD0_BUS_MCASP1AHCLKR_OUT", "Output clock"},
+       [114] = {157, 114, "DEV_BOARD0_BUS_PCIE1REFCLKP_OUT", "Output clock"},
+       [115] = {157, 115, "DEV_BOARD0_BUS_PRG2_RGMII1_RCLK_OUT", "Output clock"},
+       [116] = {157, 116, "DEV_BOARD0_BUS_SPI0CLK_OUT", "Output clock"},
+       [117] = {157, 117, "DEV_BOARD0_BUS_MCU_HYPERBUS_CLK_IN", "Input clock"},
+       [118] = {157, 118, "DEV_BOARD0_BUS_MCU_HYPERBUS_NCLK_IN", "Input clock"},
+       [119] = {2, 0, "DEV_CAL0_BUS_CLK", "Input clock"},
+       [120] = {2, 1, "DEV_CAL0_BUS_CP_C_CLK", "Input clock"},
+       [121] = {82, 0, "DEV_CBASS0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
+       [122] = {82, 1, "DEV_CBASS0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
+       [123] = {83, 0, "DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
+       [124] = {83, 1, "DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
+       [125] = {84, 0, "DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
+       [126] = {84, 1, "DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
+       [127] = {85, 0, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK", "Input muxed clock"},
+       [128] = {85, 1, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+       [129] = {85, 2, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+       [130] = {85, 3, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+       [131] = {85, 4, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+       [132] = {85, 5, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+       [133] = {85, 6, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+       [134] = {85, 7, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+       [135] = {85, 8, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+       [136] = {85, 9, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
+       [137] = {85, 10, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
+       [138] = {66, 0, "DEV_CCDEBUGSS0_BUS_ATB1_CLK", "Input clock"},
+       [139] = {66, 1, "DEV_CCDEBUGSS0_BUS_ATB0_CLK", "Input clock"},
+       [140] = {66, 2, "DEV_CCDEBUGSS0_BUS_SYS_CLK", "Input clock"},
+       [141] = {66, 3, "DEV_CCDEBUGSS0_BUS_DBG_CLK", "Input clock"},
+       [142] = {66, 4, "DEV_CCDEBUGSS0_BUS_CFG_CLK", "Input clock"},
+       [143] = {3, 0, "DEV_CMPEVENT_INTRTR0_BUS_INTR_CLK", "Input clock"},
+       [144] = {202, 0, "DEV_COMPUTE_CLUSTER_A53_0_BUS_ARM0_CLK", "Input clock"},
+       [145] = {203, 0, "DEV_COMPUTE_CLUSTER_A53_1_BUS_ARM0_CLK", "Input clock"},
+       [146] = {204, 0, "DEV_COMPUTE_CLUSTER_A53_2_BUS_ARM1_CLK", "Input clock"},
+       [147] = {205, 0, "DEV_COMPUTE_CLUSTER_A53_3_BUS_ARM1_CLK", "Input clock"},
+       [148] = {198, 0, "DEV_COMPUTE_CLUSTER_CPAC0_BUS_ARM0_CLK", "Input clock"},
+       [149] = {200, 0, "DEV_COMPUTE_CLUSTER_CPAC1_BUS_ARM1_CLK", "Input clock"},
+       [150] = {196, 0, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_DMSC_CLK", "Input clock"},
+       [151] = {196, 1, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_DBG_CLK", "Input clock"},
+       [152] = {196, 2, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_MSMC_CLK", "Input clock"},
+       [153] = {196, 3, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_CFG_CLK", "Input clock"},
+       [154] = {196, 4, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_GIC_CLK", "Input clock"},
+       [155] = {6, 0, "DEV_CPT2_AGGR0_BUS_VCLK_CLK", "Input clock"},
+       [156] = {213, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_VBUS_CLK", "Input clock"},
+       [157] = {213, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_PROBE_CLK", "Input clock"},
+       [158] = {214, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_VBUS_CLK", "Input clock"},
+       [159] = {214, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_PROBE_CLK", "Input clock"},
+       [160] = {211, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_VBUS_CLK", "Input clock"},
+       [161] = {211, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_PROBE_CLK", "Input clock"},
+       [162] = {212, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_VBUS_CLK", "Input clock"},
+       [163] = {212, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_PROBE_CLK", "Input clock"},
+       [164] = {209, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_VBUS_CLK", "Input clock"},
+       [165] = {209, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_PROBE_CLK", "Input clock"},
+       [166] = {206, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_VBUS_CLK", "Input clock"},
+       [167] = {206, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_PROBE_CLK", "Input clock"},
+       [168] = {208, 0, "DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_VBUS_CLK", "Input clock"},
+       [169] = {208, 1, "DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_PROBE_CLK", "Input clock"},
+       [170] = {215, 0, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_VBUS_CLK", "Input clock"},
+       [171] = {215, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_PROBE_CLK", "Input clock"},
+       [172] = {207, 0, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_VBUS_CLK", "Input clock"},
+       [173] = {207, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_PROBE_CLK", "Input clock"},
+       [174] = {210, 0, "DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_VBUS_CLK", "Input clock"},
+       [175] = {210, 1, "DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_PROBE_CLK", "Input clock"},
+       [176] = {99, 0, "DEV_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"},
+       [177] = {9, 0, "DEV_DCC0_BUS_DCC_INPUT00_CLK", "Input clock"},
+       [178] = {9, 1, "DEV_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       [179] = {9, 2, "DEV_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       [180] = {9, 3, "DEV_DCC0_BUS_VBUS_CLK", "Input clock"},
+       [181] = {9, 4, "DEV_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       [182] = {9, 5, "DEV_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"},
+       [183] = {9, 6, "DEV_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       [184] = {9, 7, "DEV_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"},
+       [185] = {9, 8, "DEV_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       [186] = {9, 9, "DEV_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       [187] = {9, 10, "DEV_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"},
+       [188] = {9, 11, "DEV_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       [189] = {10, 0, "DEV_DCC1_BUS_DCC_INPUT00_CLK", "Input clock"},
+       [190] = {10, 1, "DEV_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       [191] = {10, 2, "DEV_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       [192] = {10, 3, "DEV_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       [193] = {10, 4, "DEV_DCC1_BUS_VBUS_CLK", "Input clock"},
+       [194] = {10, 5, "DEV_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       [195] = {10, 6, "DEV_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"},
+       [196] = {10, 7, "DEV_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       [197] = {10, 8, "DEV_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"},
+       [198] = {10, 9, "DEV_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       [199] = {10, 10, "DEV_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       [200] = {10, 11, "DEV_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"},
+       [201] = {10, 12, "DEV_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       [202] = {11, 0, "DEV_DCC2_BUS_DCC_INPUT00_CLK", "Input clock"},
+       [203] = {11, 1, "DEV_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       [204] = {11, 2, "DEV_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       [205] = {11, 3, "DEV_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       [206] = {11, 4, "DEV_DCC2_BUS_VBUS_CLK", "Input clock"},
+       [207] = {11, 5, "DEV_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       [208] = {11, 6, "DEV_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"},
+       [209] = {11, 7, "DEV_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       [210] = {11, 8, "DEV_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"},
+       [211] = {11, 9, "DEV_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       [212] = {11, 10, "DEV_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       [213] = {11, 11, "DEV_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"},
+       [214] = {11, 12, "DEV_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       [215] = {12, 0, "DEV_DCC3_BUS_DCC_INPUT00_CLK", "Input clock"},
+       [216] = {12, 1, "DEV_DCC3_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       [217] = {12, 2, "DEV_DCC3_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       [218] = {12, 3, "DEV_DCC3_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       [219] = {12, 4, "DEV_DCC3_BUS_VBUS_CLK", "Input clock"},
+       [220] = {12, 5, "DEV_DCC3_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       [221] = {12, 6, "DEV_DCC3_BUS_DCC_INPUT01_CLK", "Input clock"},
+       [222] = {12, 7, "DEV_DCC3_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       [223] = {12, 8, "DEV_DCC3_BUS_DCC_INPUT02_CLK", "Input clock"},
+       [224] = {12, 9, "DEV_DCC3_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       [225] = {12, 10, "DEV_DCC3_BUS_DCC_INPUT10_CLK", "Input clock"},
+       [226] = {12, 11, "DEV_DCC3_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       [227] = {13, 0, "DEV_DCC4_BUS_DCC_INPUT00_CLK", "Input clock"},
+       [228] = {13, 1, "DEV_DCC4_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       [229] = {13, 2, "DEV_DCC4_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       [230] = {13, 3, "DEV_DCC4_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       [231] = {13, 4, "DEV_DCC4_BUS_VBUS_CLK", "Input clock"},
+       [232] = {13, 5, "DEV_DCC4_BUS_DCC_INPUT01_CLK", "Input clock"},
+       [233] = {13, 6, "DEV_DCC4_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       [234] = {13, 7, "DEV_DCC4_BUS_DCC_INPUT02_CLK", "Input clock"},
+       [235] = {13, 8, "DEV_DCC4_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       [236] = {13, 9, "DEV_DCC4_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       [237] = {13, 10, "DEV_DCC4_BUS_DCC_INPUT10_CLK", "Input clock"},
+       [238] = {13, 11, "DEV_DCC4_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       [239] = {14, 0, "DEV_DCC5_BUS_DCC_INPUT00_CLK", "Input clock"},
+       [240] = {14, 1, "DEV_DCC5_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       [241] = {14, 2, "DEV_DCC5_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       [242] = {14, 3, "DEV_DCC5_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       [243] = {14, 4, "DEV_DCC5_BUS_VBUS_CLK", "Input clock"},
+       [244] = {14, 5, "DEV_DCC5_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       [245] = {14, 6, "DEV_DCC5_BUS_DCC_INPUT01_CLK", "Input clock"},
+       [246] = {14, 7, "DEV_DCC5_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       [247] = {14, 8, "DEV_DCC5_BUS_DCC_INPUT02_CLK", "Input clock"},
+       [248] = {14, 9, "DEV_DCC5_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       [249] = {14, 10, "DEV_DCC5_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       [250] = {14, 11, "DEV_DCC5_BUS_DCC_INPUT10_CLK", "Input clock"},
+       [251] = {14, 12, "DEV_DCC5_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       [252] = {15, 0, "DEV_DCC6_BUS_DCC_INPUT00_CLK", "Input clock"},
+       [253] = {15, 1, "DEV_DCC6_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       [254] = {15, 2, "DEV_DCC6_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       [255] = {15, 3, "DEV_DCC6_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       [256] = {15, 4, "DEV_DCC6_BUS_VBUS_CLK", "Input clock"},
+       [257] = {15, 5, "DEV_DCC6_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       [258] = {15, 6, "DEV_DCC6_BUS_DCC_INPUT01_CLK", "Input clock"},
+       [259] = {15, 7, "DEV_DCC6_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       [260] = {15, 8, "DEV_DCC6_BUS_DCC_INPUT02_CLK", "Input clock"},
+       [261] = {15, 9, "DEV_DCC6_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       [262] = {15, 10, "DEV_DCC6_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       [263] = {15, 11, "DEV_DCC6_BUS_DCC_INPUT10_CLK", "Input clock"},
+       [264] = {15, 12, "DEV_DCC6_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       [265] = {16, 0, "DEV_DCC7_BUS_DCC_INPUT00_CLK", "Input clock"},
+       [266] = {16, 1, "DEV_DCC7_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       [267] = {16, 2, "DEV_DCC7_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       [268] = {16, 3, "DEV_DCC7_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       [269] = {16, 4, "DEV_DCC7_BUS_VBUS_CLK", "Input clock"},
+       [270] = {16, 5, "DEV_DCC7_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       [271] = {16, 6, "DEV_DCC7_BUS_DCC_INPUT01_CLK", "Input clock"},
+       [272] = {16, 7, "DEV_DCC7_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       [273] = {16, 8, "DEV_DCC7_BUS_DCC_INPUT02_CLK", "Input clock"},
+       [274] = {16, 9, "DEV_DCC7_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       [275] = {16, 10, "DEV_DCC7_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       [276] = {16, 11, "DEV_DCC7_BUS_DCC_INPUT10_CLK", "Input clock"},
+       [277] = {16, 12, "DEV_DCC7_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       [278] = {20, 0, "DEV_DDRSS0_BUS_DDRSS_VBUS_CLK", "Input clock"},
+       [279] = {20, 1, "DEV_DDRSS0_BUS_DDRSS_BYP_4X_CLK", "Input clock"},
+       [280] = {20, 2, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
+       [281] = {20, 3, "DEV_DDRSS0_BUS_DDRSS_TCLK", "Input clock"},
+       [282] = {20, 4, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
+       [283] = {20, 5, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
+       [284] = {20, 6, "DEV_DDRSS0_BUS_DDRSS_CFG_CLK", "Input clock"},
+       [285] = {20, 7, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
+       [286] = {20, 8, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
+       [287] = {20, 9, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
+       [288] = {68, 0, "DEV_DEBUGSS0_BUS_ATB1_CLK", "Input clock"},
+       [289] = {68, 1, "DEV_DEBUGSS0_BUS_ATB5_CLK", "Input clock"},
+       [290] = {68, 2, "DEV_DEBUGSS0_BUS_ATB0_CLK", "Input clock"},
+       [291] = {68, 3, "DEV_DEBUGSS0_BUS_SYS_CLK", "Input clock"},
+       [292] = {68, 4, "DEV_DEBUGSS0_BUS_ATB4_CLK", "Input clock"},
+       [293] = {68, 5, "DEV_DEBUGSS0_BUS_CFG_CLK", "Input clock"},
+       [294] = {68, 6, "DEV_DEBUGSS0_BUS_ATB2_CLK", "Input clock"},
+       [295] = {68, 7, "DEV_DEBUGSS0_BUS_DBG_CLK", "Input clock"},
+       [296] = {68, 8, "DEV_DEBUGSS0_BUS_ATB3_CLK", "Input clock"},
+       [297] = {21, 0, "DEV_DEBUGSS_WRAP0_BUS_JTAG_TCK", "Input clock"},
+       [298] = {21, 1, "DEV_DEBUGSS_WRAP0_BUS_ATB_CLK", "Input clock"},
+       [299] = {21, 2, "DEV_DEBUGSS_WRAP0_BUS_TREXPT_CLK", "Input clock"},
+       [300] = {21, 3, "DEV_DEBUGSS_WRAP0_BUS_CORE_CLK", "Input clock"},
+       [301] = {81, 0, "DEV_DEBUGSUSPENDRTR0_BUS_INTR_CLK", "Input clock"},
+       [302] = {117, 0, "DEV_DFTSS0_BUS_VBUSP_CLK_CLK", "Input clock"},
+       [303] = {67, 0, "DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN1_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"},
+       [304] = {67, 1, "DEV_DSS0_BUS_DSS_FUNC_CLK", "Input clock"},
+       [305] = {67, 2, "DEV_DSS0_BUS_DPI_1_IN_CLK", "Input muxed clock"},
+       [306] = {67, 3, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_CLOCKDIVIDER_DSS_BUS_OUT07", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"},
+       [307] = {67, 4, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_BOARD_0_BUS_DSS0EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"},
+       [308] = {67, 5, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_CLOCKDIVIDER_DSS_BUS_OUT1", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"},
+       [309] = {67, 6, "DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN0_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"},
+       [310] = {67, 7, "DEV_DSS0_BUS_DPI_1_OUT_CLK", "Output clock"},
+       [311] = {39, 0, "DEV_ECAP0_BUS_VBUS_CLK", "Input clock"},
+       [312] = {86, 0, "DEV_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"},
+       [313] = {87, 0, "DEV_ECC_AGGR1_BUS_AGGR_CLK", "Input clock"},
+       [314] = {88, 0, "DEV_ECC_AGGR2_BUS_AGGR_CLK", "Input clock"},
+       [315] = {69, 0, "DEV_EFUSE0_BUS_VBUSP_PLL_CLK_CLK", "Input clock"},
+       [316] = {69, 1, "DEV_EFUSE0_BUS_EFC1_CTL_FCLK", "Output clock"},
+       [317] = {69, 2, "DEV_EFUSE0_BUS_EFC0_CTL_FCLK", "Output clock"},
+       [318] = {40, 0, "DEV_EHRPWM0_BUS_VBUSP_CLK", "Input clock"},
+       [319] = {41, 0, "DEV_EHRPWM1_BUS_VBUSP_CLK", "Input clock"},
+       [320] = {42, 0, "DEV_EHRPWM2_BUS_VBUSP_CLK", "Input clock"},
+       [321] = {43, 0, "DEV_EHRPWM3_BUS_VBUSP_CLK", "Input clock"},
+       [322] = {44, 0, "DEV_EHRPWM4_BUS_VBUSP_CLK", "Input clock"},
+       [323] = {45, 0, "DEV_EHRPWM5_BUS_VBUSP_CLK", "Input clock"},
+       [324] = {46, 0, "DEV_ELM0_BUS_VBUSP_CLK", "Input clock"},
+       [325] = {49, 0, "DEV_EQEP0_BUS_VBUS_CLK", "Input clock"},
+       [326] = {50, 0, "DEV_EQEP1_BUS_VBUS_CLK", "Input clock"},
+       [327] = {51, 0, "DEV_EQEP2_BUS_VBUS_CLK", "Input clock"},
+       [328] = {52, 0, "DEV_ESM0_BUS_CLK", "Input clock"},
+       [329] = {56, 0, "DEV_GIC0_BUS_VCLK_CLK", "Input clock"},
+       [330] = {57, 0, "DEV_GPIO0_BUS_MMR_CLK", "Input clock"},
+       [331] = {58, 0, "DEV_GPIO1_BUS_MMR_CLK", "Input clock"},
+       [332] = {100, 0, "DEV_GPIOMUX_INTRTR0_BUS_INTR_CLK", "Input clock"},
+       [333] = {60, 0, "DEV_GPMC0_BUS_FUNC_CLK", "Input muxed clock"},
+       [334] = {60, 1, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
+       [335] = {60, 2, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK3", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
+       [336] = {60, 3, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK2", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
+       [337] = {60, 4, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
+       [338] = {60, 5, "DEV_GPMC0_BUS_PI_GPMC_RET_CLK", "Input clock"},
+       [339] = {60, 6, "DEV_GPMC0_BUS_VBUSP_CLK", "Input clock"},
+       [340] = {60, 7, "DEV_GPMC0_BUS_PO_GPMC_DEV_CLK", "Output clock"},
+       [341] = {65, 0, "DEV_GPU0_BUS_MEM_CLK", "Input clock"},
+       [342] = {65, 1, "DEV_GPU0_BUS_HYD_CORE_CLK", "Input clock"},
+       [343] = {65, 2, "DEV_GPU0_BUS_SGX_CORE_CLK", "Input clock"},
+       [344] = {65, 3, "DEV_GPU0_BUS_SYS_CLK", "Input clock"},
+       [345] = {232, 0, "DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_OSC_CLK", "Input clock"},
+       [346] = {232, 1, "DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_CLK", "Input clock"},
+       [347] = {231, 0, "DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_OSC_CLK", "Input clock"},
+       [348] = {231, 1, "DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_CLK", "Input clock"},
+       [349] = {61, 0, "DEV_GTC0_BUS_VBUSP_CLK", "Input muxed clock"},
+       [350] = {61, 1, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+       [351] = {61, 2, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+       [352] = {61, 3, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+       [353] = {61, 4, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+       [354] = {61, 5, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+       [355] = {61, 6, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+       [356] = {61, 7, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+       [357] = {61, 8, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+       [358] = {110, 0, "DEV_I2C0_BUS_CLK", "Input clock"},
+       [359] = {110, 1, "DEV_I2C0_BUS_PISYS_CLK", "Input clock"},
+       [360] = {110, 2, "DEV_I2C0_BUS_PISCL", "Output clock"},
+       [361] = {111, 0, "DEV_I2C1_BUS_CLK", "Input clock"},
+       [362] = {111, 1, "DEV_I2C1_BUS_PISYS_CLK", "Input clock"},
+       [363] = {111, 2, "DEV_I2C1_BUS_PISCL", "Output clock"},
+       [364] = {112, 0, "DEV_I2C2_BUS_CLK", "Input clock"},
+       [365] = {112, 1, "DEV_I2C2_BUS_PISYS_CLK", "Input clock"},
+       [366] = {112, 2, "DEV_I2C2_BUS_PISCL", "Output clock"},
+       [367] = {113, 0, "DEV_I2C3_BUS_CLK", "Input clock"},
+       [368] = {113, 1, "DEV_I2C3_BUS_PISYS_CLK", "Input clock"},
+       [369] = {113, 2, "DEV_I2C3_BUS_PISCL", "Output clock"},
+       [370] = {217, 0, "DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0_BUS_DBG_CLK", "Input clock"},
+       [371] = {97, 0, "DEV_MAIN2MCU_LVL_INTRTR0_BUS_INTR_CLK", "Input clock"},
+       [372] = {98, 0, "DEV_MAIN2MCU_PLS_INTRTR0_BUS_INTR_CLK", "Input clock"},
+       [373] = {104, 0, "DEV_MCASP0_BUS_AUX_CLK", "Input muxed clock"},
+       [374] = {104, 1, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+       [375] = {104, 2, "DEV_MCASP0_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+       [376] = {104, 3, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+       [377] = {104, 4, "DEV_MCASP0_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+       [378] = {104, 5, "DEV_MCASP0_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+       [379] = {104, 6, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+       [380] = {104, 7, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+       [381] = {104, 8, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+       [382] = {104, 9, "DEV_MCASP0_BUS_VBUSP_CLK", "Input clock"},
+       [383] = {104, 10, "DEV_MCASP0_BUS_MCASP_AHCLKX_PIN", "Input clock"},
+       [384] = {104, 11, "DEV_MCASP0_BUS_MCASP_AHCLKR_PIN", "Input clock"},
+       [385] = {105, 0, "DEV_MCASP1_BUS_AUX_CLK", "Input muxed clock"},
+       [386] = {105, 1, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+       [387] = {105, 2, "DEV_MCASP1_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+       [388] = {105, 3, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+       [389] = {105, 4, "DEV_MCASP1_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+       [390] = {105, 5, "DEV_MCASP1_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+       [391] = {105, 6, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+       [392] = {105, 7, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+       [393] = {105, 8, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+       [394] = {105, 9, "DEV_MCASP1_BUS_VBUSP_CLK", "Input clock"},
+       [395] = {105, 10, "DEV_MCASP1_BUS_MCASP_AHCLKX_PIN", "Input clock"},
+       [396] = {105, 11, "DEV_MCASP1_BUS_MCASP_AHCLKR_PIN", "Input clock"},
+       [397] = {106, 0, "DEV_MCASP2_BUS_AUX_CLK", "Input muxed clock"},
+       [398] = {106, 1, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+       [399] = {106, 2, "DEV_MCASP2_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+       [400] = {106, 3, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+       [401] = {106, 4, "DEV_MCASP2_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+       [402] = {106, 5, "DEV_MCASP2_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT2", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+       [403] = {106, 6, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+       [404] = {106, 7, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+       [405] = {106, 8, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+       [406] = {106, 9, "DEV_MCASP2_BUS_VBUSP_CLK", "Input clock"},
+       [407] = {106, 10, "DEV_MCASP2_BUS_MCASP_AHCLKX_PIN", "Input clock"},
+       [408] = {106, 11, "DEV_MCASP2_BUS_MCASP_AHCLKR_PIN", "Input clock"},
+       [409] = {137, 0, "DEV_MCSPI0_BUS_IO_CLKSPII_CLK", "Input clock"},
+       [410] = {137, 1, "DEV_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"},
+       [411] = {137, 2, "DEV_MCSPI0_BUS_VBUSP_CLK", "Input clock"},
+       [412] = {137, 3, "DEV_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"},
+       [413] = {138, 0, "DEV_MCSPI1_BUS_IO_CLKSPII_CLK", "Input clock"},
+       [414] = {138, 1, "DEV_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"},
+       [415] = {138, 2, "DEV_MCSPI1_BUS_VBUSP_CLK", "Input clock"},
+       [416] = {138, 3, "DEV_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"},
+       [417] = {139, 0, "DEV_MCSPI2_BUS_IO_CLKSPII_CLK", "Input clock"},
+       [418] = {139, 1, "DEV_MCSPI2_BUS_CLKSPIREF_CLK", "Input clock"},
+       [419] = {139, 2, "DEV_MCSPI2_BUS_VBUSP_CLK", "Input clock"},
+       [420] = {139, 3, "DEV_MCSPI2_BUS_IO_CLKSPIO_CLK", "Output clock"},
+       [421] = {140, 0, "DEV_MCSPI3_BUS_IO_CLKSPII_CLK", "Input clock"},
+       [422] = {140, 1, "DEV_MCSPI3_BUS_CLKSPIREF_CLK", "Input clock"},
+       [423] = {140, 2, "DEV_MCSPI3_BUS_VBUSP_CLK", "Input clock"},
+       [424] = {140, 3, "DEV_MCSPI3_BUS_IO_CLKSPIO_CLK", "Output clock"},
+       [425] = {141, 0, "DEV_MCSPI4_BUS_CLKSPIREF_CLK", "Input clock"},
+       [426] = {141, 1, "DEV_MCSPI4_BUS_VBUSP_CLK", "Input clock"},
+       [427] = {0, 0, "DEV_MCU_ADC0_BUS_VBUS_CLK", "Input clock"},
+       [428] = {0, 1, "DEV_MCU_ADC0_BUS_SYS_CLK", "Input clock"},
+       [429] = {0, 2, "DEV_MCU_ADC0_BUS_ADC_CLK", "Input muxed clock"},
+       [430] = {0, 3, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
+       [431] = {0, 4, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
+       [432] = {0, 5, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
+       [433] = {0, 6, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
+       [434] = {1, 0, "DEV_MCU_ADC1_BUS_VBUS_CLK", "Input clock"},
+       [435] = {1, 1, "DEV_MCU_ADC1_BUS_SYS_CLK", "Input clock"},
+       [436] = {1, 2, "DEV_MCU_ADC1_BUS_ADC_CLK", "Input muxed clock"},
+       [437] = {1, 3, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
+       [438] = {1, 4, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
+       [439] = {1, 5, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
+       [440] = {1, 6, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
+       [441] = {129, 0, "DEV_MCU_ARMSS0_BUS_INTERFACE_CLK", "Input clock"},
+       [442] = {159, 0, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_CLK", "Input clock"},
+       [443] = {159, 1, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE", "Input muxed clock"},
+       [444] = {159, 2, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE"},
+       [445] = {159, 3, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK", "Input muxed clock"},
+       [446] = {159, 4, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"},
+       [447] = {159, 5, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"},
+       [448] = {245, 0, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_CLK", "Input clock"},
+       [449] = {245, 1, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE", "Input muxed clock"},
+       [450] = {245, 2, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE"},
+       [451] = {245, 3, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK", "Input muxed clock"},
+       [452] = {245, 4, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"},
+       [453] = {245, 5, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"},
+       [454] = {89, 0, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_8_CLK", "Input clock"},
+       [455] = {89, 1, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_4_CLK", "Input clock"},
+       [456] = {89, 2, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"},
+       [457] = {90, 0, "DEV_MCU_CBASS_DEBUG0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"},
+       [458] = {91, 0, "DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_4_CLK", "Input clock"},
+       [459] = {91, 1, "DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"},
+       [460] = {5, 0, "DEV_MCU_CPSW0_BUS_GMII1_MR_CLK", "Input clock"},
+       [461] = {5, 1, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_250_CLK", "Input clock"},
+       [462] = {5, 2, "DEV_MCU_CPSW0_BUS_CPTS_RFT_CLK", "Input clock"},
+       [463] = {5, 3, "DEV_MCU_CPSW0_BUS_GMII1_MT_CLK", "Input clock"},
+       [464] = {5, 4, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_5_CLK", "Input clock"},
+       [465] = {5, 5, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_50_CLK", "Input clock"},
+       [466] = {5, 6, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK", "Input muxed clock"},
+       [467] = {5, 7, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"},
+       [468] = {5, 8, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_BOARD_0_BUS_MCU_RMII1_REFCLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"},
+       [469] = {5, 9, "DEV_MCU_CPSW0_BUS_GMII_RFT_CLK", "Input clock"},
+       [470] = {5, 10, "DEV_MCU_CPSW0_BUS_CPPI_CLK_CLK", "Input clock"},
+       [471] = {5, 11, "DEV_MCU_CPSW0_BUS_CPTS_GENF0_0", "Output clock"},
+       [472] = {7, 0, "DEV_MCU_CPT2_AGGR0_BUS_VCLK_CLK", "Input clock"},
+       [473] = {107, 0, "DEV_MCU_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"},
+       [474] = {17, 0, "DEV_MCU_DCC0_BUS_DCC_INPUT00_CLK", "Input clock"},
+       [475] = {17, 1, "DEV_MCU_DCC0_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       [476] = {17, 2, "DEV_MCU_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       [477] = {17, 3, "DEV_MCU_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       [478] = {17, 4, "DEV_MCU_DCC0_BUS_VBUS_CLK", "Input clock"},
+       [479] = {17, 5, "DEV_MCU_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       [480] = {17, 6, "DEV_MCU_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"},
+       [481] = {17, 7, "DEV_MCU_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       [482] = {17, 8, "DEV_MCU_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"},
+       [483] = {17, 9, "DEV_MCU_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       [484] = {17, 10, "DEV_MCU_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       [485] = {17, 11, "DEV_MCU_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"},
+       [486] = {17, 12, "DEV_MCU_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       [487] = {18, 0, "DEV_MCU_DCC1_BUS_DCC_INPUT00_CLK", "Input clock"},
+       [488] = {18, 1, "DEV_MCU_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       [489] = {18, 2, "DEV_MCU_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       [490] = {18, 3, "DEV_MCU_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       [491] = {18, 4, "DEV_MCU_DCC1_BUS_VBUS_CLK", "Input clock"},
+       [492] = {18, 5, "DEV_MCU_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       [493] = {18, 6, "DEV_MCU_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"},
+       [494] = {18, 7, "DEV_MCU_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       [495] = {18, 8, "DEV_MCU_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"},
+       [496] = {18, 9, "DEV_MCU_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       [497] = {18, 10, "DEV_MCU_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       [498] = {18, 11, "DEV_MCU_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"},
+       [499] = {18, 12, "DEV_MCU_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       [500] = {19, 0, "DEV_MCU_DCC2_BUS_DCC_INPUT00_CLK", "Input clock"},
+       [501] = {19, 1, "DEV_MCU_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       [502] = {19, 2, "DEV_MCU_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       [503] = {19, 3, "DEV_MCU_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       [504] = {19, 4, "DEV_MCU_DCC2_BUS_VBUS_CLK", "Input clock"},
+       [505] = {19, 5, "DEV_MCU_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       [506] = {19, 6, "DEV_MCU_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"},
+       [507] = {19, 7, "DEV_MCU_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       [508] = {19, 8, "DEV_MCU_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"},
+       [509] = {19, 9, "DEV_MCU_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       [510] = {19, 10, "DEV_MCU_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       [511] = {19, 11, "DEV_MCU_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"},
+       [512] = {19, 12, "DEV_MCU_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       [513] = {71, 0, "DEV_MCU_DEBUGSS0_BUS_ATB1_CLK", "Input clock"},
+       [514] = {71, 1, "DEV_MCU_DEBUGSS0_BUS_ATB0_CLK", "Input clock"},
+       [515] = {71, 2, "DEV_MCU_DEBUGSS0_BUS_SYS_CLK", "Input clock"},
+       [516] = {71, 3, "DEV_MCU_DEBUGSS0_BUS_CFG_CLK", "Input clock"},
+       [517] = {71, 4, "DEV_MCU_DEBUGSS0_BUS_ATB2_CLK", "Input clock"},
+       [518] = {71, 5, "DEV_MCU_DEBUGSS0_BUS_DBG_CLK", "Input clock"},
+       [519] = {71, 6, "DEV_MCU_DEBUGSS0_BUS_ATB3_CLK", "Input clock"},
+       [520] = {92, 0, "DEV_MCU_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"},
+       [521] = {93, 0, "DEV_MCU_ECC_AGGR1_BUS_AGGR_CLK", "Input clock"},
+       [522] = {72, 0, "DEV_MCU_EFUSE0_BUS_VBUSP_CLK_CLK", "Input clock"},
+       [523] = {72, 1, "DEV_MCU_EFUSE0_BUS_EFC3_CTL_FCLK", "Output clock"},
+       [524] = {72, 2, "DEV_MCU_EFUSE0_BUS_EFC0_CTL_FCLK", "Output clock"},
+       [525] = {72, 3, "DEV_MCU_EFUSE0_BUS_EFC1_CTL_FCLK", "Output clock"},
+       [526] = {72, 4, "DEV_MCU_EFUSE0_BUS_EFC2_CTL_FCLK", "Output clock"},
+       [527] = {53, 0, "DEV_MCU_ESM0_BUS_CLK", "Input clock"},
+       [528] = {247, 0, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_INV_CLK", "Input clock"},
+       [529] = {247, 1, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_CLK", "Input clock"},
+       [530] = {247, 2, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX2_CLK", "Input clock"},
+       [531] = {247, 3, "DEV_MCU_FSS0_HYPERBUS0_BUS_CBA_CLK", "Input clock"},
+       [532] = {247, 4, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX2_INV_CLK", "Input clock"},
+       [533] = {247, 5, "DEV_MCU_FSS0_HYPERBUS0_HPB_OUT_CLK_N", "Output clock"},
+       [534] = {247, 6, "DEV_MCU_FSS0_HYPERBUS0_HPB_OUT_CLK_P", "Output clock"},
+       [535] = {248, 0, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK", "Input muxed clock"},
+       [536] = {248, 1, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK"},
+       [537] = {248, 2, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK"},
+       [538] = {248, 3, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK", "Input muxed clock"},
+       [539] = {248, 4, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI0DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK"},
+       [540] = {248, 5, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_BUS_OSPI0_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK"},
+       [541] = {248, 6, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_PCLK_CLK", "Input clock"},
+       [542] = {248, 7, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_DQS_CLK", "Input clock"},
+       [543] = {248, 8, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_HCLK_CLK", "Input clock"},
+       [544] = {248, 9, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_OCLK_CLK", "Output clock"},
+       [545] = {249, 0, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_PCLK_CLK", "Input clock"},
+       [546] = {249, 1, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK", "Input muxed clock"},
+       [547] = {249, 2, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI1DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK"},
+       [548] = {249, 3, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_BUS_OSPI1_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK"},
+       [549] = {249, 4, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_HCLK_CLK", "Input clock"},
+       [550] = {249, 5, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_DQS_CLK", "Input clock"},
+       [551] = {249, 6, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK", "Input muxed clock"},
+       [552] = {249, 7, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK"},
+       [553] = {249, 8, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK"},
+       [554] = {249, 9, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_OCLK_CLK", "Output clock"},
+       [555] = {114, 0, "DEV_MCU_I2C0_BUS_CLK", "Input clock"},
+       [556] = {114, 1, "DEV_MCU_I2C0_BUS_PISYS_CLK", "Input clock"},
+       [557] = {114, 2, "DEV_MCU_I2C0_BUS_PISCL", "Output clock"},
+       [558] = {102, 0, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [559] = {102, 1, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
+       [560] = {102, 2, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
+       [561] = {102, 3, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
+       [562] = {102, 4, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
+       [563] = {102, 5, "DEV_MCU_MCAN0_BUS_MCANSS_HCLK_CLK", "Input clock"},
+       [564] = {103, 0, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK", "Input muxed clock"},
+       [565] = {103, 1, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
+       [566] = {103, 2, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
+       [567] = {103, 3, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
+       [568] = {103, 4, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
+       [569] = {103, 5, "DEV_MCU_MCAN1_BUS_MCANSS_HCLK_CLK", "Input clock"},
+       [570] = {142, 0, "DEV_MCU_MCSPI0_BUS_IO_CLKSPII_CLK", "Input clock"},
+       [571] = {142, 1, "DEV_MCU_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"},
+       [572] = {142, 2, "DEV_MCU_MCSPI0_BUS_VBUSP_CLK", "Input clock"},
+       [573] = {142, 3, "DEV_MCU_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"},
+       [574] = {143, 0, "DEV_MCU_MCSPI1_BUS_IO_CLKSPII_CLK", "Input clock"},
+       [575] = {143, 1, "DEV_MCU_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"},
+       [576] = {143, 2, "DEV_MCU_MCSPI1_BUS_VBUSP_CLK", "Input clock"},
+       [577] = {143, 3, "DEV_MCU_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"},
+       [578] = {144, 0, "DEV_MCU_MCSPI2_BUS_CLKSPIREF_CLK", "Input clock"},
+       [579] = {144, 1, "DEV_MCU_MCSPI2_BUS_VBUSP_CLK", "Input clock"},
+       [580] = {116, 0, "DEV_MCU_MSRAM0_BUS_CCLK_CLK", "Input clock"},
+       [581] = {116, 1, "DEV_MCU_MSRAM0_BUS_VCLK_CLK", "Input clock"},
+       [582] = {119, 0, "DEV_MCU_NAVSS0_BUS_UDMASS_VD2CLK", "Input clock"},
+       [583] = {119, 1, "DEV_MCU_NAVSS0_BUS_CPSW0CLK", "Input clock"},
+       [584] = {119, 2, "DEV_MCU_NAVSS0_BUS_MODSS_VD2CLK", "Input clock"},
+       [585] = {119, 3, "DEV_MCU_NAVSS0_BUS_PDMA_MCU1CLK", "Input clock"},
+       [586] = {75, 0, "DEV_MCU_PBIST0_BUS_CLK1_CLK", "Input clock"},
+       [587] = {75, 1, "DEV_MCU_PBIST0_BUS_CLK4_CLK", "Input clock"},
+       [588] = {75, 2, "DEV_MCU_PBIST0_BUS_CLK2_CLK", "Input clock"},
+       [589] = {125, 0, "DEV_MCU_PDMA0_BUS_VCLK", "Input clock"},
+       [590] = {126, 0, "DEV_MCU_PDMA1_BUS_VCLK", "Input clock"},
+       [591] = {108, 0, "DEV_MCU_PLL_MMR0_BUS_VBUSP_CLK", "Input clock"},
+       [592] = {127, 0, "DEV_MCU_PSRAM0_BUS_CLK_CLK", "Input clock"},
+       [593] = {78, 0, "DEV_MCU_ROM0_BUS_CLK_CLK", "Input clock"},
+       [594] = {134, 0, "DEV_MCU_RTI0_BUS_RTI_CLK", "Input muxed clock"},
+       [595] = {134, 1, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
+       [596] = {134, 2, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
+       [597] = {134, 3, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
+       [598] = {134, 4, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
+       [599] = {134, 5, "DEV_MCU_RTI0_BUS_VBUSP_CLK", "Input clock"},
+       [600] = {135, 0, "DEV_MCU_RTI1_BUS_RTI_CLK", "Input muxed clock"},
+       [601] = {135, 1, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
+       [602] = {135, 2, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
+       [603] = {135, 3, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
+       [604] = {135, 4, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
+       [605] = {135, 5, "DEV_MCU_RTI1_BUS_VBUSP_CLK", "Input clock"},
+       [606] = {109, 0, "DEV_MCU_SEC_MMR0_BUS_VBUSP_CLK", "Input clock"},
+       [607] = {35, 0, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       [608] = {35, 1, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [609] = {35, 2, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [610] = {35, 3, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [611] = {35, 4, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [612] = {35, 5, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [613] = {35, 6, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [614] = {35, 7, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [615] = {35, 8, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [616] = {35, 9, "DEV_MCU_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"},
+       [617] = {36, 0, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       [618] = {36, 1, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [619] = {36, 2, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [620] = {36, 3, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [621] = {36, 4, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [622] = {36, 5, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [623] = {36, 6, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [624] = {36, 7, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [625] = {36, 8, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [626] = {36, 9, "DEV_MCU_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"},
+       [627] = {37, 0, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       [628] = {37, 1, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [629] = {37, 2, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [630] = {37, 3, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [631] = {37, 4, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [632] = {37, 5, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [633] = {37, 6, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [634] = {37, 7, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [635] = {37, 8, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [636] = {37, 9, "DEV_MCU_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"},
+       [637] = {38, 0, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       [638] = {38, 1, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [639] = {38, 2, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [640] = {38, 3, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [641] = {38, 4, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [642] = {38, 5, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [643] = {38, 6, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [644] = {38, 7, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [645] = {38, 8, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [646] = {38, 9, "DEV_MCU_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"},
+       [647] = {149, 0, "DEV_MCU_UART0_BUS_FCLK_CLK", "Input muxed clock"},
+       [648] = {149, 1, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"},
+       [649] = {149, 2, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"},
+       [650] = {149, 3, "DEV_MCU_UART0_BUS_VBUSP_CLK", "Input clock"},
+       [651] = {47, 0, "DEV_MMCSD0_BUS_EMMCSDSS_VBUS_CLK", "Input clock"},
+       [652] = {47, 1, "DEV_MMCSD0_BUS_EMMCSDSS_XIN_CLK", "Input clock"},
+       [653] = {48, 0, "DEV_MMCSD1_BUS_EMMCSDSS_VBUS_CLK", "Input clock"},
+       [654] = {48, 1, "DEV_MMCSD1_BUS_EMMCSDSS_XIN_CLK", "Input clock"},
+       [655] = {234, 0, "DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0_BUS_UNDEFINEDCHAIN1_FCLK", "Input clock"},
+       [656] = {234, 1, "DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0_BUS_UNDEFINEDCHAIN0_FCLK", "Input clock"},
+       [657] = {235, 0, "DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN1_FCLK", "Input clock"},
+       [658] = {235, 1, "DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN0_FCLK", "Input clock"},
+       [659] = {235, 2, "DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN2_FCLK", "Input clock"},
+       [660] = {118, 0, "DEV_NAVSS0_BUS_UDMASS_VD2CLK", "Input clock"},
+       [661] = {118, 1, "DEV_NAVSS0_BUS_ICSS_G2CLK", "Input clock"},
+       [662] = {118, 2, "DEV_NAVSS0_BUS_ICSS_G0CLK", "Input clock"},
+       [663] = {118, 3, "DEV_NAVSS0_BUS_RCLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"},
+       [664] = {118, 4, "DEV_NAVSS0_BUS_MSMC0CLK", "Input clock"},
+       [665] = {118, 5, "DEV_NAVSS0_BUS_RCLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"},
+       [666] = {118, 6, "DEV_NAVSS0_BUS_RCLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"},
+       [667] = {118, 7, "DEV_NAVSS0_BUS_MODSS_VD2CLK", "Input clock"},
+       [668] = {118, 8, "DEV_NAVSS0_BUS_RCLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"},
+       [669] = {118, 9, "DEV_NAVSS0_BUS_PDMA_MAIN1CLK", "Input clock"},
+       [670] = {118, 10, "DEV_NAVSS0_BUS_NBSS_VCLK", "Input clock"},
+       [671] = {118, 11, "DEV_NAVSS0_BUS_RCLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"},
+       [672] = {118, 12, "DEV_NAVSS0_BUS_NBSS_VD2CLK", "Input clock"},
+       [673] = {118, 13, "DEV_NAVSS0_BUS_ICSS_G1CLK", "Input clock"},
+       [674] = {118, 14, "DEV_NAVSS0_BUS_RCLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"},
+       [675] = {118, 15, "DEV_NAVSS0_BUS_CPTS0_GENF4_0", "Output clock"},
+       [676] = {118, 16, "DEV_NAVSS0_BUS_CPTS0_GENF5_0", "Output clock"},
+       [677] = {118, 17, "DEV_NAVSS0_BUS_CPTS0_GENF2_0", "Output clock"},
+       [678] = {118, 18, "DEV_NAVSS0_BUS_CPTS0_GENF3_0", "Output clock"},
+       [679] = {216, 0, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_PLL_CLK", "Input clock"},
+       [680] = {216, 1, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN1_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"},
+       [681] = {216, 2, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN0_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"},
+       [682] = {73, 0, "DEV_PBIST0_BUS_CLK1_CLK", "Input clock"},
+       [683] = {73, 1, "DEV_PBIST0_BUS_CLK4_CLK", "Input clock"},
+       [684] = {73, 2, "DEV_PBIST0_BUS_CLK2_CLK", "Input clock"},
+       [685] = {74, 0, "DEV_PBIST1_BUS_CLK1_CLK", "Input clock"},
+       [686] = {74, 1, "DEV_PBIST1_BUS_CLK4_CLK", "Input clock"},
+       [687] = {74, 2, "DEV_PBIST1_BUS_CLK2_CLK", "Input clock"},
+       [688] = {120, 0, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"},
+       [689] = {120, 1, "DEV_PCIE0_BUS_PCIE_CBA_CLK", "Input clock"},
+       [690] = {120, 2, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"},
+       [691] = {120, 3, "DEV_PCIE0_BUS_PCIE_TXI0_CLK", "Input clock"},
+       [692] = {120, 4, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"},
+       [693] = {120, 5, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"},
+       [694] = {120, 6, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"},
+       [695] = {120, 7, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"},
+       [696] = {120, 8, "DEV_PCIE0_BUS_PCIE_TXR1_CLK", "Output clock"},
+       [697] = {120, 9, "DEV_PCIE0_BUS_PCIE_TXR0_CLK", "Output clock"},
+       [698] = {121, 0, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"},
+       [699] = {121, 1, "DEV_PCIE1_BUS_PCIE_CBA_CLK", "Input clock"},
+       [700] = {121, 2, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"},
+       [701] = {121, 3, "DEV_PCIE1_BUS_PCIE_TXI0_CLK", "Input clock"},
+       [702] = {121, 4, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"},
+       [703] = {121, 5, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"},
+       [704] = {121, 6, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"},
+       [705] = {121, 7, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"},
+       [706] = {121, 8, "DEV_PCIE1_BUS_PCIE_TXR0_CLK", "Output clock"},
+       [707] = {123, 0, "DEV_PDMA0_BUS_VCLK", "Input clock"},
+       [708] = {124, 0, "DEV_PDMA1_BUS_VCLK", "Input clock"},
+       [709] = {122, 0, "DEV_PDMA_DEBUG0_BUS_VCLK", "Input clock"},
+       [710] = {76, 0, "DEV_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK", "Input clock"},
+       [711] = {76, 1, "DEV_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"},
+       [712] = {76, 2, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input muxed clock"},
+       [713] = {76, 3, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"},
+       [714] = {76, 4, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"},
+       [715] = {101, 0, "DEV_PLL_MMR0_BUS_VBUSP_CLK", "Input clock"},
+       [716] = {62, 0, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_5_CLK", "Input clock"},
+       [717] = {62, 1, "DEV_PRU_ICSSG0_BUS_WIZ1_TX_SLV_CLK", "Input clock"},
+       [718] = {62, 2, "DEV_PRU_ICSSG0_BUS_WIZ0_RX_SLV_CLK", "Input clock"},
+       [719] = {62, 3, "DEV_PRU_ICSSG0_BUS_VCLK_CLK", "Input clock"},
+       [720] = {62, 4, "DEV_PRU_ICSSG0_BUS_UCLK_CLK", "Input clock"},
+       [721] = {62, 5, "DEV_PRU_ICSSG0_BUS_WIZ0_TX_SLV_CLK", "Input clock"},
+       [722] = {62, 6, "DEV_PRU_ICSSG0_BUS_WIZ1_RX_SLV_CLK", "Input clock"},
+       [723] = {62, 7, "DEV_PRU_ICSSG0_BUS_PR1_RGMII1_RXC_I", "Input clock"},
+       [724] = {62, 8, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_250_CLK", "Input clock"},
+       [725] = {62, 9, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_50_CLK", "Input clock"},
+       [726] = {62, 10, "DEV_PRU_ICSSG0_BUS_IEP_CLK", "Input muxed clock"},
+       [727] = {62, 11, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+       [728] = {62, 12, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+       [729] = {62, 13, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+       [730] = {62, 14, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+       [731] = {62, 15, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+       [732] = {62, 16, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+       [733] = {62, 17, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+       [734] = {62, 18, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+       [735] = {62, 19, "DEV_PRU_ICSSG0_BUS_CORE_CLK", "Input muxed clock"},
+       [736] = {62, 20, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"},
+       [737] = {62, 21, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"},
+       [738] = {62, 22, "DEV_PRU_ICSSG0_BUS_PR1_RGMII0_RXC_I", "Input clock"},
+       [739] = {62, 23, "DEV_PRU_ICSSG0_BUS_PR1_RGMII1_TXC_I", "Output clock"},
+       [740] = {62, 24, "DEV_PRU_ICSSG0_BUS_PR1_RGMII0_TXC_I", "Output clock"},
+       [741] = {63, 0, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_5_CLK", "Input clock"},
+       [742] = {63, 1, "DEV_PRU_ICSSG1_BUS_WIZ1_TX_SLV_CLK", "Input clock"},
+       [743] = {63, 2, "DEV_PRU_ICSSG1_BUS_WIZ0_RX_SLV_CLK", "Input clock"},
+       [744] = {63, 3, "DEV_PRU_ICSSG1_BUS_VCLK_CLK", "Input clock"},
+       [745] = {63, 4, "DEV_PRU_ICSSG1_BUS_UCLK_CLK", "Input clock"},
+       [746] = {63, 5, "DEV_PRU_ICSSG1_BUS_WIZ0_TX_SLV_CLK", "Input clock"},
+       [747] = {63, 6, "DEV_PRU_ICSSG1_BUS_WIZ1_RX_SLV_CLK", "Input clock"},
+       [748] = {63, 7, "DEV_PRU_ICSSG1_BUS_PR1_RGMII1_RXC_I", "Input clock"},
+       [749] = {63, 8, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_250_CLK", "Input clock"},
+       [750] = {63, 9, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_50_CLK", "Input clock"},
+       [751] = {63, 10, "DEV_PRU_ICSSG1_BUS_IEP_CLK", "Input muxed clock"},
+       [752] = {63, 11, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+       [753] = {63, 12, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+       [754] = {63, 13, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+       [755] = {63, 14, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+       [756] = {63, 15, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+       [757] = {63, 16, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+       [758] = {63, 17, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+       [759] = {63, 18, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+       [760] = {63, 19, "DEV_PRU_ICSSG1_BUS_CORE_CLK", "Input muxed clock"},
+       [761] = {63, 20, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"},
+       [762] = {63, 21, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"},
+       [763] = {63, 22, "DEV_PRU_ICSSG1_BUS_PR1_RGMII0_RXC_I", "Input clock"},
+       [764] = {63, 23, "DEV_PRU_ICSSG1_BUS_PR1_RGMII1_TXC_I", "Output clock"},
+       [765] = {63, 24, "DEV_PRU_ICSSG1_BUS_PR1_RGMII0_TXC_I", "Output clock"},
+       [766] = {64, 0, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_5_CLK", "Input clock"},
+       [767] = {64, 1, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_SLV_CLK", "Input clock"},
+       [768] = {64, 2, "DEV_PRU_ICSSG2_BUS_WIZ0_RX_SLV_CLK", "Input clock"},
+       [769] = {64, 3, "DEV_PRU_ICSSG2_BUS_VCLK_CLK", "Input clock"},
+       [770] = {64, 4, "DEV_PRU_ICSSG2_BUS_UCLK_CLK", "Input clock"},
+       [771] = {64, 5, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_SLV_CLK", "Input clock"},
+       [772] = {64, 6, "DEV_PRU_ICSSG2_BUS_WIZ1_RX_SLV_CLK", "Input clock"},
+       [773] = {64, 7, "DEV_PRU_ICSSG2_BUS_PR1_RGMII1_RXC_I", "Input clock"},
+       [774] = {64, 8, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_250_CLK", "Input clock"},
+       [775] = {64, 9, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_50_CLK", "Input clock"},
+       [776] = {64, 10, "DEV_PRU_ICSSG2_BUS_IEP_CLK", "Input muxed clock"},
+       [777] = {64, 11, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+       [778] = {64, 12, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+       [779] = {64, 13, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+       [780] = {64, 14, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+       [781] = {64, 15, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+       [782] = {64, 16, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+       [783] = {64, 17, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+       [784] = {64, 18, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+       [785] = {64, 19, "DEV_PRU_ICSSG2_BUS_CORE_CLK", "Input muxed clock"},
+       [786] = {64, 20, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"},
+       [787] = {64, 21, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"},
+       [788] = {64, 22, "DEV_PRU_ICSSG2_BUS_PR1_RGMII0_RXC_I", "Input clock"},
+       [789] = {64, 23, "DEV_PRU_ICSSG2_BUS_PR1_RGMII1_TXC_I", "Output clock"},
+       [790] = {64, 24, "DEV_PRU_ICSSG2_BUS_PR1_RGMII0_TXC_I", "Output clock"},
+       [791] = {64, 25, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_MST_CLK", "Output clock"},
+       [792] = {64, 26, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_MST_CLK", "Output clock"},
+       [793] = {70, 0, "DEV_PSC0_BUS_CLK", "Input clock"},
+       [794] = {70, 1, "DEV_PSC0_BUS_SLOW_CLK", "Input clock"},
+       [795] = {128, 0, "DEV_PSRAMECC0_BUS_CLK_CLK", "Input clock"},
+       [796] = {130, 0, "DEV_RTI0_BUS_RTI_CLK", "Input muxed clock"},
+       [797] = {130, 1, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+       [798] = {130, 2, "DEV_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+       [799] = {130, 3, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+       [800] = {130, 4, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+       [801] = {130, 5, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+       [802] = {130, 6, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+       [803] = {130, 7, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+       [804] = {130, 8, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+       [805] = {130, 9, "DEV_RTI0_BUS_VBUSP_CLK", "Input clock"},
+       [806] = {131, 0, "DEV_RTI1_BUS_RTI_CLK", "Input muxed clock"},
+       [807] = {131, 1, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+       [808] = {131, 2, "DEV_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+       [809] = {131, 3, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+       [810] = {131, 4, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+       [811] = {131, 5, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+       [812] = {131, 6, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+       [813] = {131, 7, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+       [814] = {131, 8, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+       [815] = {131, 9, "DEV_RTI1_BUS_VBUSP_CLK", "Input clock"},
+       [816] = {132, 0, "DEV_RTI2_BUS_RTI_CLK", "Input muxed clock"},
+       [817] = {132, 1, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+       [818] = {132, 2, "DEV_RTI2_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+       [819] = {132, 3, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+       [820] = {132, 4, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+       [821] = {132, 5, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+       [822] = {132, 6, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+       [823] = {132, 7, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+       [824] = {132, 8, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+       [825] = {132, 9, "DEV_RTI2_BUS_VBUSP_CLK", "Input clock"},
+       [826] = {133, 0, "DEV_RTI3_BUS_RTI_CLK", "Input muxed clock"},
+       [827] = {133, 1, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+       [828] = {133, 2, "DEV_RTI3_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+       [829] = {133, 3, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+       [830] = {133, 4, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+       [831] = {133, 5, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+       [832] = {133, 6, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+       [833] = {133, 7, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+       [834] = {133, 8, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+       [835] = {133, 9, "DEV_RTI3_BUS_VBUSP_CLK", "Input clock"},
+       [836] = {136, 0, "DEV_SA2_UL0_BUS_PKA_IN_CLK", "Input clock"},
+       [837] = {136, 1, "DEV_SA2_UL0_BUS_X1_CLK", "Input clock"},
+       [838] = {136, 2, "DEV_SA2_UL0_BUS_X2_CLK", "Input clock"},
+       [839] = {153, 0, "DEV_SERDES0_BUS_IP3_LN0_TXRCLK", "Input clock"},
+       [840] = {153, 1, "DEV_SERDES0_BUS_REFCLKPP", "Input clock"},
+       [841] = {153, 2, "DEV_SERDES0_BUS_CLK", "Input clock"},
+       [842] = {153, 3, "DEV_SERDES0_BUS_IP2_LN0_TXRCLK", "Input clock"},
+       [843] = {153, 4, "DEV_SERDES0_BUS_LI_REFCLK", "Input muxed clock"},
+       [844] = {153, 5, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
+       [845] = {153, 6, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
+       [846] = {153, 7, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
+       [847] = {153, 8, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
+       [848] = {153, 9, "DEV_SERDES0_BUS_REFCLKPN", "Input clock"},
+       [849] = {153, 10, "DEV_SERDES0_BUS_LN0_TXCLK", "Output clock"},
+       [850] = {153, 11, "DEV_SERDES0_BUS_LN0_RXCLK", "Output clock"},
+       [851] = {154, 0, "DEV_SERDES1_BUS_IP3_LN0_TXRCLK", "Input clock"},
+       [852] = {154, 1, "DEV_SERDES1_BUS_REFCLKPP", "Input clock"},
+       [853] = {154, 2, "DEV_SERDES1_BUS_CLK", "Input clock"},
+       [854] = {154, 3, "DEV_SERDES1_BUS_IP1_LN0_TXRCLK", "Input clock"},
+       [855] = {154, 4, "DEV_SERDES1_BUS_IP2_LN0_TXRCLK", "Input clock"},
+       [856] = {154, 5, "DEV_SERDES1_BUS_RI_REFCLK", "Input muxed clock"},
+       [857] = {154, 6, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
+       [858] = {154, 7, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
+       [859] = {154, 8, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
+       [860] = {154, 9, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
+       [861] = {154, 10, "DEV_SERDES1_BUS_REFCLKPN", "Input clock"},
+       [862] = {154, 11, "DEV_SERDES1_BUS_LN0_TXCLK", "Output clock"},
+       [863] = {154, 12, "DEV_SERDES1_BUS_LN0_RXCLK", "Output clock"},
+       [864] = {8, 0, "DEV_STM0_BUS_CORE_CLK", "Input clock"},
+       [865] = {8, 1, "DEV_STM0_BUS_ATB_CLK", "Input clock"},
+       [866] = {8, 2, "DEV_STM0_BUS_VBUSP_CLK", "Input clock"},
+       [867] = {23, 0, "DEV_TIMER0_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       [868] = {23, 1, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [869] = {23, 2, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [870] = {23, 3, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [871] = {23, 4, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [872] = {23, 5, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [873] = {23, 6, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [874] = {23, 7, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [875] = {23, 8, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [876] = {23, 9, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [877] = {23, 10, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [878] = {23, 11, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [879] = {23, 12, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [880] = {23, 13, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [881] = {23, 14, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [882] = {23, 15, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [883] = {23, 16, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       [884] = {23, 17, "DEV_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"},
+       [885] = {24, 0, "DEV_TIMER1_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       [886] = {24, 1, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [887] = {24, 2, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [888] = {24, 3, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [889] = {24, 4, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [890] = {24, 5, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [891] = {24, 6, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [892] = {24, 7, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [893] = {24, 8, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [894] = {24, 9, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [895] = {24, 10, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [896] = {24, 11, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [897] = {24, 12, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [898] = {24, 13, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [899] = {24, 14, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [900] = {24, 15, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [901] = {24, 16, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       [902] = {24, 17, "DEV_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"},
+       [903] = {25, 0, "DEV_TIMER10_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       [904] = {25, 1, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       [905] = {25, 2, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       [906] = {25, 3, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       [907] = {25, 4, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       [908] = {25, 5, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       [909] = {25, 6, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       [910] = {25, 7, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       [911] = {25, 8, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       [912] = {25, 9, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       [913] = {25, 10, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       [914] = {25, 11, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       [915] = {25, 12, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       [916] = {25, 13, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       [917] = {25, 14, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       [918] = {25, 15, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       [919] = {25, 16, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       [920] = {25, 17, "DEV_TIMER10_BUS_TIMER_HCLK_CLK", "Input clock"},
+       [921] = {26, 0, "DEV_TIMER11_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       [922] = {26, 1, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       [923] = {26, 2, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       [924] = {26, 3, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       [925] = {26, 4, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       [926] = {26, 5, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       [927] = {26, 6, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       [928] = {26, 7, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       [929] = {26, 8, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       [930] = {26, 9, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       [931] = {26, 10, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       [932] = {26, 11, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       [933] = {26, 12, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       [934] = {26, 13, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       [935] = {26, 14, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       [936] = {26, 15, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       [937] = {26, 16, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       [938] = {26, 17, "DEV_TIMER11_BUS_TIMER_HCLK_CLK", "Input clock"},
+       [939] = {27, 0, "DEV_TIMER2_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       [940] = {27, 1, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [941] = {27, 2, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [942] = {27, 3, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [943] = {27, 4, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [944] = {27, 5, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [945] = {27, 6, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [946] = {27, 7, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [947] = {27, 8, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [948] = {27, 9, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [949] = {27, 10, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [950] = {27, 11, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [951] = {27, 12, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [952] = {27, 13, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [953] = {27, 14, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [954] = {27, 15, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [955] = {27, 16, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       [956] = {27, 17, "DEV_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"},
+       [957] = {28, 0, "DEV_TIMER3_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       [958] = {28, 1, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [959] = {28, 2, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [960] = {28, 3, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [961] = {28, 4, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [962] = {28, 5, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [963] = {28, 6, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [964] = {28, 7, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [965] = {28, 8, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [966] = {28, 9, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [967] = {28, 10, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [968] = {28, 11, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [969] = {28, 12, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [970] = {28, 13, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [971] = {28, 14, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [972] = {28, 15, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [973] = {28, 16, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       [974] = {28, 17, "DEV_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"},
+       [975] = {29, 0, "DEV_TIMER4_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       [976] = {29, 1, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       [977] = {29, 2, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       [978] = {29, 3, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       [979] = {29, 4, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       [980] = {29, 5, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       [981] = {29, 6, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       [982] = {29, 7, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       [983] = {29, 8, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       [984] = {29, 9, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       [985] = {29, 10, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       [986] = {29, 11, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       [987] = {29, 12, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       [988] = {29, 13, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       [989] = {29, 14, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       [990] = {29, 15, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       [991] = {29, 16, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       [992] = {29, 17, "DEV_TIMER4_BUS_TIMER_HCLK_CLK", "Input clock"},
+       [993] = {30, 0, "DEV_TIMER5_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       [994] = {30, 1, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       [995] = {30, 2, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       [996] = {30, 3, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       [997] = {30, 4, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       [998] = {30, 5, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       [999] = {30, 6, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       [1000] = {30, 7, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       [1001] = {30, 8, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       [1002] = {30, 9, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       [1003] = {30, 10, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       [1004] = {30, 11, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       [1005] = {30, 12, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       [1006] = {30, 13, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       [1007] = {30, 14, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       [1008] = {30, 15, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       [1009] = {30, 16, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       [1010] = {30, 17, "DEV_TIMER5_BUS_TIMER_HCLK_CLK", "Input clock"},
+       [1011] = {31, 0, "DEV_TIMER6_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1012] = {31, 1, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       [1013] = {31, 2, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       [1014] = {31, 3, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       [1015] = {31, 4, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       [1016] = {31, 5, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       [1017] = {31, 6, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       [1018] = {31, 7, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       [1019] = {31, 8, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       [1020] = {31, 9, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       [1021] = {31, 10, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       [1022] = {31, 11, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       [1023] = {31, 12, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       [1024] = {31, 13, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       [1025] = {31, 14, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       [1026] = {31, 15, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       [1027] = {31, 16, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       [1028] = {31, 17, "DEV_TIMER6_BUS_TIMER_HCLK_CLK", "Input clock"},
+       [1029] = {32, 0, "DEV_TIMER7_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1030] = {32, 1, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       [1031] = {32, 2, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       [1032] = {32, 3, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       [1033] = {32, 4, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       [1034] = {32, 5, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       [1035] = {32, 6, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       [1036] = {32, 7, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       [1037] = {32, 8, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       [1038] = {32, 9, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       [1039] = {32, 10, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       [1040] = {32, 11, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       [1041] = {32, 12, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       [1042] = {32, 13, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       [1043] = {32, 14, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       [1044] = {32, 15, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       [1045] = {32, 16, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       [1046] = {32, 17, "DEV_TIMER7_BUS_TIMER_HCLK_CLK", "Input clock"},
+       [1047] = {33, 0, "DEV_TIMER8_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1048] = {33, 1, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       [1049] = {33, 2, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       [1050] = {33, 3, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       [1051] = {33, 4, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       [1052] = {33, 5, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       [1053] = {33, 6, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       [1054] = {33, 7, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       [1055] = {33, 8, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       [1056] = {33, 9, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       [1057] = {33, 10, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       [1058] = {33, 11, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       [1059] = {33, 12, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       [1060] = {33, 13, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       [1061] = {33, 14, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       [1062] = {33, 15, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       [1063] = {33, 16, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       [1064] = {33, 17, "DEV_TIMER8_BUS_TIMER_HCLK_CLK", "Input clock"},
+       [1065] = {34, 0, "DEV_TIMER9_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       [1066] = {34, 1, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       [1067] = {34, 2, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       [1068] = {34, 3, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       [1069] = {34, 4, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       [1070] = {34, 5, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       [1071] = {34, 6, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       [1072] = {34, 7, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       [1073] = {34, 8, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       [1074] = {34, 9, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       [1075] = {34, 10, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       [1076] = {34, 11, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       [1077] = {34, 12, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       [1078] = {34, 13, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       [1079] = {34, 14, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       [1080] = {34, 15, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       [1081] = {34, 16, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       [1082] = {34, 17, "DEV_TIMER9_BUS_TIMER_HCLK_CLK", "Input clock"},
+       [1083] = {145, 0, "DEV_TIMESYNC_INTRTR0_BUS_INTR_CLK", "Input clock"},
+       [1084] = {146, 0, "DEV_UART0_BUS_FCLK_CLK", "Input clock"},
+       [1085] = {146, 1, "DEV_UART0_BUS_VBUSP_CLK", "Input clock"},
+       [1086] = {147, 0, "DEV_UART1_BUS_FCLK_CLK", "Input clock"},
+       [1087] = {147, 1, "DEV_UART1_BUS_VBUSP_CLK", "Input clock"},
+       [1088] = {148, 0, "DEV_UART2_BUS_FCLK_CLK", "Input clock"},
+       [1089] = {148, 1, "DEV_UART2_BUS_VBUSP_CLK", "Input clock"},
+       [1090] = {151, 0, "DEV_USB3SS0_BUS_SUSP_CLK", "Input clock"},
+       [1091] = {151, 1, "DEV_USB3SS0_BUS_PHY2_REFCLK960M_CLK", "Input clock"},
+       [1092] = {151, 2, "DEV_USB3SS0_BUS_REF_CLK", "Input muxed clock"},
+       [1093] = {151, 3, "DEV_USB3SS0_BUS_REF_CLK_PARENT_CLOCKMUX_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"},
+       [1094] = {151, 4, "DEV_USB3SS0_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"},
+       [1095] = {151, 5, "DEV_USB3SS0_BUS_HSIC_CLK_CLK", "Input clock"},
+       [1096] = {151, 6, "DEV_USB3SS0_BUS_BUS_CLK", "Input clock"},
+       [1097] = {151, 7, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK", "Input muxed clock"},
+       [1098] = {151, 8, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"},
+       [1099] = {151, 9, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_CLOCKMUX_USB0_PIPE3_CLK_SEL_DIV_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"},
+       [1100] = {151, 10, "DEV_USB3SS0_BUS_UTMI_CLK_CLK", "Input clock"},
+       [1101] = {152, 0, "DEV_USB3SS1_BUS_SUSP_CLK", "Input clock"},
+       [1102] = {152, 1, "DEV_USB3SS1_BUS_PHY2_REFCLK960M_CLK", "Input clock"},
+       [1103] = {152, 2, "DEV_USB3SS1_BUS_REF_CLK", "Input muxed clock"},
+       [1104] = {152, 3, "DEV_USB3SS1_BUS_REF_CLK_PARENT_CLOCKMUX_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"},
+       [1105] = {152, 4, "DEV_USB3SS1_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"},
+       [1106] = {152, 5, "DEV_USB3SS1_BUS_HSIC_CLK_CLK", "Input clock"},
+       [1107] = {152, 6, "DEV_USB3SS1_BUS_BUS_CLK", "Input clock"},
+       [1108] = {152, 7, "DEV_USB3SS1_BUS_PIPE3_TXB_CLK", "Input clock"},
+       [1109] = {152, 8, "DEV_USB3SS1_BUS_UTMI_CLK_CLK", "Input clock"},
+       [1110] = {94, 0, "DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_2_CLK", "Input clock"},
+       [1111] = {94, 1, "DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_4_CLK", "Input clock"},
+       [1112] = {96, 0, "DEV_WKUP_CBASS_FW0_BUS_WKUP_MCU_PLL_OUT_2_CLK", "Input clock"},
+       [1113] = {155, 0, "DEV_WKUP_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"},
+       [1114] = {22, 0, "DEV_WKUP_DMSC0_BUS_FUNC_32K_RT_CLK", "Input clock"},
+       [1115] = {22, 1, "DEV_WKUP_DMSC0_BUS_FUNC_MOSC_CLK", "Input clock"},
+       [1116] = {22, 2, "DEV_WKUP_DMSC0_BUS_VBUS_CLK", "Input clock"},
+       [1117] = {22, 3, "DEV_WKUP_DMSC0_BUS_FUNC_32K_RC_CLK", "Input clock"},
+       [1118] = {22, 4, "DEV_WKUP_DMSC0_BUS_SEC_EFC_FCLK", "Input clock"},
+       [1119] = {22, 5, "DEV_WKUP_DMSC0_BUS_DAP_CLK", "Input clock"},
+       [1120] = {22, 6, "DEV_WKUP_DMSC0_BUS_EXT_CLK", "Input clock"},
+       [1121] = {95, 0, "DEV_WKUP_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"},
+       [1122] = {54, 0, "DEV_WKUP_ESM0_BUS_CLK", "Input clock"},
+       [1123] = {59, 0, "DEV_WKUP_GPIO0_BUS_MMR_CLK", "Input muxed clock"},
+       [1124] = {59, 1, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
+       [1125] = {59, 2, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4_DUP0", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
+       [1126] = {59, 3, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
+       [1127] = {59, 4, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
+       [1128] = {156, 0, "DEV_WKUP_GPIOMUX_INTRTR0_BUS_INTR_CLK", "Input clock"},
+       [1129] = {115, 0, "DEV_WKUP_I2C0_BUS_CLK", "Input clock"},
+       [1130] = {115, 1, "DEV_WKUP_I2C0_BUS_PISYS_CLK", "Input muxed clock"},
+       [1131] = {115, 2, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"},
+       [1132] = {115, 3, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"},
+       [1133] = {115, 4, "DEV_WKUP_I2C0_BUS_PISCL", "Output clock"},
+       [1134] = {77, 0, "DEV_WKUP_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK", "Input clock"},
+       [1135] = {77, 1, "DEV_WKUP_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"},
+       [1136] = {77, 2, "DEV_WKUP_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input clock"},
+       [1137] = {79, 0, "DEV_WKUP_PSC0_BUS_CLK", "Input clock"},
+       [1138] = {79, 1, "DEV_WKUP_PSC0_BUS_SLOW_CLK", "Input clock"},
+       [1139] = {150, 0, "DEV_WKUP_UART0_BUS_FCLK_CLK", "Input muxed clock"},
+       [1140] = {150, 1, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_CLOCKMUX_WKUPUSART_CLK_SEL_BUS_OUT0", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"},
+       [1141] = {150, 2, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"},
+       [1142] = {150, 3, "DEV_WKUP_UART0_BUS_VBUSP_CLK", "Input clock"},
+       [1143] = {80, 0, "DEV_WKUP_VTM0_BUS_FIX_REF_CLK", "Input clock"},
+       [1144] = {80, 1, "DEV_WKUP_VTM0_BUS_VBUSP_CLK", "Input clock"},
 };
index dcabfeb79074a752d821a0e8ecbb3dd28a6137e9..8152bdfe25bac881f72a12c0b9a16c511d3e2678 100644 (file)
@@ -35,7 +35,7 @@
 #ifndef __AM65X_CLOCKS_INFO_H
 #define __AM65X_CLOCKS_INFO_H
 
-#define AM65X_MAX_CLOCKS       961
+#define AM65X_MAX_CLOCKS       1145
 
 extern struct ti_sci_clocks_info am65x_clocks_info[];