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raw | patch | inline | side by side (parent: d7f38f4)
author | Bryan Brattlof <bb@ti.com> | |
Wed, 20 Apr 2022 14:53:38 +0000 (09:53 -0500) | ||
committer | Bryan Brattlof <bb@ti.com> | |
Wed, 18 May 2022 22:24:19 +0000 (17:24 -0500) |
The Device IDs represent SoC subsystems that can be modified via the
DMSC TISCI message APIs. Some subsystems define a Device ID as a
parameter, allowing us to specify the management of a particular
SoC subsystem
Provide the Device IDs that are permitted in the J721S2.
Signed-off-by: Bryan Brattlof <bb@ti.com>
DMSC TISCI message APIs. Some subsystems define a Device ID as a
parameter, allowing us to specify the management of a particular
SoC subsystem
Provide the Device IDs that are permitted in the J721S2.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Makefile | patch | blob | history | |
common/socinfo.c | patch | blob | history | |
soc/j721s2/j721s2_devices_info.c | [new file with mode: 0644] | patch | blob |
soc/j721s2/j721s2_devices_info.h | [new file with mode: 0644] | patch | blob |
diff --git a/Makefile b/Makefile
index d9d95c865126e9cf13b45c9a0751150047eab849..d384db1b784701f222e8af01a7832b304814b770 100644 (file)
--- a/Makefile
+++ b/Makefile
soc/am62x/am62x_rm_info.c \
soc/am62x/am62x_sec_proxy_info.c
+J721S2SOURCES =\
+ soc/j721s2/j721s2_devices_info.c
+
COMMONOBJECTS= $(COMMONSOURCES:.c=.o)
AM65XOBJECTS= $(AM65XSOURCES:.c=.o)
J721EOBJECTS= $(J721ESOURCES:.c=.o)
AM64XOBJECTS= $(AM64XSOURCES:.c=.o)
AM62XOBJECTS= $(AM62XSOURCES:.c=.o)
+J721S2OBJECTS= $(J721S2SOURCES:.c=.o)
ALLSOURCES= $(COMMONSOURCES) $(AM65XSOURCES) $(J721ESOURCES) \
- $(AM64XSOURCES) $(AM62XSOURCES)
+ $(AM64XSOURCES) $(AM62XSOURCES) $(J721S2SOURCES)
ALLOBJECTS= $(COMMONOBJECTS) $(AM65XOBJECTS) $(J721EOBJECTS) \
- $(AM64XOBJECTS) $(AM62XOBJECTS)
+ $(AM64XOBJECTS) $(AM62XOBJECTS) $(J721S2OBJECTS)
#
# Pretty print
diff --git a/common/socinfo.c b/common/socinfo.c
index 851e2dbd24975b62599fa4a06a228c14b5610c7b..5fb5c1791e3eda931a60e2519fd4d1e2430d19e4 100644 (file)
--- a/common/socinfo.c
+++ b/common/socinfo.c
#include <soc/am62x/am62x_processors_info.h>
#include <soc/am62x/am62x_rm_info.h>
#include <soc/am62x/am62x_sec_proxy_info.h>
+#include <soc/j721s2/j721s2_devices_info.h>
/* Assuming these addresses and definitions stay common across K3 devices */
#define CTRLMMR_WKUP_JTAG_DEVICE_ID 0x43000018
{
struct ti_sci_info *sci_info = &soc_info.sci_info;
+ sci_info->devices_info = j721s2_devices_info;
+ sci_info->num_devices = J721S2_MAX_DEVICES;
soc_info.host_id = DEFAULT_HOST_ID;
soc_info.sec_proxy = &k3_generic_sec_proxy_base;
}
diff --git a/soc/j721s2/j721s2_devices_info.c b/soc/j721s2/j721s2_devices_info.c
--- /dev/null
@@ -0,0 +1,371 @@
+/*
+ * J721S2 Devices Info
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <tisci.h>
+#include <socinfo.h>
+
+struct ti_sci_devices_info j721s2_devices_info[] = {
+ [0] = {0, "J721S2_DEV_MCU_ADC12FC_16FFC0"},
+ [1] = {1, "J721S2_DEV_MCU_ADC12FC_16FFC1"},
+ [2] = {2, "J721S2_DEV_ATL0"},
+ [3] = {3, "J721S2_DEV_C71X_0_PBIST_VD"},
+ [4] = {4, "J721S2_DEV_A72SS0"},
+ [5] = {5, "J721S2_DEV_C71X_1_PBIST_VD"},
+ [6] = {6, "J721S2_DEV_COMPUTE_CLUSTER0"},
+ [7] = {7, "J721S2_DEV_A72SS0_CORE0_PBIST_WRAP"},
+ [8] = {8, "J721S2_DEV_COMPUTE_CLUSTER0_C71SS0_0"},
+ [9] = {9, "J721S2_DEV_COMPUTE_CLUSTER0_C71SS0_MMA_0"},
+ [10] = {10, "J721S2_DEV_COMPUTE_CLUSTER0_C71SS0_PBIST_WRAP_0"},
+ [11] = {11, "J721S2_DEV_COMPUTE_CLUSTER0_C71SS1_0"},
+ [12] = {12, "J721S2_DEV_COMPUTE_CLUSTER0_C71SS1_PBIST_WRAP_0"},
+ [13] = {13, "J721S2_DEV_COMPUTE_CLUSTER0_CFG_WRAP_0"},
+ [14] = {14, "J721S2_DEV_COMPUTE_CLUSTER0_CLEC"},
+ [15] = {15, "J721S2_DEV_COMPUTE_CLUSTER0_CORE_CORE"},
+ [16] = {16, "J721S2_DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_0"},
+ [17] = {17, "J721S2_DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF1_EW_0"},
+ [18] = {18, "J721S2_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0"},
+ [19] = {19, "J721S2_DEV_COMPUTE_CLUSTER0_DIVH2_DIVH0_0"},
+ [20] = {20, "J721S2_DEV_COMPUTE_CLUSTER0_DIVH2_DIVH0_1"},
+ [21] = {21, "J721S2_DEV_COMPUTE_CLUSTER0_DIVP_TFT0_0"},
+ [22] = {22, "J721S2_DEV_WKUP_SMS0"},
+ [23] = {23, "J721S2_DEV_COMPUTE_CLUSTER0_DIVP_TFT0_1"},
+ [24] = {24, "J721S2_DEV_COMPUTE_CLUSTER0_DMSC_WRAP_0"},
+ [25] = {25, "J721S2_DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_0"},
+ [26] = {26, "J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS"},
+ [27] = {27, "J721S2_DEV_COMPUTE_CLUSTER0_PBIST_WRAP_0"},
+ [28] = {28, "J721S2_DEV_CPSW1"},
+ [29] = {29, "J721S2_DEV_MCU_CPSW0"},
+ [30] = {30, "J721S2_DEV_CPT2_AGGR1"},
+ [31] = {31, "J721S2_DEV_CPT2_AGGR5"},
+ [32] = {32, "J721S2_DEV_CPT2_AGGR2"},
+ [33] = {33, "J721S2_DEV_CPT2_AGGR4"},
+ [34] = {34, "J721S2_DEV_CPT2_AGGR3"},
+ [35] = {35, "J721S2_DEV_MCU_TIMER0"},
+ [36] = {36, "J721S2_DEV_CPT2_AGGR0"},
+ [37] = {37, "J721S2_DEV_MCU_CPT2_AGGR0"},
+ [38] = {38, "J721S2_DEV_CSI_RX_IF0"},
+ [39] = {39, "J721S2_DEV_CSI_RX_IF1"},
+ [40] = {40, "J721S2_DEV_CSI_TX_IF_V2_0"},
+ [41] = {41, "J721S2_DEV_CSI_TX_IF_V2_1"},
+ [42] = {42, "J721S2_DEV_STM0"},
+ [43] = {43, "J721S2_DEV_DCC0"},
+ [44] = {44, "J721S2_DEV_DCC1"},
+ [45] = {45, "J721S2_DEV_DCC2"},
+ [46] = {46, "J721S2_DEV_DCC3"},
+ [47] = {47, "J721S2_DEV_DCC4"},
+ [48] = {48, "J721S2_DEV_DCC5"},
+ [49] = {49, "J721S2_DEV_DCC6"},
+ [50] = {50, "J721S2_DEV_DCC7"},
+ [51] = {51, "J721S2_DEV_DCC8"},
+ [52] = {52, "J721S2_DEV_DCC9"},
+ [53] = {53, "J721S2_DEV_MCU_DCC0"},
+ [54] = {54, "J721S2_DEV_MCU_DCC1"},
+ [55] = {55, "J721S2_DEV_MCU_DCC2"},
+ [56] = {57, "J721S2_DEV_DEBUGSS_WRAP0"},
+ [57] = {58, "J721S2_DEV_DMPAC0"},
+ [58] = {59, "J721S2_DEV_DMPAC0_CTSET_0"},
+ [59] = {60, "J721S2_DEV_DMPAC0_INTD_0"},
+ [60] = {61, "J721S2_DEV_GTC0"},
+ [61] = {62, "J721S2_DEV_DMPAC0_SDE_0"},
+ [62] = {63, "J721S2_DEV_TIMER0"},
+ [63] = {64, "J721S2_DEV_TIMER1"},
+ [64] = {65, "J721S2_DEV_TIMER2"},
+ [65] = {66, "J721S2_DEV_TIMER3"},
+ [66] = {67, "J721S2_DEV_TIMER4"},
+ [67] = {68, "J721S2_DEV_TIMER5"},
+ [68] = {69, "J721S2_DEV_TIMER6"},
+ [69] = {70, "J721S2_DEV_TIMER7"},
+ [70] = {71, "J721S2_DEV_TIMER8"},
+ [71] = {72, "J721S2_DEV_TIMER9"},
+ [72] = {73, "J721S2_DEV_TIMER10"},
+ [73] = {74, "J721S2_DEV_TIMER11"},
+ [74] = {75, "J721S2_DEV_TIMER12"},
+ [75] = {76, "J721S2_DEV_TIMER13"},
+ [76] = {77, "J721S2_DEV_TIMER14"},
+ [77] = {78, "J721S2_DEV_TIMER15"},
+ [78] = {79, "J721S2_DEV_TIMER16"},
+ [79] = {80, "J721S2_DEV_TIMER17"},
+ [80] = {81, "J721S2_DEV_TIMER18"},
+ [81] = {82, "J721S2_DEV_TIMER19"},
+ [82] = {83, "J721S2_DEV_MCU_TIMER1"},
+ [83] = {84, "J721S2_DEV_MCU_TIMER2"},
+ [84] = {85, "J721S2_DEV_MCU_TIMER3"},
+ [85] = {86, "J721S2_DEV_MCU_TIMER4"},
+ [86] = {87, "J721S2_DEV_MCU_TIMER5"},
+ [87] = {88, "J721S2_DEV_MCU_TIMER6"},
+ [88] = {89, "J721S2_DEV_MCU_TIMER7"},
+ [89] = {90, "J721S2_DEV_MCU_TIMER8"},
+ [90] = {91, "J721S2_DEV_MCU_TIMER9"},
+ [91] = {92, "J721S2_DEV_ECAP0"},
+ [92] = {93, "J721S2_DEV_ECAP1"},
+ [93] = {94, "J721S2_DEV_ECAP2"},
+ [94] = {95, "J721S2_DEV_ELM0"},
+ [95] = {96, "J721S2_DEV_EMIF_DATA_0_VD"},
+ [96] = {97, "J721S2_DEV_EMIF_DATA_1_VD"},
+ [97] = {98, "J721S2_DEV_MMCSD0"},
+ [98] = {99, "J721S2_DEV_MMCSD1"},
+ [99] = {100, "J721S2_DEV_EQEP0"},
+ [100] = {101, "J721S2_DEV_EQEP1"},
+ [101] = {102, "J721S2_DEV_EQEP2"},
+ [102] = {103, "J721S2_DEV_ESM0"},
+ [103] = {104, "J721S2_DEV_WKUP_ESM0"},
+ [104] = {105, "J721S2_DEV_MCU_ESM0"},
+ [105] = {106, "J721S2_DEV_MCU_FSS0"},
+ [106] = {107, "J721S2_DEV_MCU_FSS0_FSAS_0"},
+ [107] = {108, "J721S2_DEV_MCU_FSS0_HYPERBUS1P0_0"},
+ [108] = {109, "J721S2_DEV_MCU_FSS0_OSPI_0"},
+ [109] = {110, "J721S2_DEV_MCU_FSS0_OSPI_1"},
+ [110] = {111, "J721S2_DEV_GPIO0"},
+ [111] = {112, "J721S2_DEV_GPIO2"},
+ [112] = {113, "J721S2_DEV_GPIO4"},
+ [113] = {114, "J721S2_DEV_GPIO6"},
+ [114] = {115, "J721S2_DEV_WKUP_GPIO0"},
+ [115] = {116, "J721S2_DEV_WKUP_GPIO1"},
+ [116] = {117, "J721S2_DEV_GPMC0"},
+ [117] = {118, "J721S2_DEV_MCU_I3C0"},
+ [118] = {119, "J721S2_DEV_MCU_I3C1"},
+ [119] = {120, "J721S2_DEV_LED0"},
+ [120] = {121, "J721S2_DEV_MAIN2MCU_LVL_INTRTR0"},
+ [121] = {122, "J721S2_DEV_MAIN2MCU_PLS_INTRTR0"},
+ [122] = {123, "J721S2_DEV_WKUP_PORZ_SYNC0"},
+ [123] = {124, "J721S2_DEV_TIMESYNC_INTRTR0"},
+ [124] = {125, "J721S2_DEV_WKUP_GPIOMUX_INTRTR0"},
+ [125] = {126, "J721S2_DEV_WKUP_PSC0"},
+ [126] = {127, "J721S2_DEV_J7AEP_GPU_BXS464_WRAP0"},
+ [127] = {128, "J721S2_DEV_J7AEP_GPU_BXS464_WRAP0_DFT_EMBED_PBIST_0"},
+ [128] = {130, "J721S2_DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0"},
+ [129] = {131, "J721S2_DEV_J7AM_32_64_ATB_FUNNEL0"},
+ [130] = {132, "J721S2_DEV_J7AM_32_64_ATB_FUNNEL1"},
+ [131] = {133, "J721S2_DEV_J7AM_32_64_ATB_FUNNEL2"},
+ [132] = {134, "J721S2_DEV_AGGR_ATB0"},
+ [133] = {135, "J721S2_DEV_J7AM_BOLT_PGD0"},
+ [134] = {136, "J721S2_DEV_CSI_PSILSS0"},
+ [135] = {137, "J721S2_DEV_DEBUGSUSPENDRTR0"},
+ [136] = {138, "J721S2_DEV_DDR0"},
+ [137] = {139, "J721S2_DEV_DDR1"},
+ [138] = {140, "J721S2_DEV_DMPAC_VPAC_PSILSS0"},
+ [139] = {141, "J721S2_DEV_J7AM_HWA_ATB_FUNNEL0"},
+ [140] = {142, "J721S2_DEV_J7AM_MAIN_16FF0"},
+ [141] = {143, "J721S2_DEV_PSC0"},
+ [142] = {144, "J721S2_DEV_J7AM_PULSAR_ATB_FUNNEL0"},
+ [143] = {145, "J721S2_DEV_SA2_CPSW_PSILSS0"},
+ [144] = {146, "J721S2_DEV_UART0"},
+ [145] = {147, "J721S2_DEV_WKUP_J7AM_WAKEUP_16FF0"},
+ [146] = {148, "J721S2_DEV_GPIOMUX_INTRTR0"},
+ [147] = {149, "J721S2_DEV_MCU_UART0"},
+ [148] = {150, "J721S2_DEV_CMPEVENT_INTRTR0"},
+ [149] = {151, "J721S2_DEV_WKUP_DDPA0"},
+ [150] = {152, "J721S2_DEV_DPHY_RX0"},
+ [151] = {153, "J721S2_DEV_DPHY_RX1"},
+ [152] = {154, "J721S2_DEV_DSS_DSI0"},
+ [153] = {155, "J721S2_DEV_DSS_DSI1"},
+ [154] = {156, "J721S2_DEV_DSS_EDP0"},
+ [155] = {157, "J721S2_DEV_BOARD0"},
+ [156] = {158, "J721S2_DEV_DSS0"},
+ [157] = {160, "J721S2_DEV_EPWM0"},
+ [158] = {161, "J721S2_DEV_EPWM1"},
+ [159] = {162, "J721S2_DEV_EPWM2"},
+ [160] = {163, "J721S2_DEV_EPWM3"},
+ [161] = {164, "J721S2_DEV_EPWM4"},
+ [162] = {165, "J721S2_DEV_EPWM5"},
+ [163] = {166, "J721S2_DEV_PBIST7"},
+ [164] = {167, "J721S2_DEV_PBIST5"},
+ [165] = {168, "J721S2_DEV_PBIST11"},
+ [166] = {169, "J721S2_DEV_PBIST8"},
+ [167] = {170, "J721S2_DEV_PBIST3"},
+ [168] = {171, "J721S2_DEV_PBIST0"},
+ [169] = {172, "J721S2_DEV_PBIST1"},
+ [170] = {173, "J721S2_DEV_PBIST4"},
+ [171] = {174, "J721S2_DEV_PBIST2"},
+ [172] = {175, "J721S2_DEV_PBIST10"},
+ [173] = {176, "J721S2_DEV_MCU_PBIST0"},
+ [174] = {177, "J721S2_DEV_MCU_PBIST1"},
+ [175] = {178, "J721S2_DEV_MCU_PBIST2"},
+ [176] = {179, "J721S2_DEV_CODEC0"},
+ [177] = {180, "J721S2_DEV_WKUP_VTM0"},
+ [178] = {181, "J721S2_DEV_MAIN2WKUPMCU_VD"},
+ [179] = {182, "J721S2_DEV_MCAN0"},
+ [180] = {183, "J721S2_DEV_MCAN1"},
+ [181] = {184, "J721S2_DEV_MCAN2"},
+ [182] = {185, "J721S2_DEV_MCAN3"},
+ [183] = {186, "J721S2_DEV_MCAN4"},
+ [184] = {187, "J721S2_DEV_MCAN5"},
+ [185] = {188, "J721S2_DEV_MCAN6"},
+ [186] = {189, "J721S2_DEV_MCAN7"},
+ [187] = {190, "J721S2_DEV_MCAN8"},
+ [188] = {191, "J721S2_DEV_MCAN9"},
+ [189] = {192, "J721S2_DEV_MCAN10"},
+ [190] = {193, "J721S2_DEV_MCAN11"},
+ [191] = {194, "J721S2_DEV_MCAN12"},
+ [192] = {195, "J721S2_DEV_MCAN13"},
+ [193] = {197, "J721S2_DEV_MCAN14"},
+ [194] = {199, "J721S2_DEV_MCAN15"},
+ [195] = {201, "J721S2_DEV_MCAN16"},
+ [196] = {202, "J721S2_DEV_A72SS0_CORE0"},
+ [197] = {203, "J721S2_DEV_A72SS0_CORE1"},
+ [198] = {206, "J721S2_DEV_MCAN17"},
+ [199] = {207, "J721S2_DEV_MCU_MCAN0"},
+ [200] = {208, "J721S2_DEV_MCU_MCAN1"},
+ [201] = {209, "J721S2_DEV_MCASP0"},
+ [202] = {210, "J721S2_DEV_MCASP1"},
+ [203] = {211, "J721S2_DEV_MCASP2"},
+ [204] = {212, "J721S2_DEV_MCASP3"},
+ [205] = {213, "J721S2_DEV_MCASP4"},
+ [206] = {214, "J721S2_DEV_I2C0"},
+ [207] = {215, "J721S2_DEV_I2C1"},
+ [208] = {216, "J721S2_DEV_I2C2"},
+ [209] = {217, "J721S2_DEV_I2C3"},
+ [210] = {218, "J721S2_DEV_I2C4"},
+ [211] = {219, "J721S2_DEV_I2C5"},
+ [212] = {220, "J721S2_DEV_I2C6"},
+ [213] = {221, "J721S2_DEV_MCU_I2C0"},
+ [214] = {222, "J721S2_DEV_MCU_I2C1"},
+ [215] = {223, "J721S2_DEV_WKUP_I2C0"},
+ [216] = {224, "J721S2_DEV_NAVSS0"},
+ [217] = {225, "J721S2_DEV_NAVSS0_BCDMA_0"},
+ [218] = {226, "J721S2_DEV_NAVSS0_CPTS_0"},
+ [219] = {227, "J721S2_DEV_NAVSS0_INTR_0"},
+ [220] = {228, "J721S2_DEV_NAVSS0_MAILBOX1_0"},
+ [221] = {229, "J721S2_DEV_NAVSS0_MAILBOX1_1"},
+ [222] = {230, "J721S2_DEV_NAVSS0_MAILBOX1_2"},
+ [223] = {231, "J721S2_DEV_NAVSS0_MAILBOX1_3"},
+ [224] = {232, "J721S2_DEV_NAVSS0_MAILBOX1_4"},
+ [225] = {233, "J721S2_DEV_NAVSS0_MAILBOX1_5"},
+ [226] = {234, "J721S2_DEV_NAVSS0_MAILBOX1_6"},
+ [227] = {235, "J721S2_DEV_NAVSS0_MAILBOX1_7"},
+ [228] = {236, "J721S2_DEV_NAVSS0_MAILBOX1_8"},
+ [229] = {237, "J721S2_DEV_NAVSS0_MAILBOX1_9"},
+ [230] = {238, "J721S2_DEV_NAVSS0_MAILBOX1_10"},
+ [231] = {239, "J721S2_DEV_NAVSS0_MAILBOX1_11"},
+ [232] = {240, "J721S2_DEV_NAVSS0_MAILBOX_0"},
+ [233] = {241, "J721S2_DEV_NAVSS0_MAILBOX_1"},
+ [234] = {242, "J721S2_DEV_NAVSS0_MAILBOX_2"},
+ [235] = {243, "J721S2_DEV_NAVSS0_MAILBOX_3"},
+ [236] = {244, "J721S2_DEV_NAVSS0_MAILBOX_4"},
+ [237] = {245, "J721S2_DEV_NAVSS0_MAILBOX_5"},
+ [238] = {246, "J721S2_DEV_NAVSS0_MAILBOX_6"},
+ [239] = {247, "J721S2_DEV_NAVSS0_MAILBOX_7"},
+ [240] = {248, "J721S2_DEV_NAVSS0_MAILBOX_8"},
+ [241] = {249, "J721S2_DEV_NAVSS0_MAILBOX_9"},
+ [242] = {250, "J721S2_DEV_NAVSS0_MAILBOX_10"},
+ [243] = {251, "J721S2_DEV_NAVSS0_MAILBOX_11"},
+ [244] = {252, "J721S2_DEV_NAVSS0_MCRC_0"},
+ [245] = {253, "J721S2_DEV_NAVSS0_MODSS"},
+ [246] = {254, "J721S2_DEV_NAVSS0_MODSS_INTA_0"},
+ [247] = {255, "J721S2_DEV_NAVSS0_MODSS_INTA_1"},
+ [248] = {256, "J721S2_DEV_NAVSS0_PROXY_0"},
+ [249] = {257, "J721S2_DEV_NAVSS0_PVU_0"},
+ [250] = {258, "J721S2_DEV_NAVSS0_PVU_1"},
+ [251] = {259, "J721S2_DEV_NAVSS0_RINGACC_0"},
+ [252] = {260, "J721S2_DEV_NAVSS0_SPINLOCK_0"},
+ [253] = {261, "J721S2_DEV_NAVSS0_TIMERMGR_0"},
+ [254] = {262, "J721S2_DEV_NAVSS0_TIMERMGR_1"},
+ [255] = {263, "J721S2_DEV_NAVSS0_UDMAP_0"},
+ [256] = {264, "J721S2_DEV_NAVSS0_UDMASS"},
+ [257] = {265, "J721S2_DEV_NAVSS0_UDMASS_INTA_0"},
+ [258] = {266, "J721S2_DEV_NAVSS0_VIRTSS"},
+ [259] = {267, "J721S2_DEV_MCU_NAVSS0"},
+ [260] = {268, "J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0"},
+ [261] = {269, "J721S2_DEV_MCU_NAVSS0_MCRC_0"},
+ [262] = {270, "J721S2_DEV_MCU_NAVSS0_MODSS"},
+ [263] = {271, "J721S2_DEV_MCU_NAVSS0_PROXY0"},
+ [264] = {272, "J721S2_DEV_MCU_NAVSS0_RINGACC0"},
+ [265] = {273, "J721S2_DEV_MCU_NAVSS0_UDMAP_0"},
+ [266] = {274, "J721S2_DEV_MCU_NAVSS0_UDMASS"},
+ [267] = {275, "J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0"},
+ [268] = {276, "J721S2_DEV_PCIE1"},
+ [269] = {277, "J721S2_DEV_R5FSS0"},
+ [270] = {278, "J721S2_DEV_R5FSS1"},
+ [271] = {279, "J721S2_DEV_R5FSS0_CORE0"},
+ [272] = {280, "J721S2_DEV_R5FSS0_CORE1"},
+ [273] = {281, "J721S2_DEV_R5FSS1_CORE0"},
+ [274] = {282, "J721S2_DEV_R5FSS1_CORE1"},
+ [275] = {283, "J721S2_DEV_MCU_R5FSS0"},
+ [276] = {284, "J721S2_DEV_MCU_R5FSS0_CORE0"},
+ [277] = {285, "J721S2_DEV_MCU_R5FSS0_CORE1"},
+ [278] = {286, "J721S2_DEV_RTI0"},
+ [279] = {287, "J721S2_DEV_RTI1"},
+ [280] = {288, "J721S2_DEV_RTI16"},
+ [281] = {289, "J721S2_DEV_RTI17"},
+ [282] = {290, "J721S2_DEV_RTI15"},
+ [283] = {291, "J721S2_DEV_RTI28"},
+ [284] = {292, "J721S2_DEV_RTI29"},
+ [285] = {293, "J721S2_DEV_RTI30"},
+ [286] = {294, "J721S2_DEV_RTI31"},
+ [287] = {295, "J721S2_DEV_MCU_RTI0"},
+ [288] = {296, "J721S2_DEV_MCU_RTI1"},
+ [289] = {297, "J721S2_DEV_SA2_UL0"},
+ [290] = {298, "J721S2_DEV_MCU_SA3_SS0"},
+ [291] = {299, "J721S2_DEV_MCU_SA3_SS0_DMSS_ECCAGGR_0"},
+ [292] = {300, "J721S2_DEV_MCU_SA3_SS0_INTAGGR_0"},
+ [293] = {301, "J721S2_DEV_MCU_SA3_SS0_PKTDMA_0"},
+ [294] = {302, "J721S2_DEV_MCU_SA3_SS0_RINGACC_0"},
+ [295] = {303, "J721S2_DEV_MCU_SA3_SS0_SA_UL_0"},
+ [296] = {339, "J721S2_DEV_MCSPI0"},
+ [297] = {340, "J721S2_DEV_MCSPI1"},
+ [298] = {341, "J721S2_DEV_MCSPI2"},
+ [299] = {342, "J721S2_DEV_MCSPI3"},
+ [300] = {343, "J721S2_DEV_MCSPI4"},
+ [301] = {344, "J721S2_DEV_MCSPI5"},
+ [302] = {345, "J721S2_DEV_MCSPI6"},
+ [303] = {346, "J721S2_DEV_MCSPI7"},
+ [304] = {347, "J721S2_DEV_MCU_MCSPI0"},
+ [305] = {348, "J721S2_DEV_MCU_MCSPI1"},
+ [306] = {349, "J721S2_DEV_MCU_MCSPI2"},
+ [307] = {350, "J721S2_DEV_UART1"},
+ [308] = {351, "J721S2_DEV_UART2"},
+ [309] = {352, "J721S2_DEV_UART3"},
+ [310] = {353, "J721S2_DEV_UART4"},
+ [311] = {354, "J721S2_DEV_UART5"},
+ [312] = {355, "J721S2_DEV_UART6"},
+ [313] = {356, "J721S2_DEV_UART7"},
+ [314] = {357, "J721S2_DEV_UART8"},
+ [315] = {358, "J721S2_DEV_UART9"},
+ [316] = {359, "J721S2_DEV_WKUP_UART0"},
+ [317] = {360, "J721S2_DEV_USB0"},
+ [318] = {361, "J721S2_DEV_VPAC0"},
+ [319] = {362, "J721S2_DEV_VUSR_DUAL0"},
+ [320] = {363, "J721S2_DEV_DPHY_TX0"},
+ [321] = {364, "J721S2_DEV_DPHY_TX1"},
+ [322] = {365, "J721S2_DEV_SERDES_10G0"},
+ [323] = {366, "J721S2_DEV_WKUPMCU2MAIN_VD"},
+ [324] = {367, "J721S2_DEV_FFI_MAIN_AC_CBASS_VD"},
+ [325] = {368, "J721S2_DEV_FFI_MAIN_AC_QM_CBASS_VD"},
+ [326] = {369, "J721S2_DEV_FFI_MAIN_HC_CBASS_VD"},
+ [327] = {370, "J721S2_DEV_FFI_MAIN_INFRA_CBASS_VD"},
+ [328] = {371, "J721S2_DEV_FFI_MAIN_IP_CBASS_VD"},
+ [329] = {372, "J721S2_DEV_FFI_MAIN_RC_CBASS_VD"},
+ [330] = {373, "J721S2_DEV_J7AEP_GPU_BXS464_WRAP0_GPUCORE_0"},
+ [331] = {374, "J721S2_DEV_DMPAC0_UTC_0"},
+};
diff --git a/soc/j721s2/j721s2_devices_info.h b/soc/j721s2/j721s2_devices_info.h
--- /dev/null
@@ -0,0 +1,42 @@
+/*
+ * J721S2 Devices Info
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __J721S2_DEVICES_INFO_H
+#define __J721S2_DEVICES_INFO_H
+
+#define J721S2_MAX_DEVICES 332
+
+extern struct ti_sci_devices_info j721s2_devices_info[];
+
+#endif /* __J721S2_DEVICES_INFO_H */