soc: j7200: Add host id information

Add TISCI Host Id information for AM65x sr2 devices.
Also assign this data to sci_info based on SoC detection.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/Makefile b/Makefile
index 0a415090246ace386ab1ebd66d82ea7dc0266e79..5ea905e5dcb53412d57ad0becf33783ca83845c7 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -90,7 +90,9 @@ J721ESOURCES =\
              soc/j721e/j721e_sec_proxy_info.c \
              soc/j721e/j721e_processors_info.c \
              soc/j721e/j721e_devices_info.c \
-             soc/j721e/j721e_clocks_info.c
+             soc/j721e/j721e_clocks_info.c \
+             soc/j7200/j7200_host_info.c
+
 
 COMMONOBJECTS= $(COMMONSOURCES:.c=.o)
 AM65XOBJECTS=  $(AM65XSOURCES:.c=.o)

diff --git a/common/socinfo.c b/common/socinfo.c
index 97b4daf349b8f0eb304dfa691018ee78c8d2b9ab..77dfeeb8171531b4017189f2f13f5f6a3494e0fe 100644 (file)
--- a/common/socinfo.c
+++ b/common/socinfo.c
@@ -52,6 +52,7 @@
 #include <soc/j721e/j721e_processors_info.h>
 #include <soc/j721e/j721e_devices_info.h>
 #include <soc/j721e/j721e_clocks_info.h>
+#include <soc/j7200/j7200_host_info.h>
 
 /* Assuming these addresses and definitions stay common across K3 devices */
 #define CTRLMMR_WKUP_JTAG_DEVICE_ID    0x43000018
@@ -139,6 +140,14 @@ static void j721e_init(void)
        sci_info->num_clocks = J721E_MAX_CLOCKS;
 }
 
+static void j7200_init(void)
+{
+       struct ti_sci_info *sci_info = &soc_info.sci_info;
+
+       sci_info->host_info = j7200_host_info;
+       sci_info->num_hosts = J7200_MAX_HOST_IDS;
+}
+
 int soc_init(uint32_t host_id)
 {
        char *name;
@@ -184,6 +193,8 @@ int soc_init(uint32_t host_id)
                am654_sr2_init();
        else if (soc_info.soc == J721E)
                j721e_init();
+       else if (soc_info.soc == J7200)
+               j7200_init();
 
        /* ToDo: Add error if sec_proxy_init/sci_init is failed */
        if(!k3_sec_proxy_init())

diff --git a/soc/j7200/j7200_host_info.c b/soc/j7200/j7200_host_info.c
new file mode 100644 (file)
index 0000000..386fe36
--- /dev/null
+++ b/soc/j7200/j7200_host_info.c
@@ -0,0 +1,53 @@
+/*
+ * J7200 Hosts Info
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <tisci.h>
+#include <socinfo.h>
+
+struct ti_sci_host_info j7200_host_info[] = {
+       [0] = {0, "DMSC", "Secure", "Device Management and Security Control"},
+       [1] = {3, "MCU_0_R5_0", "Non Secure", "Cortex R5 context 0 on MCU island"},
+       [2] = {4, "MCU_0_R5_1", "Secure", "Cortex R5 context 1 on MCU island(Boot)"},
+       [3] = {5, "MCU_0_R5_2", "Non Secure", "Cortex R5 context 2 on MCU island"},
+       [4] = {6, "MCU_0_R5_3", "Secure", "Cortex R5 context 3 on MCU island"},
+       [5] = {10, "A72_0", "Secure", "Cortex A72 context 0 on Main island"},
+       [6] = {11, "A72_1", "Secure", "Cortex A72 context 1 on Main island"},
+       [7] = {12, "A72_2", "Non Secure", "Cortex A72 context 2 on Main island"},
+       [8] = {13, "A72_3", "Non Secure", "Cortex A72 context 3 on Main island"},
+       [9] = {14, "A72_4", "Non Secure", "Cortex A72 context 4 on Main island"},
+       [10] = {35, "MAIN_0_R5_0", "Non Secure", "Cortex R5_0 context 0 on Main island"},
+       [11] = {36, "MAIN_0_R5_1", "Secure", "Cortex R5_0 context 1 on Main island"},
+       [12] = {37, "MAIN_0_R5_2", "Non Secure", "Cortex R5_0 context 2 on Main island"},
+       [13] = {38, "MAIN_0_R5_3", "Secure", "Cortex R5_0 context 3 on MCU island"},
+};

diff --git a/soc/j7200/j7200_host_info.h b/soc/j7200/j7200_host_info.h
new file mode 100644 (file)
index 0000000..ffb6a45
--- /dev/null
+++ b/soc/j7200/j7200_host_info.h
@@ -0,0 +1,57 @@
+/*
+ * J7200 Host Info
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __J7200_HOST_INFO_H
+#define __J7200_HOST_INFO_H
+
+#define J7200_HOST_ID_DMSC     0
+#define J7200_HOST_ID_MCU_0_R5_0       3
+#define J7200_HOST_ID_MCU_0_R5_1       4
+#define J7200_HOST_ID_MCU_0_R5_2       5
+#define J7200_HOST_ID_MCU_0_R5_3       6
+#define J7200_HOST_ID_A72_0    10
+#define J7200_HOST_ID_A72_1    11
+#define J7200_HOST_ID_A72_2    12
+#define J7200_HOST_ID_A72_3    13
+#define J7200_HOST_ID_A72_4    14
+#define J7200_HOST_ID_MAIN_0_R5_0      35
+#define J7200_HOST_ID_MAIN_0_R5_1      36
+#define J7200_HOST_ID_MAIN_0_R5_2      37
+#define J7200_HOST_ID_MAIN_0_R5_3      38
+
+#define J7200_MAX_HOST_IDS     14
+
+extern struct ti_sci_host_info j7200_host_info[];
+
+#endif /* __J7200_HOST_INFO_H */
\ No newline at end of file