soc: am65x: Add clocks information
authorLokesh Vutla <lokeshvutla@ti.com>
Thu, 22 Aug 2019 09:49:01 +0000 (15:19 +0530)
committerLokesh Vutla <lokeshvutla@ti.com>
Sun, 25 Aug 2019 03:14:04 +0000 (08:44 +0530)
Add TISCI clock information for AM65x devices

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Makefile
common/socinfo.c
include/soc/am65x/am65x_clocks_info.h [new file with mode: 0644]
include/tisci.h
soc/am65x/am65x_clocks_info.c [new file with mode: 0644]

index 12d8cc759a12895eeb6b7f4db53d6a93b3ef2d0e..cc8b74d6b0d1c3982983bab0d4e42a8733de5b42 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -70,7 +70,8 @@ AM65XSOURCES =\
              soc/am65x/am65x_host_info.c \
              soc/am65x/am65x_sec_proxy_info.c \
              soc/am65x/am65x_processors_info.c \
-             soc/am65x/am65x_devices_info.c
+             soc/am65x/am65x_devices_info.c \
+             soc/am65x/am65x_clocks_info.c
 
 J721ESOURCES =\
              soc/j721e/j721e_host_info.c \
index b938e8ee78bb15d65e1ebccee597f837d7154490..96495acfc39e3a96545d3e70a179a33c95db2568 100644 (file)
@@ -41,6 +41,7 @@
 #include <soc/am65x/am65x_sec_proxy_info.h>
 #include <soc/am65x/am65x_processors_info.h>
 #include <soc/am65x/am65x_devices_info.h>
+#include <soc/am65x/am65x_clocks_info.h>
 #include <soc/j721e/j721e_host_info.h>
 #include <soc/j721e/j721e_sec_proxy_info.h>
 #include <soc/j721e/j721e_processors_info.h>
@@ -98,6 +99,8 @@ static void am654_init(void)
        sci_info->num_processors = AM65X_MAX_PROCESSORS_IDS;
        sci_info->devices_info = am65x_devices_info;
        sci_info->num_devices = AM65X_MAX_DEVICES;
+       sci_info->clocks_info = am65x_clocks_info;
+       sci_info->num_clocks = AM65X_MAX_CLOCKS;
 }
 
 static void j721e_init(void)
diff --git a/include/soc/am65x/am65x_clocks_info.h b/include/soc/am65x/am65x_clocks_info.h
new file mode 100644 (file)
index 0000000..33f23de
--- /dev/null
@@ -0,0 +1,41 @@
+/*
+ * SoC Clocks Info
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __AM65X_CLOCKS_INFO
+#define __AM65X_CLOCKS_INFO
+
+#define AM65X_MAX_CLOCKS       1137
+
+extern struct ti_sci_clocks_info am65x_clocks_info[];
+#endif
index 418ae291295aef812fe6b31171bfb90d44ae5b10..e0b72f627d8d66603d38c8f86cd26f990df821e1 100644 (file)
@@ -75,6 +75,13 @@ struct ti_sci_devices_info {
        char name[60];
 };
 
+struct ti_sci_clocks_info {
+       uint32_t dev_id;
+       uint32_t clk_id;
+       char clk_name[100];
+       char clk_function[100];
+};
+
 struct ti_sci_info {
        uint8_t host_id;
        struct ti_sci_version_info version;
@@ -86,6 +93,8 @@ struct ti_sci_info {
        uint32_t num_processors;
        struct ti_sci_devices_info *devices_info;
        uint32_t num_devices;
+       struct ti_sci_clocks_info *clocks_info;
+       uint32_t num_clocks;
 };
 
 #define MAX_DEVICE_STATE_LENGTH                25
diff --git a/soc/am65x/am65x_clocks_info.c b/soc/am65x/am65x_clocks_info.c
new file mode 100644 (file)
index 0000000..c332c56
--- /dev/null
@@ -0,0 +1,1176 @@
+/*
+ * SoC Clocks Info
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <tisci.h>
+#include <socinfo.h>
+
+struct ti_sci_clocks_info am65x_clocks_info[] = {
+        [0] = {157, 0, "DEV_BOARD0_BUS_SCL3", "Input clock"},
+        [1] = {157, 1, "DEV_BOARD0_BUS_SCL2", "Input clock"},
+        [2] = {157, 2, "DEV_BOARD0_BUS_SCL1", "Input clock"},
+        [3] = {157, 3, "DEV_BOARD0_BUS_SCL0", "Input clock"},
+        [4] = {157, 4, "DEV_BOARD0_BUS_PRG2_RGMII2_TCLK", "Input clock"},
+        [5] = {157, 5, "DEV_BOARD0_BUS_MCU_OSPI1CLK", "Input clock"},
+        [6] = {157, 6, "DEV_BOARD0_BUS_PRG1_RGMII1_TCLK", "Input clock"},
+        [7] = {157, 7, "DEV_BOARD0_BUS_REFCLK1P", "Input muxed clock"},
+        [8] = {157, 8, "DEV_BOARD0_BUS_REFCLK1P_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P"},
+        [9] = {157, 9, "DEV_BOARD0_BUS_REFCLK1P_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P"},
+        [10] = {157, 10, "DEV_BOARD0_BUS_REFCLK1P_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P"},
+        [11] = {157, 11, "DEV_BOARD0_BUS_REFCLK1P_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P"},
+        [12] = {157, 12, "DEV_BOARD0_BUS_MCU_OSPI1LBCLKO", "Input clock"},
+        [13] = {157, 13, "DEV_BOARD0_BUS_MCU_OBSCLK", "Input clock"},
+        [14] = {157, 14, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"},
+        [15] = {157, 15, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"},
+        [16] = {157, 16, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"},
+        [17] = {157, 17, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"},
+        [18] = {157, 18, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"},
+        [19] = {157, 19, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"},
+        [20] = {157, 20, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"},
+        [21] = {157, 21, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"},
+        [22] = {157, 22, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"},
+        [23] = {157, 23, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"},
+        [24] = {157, 24, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"},
+        [25] = {157, 25, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"},
+        [26] = {157, 26, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"},
+        [27] = {157, 27, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"},
+        [28] = {157, 28, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"},
+        [29] = {157, 29, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"},
+        [30] = {157, 30, "DEV_BOARD0_BUS_PRG2_RGMII1_TCLK", "Input clock"},
+        [31] = {157, 31, "DEV_BOARD0_BUS_REFCLK1M", "Input muxed clock"},
+        [32] = {157, 32, "DEV_BOARD0_BUS_REFCLK1M_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M"},
+        [33] = {157, 33, "DEV_BOARD0_BUS_REFCLK1M_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M"},
+        [34] = {157, 34, "DEV_BOARD0_BUS_REFCLK1M_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M"},
+        [35] = {157, 35, "DEV_BOARD0_BUS_REFCLK1M_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M"},
+        [36] = {157, 36, "DEV_BOARD0_BUS_OBSCLK", "Input clock"},
+        [37] = {157, 37, "DEV_BOARD0_BUS_OBSCLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"},
+        [38] = {157, 38, "DEV_BOARD0_BUS_OBSCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"},
+        [39] = {157, 39, "DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"},
+        [40] = {157, 40, "DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"},
+        [41] = {157, 41, "DEV_BOARD0_BUS_OBSCLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"},
+        [42] = {157, 42, "DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"},
+        [43] = {157, 43, "DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLLJM_WRAP_MAIN_4_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"},
+        [44] = {157, 44, "DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLM_WRAP_MAIN_6_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"},
+        [45] = {157, 45, "DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"},
+        [46] = {157, 46, "DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"},
+        [47] = {157, 47, "DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"},
+        [48] = {157, 48, "DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLM_WRAP_MAIN_7_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"},
+        [49] = {157, 49, "DEV_BOARD0_BUS_OBSCLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"},
+        [50] = {157, 50, "DEV_BOARD0_BUS_OBSCLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"},
+        [51] = {157, 51, "DEV_BOARD0_BUS_OBSCLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"},
+        [52] = {157, 52, "DEV_BOARD0_BUS_OBSCLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"},
+        [53] = {157, 53, "DEV_BOARD0_BUS_PRG0_RGMII1_TCLK", "Input clock"},
+        [54] = {157, 54, "DEV_BOARD0_BUS_MCU_OSPI0CLK", "Input clock"},
+        [55] = {157, 55, "DEV_BOARD0_BUS_DSS0PCLK", "Input clock"},
+        [56] = {157, 56, "DEV_BOARD0_BUS_PRG0_RGMII2_TCLK", "Input clock"},
+        [57] = {157, 57, "DEV_BOARD0_BUS_WKUP_SCL0", "Input clock"},
+        [58] = {157, 58, "DEV_BOARD0_BUS_REFCLK0P", "Input muxed clock"},
+        [59] = {157, 59, "DEV_BOARD0_BUS_REFCLK0P_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P"},
+        [60] = {157, 60, "DEV_BOARD0_BUS_REFCLK0P_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P"},
+        [61] = {157, 61, "DEV_BOARD0_BUS_REFCLK0P_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P"},
+        [62] = {157, 62, "DEV_BOARD0_BUS_REFCLK0P_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P"},
+        [63] = {157, 63, "DEV_BOARD0_BUS_REFCLK0M", "Input muxed clock"},
+        [64] = {157, 64, "DEV_BOARD0_BUS_REFCLK0M_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M"},
+        [65] = {157, 65, "DEV_BOARD0_BUS_REFCLK0M_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M"},
+        [66] = {157, 66, "DEV_BOARD0_BUS_REFCLK0M_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M"},
+        [67] = {157, 67, "DEV_BOARD0_BUS_REFCLK0M_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M"},
+        [68] = {157, 68, "DEV_BOARD0_BUS_MCU_OSPI0LBCLKO", "Input clock"},
+        [69] = {157, 69, "DEV_BOARD0_BUS_MCU_CLKOUT", "Input muxed clock"},
+        [70] = {157, 70, "DEV_BOARD0_BUS_MCU_CLKOUT_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT"},
+        [71] = {157, 71, "DEV_BOARD0_BUS_MCU_CLKOUT_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK10", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT"},
+        [72] = {157, 72, "DEV_BOARD0_BUS_MCU_SCL0", "Input clock"},
+        [73] = {157, 73, "DEV_BOARD0_BUS_SYSCLKOUT", "Input clock"},
+        [74] = {157, 74, "DEV_BOARD0_BUS_MCU_SYSCLKOUT", "Input clock"},
+        [75] = {157, 75, "DEV_BOARD0_BUS_PRG1_RGMII1_RCLK", "Output clock"},
+        [76] = {157, 76, "DEV_BOARD0_BUS_PRG1_RGMII2_RCLK", "Output clock"},
+        [77] = {157, 77, "DEV_BOARD0_BUS_GPMCCLK", "Output clock"},
+        [78] = {157, 78, "DEV_BOARD0_BUS_MCASP2AHCLKX", "Output clock"},
+        [79] = {157, 79, "DEV_BOARD0_BUS_MCASP2AHCLKR", "Output clock"},
+        [80] = {157, 80, "DEV_BOARD0_BUS_PRG2_RGMII2_RCLK", "Output clock"},
+        [81] = {157, 81, "DEV_BOARD0_BUS_CPTS_RFT_CLK", "Output clock"},
+        [82] = {157, 82, "DEV_BOARD0_BUS_MCASP0ACLKR", "Output clock"},
+        [83] = {157, 83, "DEV_BOARD0_BUS_MCASP0ACLKX", "Output clock"},
+        [84] = {157, 84, "DEV_BOARD0_BUS_EXT_REFCLK1", "Output clock"},
+        [85] = {157, 85, "DEV_BOARD0_BUS_PRG0_RGMII2_RCLK", "Output clock"},
+        [86] = {157, 86, "DEV_BOARD0_BUS_MCU_OSPI0DQS", "Output clock"},
+        [87] = {157, 87, "DEV_BOARD0_BUS_USB0REFCLKP", "Output clock"},
+        [88] = {157, 88, "DEV_BOARD0_BUS_DSS0EXTPCLKIN", "Output clock"},
+        [89] = {157, 89, "DEV_BOARD0_BUS_SPI1CLK", "Output clock"},
+        [90] = {157, 90, "DEV_BOARD0_BUS_MCASP2ACLKR", "Output clock"},
+        [91] = {157, 91, "DEV_BOARD0_BUS_MCASP1ACLKX", "Output clock"},
+        [92] = {157, 92, "DEV_BOARD0_BUS_MCASP1ACLKR", "Output clock"},
+        [93] = {157, 93, "DEV_BOARD0_BUS_MCASP2ACLKX", "Output clock"},
+        [94] = {157, 94, "DEV_BOARD0_BUS_MCU_RMII1_REFCLK", "Output clock"},
+        [95] = {157, 95, "DEV_BOARD0_BUS_MCU_CPTS_RFT_CLK", "Output clock"},
+        [96] = {157, 96, "DEV_BOARD0_BUS_MCU_RGMII1_TCLK", "Output clock"},
+        [97] = {157, 97, "DEV_BOARD0_BUS_MCU_SPI0CLK", "Output clock"},
+        [98] = {157, 98, "DEV_BOARD0_BUS_MCU_SPI1CLK", "Output clock"},
+        [99] = {157, 99, "DEV_BOARD0_BUS_PRG0_RGMII1_RCLK", "Output clock"},
+        [100] = {157, 100, "DEV_BOARD0_BUS_SPI2CLK", "Output clock"},
+        [101] = {157, 101, "DEV_BOARD0_BUS_WKUP_TCK", "Output clock"},
+        [102] = {157, 102, "DEV_BOARD0_BUS_SPI3CLK", "Output clock"},
+        [103] = {157, 103, "DEV_BOARD0_BUS_USB0REFCLKM", "Output clock"},
+        [104] = {157, 104, "DEV_BOARD0_BUS_MCU_RGMII1_RCLK", "Output clock"},
+        [105] = {157, 105, "DEV_BOARD0_BUS_MCASP0AHCLKR", "Output clock"},
+        [106] = {157, 106, "DEV_BOARD0_BUS_MCU_EXT_REFCLK0", "Output clock"},
+        [107] = {157, 107, "DEV_BOARD0_BUS_MCASP0AHCLKX", "Output clock"},
+        [108] = {157, 108, "DEV_BOARD0_BUS_CCDC0_PCLK", "Output clock"},
+        [109] = {157, 109, "DEV_BOARD0_HFOSC1_CLK", "Output clock"},
+        [110] = {157, 110, "DEV_BOARD0_BUS_MCU_OSPI1DQS", "Output clock"},
+        [111] = {157, 111, "DEV_BOARD0_BUS_MCASP1AHCLKX", "Output clock"},
+        [112] = {157, 112, "DEV_BOARD0_BUS_PCIE1REFCLKM", "Output clock"},
+        [113] = {157, 113, "DEV_BOARD0_BUS_MCASP1AHCLKR", "Output clock"},
+        [114] = {157, 114, "DEV_BOARD0_BUS_PCIE1REFCLKP", "Output clock"},
+        [115] = {157, 115, "DEV_BOARD0_BUS_PRG2_RGMII1_RCLK", "Output clock"},
+        [116] = {157, 116, "DEV_BOARD0_BUS_SPI0CLK", "Output clock"},
+        [117] = {2, 0, "DEV_CAL0_BUS_CLK", "Input clock"},
+        [118] = {2, 1, "DEV_CAL0_BUS_CP_C_CLK", "Input clock"},
+        [119] = {82, 0, "DEV_CBASS0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
+        [120] = {82, 1, "DEV_CBASS0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
+        [121] = {83, 0, "DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
+        [122] = {83, 1, "DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
+        [123] = {84, 0, "DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
+        [124] = {84, 1, "DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
+        [125] = {85, 0, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK", "Input muxed clock"},
+        [126] = {85, 1, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+        [127] = {85, 2, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+        [128] = {85, 3, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+        [129] = {85, 4, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+        [130] = {85, 5, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+        [131] = {85, 6, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+        [132] = {85, 7, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+        [133] = {85, 8, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+        [134] = {85, 9, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
+        [135] = {85, 10, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
+        [136] = {66, 0, "DEV_CCDEBUGSS0_BUS_ATB1_CLK", "Input clock"},
+        [137] = {66, 1, "DEV_CCDEBUGSS0_BUS_ATB0_CLK", "Input clock"},
+        [138] = {66, 2, "DEV_CCDEBUGSS0_BUS_SYS_CLK", "Input clock"},
+        [139] = {66, 3, "DEV_CCDEBUGSS0_BUS_DBG_CLK", "Input clock"},
+        [140] = {66, 4, "DEV_CCDEBUGSS0_BUS_CFG_CLK", "Input clock"},
+        [141] = {3, 0, "DEV_CMPEVENT_INTRTR0_BUS_INTR_CLK", "Input clock"},
+        [142] = {202, 0, "DEV_COMPUTE_CLUSTER_A53_0_BUS_ARM0_CLK", "Input clock"},
+        [143] = {203, 0, "DEV_COMPUTE_CLUSTER_A53_1_BUS_ARM0_CLK", "Input clock"},
+        [144] = {204, 0, "DEV_COMPUTE_CLUSTER_A53_2_BUS_ARM1_CLK", "Input clock"},
+        [145] = {205, 0, "DEV_COMPUTE_CLUSTER_A53_3_BUS_ARM1_CLK", "Input clock"},
+        [146] = {198, 0, "DEV_COMPUTE_CLUSTER_CPAC0_BUS_ARM0_CLK", "Input clock"},
+        [147] = {200, 0, "DEV_COMPUTE_CLUSTER_CPAC1_BUS_ARM1_CLK", "Input clock"},
+        [148] = {196, 0, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_DMSC_CLK", "Input clock"},
+        [149] = {196, 1, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_DBG_CLK", "Input clock"},
+        [150] = {196, 2, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_MSMC_CLK", "Input clock"},
+        [151] = {196, 3, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_CFG_CLK", "Input clock"},
+        [152] = {196, 4, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_GIC_CLK", "Input clock"},
+        [153] = {6, 0, "DEV_CPT2_AGGR0_BUS_VCLK_CLK", "Input clock"},
+        [154] = {213, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_VBUS_CLK", "Input clock"},
+        [155] = {213, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_PROBE_CLK", "Input clock"},
+        [156] = {214, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_VBUS_CLK", "Input clock"},
+        [157] = {214, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_PROBE_CLK", "Input clock"},
+        [158] = {211, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_VBUS_CLK", "Input clock"},
+        [159] = {211, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_PROBE_CLK", "Input clock"},
+        [160] = {212, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_VBUS_CLK", "Input clock"},
+        [161] = {212, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_PROBE_CLK", "Input clock"},
+        [162] = {209, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_VBUS_CLK", "Input clock"},
+        [163] = {209, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_PROBE_CLK", "Input clock"},
+        [164] = {206, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_VBUS_CLK", "Input clock"},
+        [165] = {206, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_PROBE_CLK", "Input clock"},
+        [166] = {208, 0, "DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_VBUS_CLK", "Input clock"},
+        [167] = {208, 1, "DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_PROBE_CLK", "Input clock"},
+        [168] = {215, 0, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_VBUS_CLK", "Input clock"},
+        [169] = {215, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_PROBE_CLK", "Input clock"},
+        [170] = {207, 0, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_VBUS_CLK", "Input clock"},
+        [171] = {207, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_PROBE_CLK", "Input clock"},
+        [172] = {210, 0, "DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_VBUS_CLK", "Input clock"},
+        [173] = {210, 1, "DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_PROBE_CLK", "Input clock"},
+        [174] = {99, 0, "DEV_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"},
+        [175] = {9, 0, "DEV_DCC0_BUS_DCC_INPUT00_CLK", "Input clock"},
+        [176] = {9, 1, "DEV_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+        [177] = {9, 2, "DEV_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+        [178] = {9, 3, "DEV_DCC0_BUS_VBUS_CLK", "Input clock"},
+        [179] = {9, 4, "DEV_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+        [180] = {9, 5, "DEV_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"},
+        [181] = {9, 6, "DEV_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+        [182] = {9, 7, "DEV_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"},
+        [183] = {9, 8, "DEV_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+        [184] = {9, 9, "DEV_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+        [185] = {9, 10, "DEV_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"},
+        [186] = {9, 11, "DEV_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+        [187] = {10, 0, "DEV_DCC1_BUS_DCC_INPUT00_CLK", "Input clock"},
+        [188] = {10, 1, "DEV_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+        [189] = {10, 2, "DEV_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+        [190] = {10, 3, "DEV_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+        [191] = {10, 4, "DEV_DCC1_BUS_VBUS_CLK", "Input clock"},
+        [192] = {10, 5, "DEV_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+        [193] = {10, 6, "DEV_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"},
+        [194] = {10, 7, "DEV_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+        [195] = {10, 8, "DEV_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"},
+        [196] = {10, 9, "DEV_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+        [197] = {10, 10, "DEV_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+        [198] = {10, 11, "DEV_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"},
+        [199] = {10, 12, "DEV_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+        [200] = {11, 0, "DEV_DCC2_BUS_DCC_INPUT00_CLK", "Input clock"},
+        [201] = {11, 1, "DEV_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+        [202] = {11, 2, "DEV_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+        [203] = {11, 3, "DEV_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+        [204] = {11, 4, "DEV_DCC2_BUS_VBUS_CLK", "Input clock"},
+        [205] = {11, 5, "DEV_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+        [206] = {11, 6, "DEV_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"},
+        [207] = {11, 7, "DEV_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+        [208] = {11, 8, "DEV_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"},
+        [209] = {11, 9, "DEV_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+        [210] = {11, 10, "DEV_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+        [211] = {11, 11, "DEV_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"},
+        [212] = {11, 12, "DEV_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+        [213] = {12, 0, "DEV_DCC3_BUS_DCC_INPUT00_CLK", "Input clock"},
+        [214] = {12, 1, "DEV_DCC3_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+        [215] = {12, 2, "DEV_DCC3_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+        [216] = {12, 3, "DEV_DCC3_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+        [217] = {12, 4, "DEV_DCC3_BUS_VBUS_CLK", "Input clock"},
+        [218] = {12, 5, "DEV_DCC3_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+        [219] = {12, 6, "DEV_DCC3_BUS_DCC_INPUT01_CLK", "Input clock"},
+        [220] = {12, 7, "DEV_DCC3_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+        [221] = {12, 8, "DEV_DCC3_BUS_DCC_INPUT02_CLK", "Input clock"},
+        [222] = {12, 9, "DEV_DCC3_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+        [223] = {12, 10, "DEV_DCC3_BUS_DCC_INPUT10_CLK", "Input clock"},
+        [224] = {12, 11, "DEV_DCC3_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+        [225] = {13, 0, "DEV_DCC4_BUS_DCC_INPUT00_CLK", "Input clock"},
+        [226] = {13, 1, "DEV_DCC4_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+        [227] = {13, 2, "DEV_DCC4_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+        [228] = {13, 3, "DEV_DCC4_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+        [229] = {13, 4, "DEV_DCC4_BUS_VBUS_CLK", "Input clock"},
+        [230] = {13, 5, "DEV_DCC4_BUS_DCC_INPUT01_CLK", "Input clock"},
+        [231] = {13, 6, "DEV_DCC4_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+        [232] = {13, 7, "DEV_DCC4_BUS_DCC_INPUT02_CLK", "Input clock"},
+        [233] = {13, 8, "DEV_DCC4_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+        [234] = {13, 9, "DEV_DCC4_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+        [235] = {13, 10, "DEV_DCC4_BUS_DCC_INPUT10_CLK", "Input clock"},
+        [236] = {13, 11, "DEV_DCC4_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+        [237] = {14, 0, "DEV_DCC5_BUS_DCC_INPUT00_CLK", "Input clock"},
+        [238] = {14, 1, "DEV_DCC5_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+        [239] = {14, 2, "DEV_DCC5_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+        [240] = {14, 3, "DEV_DCC5_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+        [241] = {14, 4, "DEV_DCC5_BUS_VBUS_CLK", "Input clock"},
+        [242] = {14, 5, "DEV_DCC5_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+        [243] = {14, 6, "DEV_DCC5_BUS_DCC_INPUT01_CLK", "Input clock"},
+        [244] = {14, 7, "DEV_DCC5_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+        [245] = {14, 8, "DEV_DCC5_BUS_DCC_INPUT02_CLK", "Input clock"},
+        [246] = {14, 9, "DEV_DCC5_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+        [247] = {14, 10, "DEV_DCC5_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+        [248] = {14, 11, "DEV_DCC5_BUS_DCC_INPUT10_CLK", "Input clock"},
+        [249] = {14, 12, "DEV_DCC5_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+        [250] = {15, 0, "DEV_DCC6_BUS_DCC_INPUT00_CLK", "Input clock"},
+        [251] = {15, 1, "DEV_DCC6_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+        [252] = {15, 2, "DEV_DCC6_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+        [253] = {15, 3, "DEV_DCC6_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+        [254] = {15, 4, "DEV_DCC6_BUS_VBUS_CLK", "Input clock"},
+        [255] = {15, 5, "DEV_DCC6_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+        [256] = {15, 6, "DEV_DCC6_BUS_DCC_INPUT01_CLK", "Input clock"},
+        [257] = {15, 7, "DEV_DCC6_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+        [258] = {15, 8, "DEV_DCC6_BUS_DCC_INPUT02_CLK", "Input clock"},
+        [259] = {15, 9, "DEV_DCC6_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+        [260] = {15, 10, "DEV_DCC6_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+        [261] = {15, 11, "DEV_DCC6_BUS_DCC_INPUT10_CLK", "Input clock"},
+        [262] = {15, 12, "DEV_DCC6_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+        [263] = {16, 0, "DEV_DCC7_BUS_DCC_INPUT00_CLK", "Input clock"},
+        [264] = {16, 1, "DEV_DCC7_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+        [265] = {16, 2, "DEV_DCC7_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+        [266] = {16, 3, "DEV_DCC7_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+        [267] = {16, 4, "DEV_DCC7_BUS_VBUS_CLK", "Input clock"},
+        [268] = {16, 5, "DEV_DCC7_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+        [269] = {16, 6, "DEV_DCC7_BUS_DCC_INPUT01_CLK", "Input clock"},
+        [270] = {16, 7, "DEV_DCC7_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+        [271] = {16, 8, "DEV_DCC7_BUS_DCC_INPUT02_CLK", "Input clock"},
+        [272] = {16, 9, "DEV_DCC7_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+        [273] = {16, 10, "DEV_DCC7_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+        [274] = {16, 11, "DEV_DCC7_BUS_DCC_INPUT10_CLK", "Input clock"},
+        [275] = {16, 12, "DEV_DCC7_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+        [276] = {20, 0, "DEV_DDRSS0_BUS_DDRSS_VBUS_CLK", "Input clock"},
+        [277] = {20, 1, "DEV_DDRSS0_BUS_DDRSS_BYP_4X_CLK", "Input clock"},
+        [278] = {20, 2, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
+        [279] = {20, 3, "DEV_DDRSS0_BUS_DDRSS_TCLK", "Input clock"},
+        [280] = {20, 4, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
+        [281] = {20, 5, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
+        [282] = {20, 6, "DEV_DDRSS0_BUS_DDRSS_CFG_CLK", "Input clock"},
+        [283] = {20, 7, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
+        [284] = {20, 8, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
+        [285] = {20, 9, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
+        [286] = {68, 0, "DEV_DEBUGSS0_BUS_ATB1_CLK", "Input clock"},
+        [287] = {68, 1, "DEV_DEBUGSS0_BUS_ATB5_CLK", "Input clock"},
+        [288] = {68, 2, "DEV_DEBUGSS0_BUS_ATB0_CLK", "Input clock"},
+        [289] = {68, 3, "DEV_DEBUGSS0_BUS_SYS_CLK", "Input clock"},
+        [290] = {68, 4, "DEV_DEBUGSS0_BUS_ATB4_CLK", "Input clock"},
+        [291] = {68, 5, "DEV_DEBUGSS0_BUS_CFG_CLK", "Input clock"},
+        [292] = {68, 6, "DEV_DEBUGSS0_BUS_ATB2_CLK", "Input clock"},
+        [293] = {68, 7, "DEV_DEBUGSS0_BUS_DBG_CLK", "Input clock"},
+        [294] = {68, 8, "DEV_DEBUGSS0_BUS_ATB3_CLK", "Input clock"},
+        [295] = {21, 0, "DEV_DEBUGSS_WRAP0_BUS_JTAG_TCK", "Input clock"},
+        [296] = {21, 1, "DEV_DEBUGSS_WRAP0_BUS_ATB_CLK", "Input clock"},
+        [297] = {21, 2, "DEV_DEBUGSS_WRAP0_BUS_TREXPT_CLK", "Input clock"},
+        [298] = {21, 3, "DEV_DEBUGSS_WRAP0_BUS_CORE_CLK", "Input clock"},
+        [299] = {81, 0, "DEV_DEBUGSUSPENDRTR0_BUS_INTR_CLK", "Input clock"},
+        [300] = {117, 0, "DEV_DFTSS0_BUS_VBUSP_CLK_CLK", "Input clock"},
+        [301] = {67, 0, "DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN1_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"},
+        [302] = {67, 1, "DEV_DSS0_BUS_DSS_FUNC_CLK", "Input clock"},
+        [303] = {67, 2, "DEV_DSS0_BUS_DPI_1_IN_CLK", "Input muxed clock"},
+        [304] = {67, 3, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_CLOCKDIVIDER_DSS_BUS_OUT07", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"},
+        [305] = {67, 4, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_BOARD_0_BUS_DSS0EXTPCLKIN", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"},
+        [306] = {67, 5, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_CLOCKDIVIDER_DSS_BUS_OUT1", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"},
+        [307] = {67, 6, "DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN0_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"},
+        [308] = {67, 7, "DEV_DSS0_BUS_DPI_1_OUT_CLK", "Output clock"},
+        [309] = {39, 0, "DEV_ECAP0_BUS_VBUS_CLK", "Input clock"},
+        [310] = {86, 0, "DEV_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"},
+        [311] = {87, 0, "DEV_ECC_AGGR1_BUS_AGGR_CLK", "Input clock"},
+        [312] = {88, 0, "DEV_ECC_AGGR2_BUS_AGGR_CLK", "Input clock"},
+        [313] = {69, 0, "DEV_EFUSE0_BUS_VBUSP_PLL_CLK_CLK", "Input clock"},
+        [314] = {69, 1, "DEV_EFUSE0_BUS_EFC1_CTL_FCLK", "Output clock"},
+        [315] = {69, 2, "DEV_EFUSE0_BUS_EFC0_CTL_FCLK", "Output clock"},
+        [316] = {40, 0, "DEV_EHRPWM0_BUS_VBUSP_CLK", "Input clock"},
+        [317] = {41, 0, "DEV_EHRPWM1_BUS_VBUSP_CLK", "Input clock"},
+        [318] = {42, 0, "DEV_EHRPWM2_BUS_VBUSP_CLK", "Input clock"},
+        [319] = {43, 0, "DEV_EHRPWM3_BUS_VBUSP_CLK", "Input clock"},
+        [320] = {44, 0, "DEV_EHRPWM4_BUS_VBUSP_CLK", "Input clock"},
+        [321] = {45, 0, "DEV_EHRPWM5_BUS_VBUSP_CLK", "Input clock"},
+        [322] = {46, 0, "DEV_ELM0_BUS_VBUSP_CLK", "Input clock"},
+        [323] = {49, 0, "DEV_EQEP0_BUS_VBUS_CLK", "Input clock"},
+        [324] = {50, 0, "DEV_EQEP1_BUS_VBUS_CLK", "Input clock"},
+        [325] = {51, 0, "DEV_EQEP2_BUS_VBUS_CLK", "Input clock"},
+        [326] = {52, 0, "DEV_ESM0_BUS_CLK", "Input clock"},
+        [327] = {56, 0, "DEV_GIC0_BUS_VCLK_CLK", "Input clock"},
+        [328] = {57, 0, "DEV_GPIO0_BUS_MMR_CLK", "Input clock"},
+        [329] = {58, 0, "DEV_GPIO1_BUS_MMR_CLK", "Input clock"},
+        [330] = {100, 0, "DEV_GPIOMUX_INTRTR0_BUS_INTR_CLK", "Input clock"},
+        [331] = {60, 0, "DEV_GPMC0_BUS_FUNC_CLK", "Input muxed clock"},
+        [332] = {60, 1, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
+        [333] = {60, 2, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK3", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
+        [334] = {60, 3, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK2", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
+        [335] = {60, 4, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
+        [336] = {60, 5, "DEV_GPMC0_BUS_PI_GPMC_RET_CLK", "Input clock"},
+        [337] = {60, 6, "DEV_GPMC0_BUS_VBUSP_CLK", "Input clock"},
+        [338] = {60, 7, "DEV_GPMC0_BUS_PO_GPMC_DEV_CLK", "Output clock"},
+        [339] = {65, 0, "DEV_GPU0_BUS_MEM_CLK", "Input clock"},
+        [340] = {65, 1, "DEV_GPU0_BUS_HYD_CORE_CLK", "Input clock"},
+        [341] = {65, 2, "DEV_GPU0_BUS_SGX_CORE_CLK", "Input clock"},
+        [342] = {65, 3, "DEV_GPU0_BUS_SYS_CLK", "Input clock"},
+        [343] = {232, 0, "DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_OSC_CLK", "Input clock"},
+        [344] = {232, 1, "DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_CLK", "Input clock"},
+        [345] = {231, 0, "DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_OSC_CLK", "Input clock"},
+        [346] = {231, 1, "DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_CLK", "Input clock"},
+        [347] = {61, 0, "DEV_GTC0_BUS_VBUSP_CLK", "Input muxed clock"},
+        [348] = {61, 1, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+        [349] = {61, 2, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+        [350] = {61, 3, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+        [351] = {61, 4, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+        [352] = {61, 5, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+        [353] = {61, 6, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+        [354] = {61, 7, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+        [355] = {61, 8, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+        [356] = {110, 0, "DEV_I2C0_BUS_CLK", "Input clock"},
+        [357] = {110, 1, "DEV_I2C0_BUS_PISYS_CLK", "Input clock"},
+        [358] = {110, 2, "DEV_I2C0_BUS_PISCL", "Output clock"},
+        [359] = {111, 0, "DEV_I2C1_BUS_CLK", "Input clock"},
+        [360] = {111, 1, "DEV_I2C1_BUS_PISYS_CLK", "Input clock"},
+        [361] = {111, 2, "DEV_I2C1_BUS_PISCL", "Output clock"},
+        [362] = {112, 0, "DEV_I2C2_BUS_CLK", "Input clock"},
+        [363] = {112, 1, "DEV_I2C2_BUS_PISYS_CLK", "Input clock"},
+        [364] = {112, 2, "DEV_I2C2_BUS_PISCL", "Output clock"},
+        [365] = {113, 0, "DEV_I2C3_BUS_CLK", "Input clock"},
+        [366] = {113, 1, "DEV_I2C3_BUS_PISYS_CLK", "Input clock"},
+        [367] = {113, 2, "DEV_I2C3_BUS_PISCL", "Output clock"},
+        [368] = {217, 0, "DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0_BUS_DBG_CLK", "Input clock"},
+        [369] = {97, 0, "DEV_MAIN2MCU_LVL_INTRTR0_BUS_INTR_CLK", "Input clock"},
+        [370] = {98, 0, "DEV_MAIN2MCU_PLS_INTRTR0_BUS_INTR_CLK", "Input clock"},
+        [371] = {104, 0, "DEV_MCASP0_BUS_AUX_CLK", "Input muxed clock"},
+        [372] = {104, 1, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+        [373] = {104, 2, "DEV_MCASP0_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+        [374] = {104, 3, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+        [375] = {104, 4, "DEV_MCASP0_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+        [376] = {104, 5, "DEV_MCASP0_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+        [377] = {104, 6, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+        [378] = {104, 7, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+        [379] = {104, 8, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+        [380] = {104, 9, "DEV_MCASP0_BUS_VBUSP_CLK", "Input clock"},
+        [381] = {104, 10, "DEV_MCASP0_BUS_MCASP_AHCLKX_PIN", "Input clock"},
+        [382] = {104, 11, "DEV_MCASP0_BUS_MCASP_AHCLKR_PIN", "Input clock"},
+        [383] = {105, 0, "DEV_MCASP1_BUS_AUX_CLK", "Input muxed clock"},
+        [384] = {105, 1, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+        [385] = {105, 2, "DEV_MCASP1_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+        [386] = {105, 3, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+        [387] = {105, 4, "DEV_MCASP1_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+        [388] = {105, 5, "DEV_MCASP1_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+        [389] = {105, 6, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+        [390] = {105, 7, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+        [391] = {105, 8, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+        [392] = {105, 9, "DEV_MCASP1_BUS_VBUSP_CLK", "Input clock"},
+        [393] = {105, 10, "DEV_MCASP1_BUS_MCASP_AHCLKX_PIN", "Input clock"},
+        [394] = {105, 11, "DEV_MCASP1_BUS_MCASP_AHCLKR_PIN", "Input clock"},
+        [395] = {106, 0, "DEV_MCASP2_BUS_AUX_CLK", "Input muxed clock"},
+        [396] = {106, 1, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+        [397] = {106, 2, "DEV_MCASP2_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+        [398] = {106, 3, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+        [399] = {106, 4, "DEV_MCASP2_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+        [400] = {106, 5, "DEV_MCASP2_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT2", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+        [401] = {106, 6, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+        [402] = {106, 7, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+        [403] = {106, 8, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+        [404] = {106, 9, "DEV_MCASP2_BUS_VBUSP_CLK", "Input clock"},
+        [405] = {106, 10, "DEV_MCASP2_BUS_MCASP_AHCLKX_PIN", "Input clock"},
+        [406] = {106, 11, "DEV_MCASP2_BUS_MCASP_AHCLKR_PIN", "Input clock"},
+        [407] = {137, 0, "DEV_MCSPI0_BUS_IO_CLKSPII_CLK", "Input clock"},
+        [408] = {137, 1, "DEV_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"},
+        [409] = {137, 2, "DEV_MCSPI0_BUS_VBUSP_CLK", "Input clock"},
+        [410] = {137, 3, "DEV_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"},
+        [411] = {138, 0, "DEV_MCSPI1_BUS_IO_CLKSPII_CLK", "Input clock"},
+        [412] = {138, 1, "DEV_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"},
+        [413] = {138, 2, "DEV_MCSPI1_BUS_VBUSP_CLK", "Input clock"},
+        [414] = {138, 3, "DEV_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"},
+        [415] = {139, 0, "DEV_MCSPI2_BUS_IO_CLKSPII_CLK", "Input clock"},
+        [416] = {139, 1, "DEV_MCSPI2_BUS_CLKSPIREF_CLK", "Input clock"},
+        [417] = {139, 2, "DEV_MCSPI2_BUS_VBUSP_CLK", "Input clock"},
+        [418] = {139, 3, "DEV_MCSPI2_BUS_IO_CLKSPIO_CLK", "Output clock"},
+        [419] = {140, 0, "DEV_MCSPI3_BUS_IO_CLKSPII_CLK", "Input clock"},
+        [420] = {140, 1, "DEV_MCSPI3_BUS_CLKSPIREF_CLK", "Input clock"},
+        [421] = {140, 2, "DEV_MCSPI3_BUS_VBUSP_CLK", "Input clock"},
+        [422] = {140, 3, "DEV_MCSPI3_BUS_IO_CLKSPIO_CLK", "Output clock"},
+        [423] = {141, 0, "DEV_MCSPI4_BUS_CLKSPIREF_CLK", "Input clock"},
+        [424] = {141, 1, "DEV_MCSPI4_BUS_VBUSP_CLK", "Input clock"},
+        [425] = {0, 0, "DEV_MCU_ADC0_BUS_VBUS_CLK", "Input clock"},
+        [426] = {0, 1, "DEV_MCU_ADC0_BUS_SYS_CLK", "Input clock"},
+        [427] = {0, 2, "DEV_MCU_ADC0_BUS_ADC_CLK", "Input muxed clock"},
+        [428] = {0, 3, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
+        [429] = {0, 4, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
+        [430] = {0, 5, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
+        [431] = {0, 6, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
+        [432] = {1, 0, "DEV_MCU_ADC1_BUS_VBUS_CLK", "Input clock"},
+        [433] = {1, 1, "DEV_MCU_ADC1_BUS_SYS_CLK", "Input clock"},
+        [434] = {1, 2, "DEV_MCU_ADC1_BUS_ADC_CLK", "Input muxed clock"},
+        [435] = {1, 3, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
+        [436] = {1, 4, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
+        [437] = {1, 5, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
+        [438] = {1, 6, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
+        [439] = {129, 0, "DEV_MCU_ARMSS0_BUS_INTERFACE_CLK", "Input clock"},
+        [440] = {159, 0, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_CLK", "Input clock"},
+        [441] = {159, 1, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE", "Input muxed clock"},
+        [442] = {159, 2, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE"},
+        [443] = {159, 3, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK", "Input muxed clock"},
+        [444] = {159, 4, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"},
+        [445] = {159, 5, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"},
+        [446] = {245, 0, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_CLK", "Input clock"},
+        [447] = {245, 1, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE", "Input muxed clock"},
+        [448] = {245, 2, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE"},
+        [449] = {245, 3, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK", "Input muxed clock"},
+        [450] = {245, 4, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"},
+        [451] = {245, 5, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"},
+        [452] = {89, 0, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_8_CLK", "Input clock"},
+        [453] = {89, 1, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_4_CLK", "Input clock"},
+        [454] = {89, 2, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"},
+        [455] = {90, 0, "DEV_MCU_CBASS_DEBUG0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"},
+        [456] = {91, 0, "DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_4_CLK", "Input clock"},
+        [457] = {91, 1, "DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"},
+        [458] = {5, 0, "DEV_MCU_CPSW0_BUS_GMII1_MR_CLK", "Input clock"},
+        [459] = {5, 1, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_250_CLK", "Input clock"},
+        [460] = {5, 2, "DEV_MCU_CPSW0_BUS_CPTS_RFT_CLK", "Input clock"},
+        [461] = {5, 3, "DEV_MCU_CPSW0_BUS_GMII1_MT_CLK", "Input clock"},
+        [462] = {5, 4, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_5_CLK", "Input clock"},
+        [463] = {5, 5, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_50_CLK", "Input clock"},
+        [464] = {5, 6, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK", "Input muxed clock"},
+        [465] = {5, 7, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"},
+        [466] = {5, 8, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_BOARD_0_BUS_MCU_RMII1_REFCLK", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"},
+        [467] = {5, 9, "DEV_MCU_CPSW0_BUS_GMII_RFT_CLK", "Input clock"},
+        [468] = {5, 10, "DEV_MCU_CPSW0_BUS_CPPI_CLK_CLK", "Input clock"},
+        [469] = {5, 11, "DEV_MCU_CPSW0_BUS_CPTS_GENF0_0", "Output clock"},
+        [470] = {7, 0, "DEV_MCU_CPT2_AGGR0_BUS_VCLK_CLK", "Input clock"},
+        [471] = {107, 0, "DEV_MCU_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"},
+        [472] = {17, 0, "DEV_MCU_DCC0_BUS_DCC_INPUT00_CLK", "Input clock"},
+        [473] = {17, 1, "DEV_MCU_DCC0_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+        [474] = {17, 2, "DEV_MCU_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+        [475] = {17, 3, "DEV_MCU_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+        [476] = {17, 4, "DEV_MCU_DCC0_BUS_VBUS_CLK", "Input clock"},
+        [477] = {17, 5, "DEV_MCU_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+        [478] = {17, 6, "DEV_MCU_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"},
+        [479] = {17, 7, "DEV_MCU_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+        [480] = {17, 8, "DEV_MCU_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"},
+        [481] = {17, 9, "DEV_MCU_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+        [482] = {17, 10, "DEV_MCU_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+        [483] = {17, 11, "DEV_MCU_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"},
+        [484] = {17, 12, "DEV_MCU_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+        [485] = {18, 0, "DEV_MCU_DCC1_BUS_DCC_INPUT00_CLK", "Input clock"},
+        [486] = {18, 1, "DEV_MCU_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+        [487] = {18, 2, "DEV_MCU_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+        [488] = {18, 3, "DEV_MCU_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+        [489] = {18, 4, "DEV_MCU_DCC1_BUS_VBUS_CLK", "Input clock"},
+        [490] = {18, 5, "DEV_MCU_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+        [491] = {18, 6, "DEV_MCU_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"},
+        [492] = {18, 7, "DEV_MCU_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+        [493] = {18, 8, "DEV_MCU_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"},
+        [494] = {18, 9, "DEV_MCU_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+        [495] = {18, 10, "DEV_MCU_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+        [496] = {18, 11, "DEV_MCU_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"},
+        [497] = {18, 12, "DEV_MCU_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+        [498] = {19, 0, "DEV_MCU_DCC2_BUS_DCC_INPUT00_CLK", "Input clock"},
+        [499] = {19, 1, "DEV_MCU_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+        [500] = {19, 2, "DEV_MCU_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+        [501] = {19, 3, "DEV_MCU_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+        [502] = {19, 4, "DEV_MCU_DCC2_BUS_VBUS_CLK", "Input clock"},
+        [503] = {19, 5, "DEV_MCU_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+        [504] = {19, 6, "DEV_MCU_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"},
+        [505] = {19, 7, "DEV_MCU_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+        [506] = {19, 8, "DEV_MCU_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"},
+        [507] = {19, 9, "DEV_MCU_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+        [508] = {19, 10, "DEV_MCU_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+        [509] = {19, 11, "DEV_MCU_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"},
+        [510] = {19, 12, "DEV_MCU_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+        [511] = {71, 0, "DEV_MCU_DEBUGSS0_BUS_ATB1_CLK", "Input clock"},
+        [512] = {71, 1, "DEV_MCU_DEBUGSS0_BUS_ATB0_CLK", "Input clock"},
+        [513] = {71, 2, "DEV_MCU_DEBUGSS0_BUS_SYS_CLK", "Input clock"},
+        [514] = {71, 3, "DEV_MCU_DEBUGSS0_BUS_CFG_CLK", "Input clock"},
+        [515] = {71, 4, "DEV_MCU_DEBUGSS0_BUS_ATB2_CLK", "Input clock"},
+        [516] = {71, 5, "DEV_MCU_DEBUGSS0_BUS_DBG_CLK", "Input clock"},
+        [517] = {71, 6, "DEV_MCU_DEBUGSS0_BUS_ATB3_CLK", "Input clock"},
+        [518] = {92, 0, "DEV_MCU_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"},
+        [519] = {93, 0, "DEV_MCU_ECC_AGGR1_BUS_AGGR_CLK", "Input clock"},
+        [520] = {72, 0, "DEV_MCU_EFUSE0_BUS_VBUSP_CLK_CLK", "Input clock"},
+        [521] = {72, 1, "DEV_MCU_EFUSE0_BUS_EFC3_CTL_FCLK", "Output clock"},
+        [522] = {72, 2, "DEV_MCU_EFUSE0_BUS_EFC0_CTL_FCLK", "Output clock"},
+        [523] = {72, 3, "DEV_MCU_EFUSE0_BUS_EFC1_CTL_FCLK", "Output clock"},
+        [524] = {72, 4, "DEV_MCU_EFUSE0_BUS_EFC2_CTL_FCLK", "Output clock"},
+        [525] = {53, 0, "DEV_MCU_ESM0_BUS_CLK", "Input clock"},
+        [526] = {55, 0, "DEV_MCU_FSS0_BUS_HPB_CLKX1_INV_CLK", "Input clock"},
+        [527] = {55, 1, "DEV_MCU_FSS0_BUS_VBUS_CLK", "Input clock"},
+        [528] = {55, 2, "DEV_MCU_FSS0_BUS_OSPI1_ICLK_CLK", "Input muxed clock"},
+        [529] = {55, 3, "DEV_MCU_FSS0_BUS_OSPI1_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI1DQS", "Parent input clock option to DEV_MCU_FSS0_BUS_OSPI1_ICLK_CLK"},
+        [530] = {55, 4, "DEV_MCU_FSS0_BUS_OSPI1_ICLK_CLK_PARENT_FSS_MCU_0_BUS_OSPI1_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_BUS_OSPI1_ICLK_CLK"},
+        [531] = {55, 5, "DEV_MCU_FSS0_BUS_OSPI0_RCLK_CLK", "Input muxed clock"},
+        [532] = {55, 6, "DEV_MCU_FSS0_BUS_OSPI0_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_BUS_OSPI0_RCLK_CLK"},
+        [533] = {55, 7, "DEV_MCU_FSS0_BUS_OSPI0_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_BUS_OSPI0_RCLK_CLK"},
+        [534] = {55, 8, "DEV_MCU_FSS0_BUS_HPB_CLKX2_CLK", "Input clock"},
+        [535] = {55, 9, "DEV_MCU_FSS0_BUS_HPB_CLKX2_INV_CLK", "Input clock"},
+        [536] = {55, 10, "DEV_MCU_FSS0_BUS_OSPI0_ICLK_CLK", "Input muxed clock"},
+        [537] = {55, 11, "DEV_MCU_FSS0_BUS_OSPI0_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI0DQS", "Parent input clock option to DEV_MCU_FSS0_BUS_OSPI0_ICLK_CLK"},
+        [538] = {55, 12, "DEV_MCU_FSS0_BUS_OSPI0_ICLK_CLK_PARENT_FSS_MCU_0_BUS_OSPI0_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_BUS_OSPI0_ICLK_CLK"},
+        [539] = {55, 13, "DEV_MCU_FSS0_BUS_HPB_CLKX1_CLK", "Input clock"},
+        [540] = {55, 14, "DEV_MCU_FSS0_BUS_OSPI0_DQS_CLK", "Input clock"},
+        [541] = {55, 15, "DEV_MCU_FSS0_BUS_OSPI1_DQS_CLK", "Input clock"},
+        [542] = {55, 16, "DEV_MCU_FSS0_BUS_OSPI1_RCLK_CLK", "Input muxed clock"},
+        [543] = {55, 17, "DEV_MCU_FSS0_BUS_OSPI1_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_BUS_OSPI1_RCLK_CLK"},
+        [544] = {55, 18, "DEV_MCU_FSS0_BUS_OSPI1_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_BUS_OSPI1_RCLK_CLK"},
+        [545] = {55, 19, "DEV_MCU_FSS0_BUS_OSPI0_OCLK_CLK", "Output clock"},
+        [546] = {55, 20, "DEV_MCU_FSS0_BUS_OSPI1_OCLK_CLK", "Output clock"},
+        [547] = {114, 0, "DEV_MCU_I2C0_BUS_CLK", "Input clock"},
+        [548] = {114, 1, "DEV_MCU_I2C0_BUS_PISYS_CLK", "Input clock"},
+        [549] = {114, 2, "DEV_MCU_I2C0_BUS_PISCL", "Output clock"},
+        [550] = {102, 0, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK", "Input muxed clock"},
+        [551] = {102, 1, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
+        [552] = {102, 2, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
+        [553] = {102, 3, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
+        [554] = {102, 4, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
+        [555] = {102, 5, "DEV_MCU_MCAN0_BUS_MCANSS_HCLK_CLK", "Input clock"},
+        [556] = {103, 0, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK", "Input muxed clock"},
+        [557] = {103, 1, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
+        [558] = {103, 2, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
+        [559] = {103, 3, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
+        [560] = {103, 4, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
+        [561] = {103, 5, "DEV_MCU_MCAN1_BUS_MCANSS_HCLK_CLK", "Input clock"},
+        [562] = {142, 0, "DEV_MCU_MCSPI0_BUS_IO_CLKSPII_CLK", "Input clock"},
+        [563] = {142, 1, "DEV_MCU_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"},
+        [564] = {142, 2, "DEV_MCU_MCSPI0_BUS_VBUSP_CLK", "Input clock"},
+        [565] = {142, 3, "DEV_MCU_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"},
+        [566] = {143, 0, "DEV_MCU_MCSPI1_BUS_IO_CLKSPII_CLK", "Input clock"},
+        [567] = {143, 1, "DEV_MCU_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"},
+        [568] = {143, 2, "DEV_MCU_MCSPI1_BUS_VBUSP_CLK", "Input clock"},
+        [569] = {143, 3, "DEV_MCU_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"},
+        [570] = {144, 0, "DEV_MCU_MCSPI2_BUS_CLKSPIREF_CLK", "Input clock"},
+        [571] = {144, 1, "DEV_MCU_MCSPI2_BUS_VBUSP_CLK", "Input clock"},
+        [572] = {116, 0, "DEV_MCU_MSRAM0_BUS_CCLK_CLK", "Input clock"},
+        [573] = {116, 1, "DEV_MCU_MSRAM0_BUS_VCLK_CLK", "Input clock"},
+        [574] = {119, 0, "DEV_MCU_NAVSS0_BUS_UDMASS_VD2CLK", "Input clock"},
+        [575] = {119, 1, "DEV_MCU_NAVSS0_BUS_CPSW0CLK", "Input clock"},
+        [576] = {119, 2, "DEV_MCU_NAVSS0_BUS_MODSS_VD2CLK", "Input clock"},
+        [577] = {119, 3, "DEV_MCU_NAVSS0_BUS_PDMA_MCU1CLK", "Input clock"},
+        [578] = {75, 0, "DEV_MCU_PBIST0_BUS_CLK1_CLK", "Input clock"},
+        [579] = {75, 1, "DEV_MCU_PBIST0_BUS_CLK4_CLK", "Input clock"},
+        [580] = {75, 2, "DEV_MCU_PBIST0_BUS_CLK2_CLK", "Input clock"},
+        [581] = {125, 0, "DEV_MCU_PDMA0_BUS_VCLK", "Input clock"},
+        [582] = {126, 0, "DEV_MCU_PDMA1_BUS_VCLK", "Input clock"},
+        [583] = {108, 0, "DEV_MCU_PLL_MMR0_BUS_VBUSP_CLK", "Input clock"},
+        [584] = {127, 0, "DEV_MCU_PSRAM0_BUS_CLK_CLK", "Input clock"},
+        [585] = {78, 0, "DEV_MCU_ROM0_BUS_CLK_CLK", "Input clock"},
+        [586] = {134, 0, "DEV_MCU_RTI0_BUS_RTI_CLK", "Input muxed clock"},
+        [587] = {134, 1, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
+        [588] = {134, 2, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
+        [589] = {134, 3, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
+        [590] = {134, 4, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
+        [591] = {134, 5, "DEV_MCU_RTI0_BUS_VBUSP_CLK", "Input clock"},
+        [592] = {135, 0, "DEV_MCU_RTI1_BUS_RTI_CLK", "Input muxed clock"},
+        [593] = {135, 1, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
+        [594] = {135, 2, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
+        [595] = {135, 3, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
+        [596] = {135, 4, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
+        [597] = {135, 5, "DEV_MCU_RTI1_BUS_VBUSP_CLK", "Input clock"},
+        [598] = {109, 0, "DEV_MCU_SEC_MMR0_BUS_VBUSP_CLK", "Input clock"},
+        [599] = {35, 0, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+        [600] = {35, 1, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [601] = {35, 2, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [602] = {35, 3, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [603] = {35, 4, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [604] = {35, 5, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [605] = {35, 6, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [606] = {35, 7, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [607] = {35, 8, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [608] = {35, 9, "DEV_MCU_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"},
+        [609] = {36, 0, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+        [610] = {36, 1, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [611] = {36, 2, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [612] = {36, 3, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [613] = {36, 4, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [614] = {36, 5, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [615] = {36, 6, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [616] = {36, 7, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [617] = {36, 8, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [618] = {36, 9, "DEV_MCU_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"},
+        [619] = {37, 0, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+        [620] = {37, 1, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [621] = {37, 2, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [622] = {37, 3, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [623] = {37, 4, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [624] = {37, 5, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [625] = {37, 6, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [626] = {37, 7, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [627] = {37, 8, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [628] = {37, 9, "DEV_MCU_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"},
+        [629] = {38, 0, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+        [630] = {38, 1, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [631] = {38, 2, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [632] = {38, 3, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [633] = {38, 4, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [634] = {38, 5, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [635] = {38, 6, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [636] = {38, 7, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [637] = {38, 8, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [638] = {38, 9, "DEV_MCU_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"},
+        [639] = {149, 0, "DEV_MCU_UART0_BUS_FCLK_CLK", "Input muxed clock"},
+        [640] = {149, 1, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"},
+        [641] = {149, 2, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"},
+        [642] = {149, 3, "DEV_MCU_UART0_BUS_VBUSP_CLK", "Input clock"},
+        [643] = {47, 0, "DEV_MMCSD0_BUS_EMMCSDSS_VBUS_CLK", "Input clock"},
+        [644] = {47, 1, "DEV_MMCSD0_BUS_EMMCSDSS_XIN_CLK", "Input clock"},
+        [645] = {48, 0, "DEV_MMCSD1_BUS_EMMCSDSS_VBUS_CLK", "Input clock"},
+        [646] = {48, 1, "DEV_MMCSD1_BUS_EMMCSDSS_XIN_CLK", "Input clock"},
+        [647] = {234, 0, "DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0_BUS_UNDEFINEDCHAIN1_FCLK", "Input clock"},
+        [648] = {234, 1, "DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0_BUS_UNDEFINEDCHAIN0_FCLK", "Input clock"},
+        [649] = {235, 0, "DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN1_FCLK", "Input clock"},
+        [650] = {235, 1, "DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN0_FCLK", "Input clock"},
+        [651] = {235, 2, "DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN2_FCLK", "Input clock"},
+        [652] = {118, 0, "DEV_NAVSS0_BUS_UDMASS_VD2CLK", "Input clock"},
+        [653] = {118, 1, "DEV_NAVSS0_BUS_ICSS_G2CLK", "Input clock"},
+        [654] = {118, 2, "DEV_NAVSS0_BUS_ICSS_G0CLK", "Input clock"},
+        [655] = {118, 3, "DEV_NAVSS0_BUS_RCLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK", "Input clock"},
+        [656] = {118, 4, "DEV_NAVSS0_BUS_MSMC0CLK", "Input clock"},
+        [657] = {118, 5, "DEV_NAVSS0_BUS_RCLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"},
+        [658] = {118, 6, "DEV_NAVSS0_BUS_RCLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK", "Input clock"},
+        [659] = {118, 7, "DEV_NAVSS0_BUS_MODSS_VD2CLK", "Input clock"},
+        [660] = {118, 8, "DEV_NAVSS0_BUS_RCLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0", "Input clock"},
+        [661] = {118, 9, "DEV_NAVSS0_BUS_PDMA_MAIN1CLK", "Input clock"},
+        [662] = {118, 10, "DEV_NAVSS0_BUS_NBSS_VCLK", "Input clock"},
+        [663] = {118, 11, "DEV_NAVSS0_BUS_RCLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"},
+        [664] = {118, 12, "DEV_NAVSS0_BUS_NBSS_VD2CLK", "Input clock"},
+        [665] = {118, 13, "DEV_NAVSS0_BUS_ICSS_G1CLK", "Input clock"},
+        [666] = {118, 14, "DEV_NAVSS0_BUS_RCLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1", "Input clock"},
+        [667] = {118, 15, "DEV_NAVSS0_BUS_CPTS0_GENF4_0", "Output clock"},
+        [668] = {118, 16, "DEV_NAVSS0_BUS_CPTS0_GENF5_0", "Output clock"},
+        [669] = {118, 17, "DEV_NAVSS0_BUS_CPTS0_GENF2_0", "Output clock"},
+        [670] = {118, 18, "DEV_NAVSS0_BUS_CPTS0_GENF3_0", "Output clock"},
+        [671] = {216, 0, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_PLL_CLK", "Input clock"},
+        [672] = {216, 1, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN1_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"},
+        [673] = {216, 2, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN0_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"},
+        [674] = {73, 0, "DEV_PBIST0_BUS_CLK1_CLK", "Input clock"},
+        [675] = {73, 1, "DEV_PBIST0_BUS_CLK4_CLK", "Input clock"},
+        [676] = {73, 2, "DEV_PBIST0_BUS_CLK2_CLK", "Input clock"},
+        [677] = {74, 0, "DEV_PBIST1_BUS_CLK1_CLK", "Input clock"},
+        [678] = {74, 1, "DEV_PBIST1_BUS_CLK4_CLK", "Input clock"},
+        [679] = {74, 2, "DEV_PBIST1_BUS_CLK2_CLK", "Input clock"},
+        [680] = {120, 0, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1", "Input clock"},
+        [681] = {120, 1, "DEV_PCIE0_BUS_PCIE_CBA_CLK", "Input clock"},
+        [682] = {120, 2, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK", "Input clock"},
+        [683] = {120, 3, "DEV_PCIE0_BUS_PCIE_TXI0_CLK", "Input clock"},
+        [684] = {120, 4, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"},
+        [685] = {120, 5, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"},
+        [686] = {120, 6, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0", "Input clock"},
+        [687] = {120, 7, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK", "Input clock"},
+        [688] = {120, 8, "DEV_PCIE0_BUS_PCIE_TXR1_CLK", "Output clock"},
+        [689] = {120, 9, "DEV_PCIE0_BUS_PCIE_TXR0_CLK", "Output clock"},
+        [690] = {121, 0, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1", "Input clock"},
+        [691] = {121, 1, "DEV_PCIE1_BUS_PCIE_CBA_CLK", "Input clock"},
+        [692] = {121, 2, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK", "Input clock"},
+        [693] = {121, 3, "DEV_PCIE1_BUS_PCIE_TXI0_CLK", "Input clock"},
+        [694] = {121, 4, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"},
+        [695] = {121, 5, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"},
+        [696] = {121, 6, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0", "Input clock"},
+        [697] = {121, 7, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK", "Input clock"},
+        [698] = {121, 8, "DEV_PCIE1_BUS_PCIE_TXR0_CLK", "Output clock"},
+        [699] = {123, 0, "DEV_PDMA0_BUS_VCLK", "Input clock"},
+        [700] = {124, 0, "DEV_PDMA1_BUS_VCLK", "Input clock"},
+        [701] = {122, 0, "DEV_PDMA_DEBUG0_BUS_VCLK", "Input clock"},
+        [702] = {76, 0, "DEV_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK", "Input clock"},
+        [703] = {76, 1, "DEV_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"},
+        [704] = {76, 2, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input muxed clock"},
+        [705] = {76, 3, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"},
+        [706] = {76, 4, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"},
+        [707] = {101, 0, "DEV_PLL_MMR0_BUS_VBUSP_CLK", "Input clock"},
+        [708] = {62, 0, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_5_CLK", "Input clock"},
+        [709] = {62, 1, "DEV_PRU_ICSSG0_BUS_WIZ1_TX_SLV_CLK", "Input clock"},
+        [710] = {62, 2, "DEV_PRU_ICSSG0_BUS_WIZ0_RX_SLV_CLK", "Input clock"},
+        [711] = {62, 3, "DEV_PRU_ICSSG0_BUS_VCLK_CLK", "Input clock"},
+        [712] = {62, 4, "DEV_PRU_ICSSG0_BUS_UCLK_CLK", "Input clock"},
+        [713] = {62, 5, "DEV_PRU_ICSSG0_BUS_WIZ0_TX_SLV_CLK", "Input clock"},
+        [714] = {62, 6, "DEV_PRU_ICSSG0_BUS_WIZ1_RX_SLV_CLK", "Input clock"},
+        [715] = {62, 7, "DEV_PRU_ICSSG0_BUS_PR1_RGMII1_RXC_I", "Input clock"},
+        [716] = {62, 8, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_250_CLK", "Input clock"},
+        [717] = {62, 9, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_50_CLK", "Input clock"},
+        [718] = {62, 10, "DEV_PRU_ICSSG0_BUS_IEP_CLK", "Input muxed clock"},
+        [719] = {62, 11, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+        [720] = {62, 12, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+        [721] = {62, 13, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+        [722] = {62, 14, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+        [723] = {62, 15, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+        [724] = {62, 16, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+        [725] = {62, 17, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+        [726] = {62, 18, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+        [727] = {62, 19, "DEV_PRU_ICSSG0_BUS_CORE_CLK", "Input muxed clock"},
+        [728] = {62, 20, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"},
+        [729] = {62, 21, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"},
+        [730] = {62, 22, "DEV_PRU_ICSSG0_BUS_PR1_RGMII0_RXC_I", "Input clock"},
+        [731] = {62, 23, "DEV_PRU_ICSSG0_BUS_PR1_RGMII1_TXC_I", "Output clock"},
+        [732] = {62, 24, "DEV_PRU_ICSSG0_BUS_PR1_RGMII0_TXC_I", "Output clock"},
+        [733] = {63, 0, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_5_CLK", "Input clock"},
+        [734] = {63, 1, "DEV_PRU_ICSSG1_BUS_WIZ1_TX_SLV_CLK", "Input clock"},
+        [735] = {63, 2, "DEV_PRU_ICSSG1_BUS_WIZ0_RX_SLV_CLK", "Input clock"},
+        [736] = {63, 3, "DEV_PRU_ICSSG1_BUS_VCLK_CLK", "Input clock"},
+        [737] = {63, 4, "DEV_PRU_ICSSG1_BUS_UCLK_CLK", "Input clock"},
+        [738] = {63, 5, "DEV_PRU_ICSSG1_BUS_WIZ0_TX_SLV_CLK", "Input clock"},
+        [739] = {63, 6, "DEV_PRU_ICSSG1_BUS_WIZ1_RX_SLV_CLK", "Input clock"},
+        [740] = {63, 7, "DEV_PRU_ICSSG1_BUS_PR1_RGMII1_RXC_I", "Input clock"},
+        [741] = {63, 8, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_250_CLK", "Input clock"},
+        [742] = {63, 9, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_50_CLK", "Input clock"},
+        [743] = {63, 10, "DEV_PRU_ICSSG1_BUS_IEP_CLK", "Input muxed clock"},
+        [744] = {63, 11, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+        [745] = {63, 12, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+        [746] = {63, 13, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+        [747] = {63, 14, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+        [748] = {63, 15, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+        [749] = {63, 16, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+        [750] = {63, 17, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+        [751] = {63, 18, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+        [752] = {63, 19, "DEV_PRU_ICSSG1_BUS_CORE_CLK", "Input muxed clock"},
+        [753] = {63, 20, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"},
+        [754] = {63, 21, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"},
+        [755] = {63, 22, "DEV_PRU_ICSSG1_BUS_PR1_RGMII0_RXC_I", "Input clock"},
+        [756] = {63, 23, "DEV_PRU_ICSSG1_BUS_PR1_RGMII1_TXC_I", "Output clock"},
+        [757] = {63, 24, "DEV_PRU_ICSSG1_BUS_PR1_RGMII0_TXC_I", "Output clock"},
+        [758] = {64, 0, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_5_CLK", "Input clock"},
+        [759] = {64, 1, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_SLV_CLK", "Input clock"},
+        [760] = {64, 2, "DEV_PRU_ICSSG2_BUS_WIZ0_RX_SLV_CLK", "Input clock"},
+        [761] = {64, 3, "DEV_PRU_ICSSG2_BUS_VCLK_CLK", "Input clock"},
+        [762] = {64, 4, "DEV_PRU_ICSSG2_BUS_UCLK_CLK", "Input clock"},
+        [763] = {64, 5, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_SLV_CLK", "Input clock"},
+        [764] = {64, 6, "DEV_PRU_ICSSG2_BUS_WIZ1_RX_SLV_CLK", "Input clock"},
+        [765] = {64, 7, "DEV_PRU_ICSSG2_BUS_PR1_RGMII1_RXC_I", "Input clock"},
+        [766] = {64, 8, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_250_CLK", "Input clock"},
+        [767] = {64, 9, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_50_CLK", "Input clock"},
+        [768] = {64, 10, "DEV_PRU_ICSSG2_BUS_IEP_CLK", "Input muxed clock"},
+        [769] = {64, 11, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+        [770] = {64, 12, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+        [771] = {64, 13, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+        [772] = {64, 14, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+        [773] = {64, 15, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+        [774] = {64, 16, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+        [775] = {64, 17, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+        [776] = {64, 18, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+        [777] = {64, 19, "DEV_PRU_ICSSG2_BUS_CORE_CLK", "Input muxed clock"},
+        [778] = {64, 20, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"},
+        [779] = {64, 21, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"},
+        [780] = {64, 22, "DEV_PRU_ICSSG2_BUS_PR1_RGMII0_RXC_I", "Input clock"},
+        [781] = {64, 23, "DEV_PRU_ICSSG2_BUS_PR1_RGMII1_TXC_I", "Output clock"},
+        [782] = {64, 24, "DEV_PRU_ICSSG2_BUS_PR1_RGMII0_TXC_I", "Output clock"},
+        [783] = {64, 25, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_MST_CLK", "Output clock"},
+        [784] = {64, 26, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_MST_CLK", "Output clock"},
+        [785] = {70, 0, "DEV_PSC0_BUS_CLK", "Input clock"},
+        [786] = {70, 1, "DEV_PSC0_BUS_SLOW_CLK", "Input clock"},
+        [787] = {128, 0, "DEV_PSRAMECC0_BUS_CLK_CLK", "Input clock"},
+        [788] = {130, 0, "DEV_RTI0_BUS_RTI_CLK", "Input muxed clock"},
+        [789] = {130, 1, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+        [790] = {130, 2, "DEV_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+        [791] = {130, 3, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+        [792] = {130, 4, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+        [793] = {130, 5, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+        [794] = {130, 6, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+        [795] = {130, 7, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+        [796] = {130, 8, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP2", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+        [797] = {130, 9, "DEV_RTI0_BUS_VBUSP_CLK", "Input clock"},
+        [798] = {131, 0, "DEV_RTI1_BUS_RTI_CLK", "Input muxed clock"},
+        [799] = {131, 1, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+        [800] = {131, 2, "DEV_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+        [801] = {131, 3, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+        [802] = {131, 4, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+        [803] = {131, 5, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+        [804] = {131, 6, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+        [805] = {131, 7, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+        [806] = {131, 8, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP2", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+        [807] = {131, 9, "DEV_RTI1_BUS_VBUSP_CLK", "Input clock"},
+        [808] = {132, 0, "DEV_RTI2_BUS_RTI_CLK", "Input muxed clock"},
+        [809] = {132, 1, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+        [810] = {132, 2, "DEV_RTI2_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+        [811] = {132, 3, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+        [812] = {132, 4, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+        [813] = {132, 5, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+        [814] = {132, 6, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+        [815] = {132, 7, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+        [816] = {132, 8, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP2", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+        [817] = {132, 9, "DEV_RTI2_BUS_VBUSP_CLK", "Input clock"},
+        [818] = {133, 0, "DEV_RTI3_BUS_RTI_CLK", "Input muxed clock"},
+        [819] = {133, 1, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+        [820] = {133, 2, "DEV_RTI3_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+        [821] = {133, 3, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+        [822] = {133, 4, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+        [823] = {133, 5, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+        [824] = {133, 6, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+        [825] = {133, 7, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+        [826] = {133, 8, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP2", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+        [827] = {133, 9, "DEV_RTI3_BUS_VBUSP_CLK", "Input clock"},
+        [828] = {136, 0, "DEV_SA2_UL0_BUS_PKA_IN_CLK", "Input clock"},
+        [829] = {136, 1, "DEV_SA2_UL0_BUS_X1_CLK", "Input clock"},
+        [830] = {136, 2, "DEV_SA2_UL0_BUS_X2_CLK", "Input clock"},
+        [831] = {153, 0, "DEV_SERDES0_BUS_IP3_LN0_TXRCLK", "Input clock"},
+        [832] = {153, 1, "DEV_SERDES0_BUS_REFCLKPP", "Input clock"},
+        [833] = {153, 2, "DEV_SERDES0_BUS_CLK", "Input clock"},
+        [834] = {153, 3, "DEV_SERDES0_BUS_IP2_LN0_TXRCLK", "Input clock"},
+        [835] = {153, 4, "DEV_SERDES0_BUS_LI_REFCLK", "Input muxed clock"},
+        [836] = {153, 5, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
+        [837] = {153, 6, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
+        [838] = {153, 7, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
+        [839] = {153, 8, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
+        [840] = {153, 9, "DEV_SERDES0_BUS_REFCLKPN", "Input clock"},
+        [841] = {153, 10, "DEV_SERDES0_BUS_LN0_TXCLK", "Output clock"},
+        [842] = {153, 11, "DEV_SERDES0_BUS_LN0_RXCLK", "Output clock"},
+        [843] = {154, 0, "DEV_SERDES1_BUS_IP3_LN0_TXRCLK", "Input clock"},
+        [844] = {154, 1, "DEV_SERDES1_BUS_REFCLKPP", "Input clock"},
+        [845] = {154, 2, "DEV_SERDES1_BUS_CLK", "Input clock"},
+        [846] = {154, 3, "DEV_SERDES1_BUS_IP1_LN0_TXRCLK", "Input clock"},
+        [847] = {154, 4, "DEV_SERDES1_BUS_IP2_LN0_TXRCLK", "Input clock"},
+        [848] = {154, 5, "DEV_SERDES1_BUS_RI_REFCLK", "Input muxed clock"},
+        [849] = {154, 6, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
+        [850] = {154, 7, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
+        [851] = {154, 8, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
+        [852] = {154, 9, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
+        [853] = {154, 10, "DEV_SERDES1_BUS_REFCLKPN", "Input clock"},
+        [854] = {154, 11, "DEV_SERDES1_BUS_LN0_TXCLK", "Output clock"},
+        [855] = {154, 12, "DEV_SERDES1_BUS_LN0_RXCLK", "Output clock"},
+        [856] = {8, 0, "DEV_STM0_BUS_CORE_CLK", "Input clock"},
+        [857] = {8, 1, "DEV_STM0_BUS_ATB_CLK", "Input clock"},
+        [858] = {8, 2, "DEV_STM0_BUS_VBUSP_CLK", "Input clock"},
+        [859] = {23, 0, "DEV_TIMER0_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+        [860] = {23, 1, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [861] = {23, 2, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [862] = {23, 3, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [863] = {23, 4, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [864] = {23, 5, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [865] = {23, 6, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [866] = {23, 7, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [867] = {23, 8, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [868] = {23, 9, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [869] = {23, 10, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [870] = {23, 11, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [871] = {23, 12, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [872] = {23, 13, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [873] = {23, 14, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [874] = {23, 15, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [875] = {23, 16, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+        [876] = {23, 17, "DEV_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"},
+        [877] = {24, 0, "DEV_TIMER1_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+        [878] = {24, 1, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [879] = {24, 2, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [880] = {24, 3, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [881] = {24, 4, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [882] = {24, 5, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [883] = {24, 6, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [884] = {24, 7, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [885] = {24, 8, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [886] = {24, 9, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [887] = {24, 10, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [888] = {24, 11, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [889] = {24, 12, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [890] = {24, 13, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [891] = {24, 14, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [892] = {24, 15, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [893] = {24, 16, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+        [894] = {24, 17, "DEV_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"},
+        [895] = {25, 0, "DEV_TIMER10_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+        [896] = {25, 1, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+        [897] = {25, 2, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+        [898] = {25, 3, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+        [899] = {25, 4, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+        [900] = {25, 5, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+        [901] = {25, 6, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+        [902] = {25, 7, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+        [903] = {25, 8, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+        [904] = {25, 9, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+        [905] = {25, 10, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+        [906] = {25, 11, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+        [907] = {25, 12, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+        [908] = {25, 13, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+        [909] = {25, 14, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+        [910] = {25, 15, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+        [911] = {25, 16, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+        [912] = {25, 17, "DEV_TIMER10_BUS_TIMER_HCLK_CLK", "Input clock"},
+        [913] = {26, 0, "DEV_TIMER11_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+        [914] = {26, 1, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+        [915] = {26, 2, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+        [916] = {26, 3, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+        [917] = {26, 4, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+        [918] = {26, 5, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+        [919] = {26, 6, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+        [920] = {26, 7, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+        [921] = {26, 8, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+        [922] = {26, 9, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+        [923] = {26, 10, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+        [924] = {26, 11, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+        [925] = {26, 12, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+        [926] = {26, 13, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+        [927] = {26, 14, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+        [928] = {26, 15, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+        [929] = {26, 16, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+        [930] = {26, 17, "DEV_TIMER11_BUS_TIMER_HCLK_CLK", "Input clock"},
+        [931] = {27, 0, "DEV_TIMER2_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+        [932] = {27, 1, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [933] = {27, 2, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [934] = {27, 3, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [935] = {27, 4, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [936] = {27, 5, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [937] = {27, 6, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [938] = {27, 7, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [939] = {27, 8, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [940] = {27, 9, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [941] = {27, 10, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [942] = {27, 11, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [943] = {27, 12, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [944] = {27, 13, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [945] = {27, 14, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [946] = {27, 15, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [947] = {27, 16, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+        [948] = {27, 17, "DEV_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"},
+        [949] = {28, 0, "DEV_TIMER3_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+        [950] = {28, 1, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [951] = {28, 2, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [952] = {28, 3, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [953] = {28, 4, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [954] = {28, 5, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [955] = {28, 6, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [956] = {28, 7, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [957] = {28, 8, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [958] = {28, 9, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [959] = {28, 10, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [960] = {28, 11, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [961] = {28, 12, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [962] = {28, 13, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [963] = {28, 14, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [964] = {28, 15, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [965] = {28, 16, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+        [966] = {28, 17, "DEV_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"},
+        [967] = {29, 0, "DEV_TIMER4_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+        [968] = {29, 1, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+        [969] = {29, 2, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+        [970] = {29, 3, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+        [971] = {29, 4, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+        [972] = {29, 5, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+        [973] = {29, 6, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+        [974] = {29, 7, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+        [975] = {29, 8, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+        [976] = {29, 9, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+        [977] = {29, 10, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+        [978] = {29, 11, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+        [979] = {29, 12, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+        [980] = {29, 13, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+        [981] = {29, 14, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+        [982] = {29, 15, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+        [983] = {29, 16, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+        [984] = {29, 17, "DEV_TIMER4_BUS_TIMER_HCLK_CLK", "Input clock"},
+        [985] = {30, 0, "DEV_TIMER5_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+        [986] = {30, 1, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+        [987] = {30, 2, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+        [988] = {30, 3, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+        [989] = {30, 4, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+        [990] = {30, 5, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+        [991] = {30, 6, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+        [992] = {30, 7, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+        [993] = {30, 8, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+        [994] = {30, 9, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+        [995] = {30, 10, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+        [996] = {30, 11, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+        [997] = {30, 12, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+        [998] = {30, 13, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+        [999] = {30, 14, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+        [1000] = {30, 15, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+        [1001] = {30, 16, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+        [1002] = {30, 17, "DEV_TIMER5_BUS_TIMER_HCLK_CLK", "Input clock"},
+        [1003] = {31, 0, "DEV_TIMER6_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+        [1004] = {31, 1, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+        [1005] = {31, 2, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+        [1006] = {31, 3, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+        [1007] = {31, 4, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+        [1008] = {31, 5, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+        [1009] = {31, 6, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+        [1010] = {31, 7, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+        [1011] = {31, 8, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+        [1012] = {31, 9, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+        [1013] = {31, 10, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+        [1014] = {31, 11, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+        [1015] = {31, 12, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+        [1016] = {31, 13, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+        [1017] = {31, 14, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+        [1018] = {31, 15, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+        [1019] = {31, 16, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+        [1020] = {31, 17, "DEV_TIMER6_BUS_TIMER_HCLK_CLK", "Input clock"},
+        [1021] = {32, 0, "DEV_TIMER7_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+        [1022] = {32, 1, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+        [1023] = {32, 2, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+        [1024] = {32, 3, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+        [1025] = {32, 4, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+        [1026] = {32, 5, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+        [1027] = {32, 6, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+        [1028] = {32, 7, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+        [1029] = {32, 8, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+        [1030] = {32, 9, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+        [1031] = {32, 10, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+        [1032] = {32, 11, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+        [1033] = {32, 12, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+        [1034] = {32, 13, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+        [1035] = {32, 14, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+        [1036] = {32, 15, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+        [1037] = {32, 16, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+        [1038] = {32, 17, "DEV_TIMER7_BUS_TIMER_HCLK_CLK", "Input clock"},
+        [1039] = {33, 0, "DEV_TIMER8_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+        [1040] = {33, 1, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+        [1041] = {33, 2, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+        [1042] = {33, 3, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+        [1043] = {33, 4, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+        [1044] = {33, 5, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+        [1045] = {33, 6, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+        [1046] = {33, 7, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+        [1047] = {33, 8, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+        [1048] = {33, 9, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+        [1049] = {33, 10, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+        [1050] = {33, 11, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+        [1051] = {33, 12, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+        [1052] = {33, 13, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+        [1053] = {33, 14, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+        [1054] = {33, 15, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+        [1055] = {33, 16, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+        [1056] = {33, 17, "DEV_TIMER8_BUS_TIMER_HCLK_CLK", "Input clock"},
+        [1057] = {34, 0, "DEV_TIMER9_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+        [1058] = {34, 1, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+        [1059] = {34, 2, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+        [1060] = {34, 3, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+        [1061] = {34, 4, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+        [1062] = {34, 5, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+        [1063] = {34, 6, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+        [1064] = {34, 7, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+        [1065] = {34, 8, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+        [1066] = {34, 9, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+        [1067] = {34, 10, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+        [1068] = {34, 11, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+        [1069] = {34, 12, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+        [1070] = {34, 13, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+        [1071] = {34, 14, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+        [1072] = {34, 15, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+        [1073] = {34, 16, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+        [1074] = {34, 17, "DEV_TIMER9_BUS_TIMER_HCLK_CLK", "Input clock"},
+        [1075] = {145, 0, "DEV_TIMESYNC_INTRTR0_BUS_INTR_CLK", "Input clock"},
+        [1076] = {146, 0, "DEV_UART0_BUS_FCLK_CLK", "Input clock"},
+        [1077] = {146, 1, "DEV_UART0_BUS_VBUSP_CLK", "Input clock"},
+        [1078] = {147, 0, "DEV_UART1_BUS_FCLK_CLK", "Input clock"},
+        [1079] = {147, 1, "DEV_UART1_BUS_VBUSP_CLK", "Input clock"},
+        [1080] = {148, 0, "DEV_UART2_BUS_FCLK_CLK", "Input clock"},
+        [1081] = {148, 1, "DEV_UART2_BUS_VBUSP_CLK", "Input clock"},
+        [1082] = {151, 0, "DEV_USB3SS0_BUS_SUSP_CLK", "Input clock"},
+        [1083] = {151, 1, "DEV_USB3SS0_BUS_PHY2_REFCLK960M_CLK", "Input clock"},
+        [1084] = {151, 2, "DEV_USB3SS0_BUS_REF_CLK", "Input muxed clock"},
+        [1085] = {151, 3, "DEV_USB3SS0_BUS_REF_CLK_PARENT_CLOCKMUX_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"},
+        [1086] = {151, 4, "DEV_USB3SS0_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"},
+        [1087] = {151, 5, "DEV_USB3SS0_BUS_HSIC_CLK_CLK", "Input clock"},
+        [1088] = {151, 6, "DEV_USB3SS0_BUS_BUS_CLK", "Input clock"},
+        [1089] = {151, 7, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK", "Input muxed clock"},
+        [1090] = {151, 8, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"},
+        [1091] = {151, 9, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_CLOCKMUX_USB0_PIPE3_CLK_SEL_DIV_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"},
+        [1092] = {151, 10, "DEV_USB3SS0_BUS_UTMI_CLK_CLK", "Input clock"},
+        [1093] = {152, 0, "DEV_USB3SS1_BUS_SUSP_CLK", "Input clock"},
+        [1094] = {152, 1, "DEV_USB3SS1_BUS_PHY2_REFCLK960M_CLK", "Input clock"},
+        [1095] = {152, 2, "DEV_USB3SS1_BUS_REF_CLK", "Input muxed clock"},
+        [1096] = {152, 3, "DEV_USB3SS1_BUS_REF_CLK_PARENT_CLOCKMUX_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"},
+        [1097] = {152, 4, "DEV_USB3SS1_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"},
+        [1098] = {152, 5, "DEV_USB3SS1_BUS_HSIC_CLK_CLK", "Input clock"},
+        [1099] = {152, 6, "DEV_USB3SS1_BUS_BUS_CLK", "Input clock"},
+        [1100] = {152, 7, "DEV_USB3SS1_BUS_PIPE3_TXB_CLK", "Input clock"},
+        [1101] = {152, 8, "DEV_USB3SS1_BUS_UTMI_CLK_CLK", "Input clock"},
+        [1102] = {94, 0, "DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_2_CLK", "Input clock"},
+        [1103] = {94, 1, "DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_4_CLK", "Input clock"},
+        [1104] = {96, 0, "DEV_WKUP_CBASS_FW0_BUS_WKUP_MCU_PLL_OUT_2_CLK", "Input clock"},
+        [1105] = {155, 0, "DEV_WKUP_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"},
+        [1106] = {22, 0, "DEV_WKUP_DMSC0_BUS_FUNC_32K_RT_CLK", "Input clock"},
+        [1107] = {22, 1, "DEV_WKUP_DMSC0_BUS_FUNC_MOSC_CLK", "Input clock"},
+        [1108] = {22, 2, "DEV_WKUP_DMSC0_BUS_VBUS_CLK", "Input clock"},
+        [1109] = {22, 3, "DEV_WKUP_DMSC0_BUS_FUNC_32K_RC_CLK", "Input clock"},
+        [1110] = {22, 4, "DEV_WKUP_DMSC0_BUS_SEC_EFC_FCLK", "Input clock"},
+        [1111] = {22, 5, "DEV_WKUP_DMSC0_BUS_DAP_CLK", "Input clock"},
+        [1112] = {22, 6, "DEV_WKUP_DMSC0_BUS_EXT_CLK", "Input clock"},
+        [1113] = {95, 0, "DEV_WKUP_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"},
+        [1114] = {54, 0, "DEV_WKUP_ESM0_BUS_CLK", "Input clock"},
+        [1115] = {59, 0, "DEV_WKUP_GPIO0_BUS_MMR_CLK", "Input muxed clock"},
+        [1116] = {59, 1, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
+        [1117] = {59, 2, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4_DUP0", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
+        [1118] = {59, 3, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
+        [1119] = {59, 4, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
+        [1120] = {156, 0, "DEV_WKUP_GPIOMUX_INTRTR0_BUS_INTR_CLK", "Input clock"},
+        [1121] = {115, 0, "DEV_WKUP_I2C0_BUS_CLK", "Input clock"},
+        [1122] = {115, 1, "DEV_WKUP_I2C0_BUS_PISYS_CLK", "Input muxed clock"},
+        [1123] = {115, 2, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"},
+        [1124] = {115, 3, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"},
+        [1125] = {115, 4, "DEV_WKUP_I2C0_BUS_PISCL", "Output clock"},
+        [1126] = {77, 0, "DEV_WKUP_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK", "Input clock"},
+        [1127] = {77, 1, "DEV_WKUP_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"},
+        [1128] = {77, 2, "DEV_WKUP_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input clock"},
+        [1129] = {79, 0, "DEV_WKUP_PSC0_BUS_CLK", "Input clock"},
+        [1130] = {79, 1, "DEV_WKUP_PSC0_BUS_SLOW_CLK", "Input clock"},
+        [1131] = {150, 0, "DEV_WKUP_UART0_BUS_FCLK_CLK", "Input muxed clock"},
+        [1132] = {150, 1, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_CLOCKMUX_WKUPUSART_CLK_SEL_BUS_OUT0", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"},
+        [1133] = {150, 2, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"},
+        [1134] = {150, 3, "DEV_WKUP_UART0_BUS_VBUSP_CLK", "Input clock"},
+        [1135] = {80, 0, "DEV_WKUP_VTM0_BUS_FIX_REF_CLK", "Input clock"},
+        [1136] = {80, 1, "DEV_WKUP_VTM0_BUS_VBUSP_CLK", "Input clock"},
+};