From: Lokesh Vutla Date: Wed, 11 Nov 2020 15:34:15 +0000 (+0530) Subject: soc: am64x: Add host id information X-Git-Tag: v0.2~7 X-Git-Url: https://git.ti.com/gitweb?p=k3conf%2Fk3conf.git;a=commitdiff_plain;h=17d2dee94666b0cad03f44f33dd5224fbe7edd8a soc: am64x: Add host id information Add TISCI Host Id information for AM64x devices. Data based on sysfw v2020.08b. Also assign this data to sci_info based on SoC detection. Signed-off-by: Lokesh Vutla --- diff --git a/Makefile b/Makefile index 52ffa9f..88cf904 100644 --- a/Makefile +++ b/Makefile @@ -102,13 +102,17 @@ J721ESOURCES =\ soc/j7200/j7200_rm_info.c +AM64XSOURCES =\ + soc/am64x/am64x_host_info.c \ + COMMONOBJECTS= $(COMMONSOURCES:.c=.o) AM65XOBJECTS= $(AM65XSOURCES:.c=.o) J721EOBJECTS= $(J721ESOURCES:.c=.o) +AM64XOBJECTS= $(AM64XSOURCES:.c=.o) -ALLSOURCES= $(COMMONSOURCES) $(AM65XSOURCES) $(J721ESOURCES) +ALLSOURCES= $(COMMONSOURCES) $(AM65XSOURCES) $(J721ESOURCES) $(AM64XSOURCES) -ALLOBJECTS= $(COMMONOBJECTS) $(AM65XOBJECTS) $(J721EOBJECTS) +ALLOBJECTS= $(COMMONOBJECTS) $(AM65XOBJECTS) $(J721EOBJECTS) $(AM64XOBJECTS) # # Pretty print diff --git a/common/socinfo.c b/common/socinfo.c index ce0ae52..4c72ec1 100644 --- a/common/socinfo.c +++ b/common/socinfo.c @@ -61,6 +61,7 @@ #include #include #include +#include /* Assuming these addresses and definitions stay common across K3 devices */ #define CTRLMMR_WKUP_JTAG_DEVICE_ID 0x43000018 @@ -184,6 +185,11 @@ static void j7200_init(void) static void am64x_init(void) { + struct ti_sci_info *sci_info = &soc_info.sci_info; + + sci_info->host_info = am64x_host_info; + sci_info->num_hosts = AM64X_MAX_HOST_IDS; + soc_info.host_id = 13; soc_info.sec_proxy = &k3_lite_sec_proxy_base; } diff --git a/soc/am64x/am64x_host_info.c b/soc/am64x/am64x_host_info.c new file mode 100644 index 0000000..01027a6 --- /dev/null +++ b/soc/am64x/am64x_host_info.c @@ -0,0 +1,54 @@ +/* + * AM64X Hosts Info + * + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +struct ti_sci_host_info am64x_host_info[] = { + [0] = {0, "DMSC", "Secure", "Device Management and Security Control"}, + [1] = {35, "MAIN_0_R5_0", "Secure", "Cortex R5_0 context 0 on Main island(BOOT)"}, + [2] = {36, "MAIN_0_R5_1", "Non Secure", "Cortex R5_0 context 1 on Main island"}, + [3] = {37, "MAIN_0_R5_2", "Secure", "Cortex R5_0 context 2 on Main island"}, + [4] = {38, "MAIN_0_R5_3", "Non Secure", "Cortex R5_0 context 3 on Main island"}, + [5] = {10, "A53_0", "Secure", "Cortex a53 context 0 on Main islana - ATF"}, + [6] = {11, "A53_1", "Non Secure", "Cortex A53 context 1 on Main island - EL2/Hyp"}, + [7] = {12, "A53_2", "Non Secure", "Cortex A53 context 2 on Main island - VM/OS1"}, + [8] = {13, "A53_3", "Non Secure", "Cortex A53 context 3 on Main island - VM2/OS2"}, + [9] = {30, "M4_0", "Non Secure", "M4"}, + [10] = {40, "MAIN_1_R5_0", "Secure", "Cortex R5_1 context 0 on Main island"}, + [11] = {41, "MAIN_1_R5_1", "Non Secure", "Cortex R5_1 context 1 on Main island"}, + [12] = {42, "MAIN_1_R5_2", "Secure", "Cortex R5_1 context 2 on Main island"}, + [13] = {43, "MAIN_1_R5_3", "Non Secure", "Cortex R5_1 context 3 on Main island"}, + [14] = {50, "ICSSG_0", "Non Secure", "ICSSG context 0 on Main island"}, +}; diff --git a/soc/am64x/am64x_host_info.h b/soc/am64x/am64x_host_info.h new file mode 100644 index 0000000..c459a03 --- /dev/null +++ b/soc/am64x/am64x_host_info.h @@ -0,0 +1,58 @@ +/* + * AM64X Host Info + * + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __AM64X_HOST_INFO_H +#define __AM64X_HOST_INFO_H + +#define AM64X_HOST_ID_DMSC 0 +#define AM64X_HOST_ID_MAIN_0_R5_0 35 +#define AM64X_HOST_ID_MAIN_0_R5_1 36 +#define AM64X_HOST_ID_MAIN_0_R5_2 37 +#define AM64X_HOST_ID_MAIN_0_R5_3 38 +#define AM64X_HOST_ID_A53_0 10 +#define AM64X_HOST_ID_A53_1 11 +#define AM64X_HOST_ID_A53_2 12 +#define AM64X_HOST_ID_A53_3 13 +#define AM64X_HOST_ID_M4_0 30 +#define AM64X_HOST_ID_MAIN_1_R5_0 40 +#define AM64X_HOST_ID_MAIN_1_R5_1 41 +#define AM64X_HOST_ID_MAIN_1_R5_2 42 +#define AM64X_HOST_ID_MAIN_1_R5_3 43 +#define AM64X_HOST_ID_ICSSG_0 50 + +#define AM64X_MAX_HOST_IDS 15 + +extern struct ti_sci_host_info am64x_host_info[]; + +#endif /* __AM64X_HOST_INFO_H */ \ No newline at end of file