From: Lokesh Vutla Date: Fri, 10 Apr 2020 10:08:56 +0000 (+0530) Subject: soc: am65x: Update to 2019.12 sysfw documentaion X-Git-Tag: v0.2~41 X-Git-Url: https://git.ti.com/gitweb?p=k3conf%2Fk3conf.git;a=commitdiff_plain;h=1cb1a8dbab5a051b2978b2d97df9b8b4ee33ac7c soc: am65x: Update to 2019.12 sysfw documentaion Update SoC information using sysfw 2019.12 Docs. Signed-off-by: Lokesh Vutla --- diff --git a/soc/am65x/am65x_clocks_info.c b/soc/am65x/am65x_clocks_info.c index c332c56..cf45a9c 100644 --- a/soc/am65x/am65x_clocks_info.c +++ b/soc/am65x/am65x_clocks_info.c @@ -1,7 +1,7 @@ /* - * SoC Clocks Info + * AM65X Clocks Info * - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -36,1141 +36,965 @@ #include struct ti_sci_clocks_info am65x_clocks_info[] = { - [0] = {157, 0, "DEV_BOARD0_BUS_SCL3", "Input clock"}, - [1] = {157, 1, "DEV_BOARD0_BUS_SCL2", "Input clock"}, - [2] = {157, 2, "DEV_BOARD0_BUS_SCL1", "Input clock"}, - [3] = {157, 3, "DEV_BOARD0_BUS_SCL0", "Input clock"}, - [4] = {157, 4, "DEV_BOARD0_BUS_PRG2_RGMII2_TCLK", "Input clock"}, - [5] = {157, 5, "DEV_BOARD0_BUS_MCU_OSPI1CLK", "Input clock"}, - [6] = {157, 6, "DEV_BOARD0_BUS_PRG1_RGMII1_TCLK", "Input clock"}, - [7] = {157, 7, "DEV_BOARD0_BUS_REFCLK1P", "Input muxed clock"}, - [8] = {157, 8, "DEV_BOARD0_BUS_REFCLK1P_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P"}, - [9] = {157, 9, "DEV_BOARD0_BUS_REFCLK1P_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P"}, - [10] = {157, 10, "DEV_BOARD0_BUS_REFCLK1P_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P"}, - [11] = {157, 11, "DEV_BOARD0_BUS_REFCLK1P_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P"}, - [12] = {157, 12, "DEV_BOARD0_BUS_MCU_OSPI1LBCLKO", "Input clock"}, - [13] = {157, 13, "DEV_BOARD0_BUS_MCU_OBSCLK", "Input clock"}, - [14] = {157, 14, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"}, - [15] = {157, 15, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"}, - [16] = {157, 16, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"}, - [17] = {157, 17, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"}, - [18] = {157, 18, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"}, - [19] = {157, 19, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"}, - [20] = {157, 20, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"}, - [21] = {157, 21, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"}, - [22] = {157, 22, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"}, - [23] = {157, 23, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"}, - [24] = {157, 24, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"}, - [25] = {157, 25, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"}, - [26] = {157, 26, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"}, - [27] = {157, 27, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"}, - [28] = {157, 28, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"}, - [29] = {157, 29, "DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK"}, - [30] = {157, 30, "DEV_BOARD0_BUS_PRG2_RGMII1_TCLK", "Input clock"}, - [31] = {157, 31, "DEV_BOARD0_BUS_REFCLK1M", "Input muxed clock"}, - [32] = {157, 32, "DEV_BOARD0_BUS_REFCLK1M_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M"}, - [33] = {157, 33, "DEV_BOARD0_BUS_REFCLK1M_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M"}, - [34] = {157, 34, "DEV_BOARD0_BUS_REFCLK1M_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M"}, - [35] = {157, 35, "DEV_BOARD0_BUS_REFCLK1M_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M"}, - [36] = {157, 36, "DEV_BOARD0_BUS_OBSCLK", "Input clock"}, - [37] = {157, 37, "DEV_BOARD0_BUS_OBSCLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"}, - [38] = {157, 38, "DEV_BOARD0_BUS_OBSCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"}, - [39] = {157, 39, "DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"}, - [40] = {157, 40, "DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"}, - [41] = {157, 41, "DEV_BOARD0_BUS_OBSCLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"}, - [42] = {157, 42, "DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"}, - [43] = {157, 43, "DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLLJM_WRAP_MAIN_4_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"}, - [44] = {157, 44, "DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLM_WRAP_MAIN_6_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"}, - [45] = {157, 45, "DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"}, - [46] = {157, 46, "DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"}, - [47] = {157, 47, "DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"}, - [48] = {157, 48, "DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLM_WRAP_MAIN_7_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"}, - [49] = {157, 49, "DEV_BOARD0_BUS_OBSCLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"}, - [50] = {157, 50, "DEV_BOARD0_BUS_OBSCLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"}, - [51] = {157, 51, "DEV_BOARD0_BUS_OBSCLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"}, - [52] = {157, 52, "DEV_BOARD0_BUS_OBSCLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK"}, - [53] = {157, 53, "DEV_BOARD0_BUS_PRG0_RGMII1_TCLK", "Input clock"}, - [54] = {157, 54, "DEV_BOARD0_BUS_MCU_OSPI0CLK", "Input clock"}, - [55] = {157, 55, "DEV_BOARD0_BUS_DSS0PCLK", "Input clock"}, - [56] = {157, 56, "DEV_BOARD0_BUS_PRG0_RGMII2_TCLK", "Input clock"}, - [57] = {157, 57, "DEV_BOARD0_BUS_WKUP_SCL0", "Input clock"}, - [58] = {157, 58, "DEV_BOARD0_BUS_REFCLK0P", "Input muxed clock"}, - [59] = {157, 59, "DEV_BOARD0_BUS_REFCLK0P_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P"}, - [60] = {157, 60, "DEV_BOARD0_BUS_REFCLK0P_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P"}, - [61] = {157, 61, "DEV_BOARD0_BUS_REFCLK0P_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P"}, - [62] = {157, 62, "DEV_BOARD0_BUS_REFCLK0P_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P"}, - [63] = {157, 63, "DEV_BOARD0_BUS_REFCLK0M", "Input muxed clock"}, - [64] = {157, 64, "DEV_BOARD0_BUS_REFCLK0M_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M"}, - [65] = {157, 65, "DEV_BOARD0_BUS_REFCLK0M_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M"}, - [66] = {157, 66, "DEV_BOARD0_BUS_REFCLK0M_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M"}, - [67] = {157, 67, "DEV_BOARD0_BUS_REFCLK0M_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M"}, - [68] = {157, 68, "DEV_BOARD0_BUS_MCU_OSPI0LBCLKO", "Input clock"}, - [69] = {157, 69, "DEV_BOARD0_BUS_MCU_CLKOUT", "Input muxed clock"}, - [70] = {157, 70, "DEV_BOARD0_BUS_MCU_CLKOUT_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT"}, - [71] = {157, 71, "DEV_BOARD0_BUS_MCU_CLKOUT_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK10", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT"}, - [72] = {157, 72, "DEV_BOARD0_BUS_MCU_SCL0", "Input clock"}, - [73] = {157, 73, "DEV_BOARD0_BUS_SYSCLKOUT", "Input clock"}, - [74] = {157, 74, "DEV_BOARD0_BUS_MCU_SYSCLKOUT", "Input clock"}, - [75] = {157, 75, "DEV_BOARD0_BUS_PRG1_RGMII1_RCLK", "Output clock"}, - [76] = {157, 76, "DEV_BOARD0_BUS_PRG1_RGMII2_RCLK", "Output clock"}, - [77] = {157, 77, "DEV_BOARD0_BUS_GPMCCLK", "Output clock"}, - [78] = {157, 78, "DEV_BOARD0_BUS_MCASP2AHCLKX", "Output clock"}, - [79] = {157, 79, "DEV_BOARD0_BUS_MCASP2AHCLKR", "Output clock"}, - [80] = {157, 80, "DEV_BOARD0_BUS_PRG2_RGMII2_RCLK", "Output clock"}, - [81] = {157, 81, "DEV_BOARD0_BUS_CPTS_RFT_CLK", "Output clock"}, - [82] = {157, 82, "DEV_BOARD0_BUS_MCASP0ACLKR", "Output clock"}, - [83] = {157, 83, "DEV_BOARD0_BUS_MCASP0ACLKX", "Output clock"}, - [84] = {157, 84, "DEV_BOARD0_BUS_EXT_REFCLK1", "Output clock"}, - [85] = {157, 85, "DEV_BOARD0_BUS_PRG0_RGMII2_RCLK", "Output clock"}, - [86] = {157, 86, "DEV_BOARD0_BUS_MCU_OSPI0DQS", "Output clock"}, - [87] = {157, 87, "DEV_BOARD0_BUS_USB0REFCLKP", "Output clock"}, - [88] = {157, 88, "DEV_BOARD0_BUS_DSS0EXTPCLKIN", "Output clock"}, - [89] = {157, 89, "DEV_BOARD0_BUS_SPI1CLK", "Output clock"}, - [90] = {157, 90, "DEV_BOARD0_BUS_MCASP2ACLKR", "Output clock"}, - [91] = {157, 91, "DEV_BOARD0_BUS_MCASP1ACLKX", "Output clock"}, - [92] = {157, 92, "DEV_BOARD0_BUS_MCASP1ACLKR", "Output clock"}, - [93] = {157, 93, "DEV_BOARD0_BUS_MCASP2ACLKX", "Output clock"}, - [94] = {157, 94, "DEV_BOARD0_BUS_MCU_RMII1_REFCLK", "Output clock"}, - [95] = {157, 95, "DEV_BOARD0_BUS_MCU_CPTS_RFT_CLK", "Output clock"}, - [96] = {157, 96, "DEV_BOARD0_BUS_MCU_RGMII1_TCLK", "Output clock"}, - [97] = {157, 97, "DEV_BOARD0_BUS_MCU_SPI0CLK", "Output clock"}, - [98] = {157, 98, "DEV_BOARD0_BUS_MCU_SPI1CLK", "Output clock"}, - [99] = {157, 99, "DEV_BOARD0_BUS_PRG0_RGMII1_RCLK", "Output clock"}, - [100] = {157, 100, "DEV_BOARD0_BUS_SPI2CLK", "Output clock"}, - [101] = {157, 101, "DEV_BOARD0_BUS_WKUP_TCK", "Output clock"}, - [102] = {157, 102, "DEV_BOARD0_BUS_SPI3CLK", "Output clock"}, - [103] = {157, 103, "DEV_BOARD0_BUS_USB0REFCLKM", "Output clock"}, - [104] = {157, 104, "DEV_BOARD0_BUS_MCU_RGMII1_RCLK", "Output clock"}, - [105] = {157, 105, "DEV_BOARD0_BUS_MCASP0AHCLKR", "Output clock"}, - [106] = {157, 106, "DEV_BOARD0_BUS_MCU_EXT_REFCLK0", "Output clock"}, - [107] = {157, 107, "DEV_BOARD0_BUS_MCASP0AHCLKX", "Output clock"}, - [108] = {157, 108, "DEV_BOARD0_BUS_CCDC0_PCLK", "Output clock"}, - [109] = {157, 109, "DEV_BOARD0_HFOSC1_CLK", "Output clock"}, - [110] = {157, 110, "DEV_BOARD0_BUS_MCU_OSPI1DQS", "Output clock"}, - [111] = {157, 111, "DEV_BOARD0_BUS_MCASP1AHCLKX", "Output clock"}, - [112] = {157, 112, "DEV_BOARD0_BUS_PCIE1REFCLKM", "Output clock"}, - [113] = {157, 113, "DEV_BOARD0_BUS_MCASP1AHCLKR", "Output clock"}, - [114] = {157, 114, "DEV_BOARD0_BUS_PCIE1REFCLKP", "Output clock"}, - [115] = {157, 115, "DEV_BOARD0_BUS_PRG2_RGMII1_RCLK", "Output clock"}, - [116] = {157, 116, "DEV_BOARD0_BUS_SPI0CLK", "Output clock"}, - [117] = {2, 0, "DEV_CAL0_BUS_CLK", "Input clock"}, - [118] = {2, 1, "DEV_CAL0_BUS_CP_C_CLK", "Input clock"}, - [119] = {82, 0, "DEV_CBASS0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"}, - [120] = {82, 1, "DEV_CBASS0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"}, - [121] = {83, 0, "DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"}, - [122] = {83, 1, "DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"}, - [123] = {84, 0, "DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"}, - [124] = {84, 1, "DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"}, - [125] = {85, 0, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK", "Input muxed clock"}, - [126] = {85, 1, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, - [127] = {85, 2, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, - [128] = {85, 3, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, - [129] = {85, 4, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, - [130] = {85, 5, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, - [131] = {85, 6, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, - [132] = {85, 7, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, - [133] = {85, 8, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, - [134] = {85, 9, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"}, - [135] = {85, 10, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"}, - [136] = {66, 0, "DEV_CCDEBUGSS0_BUS_ATB1_CLK", "Input clock"}, - [137] = {66, 1, "DEV_CCDEBUGSS0_BUS_ATB0_CLK", "Input clock"}, - [138] = {66, 2, "DEV_CCDEBUGSS0_BUS_SYS_CLK", "Input clock"}, - [139] = {66, 3, "DEV_CCDEBUGSS0_BUS_DBG_CLK", "Input clock"}, - [140] = {66, 4, "DEV_CCDEBUGSS0_BUS_CFG_CLK", "Input clock"}, - [141] = {3, 0, "DEV_CMPEVENT_INTRTR0_BUS_INTR_CLK", "Input clock"}, - [142] = {202, 0, "DEV_COMPUTE_CLUSTER_A53_0_BUS_ARM0_CLK", "Input clock"}, - [143] = {203, 0, "DEV_COMPUTE_CLUSTER_A53_1_BUS_ARM0_CLK", "Input clock"}, - [144] = {204, 0, "DEV_COMPUTE_CLUSTER_A53_2_BUS_ARM1_CLK", "Input clock"}, - [145] = {205, 0, "DEV_COMPUTE_CLUSTER_A53_3_BUS_ARM1_CLK", "Input clock"}, - [146] = {198, 0, "DEV_COMPUTE_CLUSTER_CPAC0_BUS_ARM0_CLK", "Input clock"}, - [147] = {200, 0, "DEV_COMPUTE_CLUSTER_CPAC1_BUS_ARM1_CLK", "Input clock"}, - [148] = {196, 0, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_DMSC_CLK", "Input clock"}, - [149] = {196, 1, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_DBG_CLK", "Input clock"}, - [150] = {196, 2, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_MSMC_CLK", "Input clock"}, - [151] = {196, 3, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_CFG_CLK", "Input clock"}, - [152] = {196, 4, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_GIC_CLK", "Input clock"}, - [153] = {6, 0, "DEV_CPT2_AGGR0_BUS_VCLK_CLK", "Input clock"}, - [154] = {213, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_VBUS_CLK", "Input clock"}, - [155] = {213, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_PROBE_CLK", "Input clock"}, - [156] = {214, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_VBUS_CLK", "Input clock"}, - [157] = {214, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_PROBE_CLK", "Input clock"}, - [158] = {211, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_VBUS_CLK", "Input clock"}, - [159] = {211, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_PROBE_CLK", "Input clock"}, - [160] = {212, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_VBUS_CLK", "Input clock"}, - [161] = {212, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_PROBE_CLK", "Input clock"}, - [162] = {209, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_VBUS_CLK", "Input clock"}, - [163] = {209, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_PROBE_CLK", "Input clock"}, - [164] = {206, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_VBUS_CLK", "Input clock"}, - [165] = {206, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_PROBE_CLK", "Input clock"}, - [166] = {208, 0, "DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_VBUS_CLK", "Input clock"}, - [167] = {208, 1, "DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_PROBE_CLK", "Input clock"}, - [168] = {215, 0, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_VBUS_CLK", "Input clock"}, - [169] = {215, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_PROBE_CLK", "Input clock"}, - [170] = {207, 0, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_VBUS_CLK", "Input clock"}, - [171] = {207, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_PROBE_CLK", "Input clock"}, - [172] = {210, 0, "DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_VBUS_CLK", "Input clock"}, - [173] = {210, 1, "DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_PROBE_CLK", "Input clock"}, - [174] = {99, 0, "DEV_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"}, - [175] = {9, 0, "DEV_DCC0_BUS_DCC_INPUT00_CLK", "Input clock"}, - [176] = {9, 1, "DEV_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"}, - [177] = {9, 2, "DEV_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"}, - [178] = {9, 3, "DEV_DCC0_BUS_VBUS_CLK", "Input clock"}, - [179] = {9, 4, "DEV_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"}, - [180] = {9, 5, "DEV_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"}, - [181] = {9, 6, "DEV_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"}, - [182] = {9, 7, "DEV_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"}, - [183] = {9, 8, "DEV_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"}, - [184] = {9, 9, "DEV_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"}, - [185] = {9, 10, "DEV_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"}, - [186] = {9, 11, "DEV_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"}, - [187] = {10, 0, "DEV_DCC1_BUS_DCC_INPUT00_CLK", "Input clock"}, - [188] = {10, 1, "DEV_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"}, - [189] = {10, 2, "DEV_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"}, - [190] = {10, 3, "DEV_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"}, - [191] = {10, 4, "DEV_DCC1_BUS_VBUS_CLK", "Input clock"}, - [192] = {10, 5, "DEV_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"}, - [193] = {10, 6, "DEV_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"}, - [194] = {10, 7, "DEV_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"}, - [195] = {10, 8, "DEV_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"}, - [196] = {10, 9, "DEV_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"}, - [197] = {10, 10, "DEV_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"}, - [198] = {10, 11, "DEV_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"}, - [199] = {10, 12, "DEV_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"}, - [200] = {11, 0, "DEV_DCC2_BUS_DCC_INPUT00_CLK", "Input clock"}, - [201] = {11, 1, "DEV_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"}, - [202] = {11, 2, "DEV_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"}, - [203] = {11, 3, "DEV_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"}, - [204] = {11, 4, "DEV_DCC2_BUS_VBUS_CLK", "Input clock"}, - [205] = {11, 5, "DEV_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"}, - [206] = {11, 6, "DEV_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"}, - [207] = {11, 7, "DEV_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"}, - [208] = {11, 8, "DEV_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"}, - [209] = {11, 9, "DEV_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"}, - [210] = {11, 10, "DEV_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"}, - [211] = {11, 11, "DEV_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"}, - [212] = {11, 12, "DEV_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"}, - [213] = {12, 0, "DEV_DCC3_BUS_DCC_INPUT00_CLK", "Input clock"}, - [214] = {12, 1, "DEV_DCC3_BUS_DCC_CLKSRC7_CLK", "Input clock"}, - [215] = {12, 2, "DEV_DCC3_BUS_DCC_CLKSRC4_CLK", "Input clock"}, - [216] = {12, 3, "DEV_DCC3_BUS_DCC_CLKSRC3_CLK", "Input clock"}, - [217] = {12, 4, "DEV_DCC3_BUS_VBUS_CLK", "Input clock"}, - [218] = {12, 5, "DEV_DCC3_BUS_DCC_CLKSRC1_CLK", "Input clock"}, - [219] = {12, 6, "DEV_DCC3_BUS_DCC_INPUT01_CLK", "Input clock"}, - [220] = {12, 7, "DEV_DCC3_BUS_DCC_CLKSRC5_CLK", "Input clock"}, - [221] = {12, 8, "DEV_DCC3_BUS_DCC_INPUT02_CLK", "Input clock"}, - [222] = {12, 9, "DEV_DCC3_BUS_DCC_CLKSRC0_CLK", "Input clock"}, - [223] = {12, 10, "DEV_DCC3_BUS_DCC_INPUT10_CLK", "Input clock"}, - [224] = {12, 11, "DEV_DCC3_BUS_DCC_CLKSRC2_CLK", "Input clock"}, - [225] = {13, 0, "DEV_DCC4_BUS_DCC_INPUT00_CLK", "Input clock"}, - [226] = {13, 1, "DEV_DCC4_BUS_DCC_CLKSRC7_CLK", "Input clock"}, - [227] = {13, 2, "DEV_DCC4_BUS_DCC_CLKSRC4_CLK", "Input clock"}, - [228] = {13, 3, "DEV_DCC4_BUS_DCC_CLKSRC3_CLK", "Input clock"}, - [229] = {13, 4, "DEV_DCC4_BUS_VBUS_CLK", "Input clock"}, - [230] = {13, 5, "DEV_DCC4_BUS_DCC_INPUT01_CLK", "Input clock"}, - [231] = {13, 6, "DEV_DCC4_BUS_DCC_CLKSRC5_CLK", "Input clock"}, - [232] = {13, 7, "DEV_DCC4_BUS_DCC_INPUT02_CLK", "Input clock"}, - [233] = {13, 8, "DEV_DCC4_BUS_DCC_CLKSRC0_CLK", "Input clock"}, - [234] = {13, 9, "DEV_DCC4_BUS_DCC_CLKSRC6_CLK", "Input clock"}, - [235] = {13, 10, "DEV_DCC4_BUS_DCC_INPUT10_CLK", "Input clock"}, - [236] = {13, 11, "DEV_DCC4_BUS_DCC_CLKSRC2_CLK", "Input clock"}, - [237] = {14, 0, "DEV_DCC5_BUS_DCC_INPUT00_CLK", "Input clock"}, - [238] = {14, 1, "DEV_DCC5_BUS_DCC_CLKSRC7_CLK", "Input clock"}, - [239] = {14, 2, "DEV_DCC5_BUS_DCC_CLKSRC4_CLK", "Input clock"}, - [240] = {14, 3, "DEV_DCC5_BUS_DCC_CLKSRC3_CLK", "Input clock"}, - [241] = {14, 4, "DEV_DCC5_BUS_VBUS_CLK", "Input clock"}, - [242] = {14, 5, "DEV_DCC5_BUS_DCC_CLKSRC1_CLK", "Input clock"}, - [243] = {14, 6, "DEV_DCC5_BUS_DCC_INPUT01_CLK", "Input clock"}, - [244] = {14, 7, "DEV_DCC5_BUS_DCC_CLKSRC5_CLK", "Input clock"}, - [245] = {14, 8, "DEV_DCC5_BUS_DCC_INPUT02_CLK", "Input clock"}, - [246] = {14, 9, "DEV_DCC5_BUS_DCC_CLKSRC0_CLK", "Input clock"}, - [247] = {14, 10, "DEV_DCC5_BUS_DCC_CLKSRC6_CLK", "Input clock"}, - [248] = {14, 11, "DEV_DCC5_BUS_DCC_INPUT10_CLK", "Input clock"}, - [249] = {14, 12, "DEV_DCC5_BUS_DCC_CLKSRC2_CLK", "Input clock"}, - [250] = {15, 0, "DEV_DCC6_BUS_DCC_INPUT00_CLK", "Input clock"}, - [251] = {15, 1, "DEV_DCC6_BUS_DCC_CLKSRC7_CLK", "Input clock"}, - [252] = {15, 2, "DEV_DCC6_BUS_DCC_CLKSRC4_CLK", "Input clock"}, - [253] = {15, 3, "DEV_DCC6_BUS_DCC_CLKSRC3_CLK", "Input clock"}, - [254] = {15, 4, "DEV_DCC6_BUS_VBUS_CLK", "Input clock"}, - [255] = {15, 5, "DEV_DCC6_BUS_DCC_CLKSRC1_CLK", "Input clock"}, - [256] = {15, 6, "DEV_DCC6_BUS_DCC_INPUT01_CLK", "Input clock"}, - [257] = {15, 7, "DEV_DCC6_BUS_DCC_CLKSRC5_CLK", "Input clock"}, - [258] = {15, 8, "DEV_DCC6_BUS_DCC_INPUT02_CLK", "Input clock"}, - [259] = {15, 9, "DEV_DCC6_BUS_DCC_CLKSRC0_CLK", "Input clock"}, - [260] = {15, 10, "DEV_DCC6_BUS_DCC_CLKSRC6_CLK", "Input clock"}, - [261] = {15, 11, "DEV_DCC6_BUS_DCC_INPUT10_CLK", "Input clock"}, - [262] = {15, 12, "DEV_DCC6_BUS_DCC_CLKSRC2_CLK", "Input clock"}, - [263] = {16, 0, "DEV_DCC7_BUS_DCC_INPUT00_CLK", "Input clock"}, - [264] = {16, 1, "DEV_DCC7_BUS_DCC_CLKSRC7_CLK", "Input clock"}, - [265] = {16, 2, "DEV_DCC7_BUS_DCC_CLKSRC4_CLK", "Input clock"}, - [266] = {16, 3, "DEV_DCC7_BUS_DCC_CLKSRC3_CLK", "Input clock"}, - [267] = {16, 4, "DEV_DCC7_BUS_VBUS_CLK", "Input clock"}, - [268] = {16, 5, "DEV_DCC7_BUS_DCC_CLKSRC1_CLK", "Input clock"}, - [269] = {16, 6, "DEV_DCC7_BUS_DCC_INPUT01_CLK", "Input clock"}, - [270] = {16, 7, "DEV_DCC7_BUS_DCC_CLKSRC5_CLK", "Input clock"}, - [271] = {16, 8, "DEV_DCC7_BUS_DCC_INPUT02_CLK", "Input clock"}, - [272] = {16, 9, "DEV_DCC7_BUS_DCC_CLKSRC0_CLK", "Input clock"}, - [273] = {16, 10, "DEV_DCC7_BUS_DCC_CLKSRC6_CLK", "Input clock"}, - [274] = {16, 11, "DEV_DCC7_BUS_DCC_INPUT10_CLK", "Input clock"}, - [275] = {16, 12, "DEV_DCC7_BUS_DCC_CLKSRC2_CLK", "Input clock"}, - [276] = {20, 0, "DEV_DDRSS0_BUS_DDRSS_VBUS_CLK", "Input clock"}, - [277] = {20, 1, "DEV_DDRSS0_BUS_DDRSS_BYP_4X_CLK", "Input clock"}, - [278] = {20, 2, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, - [279] = {20, 3, "DEV_DDRSS0_BUS_DDRSS_TCLK", "Input clock"}, - [280] = {20, 4, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, - [281] = {20, 5, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, - [282] = {20, 6, "DEV_DDRSS0_BUS_DDRSS_CFG_CLK", "Input clock"}, - [283] = {20, 7, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, - [284] = {20, 8, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, - [285] = {20, 9, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, - [286] = {68, 0, "DEV_DEBUGSS0_BUS_ATB1_CLK", "Input clock"}, - [287] = {68, 1, "DEV_DEBUGSS0_BUS_ATB5_CLK", "Input clock"}, - [288] = {68, 2, "DEV_DEBUGSS0_BUS_ATB0_CLK", "Input clock"}, - [289] = {68, 3, "DEV_DEBUGSS0_BUS_SYS_CLK", "Input clock"}, - [290] = {68, 4, "DEV_DEBUGSS0_BUS_ATB4_CLK", "Input clock"}, - [291] = {68, 5, "DEV_DEBUGSS0_BUS_CFG_CLK", "Input clock"}, - [292] = {68, 6, "DEV_DEBUGSS0_BUS_ATB2_CLK", "Input clock"}, - [293] = {68, 7, "DEV_DEBUGSS0_BUS_DBG_CLK", "Input clock"}, - [294] = {68, 8, "DEV_DEBUGSS0_BUS_ATB3_CLK", "Input clock"}, - [295] = {21, 0, "DEV_DEBUGSS_WRAP0_BUS_JTAG_TCK", "Input clock"}, - [296] = {21, 1, "DEV_DEBUGSS_WRAP0_BUS_ATB_CLK", "Input clock"}, - [297] = {21, 2, "DEV_DEBUGSS_WRAP0_BUS_TREXPT_CLK", "Input clock"}, - [298] = {21, 3, "DEV_DEBUGSS_WRAP0_BUS_CORE_CLK", "Input clock"}, - [299] = {81, 0, "DEV_DEBUGSUSPENDRTR0_BUS_INTR_CLK", "Input clock"}, - [300] = {117, 0, "DEV_DFTSS0_BUS_VBUSP_CLK_CLK", "Input clock"}, - [301] = {67, 0, "DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN1_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"}, - [302] = {67, 1, "DEV_DSS0_BUS_DSS_FUNC_CLK", "Input clock"}, - [303] = {67, 2, "DEV_DSS0_BUS_DPI_1_IN_CLK", "Input muxed clock"}, - [304] = {67, 3, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_CLOCKDIVIDER_DSS_BUS_OUT07", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"}, - [305] = {67, 4, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_BOARD_0_BUS_DSS0EXTPCLKIN", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"}, - [306] = {67, 5, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_CLOCKDIVIDER_DSS_BUS_OUT1", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"}, - [307] = {67, 6, "DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN0_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"}, - [308] = {67, 7, "DEV_DSS0_BUS_DPI_1_OUT_CLK", "Output clock"}, - [309] = {39, 0, "DEV_ECAP0_BUS_VBUS_CLK", "Input clock"}, - [310] = {86, 0, "DEV_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"}, - [311] = {87, 0, "DEV_ECC_AGGR1_BUS_AGGR_CLK", "Input clock"}, - [312] = {88, 0, "DEV_ECC_AGGR2_BUS_AGGR_CLK", "Input clock"}, - [313] = {69, 0, "DEV_EFUSE0_BUS_VBUSP_PLL_CLK_CLK", "Input clock"}, - [314] = {69, 1, "DEV_EFUSE0_BUS_EFC1_CTL_FCLK", "Output clock"}, - [315] = {69, 2, "DEV_EFUSE0_BUS_EFC0_CTL_FCLK", "Output clock"}, - [316] = {40, 0, "DEV_EHRPWM0_BUS_VBUSP_CLK", "Input clock"}, - [317] = {41, 0, "DEV_EHRPWM1_BUS_VBUSP_CLK", "Input clock"}, - [318] = {42, 0, "DEV_EHRPWM2_BUS_VBUSP_CLK", "Input clock"}, - [319] = {43, 0, "DEV_EHRPWM3_BUS_VBUSP_CLK", "Input clock"}, - [320] = {44, 0, "DEV_EHRPWM4_BUS_VBUSP_CLK", "Input clock"}, - [321] = {45, 0, "DEV_EHRPWM5_BUS_VBUSP_CLK", "Input clock"}, - [322] = {46, 0, "DEV_ELM0_BUS_VBUSP_CLK", "Input clock"}, - [323] = {49, 0, "DEV_EQEP0_BUS_VBUS_CLK", "Input clock"}, - [324] = {50, 0, "DEV_EQEP1_BUS_VBUS_CLK", "Input clock"}, - [325] = {51, 0, "DEV_EQEP2_BUS_VBUS_CLK", "Input clock"}, - [326] = {52, 0, "DEV_ESM0_BUS_CLK", "Input clock"}, - [327] = {56, 0, "DEV_GIC0_BUS_VCLK_CLK", "Input clock"}, - [328] = {57, 0, "DEV_GPIO0_BUS_MMR_CLK", "Input clock"}, - [329] = {58, 0, "DEV_GPIO1_BUS_MMR_CLK", "Input clock"}, - [330] = {100, 0, "DEV_GPIOMUX_INTRTR0_BUS_INTR_CLK", "Input clock"}, - [331] = {60, 0, "DEV_GPMC0_BUS_FUNC_CLK", "Input muxed clock"}, - [332] = {60, 1, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"}, - [333] = {60, 2, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK3", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"}, - [334] = {60, 3, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK2", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"}, - [335] = {60, 4, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"}, - [336] = {60, 5, "DEV_GPMC0_BUS_PI_GPMC_RET_CLK", "Input clock"}, - [337] = {60, 6, "DEV_GPMC0_BUS_VBUSP_CLK", "Input clock"}, - [338] = {60, 7, "DEV_GPMC0_BUS_PO_GPMC_DEV_CLK", "Output clock"}, - [339] = {65, 0, "DEV_GPU0_BUS_MEM_CLK", "Input clock"}, - [340] = {65, 1, "DEV_GPU0_BUS_HYD_CORE_CLK", "Input clock"}, - [341] = {65, 2, "DEV_GPU0_BUS_SGX_CORE_CLK", "Input clock"}, - [342] = {65, 3, "DEV_GPU0_BUS_SYS_CLK", "Input clock"}, - [343] = {232, 0, "DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_OSC_CLK", "Input clock"}, - [344] = {232, 1, "DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_CLK", "Input clock"}, - [345] = {231, 0, "DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_OSC_CLK", "Input clock"}, - [346] = {231, 1, "DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_CLK", "Input clock"}, - [347] = {61, 0, "DEV_GTC0_BUS_VBUSP_CLK", "Input muxed clock"}, - [348] = {61, 1, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, - [349] = {61, 2, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, - [350] = {61, 3, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, - [351] = {61, 4, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, - [352] = {61, 5, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, - [353] = {61, 6, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, - [354] = {61, 7, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, - [355] = {61, 8, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, - [356] = {110, 0, "DEV_I2C0_BUS_CLK", "Input clock"}, - [357] = {110, 1, "DEV_I2C0_BUS_PISYS_CLK", "Input clock"}, - [358] = {110, 2, "DEV_I2C0_BUS_PISCL", "Output clock"}, - [359] = {111, 0, "DEV_I2C1_BUS_CLK", "Input clock"}, - [360] = {111, 1, "DEV_I2C1_BUS_PISYS_CLK", "Input clock"}, - [361] = {111, 2, "DEV_I2C1_BUS_PISCL", "Output clock"}, - [362] = {112, 0, "DEV_I2C2_BUS_CLK", "Input clock"}, - [363] = {112, 1, "DEV_I2C2_BUS_PISYS_CLK", "Input clock"}, - [364] = {112, 2, "DEV_I2C2_BUS_PISCL", "Output clock"}, - [365] = {113, 0, "DEV_I2C3_BUS_CLK", "Input clock"}, - [366] = {113, 1, "DEV_I2C3_BUS_PISYS_CLK", "Input clock"}, - [367] = {113, 2, "DEV_I2C3_BUS_PISCL", "Output clock"}, - [368] = {217, 0, "DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0_BUS_DBG_CLK", "Input clock"}, - [369] = {97, 0, "DEV_MAIN2MCU_LVL_INTRTR0_BUS_INTR_CLK", "Input clock"}, - [370] = {98, 0, "DEV_MAIN2MCU_PLS_INTRTR0_BUS_INTR_CLK", "Input clock"}, - [371] = {104, 0, "DEV_MCASP0_BUS_AUX_CLK", "Input muxed clock"}, - [372] = {104, 1, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, - [373] = {104, 2, "DEV_MCASP0_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, - [374] = {104, 3, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, - [375] = {104, 4, "DEV_MCASP0_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, - [376] = {104, 5, "DEV_MCASP0_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, - [377] = {104, 6, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, - [378] = {104, 7, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, - [379] = {104, 8, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, - [380] = {104, 9, "DEV_MCASP0_BUS_VBUSP_CLK", "Input clock"}, - [381] = {104, 10, "DEV_MCASP0_BUS_MCASP_AHCLKX_PIN", "Input clock"}, - [382] = {104, 11, "DEV_MCASP0_BUS_MCASP_AHCLKR_PIN", "Input clock"}, - [383] = {105, 0, "DEV_MCASP1_BUS_AUX_CLK", "Input muxed clock"}, - [384] = {105, 1, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, - [385] = {105, 2, "DEV_MCASP1_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, - [386] = {105, 3, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, - [387] = {105, 4, "DEV_MCASP1_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, - [388] = {105, 5, "DEV_MCASP1_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, - [389] = {105, 6, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, - [390] = {105, 7, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, - [391] = {105, 8, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, - [392] = {105, 9, "DEV_MCASP1_BUS_VBUSP_CLK", "Input clock"}, - [393] = {105, 10, "DEV_MCASP1_BUS_MCASP_AHCLKX_PIN", "Input clock"}, - [394] = {105, 11, "DEV_MCASP1_BUS_MCASP_AHCLKR_PIN", "Input clock"}, - [395] = {106, 0, "DEV_MCASP2_BUS_AUX_CLK", "Input muxed clock"}, - [396] = {106, 1, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, - [397] = {106, 2, "DEV_MCASP2_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, - [398] = {106, 3, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, - [399] = {106, 4, "DEV_MCASP2_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, - [400] = {106, 5, "DEV_MCASP2_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT2", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, - [401] = {106, 6, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, - [402] = {106, 7, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, - [403] = {106, 8, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, - [404] = {106, 9, "DEV_MCASP2_BUS_VBUSP_CLK", "Input clock"}, - [405] = {106, 10, "DEV_MCASP2_BUS_MCASP_AHCLKX_PIN", "Input clock"}, - [406] = {106, 11, "DEV_MCASP2_BUS_MCASP_AHCLKR_PIN", "Input clock"}, - [407] = {137, 0, "DEV_MCSPI0_BUS_IO_CLKSPII_CLK", "Input clock"}, - [408] = {137, 1, "DEV_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"}, - [409] = {137, 2, "DEV_MCSPI0_BUS_VBUSP_CLK", "Input clock"}, - [410] = {137, 3, "DEV_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"}, - [411] = {138, 0, "DEV_MCSPI1_BUS_IO_CLKSPII_CLK", "Input clock"}, - [412] = {138, 1, "DEV_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"}, - [413] = {138, 2, "DEV_MCSPI1_BUS_VBUSP_CLK", "Input clock"}, - [414] = {138, 3, "DEV_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"}, - [415] = {139, 0, "DEV_MCSPI2_BUS_IO_CLKSPII_CLK", "Input clock"}, - [416] = {139, 1, "DEV_MCSPI2_BUS_CLKSPIREF_CLK", "Input clock"}, - [417] = {139, 2, "DEV_MCSPI2_BUS_VBUSP_CLK", "Input clock"}, - [418] = {139, 3, "DEV_MCSPI2_BUS_IO_CLKSPIO_CLK", "Output clock"}, - [419] = {140, 0, "DEV_MCSPI3_BUS_IO_CLKSPII_CLK", "Input clock"}, - [420] = {140, 1, "DEV_MCSPI3_BUS_CLKSPIREF_CLK", "Input clock"}, - [421] = {140, 2, "DEV_MCSPI3_BUS_VBUSP_CLK", "Input clock"}, - [422] = {140, 3, "DEV_MCSPI3_BUS_IO_CLKSPIO_CLK", "Output clock"}, - [423] = {141, 0, "DEV_MCSPI4_BUS_CLKSPIREF_CLK", "Input clock"}, - [424] = {141, 1, "DEV_MCSPI4_BUS_VBUSP_CLK", "Input clock"}, - [425] = {0, 0, "DEV_MCU_ADC0_BUS_VBUS_CLK", "Input clock"}, - [426] = {0, 1, "DEV_MCU_ADC0_BUS_SYS_CLK", "Input clock"}, - [427] = {0, 2, "DEV_MCU_ADC0_BUS_ADC_CLK", "Input muxed clock"}, - [428] = {0, 3, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"}, - [429] = {0, 4, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"}, - [430] = {0, 5, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"}, - [431] = {0, 6, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"}, - [432] = {1, 0, "DEV_MCU_ADC1_BUS_VBUS_CLK", "Input clock"}, - [433] = {1, 1, "DEV_MCU_ADC1_BUS_SYS_CLK", "Input clock"}, - [434] = {1, 2, "DEV_MCU_ADC1_BUS_ADC_CLK", "Input muxed clock"}, - [435] = {1, 3, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"}, - [436] = {1, 4, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"}, - [437] = {1, 5, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"}, - [438] = {1, 6, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"}, - [439] = {129, 0, "DEV_MCU_ARMSS0_BUS_INTERFACE_CLK", "Input clock"}, - [440] = {159, 0, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_CLK", "Input clock"}, - [441] = {159, 1, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE", "Input muxed clock"}, - [442] = {159, 2, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE"}, - [443] = {159, 3, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK", "Input muxed clock"}, - [444] = {159, 4, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"}, - [445] = {159, 5, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"}, - [446] = {245, 0, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_CLK", "Input clock"}, - [447] = {245, 1, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE", "Input muxed clock"}, - [448] = {245, 2, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE"}, - [449] = {245, 3, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK", "Input muxed clock"}, - [450] = {245, 4, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"}, - [451] = {245, 5, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"}, - [452] = {89, 0, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_8_CLK", "Input clock"}, - [453] = {89, 1, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_4_CLK", "Input clock"}, - [454] = {89, 2, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"}, - [455] = {90, 0, "DEV_MCU_CBASS_DEBUG0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"}, - [456] = {91, 0, "DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_4_CLK", "Input clock"}, - [457] = {91, 1, "DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"}, - [458] = {5, 0, "DEV_MCU_CPSW0_BUS_GMII1_MR_CLK", "Input clock"}, - [459] = {5, 1, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_250_CLK", "Input clock"}, - [460] = {5, 2, "DEV_MCU_CPSW0_BUS_CPTS_RFT_CLK", "Input clock"}, - [461] = {5, 3, "DEV_MCU_CPSW0_BUS_GMII1_MT_CLK", "Input clock"}, - [462] = {5, 4, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_5_CLK", "Input clock"}, - [463] = {5, 5, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_50_CLK", "Input clock"}, - [464] = {5, 6, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK", "Input muxed clock"}, - [465] = {5, 7, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"}, - [466] = {5, 8, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_BOARD_0_BUS_MCU_RMII1_REFCLK", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"}, - [467] = {5, 9, "DEV_MCU_CPSW0_BUS_GMII_RFT_CLK", "Input clock"}, - [468] = {5, 10, "DEV_MCU_CPSW0_BUS_CPPI_CLK_CLK", "Input clock"}, - [469] = {5, 11, "DEV_MCU_CPSW0_BUS_CPTS_GENF0_0", "Output clock"}, - [470] = {7, 0, "DEV_MCU_CPT2_AGGR0_BUS_VCLK_CLK", "Input clock"}, - [471] = {107, 0, "DEV_MCU_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"}, - [472] = {17, 0, "DEV_MCU_DCC0_BUS_DCC_INPUT00_CLK", "Input clock"}, - [473] = {17, 1, "DEV_MCU_DCC0_BUS_DCC_CLKSRC7_CLK", "Input clock"}, - [474] = {17, 2, "DEV_MCU_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"}, - [475] = {17, 3, "DEV_MCU_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"}, - [476] = {17, 4, "DEV_MCU_DCC0_BUS_VBUS_CLK", "Input clock"}, - [477] = {17, 5, "DEV_MCU_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"}, - [478] = {17, 6, "DEV_MCU_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"}, - [479] = {17, 7, "DEV_MCU_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"}, - [480] = {17, 8, "DEV_MCU_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"}, - [481] = {17, 9, "DEV_MCU_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"}, - [482] = {17, 10, "DEV_MCU_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"}, - [483] = {17, 11, "DEV_MCU_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"}, - [484] = {17, 12, "DEV_MCU_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"}, - [485] = {18, 0, "DEV_MCU_DCC1_BUS_DCC_INPUT00_CLK", "Input clock"}, - [486] = {18, 1, "DEV_MCU_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"}, - [487] = {18, 2, "DEV_MCU_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"}, - [488] = {18, 3, "DEV_MCU_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"}, - [489] = {18, 4, "DEV_MCU_DCC1_BUS_VBUS_CLK", "Input clock"}, - [490] = {18, 5, "DEV_MCU_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"}, - [491] = {18, 6, "DEV_MCU_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"}, - [492] = {18, 7, "DEV_MCU_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"}, - [493] = {18, 8, "DEV_MCU_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"}, - [494] = {18, 9, "DEV_MCU_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"}, - [495] = {18, 10, "DEV_MCU_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"}, - [496] = {18, 11, "DEV_MCU_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"}, - [497] = {18, 12, "DEV_MCU_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"}, - [498] = {19, 0, "DEV_MCU_DCC2_BUS_DCC_INPUT00_CLK", "Input clock"}, - [499] = {19, 1, "DEV_MCU_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"}, - [500] = {19, 2, "DEV_MCU_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"}, - [501] = {19, 3, "DEV_MCU_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"}, - [502] = {19, 4, "DEV_MCU_DCC2_BUS_VBUS_CLK", "Input clock"}, - [503] = {19, 5, "DEV_MCU_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"}, - [504] = {19, 6, "DEV_MCU_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"}, - [505] = {19, 7, "DEV_MCU_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"}, - [506] = {19, 8, "DEV_MCU_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"}, - [507] = {19, 9, "DEV_MCU_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"}, - [508] = {19, 10, "DEV_MCU_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"}, - [509] = {19, 11, "DEV_MCU_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"}, - [510] = {19, 12, "DEV_MCU_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"}, - [511] = {71, 0, "DEV_MCU_DEBUGSS0_BUS_ATB1_CLK", "Input clock"}, - [512] = {71, 1, "DEV_MCU_DEBUGSS0_BUS_ATB0_CLK", "Input clock"}, - [513] = {71, 2, "DEV_MCU_DEBUGSS0_BUS_SYS_CLK", "Input clock"}, - [514] = {71, 3, "DEV_MCU_DEBUGSS0_BUS_CFG_CLK", "Input clock"}, - [515] = {71, 4, "DEV_MCU_DEBUGSS0_BUS_ATB2_CLK", "Input clock"}, - [516] = {71, 5, "DEV_MCU_DEBUGSS0_BUS_DBG_CLK", "Input clock"}, - [517] = {71, 6, "DEV_MCU_DEBUGSS0_BUS_ATB3_CLK", "Input clock"}, - [518] = {92, 0, "DEV_MCU_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"}, - [519] = {93, 0, "DEV_MCU_ECC_AGGR1_BUS_AGGR_CLK", "Input clock"}, - [520] = {72, 0, "DEV_MCU_EFUSE0_BUS_VBUSP_CLK_CLK", "Input clock"}, - [521] = {72, 1, "DEV_MCU_EFUSE0_BUS_EFC3_CTL_FCLK", "Output clock"}, - [522] = {72, 2, "DEV_MCU_EFUSE0_BUS_EFC0_CTL_FCLK", "Output clock"}, - [523] = {72, 3, "DEV_MCU_EFUSE0_BUS_EFC1_CTL_FCLK", "Output clock"}, - [524] = {72, 4, "DEV_MCU_EFUSE0_BUS_EFC2_CTL_FCLK", "Output clock"}, - [525] = {53, 0, "DEV_MCU_ESM0_BUS_CLK", "Input clock"}, - [526] = {55, 0, "DEV_MCU_FSS0_BUS_HPB_CLKX1_INV_CLK", "Input clock"}, - [527] = {55, 1, "DEV_MCU_FSS0_BUS_VBUS_CLK", "Input clock"}, - [528] = {55, 2, "DEV_MCU_FSS0_BUS_OSPI1_ICLK_CLK", "Input muxed clock"}, - [529] = {55, 3, "DEV_MCU_FSS0_BUS_OSPI1_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI1DQS", "Parent input clock option to DEV_MCU_FSS0_BUS_OSPI1_ICLK_CLK"}, - [530] = {55, 4, "DEV_MCU_FSS0_BUS_OSPI1_ICLK_CLK_PARENT_FSS_MCU_0_BUS_OSPI1_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_BUS_OSPI1_ICLK_CLK"}, - [531] = {55, 5, "DEV_MCU_FSS0_BUS_OSPI0_RCLK_CLK", "Input muxed clock"}, - [532] = {55, 6, "DEV_MCU_FSS0_BUS_OSPI0_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_BUS_OSPI0_RCLK_CLK"}, - [533] = {55, 7, "DEV_MCU_FSS0_BUS_OSPI0_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_BUS_OSPI0_RCLK_CLK"}, - [534] = {55, 8, "DEV_MCU_FSS0_BUS_HPB_CLKX2_CLK", "Input clock"}, - [535] = {55, 9, "DEV_MCU_FSS0_BUS_HPB_CLKX2_INV_CLK", "Input clock"}, - [536] = {55, 10, "DEV_MCU_FSS0_BUS_OSPI0_ICLK_CLK", "Input muxed clock"}, - [537] = {55, 11, "DEV_MCU_FSS0_BUS_OSPI0_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI0DQS", "Parent input clock option to DEV_MCU_FSS0_BUS_OSPI0_ICLK_CLK"}, - [538] = {55, 12, "DEV_MCU_FSS0_BUS_OSPI0_ICLK_CLK_PARENT_FSS_MCU_0_BUS_OSPI0_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_BUS_OSPI0_ICLK_CLK"}, - [539] = {55, 13, "DEV_MCU_FSS0_BUS_HPB_CLKX1_CLK", "Input clock"}, - [540] = {55, 14, "DEV_MCU_FSS0_BUS_OSPI0_DQS_CLK", "Input clock"}, - [541] = {55, 15, "DEV_MCU_FSS0_BUS_OSPI1_DQS_CLK", "Input clock"}, - [542] = {55, 16, "DEV_MCU_FSS0_BUS_OSPI1_RCLK_CLK", "Input muxed clock"}, - [543] = {55, 17, "DEV_MCU_FSS0_BUS_OSPI1_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_BUS_OSPI1_RCLK_CLK"}, - [544] = {55, 18, "DEV_MCU_FSS0_BUS_OSPI1_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_BUS_OSPI1_RCLK_CLK"}, - [545] = {55, 19, "DEV_MCU_FSS0_BUS_OSPI0_OCLK_CLK", "Output clock"}, - [546] = {55, 20, "DEV_MCU_FSS0_BUS_OSPI1_OCLK_CLK", "Output clock"}, - [547] = {114, 0, "DEV_MCU_I2C0_BUS_CLK", "Input clock"}, - [548] = {114, 1, "DEV_MCU_I2C0_BUS_PISYS_CLK", "Input clock"}, - [549] = {114, 2, "DEV_MCU_I2C0_BUS_PISCL", "Output clock"}, - [550] = {102, 0, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK", "Input muxed clock"}, - [551] = {102, 1, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"}, - [552] = {102, 2, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"}, - [553] = {102, 3, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"}, - [554] = {102, 4, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"}, - [555] = {102, 5, "DEV_MCU_MCAN0_BUS_MCANSS_HCLK_CLK", "Input clock"}, - [556] = {103, 0, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK", "Input muxed clock"}, - [557] = {103, 1, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"}, - [558] = {103, 2, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"}, - [559] = {103, 3, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"}, - [560] = {103, 4, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"}, - [561] = {103, 5, "DEV_MCU_MCAN1_BUS_MCANSS_HCLK_CLK", "Input clock"}, - [562] = {142, 0, "DEV_MCU_MCSPI0_BUS_IO_CLKSPII_CLK", "Input clock"}, - [563] = {142, 1, "DEV_MCU_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"}, - [564] = {142, 2, "DEV_MCU_MCSPI0_BUS_VBUSP_CLK", "Input clock"}, - [565] = {142, 3, "DEV_MCU_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"}, - [566] = {143, 0, "DEV_MCU_MCSPI1_BUS_IO_CLKSPII_CLK", "Input clock"}, - [567] = {143, 1, "DEV_MCU_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"}, - [568] = {143, 2, "DEV_MCU_MCSPI1_BUS_VBUSP_CLK", "Input clock"}, - [569] = {143, 3, "DEV_MCU_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"}, - [570] = {144, 0, "DEV_MCU_MCSPI2_BUS_CLKSPIREF_CLK", "Input clock"}, - [571] = {144, 1, "DEV_MCU_MCSPI2_BUS_VBUSP_CLK", "Input clock"}, - [572] = {116, 0, "DEV_MCU_MSRAM0_BUS_CCLK_CLK", "Input clock"}, - [573] = {116, 1, "DEV_MCU_MSRAM0_BUS_VCLK_CLK", "Input clock"}, - [574] = {119, 0, "DEV_MCU_NAVSS0_BUS_UDMASS_VD2CLK", "Input clock"}, - [575] = {119, 1, "DEV_MCU_NAVSS0_BUS_CPSW0CLK", "Input clock"}, - [576] = {119, 2, "DEV_MCU_NAVSS0_BUS_MODSS_VD2CLK", "Input clock"}, - [577] = {119, 3, "DEV_MCU_NAVSS0_BUS_PDMA_MCU1CLK", "Input clock"}, - [578] = {75, 0, "DEV_MCU_PBIST0_BUS_CLK1_CLK", "Input clock"}, - [579] = {75, 1, "DEV_MCU_PBIST0_BUS_CLK4_CLK", "Input clock"}, - [580] = {75, 2, "DEV_MCU_PBIST0_BUS_CLK2_CLK", "Input clock"}, - [581] = {125, 0, "DEV_MCU_PDMA0_BUS_VCLK", "Input clock"}, - [582] = {126, 0, "DEV_MCU_PDMA1_BUS_VCLK", "Input clock"}, - [583] = {108, 0, "DEV_MCU_PLL_MMR0_BUS_VBUSP_CLK", "Input clock"}, - [584] = {127, 0, "DEV_MCU_PSRAM0_BUS_CLK_CLK", "Input clock"}, - [585] = {78, 0, "DEV_MCU_ROM0_BUS_CLK_CLK", "Input clock"}, - [586] = {134, 0, "DEV_MCU_RTI0_BUS_RTI_CLK", "Input muxed clock"}, - [587] = {134, 1, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"}, - [588] = {134, 2, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"}, - [589] = {134, 3, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"}, - [590] = {134, 4, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"}, - [591] = {134, 5, "DEV_MCU_RTI0_BUS_VBUSP_CLK", "Input clock"}, - [592] = {135, 0, "DEV_MCU_RTI1_BUS_RTI_CLK", "Input muxed clock"}, - [593] = {135, 1, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"}, - [594] = {135, 2, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"}, - [595] = {135, 3, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"}, - [596] = {135, 4, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"}, - [597] = {135, 5, "DEV_MCU_RTI1_BUS_VBUSP_CLK", "Input clock"}, - [598] = {109, 0, "DEV_MCU_SEC_MMR0_BUS_VBUSP_CLK", "Input clock"}, - [599] = {35, 0, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, - [600] = {35, 1, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, - [601] = {35, 2, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, - [602] = {35, 3, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, - [603] = {35, 4, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, - [604] = {35, 5, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, - [605] = {35, 6, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, - [606] = {35, 7, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, - [607] = {35, 8, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, - [608] = {35, 9, "DEV_MCU_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"}, - [609] = {36, 0, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, - [610] = {36, 1, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, - [611] = {36, 2, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, - [612] = {36, 3, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, - [613] = {36, 4, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, - [614] = {36, 5, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, - [615] = {36, 6, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, - [616] = {36, 7, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, - [617] = {36, 8, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, - [618] = {36, 9, "DEV_MCU_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"}, - [619] = {37, 0, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, - [620] = {37, 1, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, - [621] = {37, 2, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, - [622] = {37, 3, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, - [623] = {37, 4, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, - [624] = {37, 5, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, - [625] = {37, 6, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, - [626] = {37, 7, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, - [627] = {37, 8, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, - [628] = {37, 9, "DEV_MCU_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"}, - [629] = {38, 0, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, - [630] = {38, 1, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, - [631] = {38, 2, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, - [632] = {38, 3, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, - [633] = {38, 4, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, - [634] = {38, 5, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, - [635] = {38, 6, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, - [636] = {38, 7, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, - [637] = {38, 8, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, - [638] = {38, 9, "DEV_MCU_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"}, - [639] = {149, 0, "DEV_MCU_UART0_BUS_FCLK_CLK", "Input muxed clock"}, - [640] = {149, 1, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"}, - [641] = {149, 2, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"}, - [642] = {149, 3, "DEV_MCU_UART0_BUS_VBUSP_CLK", "Input clock"}, - [643] = {47, 0, "DEV_MMCSD0_BUS_EMMCSDSS_VBUS_CLK", "Input clock"}, - [644] = {47, 1, "DEV_MMCSD0_BUS_EMMCSDSS_XIN_CLK", "Input clock"}, - [645] = {48, 0, "DEV_MMCSD1_BUS_EMMCSDSS_VBUS_CLK", "Input clock"}, - [646] = {48, 1, "DEV_MMCSD1_BUS_EMMCSDSS_XIN_CLK", "Input clock"}, - [647] = {234, 0, "DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0_BUS_UNDEFINEDCHAIN1_FCLK", "Input clock"}, - [648] = {234, 1, "DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0_BUS_UNDEFINEDCHAIN0_FCLK", "Input clock"}, - [649] = {235, 0, "DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN1_FCLK", "Input clock"}, - [650] = {235, 1, "DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN0_FCLK", "Input clock"}, - [651] = {235, 2, "DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN2_FCLK", "Input clock"}, - [652] = {118, 0, "DEV_NAVSS0_BUS_UDMASS_VD2CLK", "Input clock"}, - [653] = {118, 1, "DEV_NAVSS0_BUS_ICSS_G2CLK", "Input clock"}, - [654] = {118, 2, "DEV_NAVSS0_BUS_ICSS_G0CLK", "Input clock"}, - [655] = {118, 3, "DEV_NAVSS0_BUS_RCLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK", "Input clock"}, - [656] = {118, 4, "DEV_NAVSS0_BUS_MSMC0CLK", "Input clock"}, - [657] = {118, 5, "DEV_NAVSS0_BUS_RCLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"}, - [658] = {118, 6, "DEV_NAVSS0_BUS_RCLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK", "Input clock"}, - [659] = {118, 7, "DEV_NAVSS0_BUS_MODSS_VD2CLK", "Input clock"}, - [660] = {118, 8, "DEV_NAVSS0_BUS_RCLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0", "Input clock"}, - [661] = {118, 9, "DEV_NAVSS0_BUS_PDMA_MAIN1CLK", "Input clock"}, - [662] = {118, 10, "DEV_NAVSS0_BUS_NBSS_VCLK", "Input clock"}, - [663] = {118, 11, "DEV_NAVSS0_BUS_RCLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"}, - [664] = {118, 12, "DEV_NAVSS0_BUS_NBSS_VD2CLK", "Input clock"}, - [665] = {118, 13, "DEV_NAVSS0_BUS_ICSS_G1CLK", "Input clock"}, - [666] = {118, 14, "DEV_NAVSS0_BUS_RCLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1", "Input clock"}, - [667] = {118, 15, "DEV_NAVSS0_BUS_CPTS0_GENF4_0", "Output clock"}, - [668] = {118, 16, "DEV_NAVSS0_BUS_CPTS0_GENF5_0", "Output clock"}, - [669] = {118, 17, "DEV_NAVSS0_BUS_CPTS0_GENF2_0", "Output clock"}, - [670] = {118, 18, "DEV_NAVSS0_BUS_CPTS0_GENF3_0", "Output clock"}, - [671] = {216, 0, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_PLL_CLK", "Input clock"}, - [672] = {216, 1, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN1_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"}, - [673] = {216, 2, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN0_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"}, - [674] = {73, 0, "DEV_PBIST0_BUS_CLK1_CLK", "Input clock"}, - [675] = {73, 1, "DEV_PBIST0_BUS_CLK4_CLK", "Input clock"}, - [676] = {73, 2, "DEV_PBIST0_BUS_CLK2_CLK", "Input clock"}, - [677] = {74, 0, "DEV_PBIST1_BUS_CLK1_CLK", "Input clock"}, - [678] = {74, 1, "DEV_PBIST1_BUS_CLK4_CLK", "Input clock"}, - [679] = {74, 2, "DEV_PBIST1_BUS_CLK2_CLK", "Input clock"}, - [680] = {120, 0, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1", "Input clock"}, - [681] = {120, 1, "DEV_PCIE0_BUS_PCIE_CBA_CLK", "Input clock"}, - [682] = {120, 2, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK", "Input clock"}, - [683] = {120, 3, "DEV_PCIE0_BUS_PCIE_TXI0_CLK", "Input clock"}, - [684] = {120, 4, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"}, - [685] = {120, 5, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"}, - [686] = {120, 6, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0", "Input clock"}, - [687] = {120, 7, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK", "Input clock"}, - [688] = {120, 8, "DEV_PCIE0_BUS_PCIE_TXR1_CLK", "Output clock"}, - [689] = {120, 9, "DEV_PCIE0_BUS_PCIE_TXR0_CLK", "Output clock"}, - [690] = {121, 0, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1", "Input clock"}, - [691] = {121, 1, "DEV_PCIE1_BUS_PCIE_CBA_CLK", "Input clock"}, - [692] = {121, 2, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK", "Input clock"}, - [693] = {121, 3, "DEV_PCIE1_BUS_PCIE_TXI0_CLK", "Input clock"}, - [694] = {121, 4, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"}, - [695] = {121, 5, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"}, - [696] = {121, 6, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0", "Input clock"}, - [697] = {121, 7, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK", "Input clock"}, - [698] = {121, 8, "DEV_PCIE1_BUS_PCIE_TXR0_CLK", "Output clock"}, - [699] = {123, 0, "DEV_PDMA0_BUS_VCLK", "Input clock"}, - [700] = {124, 0, "DEV_PDMA1_BUS_VCLK", "Input clock"}, - [701] = {122, 0, "DEV_PDMA_DEBUG0_BUS_VCLK", "Input clock"}, - [702] = {76, 0, "DEV_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK", "Input clock"}, - [703] = {76, 1, "DEV_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"}, - [704] = {76, 2, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input muxed clock"}, - [705] = {76, 3, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"}, - [706] = {76, 4, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"}, - [707] = {101, 0, "DEV_PLL_MMR0_BUS_VBUSP_CLK", "Input clock"}, - [708] = {62, 0, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_5_CLK", "Input clock"}, - [709] = {62, 1, "DEV_PRU_ICSSG0_BUS_WIZ1_TX_SLV_CLK", "Input clock"}, - [710] = {62, 2, "DEV_PRU_ICSSG0_BUS_WIZ0_RX_SLV_CLK", "Input clock"}, - [711] = {62, 3, "DEV_PRU_ICSSG0_BUS_VCLK_CLK", "Input clock"}, - [712] = {62, 4, "DEV_PRU_ICSSG0_BUS_UCLK_CLK", "Input clock"}, - [713] = {62, 5, "DEV_PRU_ICSSG0_BUS_WIZ0_TX_SLV_CLK", "Input clock"}, - [714] = {62, 6, "DEV_PRU_ICSSG0_BUS_WIZ1_RX_SLV_CLK", "Input clock"}, - [715] = {62, 7, "DEV_PRU_ICSSG0_BUS_PR1_RGMII1_RXC_I", "Input clock"}, - [716] = {62, 8, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_250_CLK", "Input clock"}, - [717] = {62, 9, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_50_CLK", "Input clock"}, - [718] = {62, 10, "DEV_PRU_ICSSG0_BUS_IEP_CLK", "Input muxed clock"}, - [719] = {62, 11, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, - [720] = {62, 12, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, - [721] = {62, 13, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, - [722] = {62, 14, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, - [723] = {62, 15, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, - [724] = {62, 16, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, - [725] = {62, 17, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, - [726] = {62, 18, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, - [727] = {62, 19, "DEV_PRU_ICSSG0_BUS_CORE_CLK", "Input muxed clock"}, - [728] = {62, 20, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"}, - [729] = {62, 21, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"}, - [730] = {62, 22, "DEV_PRU_ICSSG0_BUS_PR1_RGMII0_RXC_I", "Input clock"}, - [731] = {62, 23, "DEV_PRU_ICSSG0_BUS_PR1_RGMII1_TXC_I", "Output clock"}, - [732] = {62, 24, "DEV_PRU_ICSSG0_BUS_PR1_RGMII0_TXC_I", "Output clock"}, - [733] = {63, 0, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_5_CLK", "Input clock"}, - [734] = {63, 1, "DEV_PRU_ICSSG1_BUS_WIZ1_TX_SLV_CLK", "Input clock"}, - [735] = {63, 2, "DEV_PRU_ICSSG1_BUS_WIZ0_RX_SLV_CLK", "Input clock"}, - [736] = {63, 3, "DEV_PRU_ICSSG1_BUS_VCLK_CLK", "Input clock"}, - [737] = {63, 4, "DEV_PRU_ICSSG1_BUS_UCLK_CLK", "Input clock"}, - [738] = {63, 5, "DEV_PRU_ICSSG1_BUS_WIZ0_TX_SLV_CLK", "Input clock"}, - [739] = {63, 6, "DEV_PRU_ICSSG1_BUS_WIZ1_RX_SLV_CLK", "Input clock"}, - [740] = {63, 7, "DEV_PRU_ICSSG1_BUS_PR1_RGMII1_RXC_I", "Input clock"}, - [741] = {63, 8, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_250_CLK", "Input clock"}, - [742] = {63, 9, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_50_CLK", "Input clock"}, - [743] = {63, 10, "DEV_PRU_ICSSG1_BUS_IEP_CLK", "Input muxed clock"}, - [744] = {63, 11, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, - [745] = {63, 12, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, - [746] = {63, 13, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, - [747] = {63, 14, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, - [748] = {63, 15, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, - [749] = {63, 16, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, - [750] = {63, 17, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, - [751] = {63, 18, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, - [752] = {63, 19, "DEV_PRU_ICSSG1_BUS_CORE_CLK", "Input muxed clock"}, - [753] = {63, 20, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"}, - [754] = {63, 21, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"}, - [755] = {63, 22, "DEV_PRU_ICSSG1_BUS_PR1_RGMII0_RXC_I", "Input clock"}, - [756] = {63, 23, "DEV_PRU_ICSSG1_BUS_PR1_RGMII1_TXC_I", "Output clock"}, - [757] = {63, 24, "DEV_PRU_ICSSG1_BUS_PR1_RGMII0_TXC_I", "Output clock"}, - [758] = {64, 0, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_5_CLK", "Input clock"}, - [759] = {64, 1, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_SLV_CLK", "Input clock"}, - [760] = {64, 2, "DEV_PRU_ICSSG2_BUS_WIZ0_RX_SLV_CLK", "Input clock"}, - [761] = {64, 3, "DEV_PRU_ICSSG2_BUS_VCLK_CLK", "Input clock"}, - [762] = {64, 4, "DEV_PRU_ICSSG2_BUS_UCLK_CLK", "Input clock"}, - [763] = {64, 5, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_SLV_CLK", "Input clock"}, - [764] = {64, 6, "DEV_PRU_ICSSG2_BUS_WIZ1_RX_SLV_CLK", "Input clock"}, - [765] = {64, 7, "DEV_PRU_ICSSG2_BUS_PR1_RGMII1_RXC_I", "Input clock"}, - [766] = {64, 8, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_250_CLK", "Input clock"}, - [767] = {64, 9, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_50_CLK", "Input clock"}, - [768] = {64, 10, "DEV_PRU_ICSSG2_BUS_IEP_CLK", "Input muxed clock"}, - [769] = {64, 11, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, - [770] = {64, 12, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, - [771] = {64, 13, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, - [772] = {64, 14, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, - [773] = {64, 15, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, - [774] = {64, 16, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, - [775] = {64, 17, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, - [776] = {64, 18, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, - [777] = {64, 19, "DEV_PRU_ICSSG2_BUS_CORE_CLK", "Input muxed clock"}, - [778] = {64, 20, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"}, - [779] = {64, 21, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"}, - [780] = {64, 22, "DEV_PRU_ICSSG2_BUS_PR1_RGMII0_RXC_I", "Input clock"}, - [781] = {64, 23, "DEV_PRU_ICSSG2_BUS_PR1_RGMII1_TXC_I", "Output clock"}, - [782] = {64, 24, "DEV_PRU_ICSSG2_BUS_PR1_RGMII0_TXC_I", "Output clock"}, - [783] = {64, 25, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_MST_CLK", "Output clock"}, - [784] = {64, 26, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_MST_CLK", "Output clock"}, - [785] = {70, 0, "DEV_PSC0_BUS_CLK", "Input clock"}, - [786] = {70, 1, "DEV_PSC0_BUS_SLOW_CLK", "Input clock"}, - [787] = {128, 0, "DEV_PSRAMECC0_BUS_CLK_CLK", "Input clock"}, - [788] = {130, 0, "DEV_RTI0_BUS_RTI_CLK", "Input muxed clock"}, - [789] = {130, 1, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, - [790] = {130, 2, "DEV_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, - [791] = {130, 3, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, - [792] = {130, 4, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, - [793] = {130, 5, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, - [794] = {130, 6, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, - [795] = {130, 7, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, - [796] = {130, 8, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP2", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, - [797] = {130, 9, "DEV_RTI0_BUS_VBUSP_CLK", "Input clock"}, - [798] = {131, 0, "DEV_RTI1_BUS_RTI_CLK", "Input muxed clock"}, - [799] = {131, 1, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, - [800] = {131, 2, "DEV_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, - [801] = {131, 3, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, - [802] = {131, 4, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, - [803] = {131, 5, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, - [804] = {131, 6, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, - [805] = {131, 7, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, - [806] = {131, 8, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP2", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, - [807] = {131, 9, "DEV_RTI1_BUS_VBUSP_CLK", "Input clock"}, - [808] = {132, 0, "DEV_RTI2_BUS_RTI_CLK", "Input muxed clock"}, - [809] = {132, 1, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, - [810] = {132, 2, "DEV_RTI2_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, - [811] = {132, 3, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, - [812] = {132, 4, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, - [813] = {132, 5, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, - [814] = {132, 6, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, - [815] = {132, 7, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, - [816] = {132, 8, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP2", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, - [817] = {132, 9, "DEV_RTI2_BUS_VBUSP_CLK", "Input clock"}, - [818] = {133, 0, "DEV_RTI3_BUS_RTI_CLK", "Input muxed clock"}, - [819] = {133, 1, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, - [820] = {133, 2, "DEV_RTI3_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, - [821] = {133, 3, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, - [822] = {133, 4, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, - [823] = {133, 5, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, - [824] = {133, 6, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, - [825] = {133, 7, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, - [826] = {133, 8, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP2", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, - [827] = {133, 9, "DEV_RTI3_BUS_VBUSP_CLK", "Input clock"}, - [828] = {136, 0, "DEV_SA2_UL0_BUS_PKA_IN_CLK", "Input clock"}, - [829] = {136, 1, "DEV_SA2_UL0_BUS_X1_CLK", "Input clock"}, - [830] = {136, 2, "DEV_SA2_UL0_BUS_X2_CLK", "Input clock"}, - [831] = {153, 0, "DEV_SERDES0_BUS_IP3_LN0_TXRCLK", "Input clock"}, - [832] = {153, 1, "DEV_SERDES0_BUS_REFCLKPP", "Input clock"}, - [833] = {153, 2, "DEV_SERDES0_BUS_CLK", "Input clock"}, - [834] = {153, 3, "DEV_SERDES0_BUS_IP2_LN0_TXRCLK", "Input clock"}, - [835] = {153, 4, "DEV_SERDES0_BUS_LI_REFCLK", "Input muxed clock"}, - [836] = {153, 5, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"}, - [837] = {153, 6, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"}, - [838] = {153, 7, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"}, - [839] = {153, 8, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"}, - [840] = {153, 9, "DEV_SERDES0_BUS_REFCLKPN", "Input clock"}, - [841] = {153, 10, "DEV_SERDES0_BUS_LN0_TXCLK", "Output clock"}, - [842] = {153, 11, "DEV_SERDES0_BUS_LN0_RXCLK", "Output clock"}, - [843] = {154, 0, "DEV_SERDES1_BUS_IP3_LN0_TXRCLK", "Input clock"}, - [844] = {154, 1, "DEV_SERDES1_BUS_REFCLKPP", "Input clock"}, - [845] = {154, 2, "DEV_SERDES1_BUS_CLK", "Input clock"}, - [846] = {154, 3, "DEV_SERDES1_BUS_IP1_LN0_TXRCLK", "Input clock"}, - [847] = {154, 4, "DEV_SERDES1_BUS_IP2_LN0_TXRCLK", "Input clock"}, - [848] = {154, 5, "DEV_SERDES1_BUS_RI_REFCLK", "Input muxed clock"}, - [849] = {154, 6, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"}, - [850] = {154, 7, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"}, - [851] = {154, 8, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"}, - [852] = {154, 9, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"}, - [853] = {154, 10, "DEV_SERDES1_BUS_REFCLKPN", "Input clock"}, - [854] = {154, 11, "DEV_SERDES1_BUS_LN0_TXCLK", "Output clock"}, - [855] = {154, 12, "DEV_SERDES1_BUS_LN0_RXCLK", "Output clock"}, - [856] = {8, 0, "DEV_STM0_BUS_CORE_CLK", "Input clock"}, - [857] = {8, 1, "DEV_STM0_BUS_ATB_CLK", "Input clock"}, - [858] = {8, 2, "DEV_STM0_BUS_VBUSP_CLK", "Input clock"}, - [859] = {23, 0, "DEV_TIMER0_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, - [860] = {23, 1, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, - [861] = {23, 2, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, - [862] = {23, 3, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, - [863] = {23, 4, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, - [864] = {23, 5, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, - [865] = {23, 6, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, - [866] = {23, 7, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, - [867] = {23, 8, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, - [868] = {23, 9, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, - [869] = {23, 10, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, - [870] = {23, 11, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, - [871] = {23, 12, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, - [872] = {23, 13, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, - [873] = {23, 14, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, - [874] = {23, 15, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, - [875] = {23, 16, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, - [876] = {23, 17, "DEV_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"}, - [877] = {24, 0, "DEV_TIMER1_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, - [878] = {24, 1, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, - [879] = {24, 2, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, - [880] = {24, 3, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, - [881] = {24, 4, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, - [882] = {24, 5, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, - [883] = {24, 6, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, - [884] = {24, 7, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, - [885] = {24, 8, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, - [886] = {24, 9, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, - [887] = {24, 10, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, - [888] = {24, 11, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, - [889] = {24, 12, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, - [890] = {24, 13, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, - [891] = {24, 14, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, - [892] = {24, 15, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, - [893] = {24, 16, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, - [894] = {24, 17, "DEV_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"}, - [895] = {25, 0, "DEV_TIMER10_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, - [896] = {25, 1, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, - [897] = {25, 2, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, - [898] = {25, 3, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, - [899] = {25, 4, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, - [900] = {25, 5, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, - [901] = {25, 6, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, - [902] = {25, 7, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, - [903] = {25, 8, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, - [904] = {25, 9, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, - [905] = {25, 10, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, - [906] = {25, 11, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, - [907] = {25, 12, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, - [908] = {25, 13, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, - [909] = {25, 14, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, - [910] = {25, 15, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, - [911] = {25, 16, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, - [912] = {25, 17, "DEV_TIMER10_BUS_TIMER_HCLK_CLK", "Input clock"}, - [913] = {26, 0, "DEV_TIMER11_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, - [914] = {26, 1, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, - [915] = {26, 2, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, - [916] = {26, 3, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, - [917] = {26, 4, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, - [918] = {26, 5, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, - [919] = {26, 6, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, - [920] = {26, 7, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, - [921] = {26, 8, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, - [922] = {26, 9, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, - [923] = {26, 10, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, - [924] = {26, 11, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, - [925] = {26, 12, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, - [926] = {26, 13, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, - [927] = {26, 14, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, - [928] = {26, 15, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, - [929] = {26, 16, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, - [930] = {26, 17, "DEV_TIMER11_BUS_TIMER_HCLK_CLK", "Input clock"}, - [931] = {27, 0, "DEV_TIMER2_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, - [932] = {27, 1, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, - [933] = {27, 2, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, - [934] = {27, 3, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, - [935] = {27, 4, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, - [936] = {27, 5, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, - [937] = {27, 6, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, - [938] = {27, 7, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, - [939] = {27, 8, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, - [940] = {27, 9, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, - [941] = {27, 10, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, - [942] = {27, 11, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, - [943] = {27, 12, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, - [944] = {27, 13, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, - [945] = {27, 14, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, - [946] = {27, 15, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, - [947] = {27, 16, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, - [948] = {27, 17, "DEV_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"}, - [949] = {28, 0, "DEV_TIMER3_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, - [950] = {28, 1, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, - [951] = {28, 2, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, - [952] = {28, 3, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, - [953] = {28, 4, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, - [954] = {28, 5, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, - [955] = {28, 6, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, - [956] = {28, 7, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, - [957] = {28, 8, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, - [958] = {28, 9, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, - [959] = {28, 10, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, - [960] = {28, 11, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, - [961] = {28, 12, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, - [962] = {28, 13, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, - [963] = {28, 14, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, - [964] = {28, 15, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, - [965] = {28, 16, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, - [966] = {28, 17, "DEV_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"}, - [967] = {29, 0, "DEV_TIMER4_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, - [968] = {29, 1, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, - [969] = {29, 2, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, - [970] = {29, 3, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, - [971] = {29, 4, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, - [972] = {29, 5, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, - [973] = {29, 6, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, - [974] = {29, 7, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, - [975] = {29, 8, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, - [976] = {29, 9, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, - [977] = {29, 10, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, - [978] = {29, 11, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, - [979] = {29, 12, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, - [980] = {29, 13, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, - [981] = {29, 14, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, - [982] = {29, 15, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, - [983] = {29, 16, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, - [984] = {29, 17, "DEV_TIMER4_BUS_TIMER_HCLK_CLK", "Input clock"}, - [985] = {30, 0, "DEV_TIMER5_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, - [986] = {30, 1, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, - [987] = {30, 2, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, - [988] = {30, 3, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, - [989] = {30, 4, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, - [990] = {30, 5, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, - [991] = {30, 6, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, - [992] = {30, 7, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, - [993] = {30, 8, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, - [994] = {30, 9, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, - [995] = {30, 10, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, - [996] = {30, 11, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, - [997] = {30, 12, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, - [998] = {30, 13, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, - [999] = {30, 14, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, - [1000] = {30, 15, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, - [1001] = {30, 16, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, - [1002] = {30, 17, "DEV_TIMER5_BUS_TIMER_HCLK_CLK", "Input clock"}, - [1003] = {31, 0, "DEV_TIMER6_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, - [1004] = {31, 1, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, - [1005] = {31, 2, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, - [1006] = {31, 3, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, - [1007] = {31, 4, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, - [1008] = {31, 5, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, - [1009] = {31, 6, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, - [1010] = {31, 7, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, - [1011] = {31, 8, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, - [1012] = {31, 9, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, - [1013] = {31, 10, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, - [1014] = {31, 11, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, - [1015] = {31, 12, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, - [1016] = {31, 13, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, - [1017] = {31, 14, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, - [1018] = {31, 15, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, - [1019] = {31, 16, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, - [1020] = {31, 17, "DEV_TIMER6_BUS_TIMER_HCLK_CLK", "Input clock"}, - [1021] = {32, 0, "DEV_TIMER7_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, - [1022] = {32, 1, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, - [1023] = {32, 2, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, - [1024] = {32, 3, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, - [1025] = {32, 4, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, - [1026] = {32, 5, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, - [1027] = {32, 6, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, - [1028] = {32, 7, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, - [1029] = {32, 8, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, - [1030] = {32, 9, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, - [1031] = {32, 10, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, - [1032] = {32, 11, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, - [1033] = {32, 12, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, - [1034] = {32, 13, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, - [1035] = {32, 14, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, - [1036] = {32, 15, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, - [1037] = {32, 16, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, - [1038] = {32, 17, "DEV_TIMER7_BUS_TIMER_HCLK_CLK", "Input clock"}, - [1039] = {33, 0, "DEV_TIMER8_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, - [1040] = {33, 1, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, - [1041] = {33, 2, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, - [1042] = {33, 3, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, - [1043] = {33, 4, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, - [1044] = {33, 5, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, - [1045] = {33, 6, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, - [1046] = {33, 7, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, - [1047] = {33, 8, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, - [1048] = {33, 9, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, - [1049] = {33, 10, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, - [1050] = {33, 11, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, - [1051] = {33, 12, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, - [1052] = {33, 13, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, - [1053] = {33, 14, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, - [1054] = {33, 15, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, - [1055] = {33, 16, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, - [1056] = {33, 17, "DEV_TIMER8_BUS_TIMER_HCLK_CLK", "Input clock"}, - [1057] = {34, 0, "DEV_TIMER9_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, - [1058] = {34, 1, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, - [1059] = {34, 2, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, - [1060] = {34, 3, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, - [1061] = {34, 4, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, - [1062] = {34, 5, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, - [1063] = {34, 6, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, - [1064] = {34, 7, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, - [1065] = {34, 8, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, - [1066] = {34, 9, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, - [1067] = {34, 10, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, - [1068] = {34, 11, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, - [1069] = {34, 12, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, - [1070] = {34, 13, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, - [1071] = {34, 14, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, - [1072] = {34, 15, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, - [1073] = {34, 16, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, - [1074] = {34, 17, "DEV_TIMER9_BUS_TIMER_HCLK_CLK", "Input clock"}, - [1075] = {145, 0, "DEV_TIMESYNC_INTRTR0_BUS_INTR_CLK", "Input clock"}, - [1076] = {146, 0, "DEV_UART0_BUS_FCLK_CLK", "Input clock"}, - [1077] = {146, 1, "DEV_UART0_BUS_VBUSP_CLK", "Input clock"}, - [1078] = {147, 0, "DEV_UART1_BUS_FCLK_CLK", "Input clock"}, - [1079] = {147, 1, "DEV_UART1_BUS_VBUSP_CLK", "Input clock"}, - [1080] = {148, 0, "DEV_UART2_BUS_FCLK_CLK", "Input clock"}, - [1081] = {148, 1, "DEV_UART2_BUS_VBUSP_CLK", "Input clock"}, - [1082] = {151, 0, "DEV_USB3SS0_BUS_SUSP_CLK", "Input clock"}, - [1083] = {151, 1, "DEV_USB3SS0_BUS_PHY2_REFCLK960M_CLK", "Input clock"}, - [1084] = {151, 2, "DEV_USB3SS0_BUS_REF_CLK", "Input muxed clock"}, - [1085] = {151, 3, "DEV_USB3SS0_BUS_REF_CLK_PARENT_CLOCKMUX_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"}, - [1086] = {151, 4, "DEV_USB3SS0_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"}, - [1087] = {151, 5, "DEV_USB3SS0_BUS_HSIC_CLK_CLK", "Input clock"}, - [1088] = {151, 6, "DEV_USB3SS0_BUS_BUS_CLK", "Input clock"}, - [1089] = {151, 7, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK", "Input muxed clock"}, - [1090] = {151, 8, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"}, - [1091] = {151, 9, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_CLOCKMUX_USB0_PIPE3_CLK_SEL_DIV_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"}, - [1092] = {151, 10, "DEV_USB3SS0_BUS_UTMI_CLK_CLK", "Input clock"}, - [1093] = {152, 0, "DEV_USB3SS1_BUS_SUSP_CLK", "Input clock"}, - [1094] = {152, 1, "DEV_USB3SS1_BUS_PHY2_REFCLK960M_CLK", "Input clock"}, - [1095] = {152, 2, "DEV_USB3SS1_BUS_REF_CLK", "Input muxed clock"}, - [1096] = {152, 3, "DEV_USB3SS1_BUS_REF_CLK_PARENT_CLOCKMUX_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"}, - [1097] = {152, 4, "DEV_USB3SS1_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"}, - [1098] = {152, 5, "DEV_USB3SS1_BUS_HSIC_CLK_CLK", "Input clock"}, - [1099] = {152, 6, "DEV_USB3SS1_BUS_BUS_CLK", "Input clock"}, - [1100] = {152, 7, "DEV_USB3SS1_BUS_PIPE3_TXB_CLK", "Input clock"}, - [1101] = {152, 8, "DEV_USB3SS1_BUS_UTMI_CLK_CLK", "Input clock"}, - [1102] = {94, 0, "DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_2_CLK", "Input clock"}, - [1103] = {94, 1, "DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_4_CLK", "Input clock"}, - [1104] = {96, 0, "DEV_WKUP_CBASS_FW0_BUS_WKUP_MCU_PLL_OUT_2_CLK", "Input clock"}, - [1105] = {155, 0, "DEV_WKUP_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"}, - [1106] = {22, 0, "DEV_WKUP_DMSC0_BUS_FUNC_32K_RT_CLK", "Input clock"}, - [1107] = {22, 1, "DEV_WKUP_DMSC0_BUS_FUNC_MOSC_CLK", "Input clock"}, - [1108] = {22, 2, "DEV_WKUP_DMSC0_BUS_VBUS_CLK", "Input clock"}, - [1109] = {22, 3, "DEV_WKUP_DMSC0_BUS_FUNC_32K_RC_CLK", "Input clock"}, - [1110] = {22, 4, "DEV_WKUP_DMSC0_BUS_SEC_EFC_FCLK", "Input clock"}, - [1111] = {22, 5, "DEV_WKUP_DMSC0_BUS_DAP_CLK", "Input clock"}, - [1112] = {22, 6, "DEV_WKUP_DMSC0_BUS_EXT_CLK", "Input clock"}, - [1113] = {95, 0, "DEV_WKUP_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"}, - [1114] = {54, 0, "DEV_WKUP_ESM0_BUS_CLK", "Input clock"}, - [1115] = {59, 0, "DEV_WKUP_GPIO0_BUS_MMR_CLK", "Input muxed clock"}, - [1116] = {59, 1, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"}, - [1117] = {59, 2, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4_DUP0", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"}, - [1118] = {59, 3, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"}, - [1119] = {59, 4, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"}, - [1120] = {156, 0, "DEV_WKUP_GPIOMUX_INTRTR0_BUS_INTR_CLK", "Input clock"}, - [1121] = {115, 0, "DEV_WKUP_I2C0_BUS_CLK", "Input clock"}, - [1122] = {115, 1, "DEV_WKUP_I2C0_BUS_PISYS_CLK", "Input muxed clock"}, - [1123] = {115, 2, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"}, - [1124] = {115, 3, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"}, - [1125] = {115, 4, "DEV_WKUP_I2C0_BUS_PISCL", "Output clock"}, - [1126] = {77, 0, "DEV_WKUP_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK", "Input clock"}, - [1127] = {77, 1, "DEV_WKUP_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"}, - [1128] = {77, 2, "DEV_WKUP_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input clock"}, - [1129] = {79, 0, "DEV_WKUP_PSC0_BUS_CLK", "Input clock"}, - [1130] = {79, 1, "DEV_WKUP_PSC0_BUS_SLOW_CLK", "Input clock"}, - [1131] = {150, 0, "DEV_WKUP_UART0_BUS_FCLK_CLK", "Input muxed clock"}, - [1132] = {150, 1, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_CLOCKMUX_WKUPUSART_CLK_SEL_BUS_OUT0", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"}, - [1133] = {150, 2, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"}, - [1134] = {150, 3, "DEV_WKUP_UART0_BUS_VBUSP_CLK", "Input clock"}, - [1135] = {80, 0, "DEV_WKUP_VTM0_BUS_FIX_REF_CLK", "Input clock"}, - [1136] = {80, 1, "DEV_WKUP_VTM0_BUS_VBUSP_CLK", "Input clock"}, + [0] = {157, 1, "DEV_BOARD0_BUS_SCL2_IN", "Input clock"}, + [1] = {157, 2, "DEV_BOARD0_BUS_SCL1_IN", "Input clock"}, + [2] = {157, 3, "DEV_BOARD0_BUS_SCL0_IN", "Input clock"}, + [3] = {157, 4, "DEV_BOARD0_BUS_PRG2_RGMII2_TCLK_IN", "Input clock"}, + [4] = {157, 5, "DEV_BOARD0_BUS_MCU_OSPI1CLK_IN", "Input clock"}, + [5] = {157, 6, "DEV_BOARD0_BUS_PRG1_RGMII1_TCLK_IN", "Input clock"}, + [6] = {157, 7, "DEV_BOARD0_BUS_REFCLK1P_IN", "Input muxed clock"}, + [7] = {157, 8, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"}, + [8] = {157, 9, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"}, + [9] = {157, 10, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"}, + [10] = {157, 11, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"}, + [11] = {157, 12, "DEV_BOARD0_BUS_MCU_OSPI1LBCLKO_IN", "Input clock"}, + [12] = {157, 13, "DEV_BOARD0_BUS_MCU_OBSCLK_IN", "Input clock"}, + [13] = {157, 14, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, + [14] = {157, 15, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, + [15] = {157, 16, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, + [16] = {157, 17, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, + [17] = {157, 18, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, + [18] = {157, 19, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, + [19] = {157, 20, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, + [20] = {157, 21, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, + [21] = {157, 22, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, + [22] = {157, 23, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, + [23] = {157, 24, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, + [24] = {157, 25, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, + [25] = {157, 26, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, + [26] = {157, 27, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, + [27] = {157, 28, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, + [28] = {157, 29, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, + [29] = {157, 30, "DEV_BOARD0_BUS_PRG2_RGMII1_TCLK_IN", "Input clock"}, + [30] = {157, 31, "DEV_BOARD0_BUS_REFCLK1M_IN", "Input muxed clock"}, + [31] = {157, 32, "DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M_IN"}, + [32] = {157, 33, "DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M_IN"}, + [33] = {157, 34, "DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M_IN"}, + [34] = {157, 35, "DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M_IN"}, + [35] = {157, 36, "DEV_BOARD0_BUS_OBSCLK_IN", "Input clock"}, + [36] = {157, 37, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, + [37] = {157, 38, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, + [38] = {157, 39, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, + [39] = {157, 40, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, + [40] = {157, 41, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, + [41] = {157, 42, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, + [42] = {157, 43, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_4_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, + [43] = {157, 44, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_6_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, + [44] = {157, 45, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, + [45] = {157, 46, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, + [46] = {157, 47, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, + [47] = {157, 48, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_7_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, + [48] = {157, 49, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, + [49] = {157, 50, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, + [50] = {157, 51, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, + [51] = {157, 52, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, + [52] = {157, 53, "DEV_BOARD0_BUS_PRG0_RGMII1_TCLK_IN", "Input clock"}, + [53] = {157, 54, "DEV_BOARD0_BUS_MCU_OSPI0CLK_IN", "Input clock"}, + [54] = {157, 55, "DEV_BOARD0_BUS_DSS0PCLK_IN", "Input clock"}, + [55] = {157, 56, "DEV_BOARD0_BUS_PRG0_RGMII2_TCLK_IN", "Input clock"}, + [56] = {157, 57, "DEV_BOARD0_BUS_WKUP_SCL0_IN", "Input clock"}, + [57] = {157, 58, "DEV_BOARD0_BUS_REFCLK0P_IN", "Input muxed clock"}, + [58] = {157, 59, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"}, + [59] = {157, 60, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"}, + [60] = {157, 61, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"}, + [61] = {157, 62, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"}, + [62] = {157, 63, "DEV_BOARD0_BUS_REFCLK0M_IN", "Input muxed clock"}, + [63] = {157, 64, "DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M_IN"}, + [64] = {157, 65, "DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M_IN"}, + [65] = {157, 66, "DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M_IN"}, + [66] = {157, 67, "DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M_IN"}, + [67] = {157, 68, "DEV_BOARD0_BUS_MCU_OSPI0LBCLKO_IN", "Input clock"}, + [68] = {157, 69, "DEV_BOARD0_BUS_MCU_CLKOUT_IN", "Input muxed clock"}, + [69] = {157, 70, "DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN"}, + [70] = {157, 71, "DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK10", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN"}, + [71] = {157, 72, "DEV_BOARD0_BUS_MCU_SCL0_IN", "Input clock"}, + [72] = {157, 73, "DEV_BOARD0_BUS_SYSCLKOUT_IN", "Input clock"}, + [73] = {157, 74, "DEV_BOARD0_BUS_MCU_SYSCLKOUT_IN", "Input clock"}, + [74] = {157, 75, "DEV_BOARD0_BUS_PRG1_RGMII1_RCLK_OUT", "Output clock"}, + [75] = {157, 76, "DEV_BOARD0_BUS_PRG1_RGMII2_RCLK_OUT", "Output clock"}, + [76] = {157, 77, "DEV_BOARD0_BUS_GPMCCLK_OUT", "Output clock"}, + [77] = {157, 78, "DEV_BOARD0_BUS_MCASP2AHCLKX_OUT", "Output clock"}, + [78] = {157, 79, "DEV_BOARD0_BUS_MCASP2AHCLKR_OUT", "Output clock"}, + [79] = {157, 80, "DEV_BOARD0_BUS_PRG2_RGMII2_RCLK_OUT", "Output clock"}, + [80] = {157, 81, "DEV_BOARD0_BUS_CPTS_RFT_CLK_OUT", "Output clock"}, + [81] = {157, 82, "DEV_BOARD0_BUS_MCASP0ACLKR_OUT", "Output clock"}, + [82] = {157, 83, "DEV_BOARD0_BUS_MCASP0ACLKX_OUT", "Output clock"}, + [83] = {157, 84, "DEV_BOARD0_BUS_EXT_REFCLK1_OUT", "Output clock"}, + [84] = {157, 85, "DEV_BOARD0_BUS_PRG0_RGMII2_RCLK_OUT", "Output clock"}, + [85] = {157, 86, "DEV_BOARD0_BUS_MCU_OSPI0DQS_OUT", "Output clock"}, + [86] = {157, 87, "DEV_BOARD0_BUS_USB0REFCLKP_OUT", "Output clock"}, + [87] = {157, 88, "DEV_BOARD0_BUS_DSS0EXTPCLKIN_OUT", "Output clock"}, + [88] = {157, 89, "DEV_BOARD0_BUS_SPI1CLK_OUT", "Output clock"}, + [89] = {157, 90, "DEV_BOARD0_BUS_MCASP2ACLKR_OUT", "Output clock"}, + [90] = {157, 91, "DEV_BOARD0_BUS_MCASP1ACLKX_OUT", "Output clock"}, + [91] = {157, 92, "DEV_BOARD0_BUS_MCASP1ACLKR_OUT", "Output clock"}, + [92] = {157, 93, "DEV_BOARD0_BUS_MCASP2ACLKX_OUT", "Output clock"}, + [93] = {157, 94, "DEV_BOARD0_BUS_MCU_RMII1_REFCLK_OUT", "Output clock"}, + [94] = {157, 95, "DEV_BOARD0_BUS_MCU_CPTS_RFT_CLK_OUT", "Output clock"}, + [95] = {157, 96, "DEV_BOARD0_BUS_MCU_RGMII1_TCLK_OUT", "Output clock"}, + [96] = {157, 97, "DEV_BOARD0_BUS_MCU_SPI0CLK_OUT", "Output clock"}, + [97] = {157, 98, "DEV_BOARD0_BUS_MCU_SPI1CLK_OUT", "Output clock"}, + [98] = {157, 99, "DEV_BOARD0_BUS_PRG0_RGMII1_RCLK_OUT", "Output clock"}, + [99] = {157, 100, "DEV_BOARD0_BUS_SPI2CLK_OUT", "Output clock"}, + [100] = {157, 101, "DEV_BOARD0_BUS_WKUP_TCK_OUT", "Output clock"}, + [101] = {157, 102, "DEV_BOARD0_BUS_SPI3CLK_OUT", "Output clock"}, + [102] = {157, 103, "DEV_BOARD0_BUS_USB0REFCLKM_OUT", "Output clock"}, + [103] = {157, 104, "DEV_BOARD0_BUS_MCU_RGMII1_RCLK_OUT", "Output clock"}, + [104] = {157, 105, "DEV_BOARD0_BUS_MCASP0AHCLKR_OUT", "Output clock"}, + [105] = {157, 106, "DEV_BOARD0_BUS_MCU_EXT_REFCLK0_OUT", "Output clock"}, + [106] = {157, 107, "DEV_BOARD0_BUS_MCASP0AHCLKX_OUT", "Output clock"}, + [107] = {157, 108, "DEV_BOARD0_BUS_CCDC0_PCLK_OUT", "Output clock"}, + [108] = {157, 109, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"}, + [109] = {157, 110, "DEV_BOARD0_BUS_MCU_OSPI1DQS_OUT", "Output clock"}, + [110] = {157, 111, "DEV_BOARD0_BUS_MCASP1AHCLKX_OUT", "Output clock"}, + [111] = {157, 112, "DEV_BOARD0_BUS_PCIE1REFCLKM_OUT", "Output clock"}, + [112] = {157, 113, "DEV_BOARD0_BUS_MCASP1AHCLKR_OUT", "Output clock"}, + [113] = {157, 114, "DEV_BOARD0_BUS_PCIE1REFCLKP_OUT", "Output clock"}, + [114] = {157, 115, "DEV_BOARD0_BUS_PRG2_RGMII1_RCLK_OUT", "Output clock"}, + [115] = {157, 116, "DEV_BOARD0_BUS_SPI0CLK_OUT", "Output clock"}, + [116] = {157, 117, "DEV_BOARD0_BUS_MCU_HYPERBUS_CLK_IN", "Input clock"}, + [117] = {157, 118, "DEV_BOARD0_BUS_MCU_HYPERBUS_NCLK_IN", "Input clock"}, + [118] = {2, 1, "DEV_CAL0_BUS_CP_C_CLK", "Input clock"}, + [119] = {82, 1, "DEV_CBASS0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"}, + [120] = {83, 1, "DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"}, + [121] = {84, 1, "DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"}, + [122] = {85, 1, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, + [123] = {85, 2, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, + [124] = {85, 3, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, + [125] = {85, 4, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, + [126] = {85, 5, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, + [127] = {85, 6, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, + [128] = {85, 7, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, + [129] = {85, 8, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, + [130] = {85, 9, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"}, + [131] = {85, 10, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"}, + [132] = {66, 1, "DEV_CCDEBUGSS0_BUS_ATB0_CLK", "Input clock"}, + [133] = {66, 2, "DEV_CCDEBUGSS0_BUS_SYS_CLK", "Input clock"}, + [134] = {66, 3, "DEV_CCDEBUGSS0_BUS_DBG_CLK", "Input clock"}, + [135] = {66, 4, "DEV_CCDEBUGSS0_BUS_CFG_CLK", "Input clock"}, + [136] = {196, 1, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_DBG_CLK", "Input clock"}, + [137] = {196, 2, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_MSMC_CLK", "Input clock"}, + [138] = {196, 3, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_CFG_CLK", "Input clock"}, + [139] = {196, 4, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_GIC_CLK", "Input clock"}, + [140] = {213, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_PROBE_CLK", "Input clock"}, + [141] = {214, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_PROBE_CLK", "Input clock"}, + [142] = {211, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_PROBE_CLK", "Input clock"}, + [143] = {212, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_PROBE_CLK", "Input clock"}, + [144] = {209, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_PROBE_CLK", "Input clock"}, + [145] = {206, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_PROBE_CLK", "Input clock"}, + [146] = {208, 1, "DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_PROBE_CLK", "Input clock"}, + [147] = {215, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_PROBE_CLK", "Input clock"}, + [148] = {207, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_PROBE_CLK", "Input clock"}, + [149] = {210, 1, "DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_PROBE_CLK", "Input clock"}, + [150] = {9, 1, "DEV_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"}, + [151] = {9, 2, "DEV_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"}, + [152] = {9, 3, "DEV_DCC0_BUS_VBUS_CLK", "Input clock"}, + [153] = {9, 4, "DEV_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"}, + [154] = {9, 5, "DEV_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"}, + [155] = {9, 6, "DEV_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"}, + [156] = {9, 7, "DEV_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"}, + [157] = {9, 8, "DEV_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"}, + [158] = {9, 9, "DEV_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"}, + [159] = {9, 10, "DEV_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"}, + [160] = {9, 11, "DEV_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"}, + [161] = {10, 1, "DEV_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"}, + [162] = {10, 2, "DEV_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"}, + [163] = {10, 3, "DEV_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"}, + [164] = {10, 4, "DEV_DCC1_BUS_VBUS_CLK", "Input clock"}, + [165] = {10, 5, "DEV_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"}, + [166] = {10, 6, "DEV_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"}, + [167] = {10, 7, "DEV_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"}, + [168] = {10, 8, "DEV_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"}, + [169] = {10, 9, "DEV_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"}, + [170] = {10, 10, "DEV_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"}, + [171] = {10, 11, "DEV_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"}, + [172] = {10, 12, "DEV_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"}, + [173] = {11, 1, "DEV_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"}, + [174] = {11, 2, "DEV_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"}, + [175] = {11, 3, "DEV_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"}, + [176] = {11, 4, "DEV_DCC2_BUS_VBUS_CLK", "Input clock"}, + [177] = {11, 5, "DEV_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"}, + [178] = {11, 6, "DEV_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"}, + [179] = {11, 7, "DEV_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"}, + [180] = {11, 8, "DEV_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"}, + [181] = {11, 9, "DEV_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"}, + [182] = {11, 10, "DEV_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"}, + [183] = {11, 11, "DEV_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"}, + [184] = {11, 12, "DEV_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"}, + [185] = {12, 1, "DEV_DCC3_BUS_DCC_CLKSRC7_CLK", "Input clock"}, + [186] = {12, 2, "DEV_DCC3_BUS_DCC_CLKSRC4_CLK", "Input clock"}, + [187] = {12, 3, "DEV_DCC3_BUS_DCC_CLKSRC3_CLK", "Input clock"}, + [188] = {12, 4, "DEV_DCC3_BUS_VBUS_CLK", "Input clock"}, + [189] = {12, 5, "DEV_DCC3_BUS_DCC_CLKSRC1_CLK", "Input clock"}, + [190] = {12, 6, "DEV_DCC3_BUS_DCC_INPUT01_CLK", "Input clock"}, + [191] = {12, 7, "DEV_DCC3_BUS_DCC_CLKSRC5_CLK", "Input clock"}, + [192] = {12, 8, "DEV_DCC3_BUS_DCC_INPUT02_CLK", "Input clock"}, + [193] = {12, 9, "DEV_DCC3_BUS_DCC_CLKSRC0_CLK", "Input clock"}, + [194] = {12, 10, "DEV_DCC3_BUS_DCC_INPUT10_CLK", "Input clock"}, + [195] = {12, 11, "DEV_DCC3_BUS_DCC_CLKSRC2_CLK", "Input clock"}, + [196] = {13, 1, "DEV_DCC4_BUS_DCC_CLKSRC7_CLK", "Input clock"}, + [197] = {13, 2, "DEV_DCC4_BUS_DCC_CLKSRC4_CLK", "Input clock"}, + [198] = {13, 3, "DEV_DCC4_BUS_DCC_CLKSRC3_CLK", "Input clock"}, + [199] = {13, 4, "DEV_DCC4_BUS_VBUS_CLK", "Input clock"}, + [200] = {13, 5, "DEV_DCC4_BUS_DCC_INPUT01_CLK", "Input clock"}, + [201] = {13, 6, "DEV_DCC4_BUS_DCC_CLKSRC5_CLK", "Input clock"}, + [202] = {13, 7, "DEV_DCC4_BUS_DCC_INPUT02_CLK", "Input clock"}, + [203] = {13, 8, "DEV_DCC4_BUS_DCC_CLKSRC0_CLK", "Input clock"}, + [204] = {13, 9, "DEV_DCC4_BUS_DCC_CLKSRC6_CLK", "Input clock"}, + [205] = {13, 10, "DEV_DCC4_BUS_DCC_INPUT10_CLK", "Input clock"}, + [206] = {13, 11, "DEV_DCC4_BUS_DCC_CLKSRC2_CLK", "Input clock"}, + [207] = {14, 1, "DEV_DCC5_BUS_DCC_CLKSRC7_CLK", "Input clock"}, + [208] = {14, 2, "DEV_DCC5_BUS_DCC_CLKSRC4_CLK", "Input clock"}, + [209] = {14, 3, "DEV_DCC5_BUS_DCC_CLKSRC3_CLK", "Input clock"}, + [210] = {14, 4, "DEV_DCC5_BUS_VBUS_CLK", "Input clock"}, + [211] = {14, 5, "DEV_DCC5_BUS_DCC_CLKSRC1_CLK", "Input clock"}, + [212] = {14, 6, "DEV_DCC5_BUS_DCC_INPUT01_CLK", "Input clock"}, + [213] = {14, 7, "DEV_DCC5_BUS_DCC_CLKSRC5_CLK", "Input clock"}, + [214] = {14, 8, "DEV_DCC5_BUS_DCC_INPUT02_CLK", "Input clock"}, + [215] = {14, 9, "DEV_DCC5_BUS_DCC_CLKSRC0_CLK", "Input clock"}, + [216] = {14, 10, "DEV_DCC5_BUS_DCC_CLKSRC6_CLK", "Input clock"}, + [217] = {14, 11, "DEV_DCC5_BUS_DCC_INPUT10_CLK", "Input clock"}, + [218] = {14, 12, "DEV_DCC5_BUS_DCC_CLKSRC2_CLK", "Input clock"}, + [219] = {15, 1, "DEV_DCC6_BUS_DCC_CLKSRC7_CLK", "Input clock"}, + [220] = {15, 2, "DEV_DCC6_BUS_DCC_CLKSRC4_CLK", "Input clock"}, + [221] = {15, 3, "DEV_DCC6_BUS_DCC_CLKSRC3_CLK", "Input clock"}, + [222] = {15, 4, "DEV_DCC6_BUS_VBUS_CLK", "Input clock"}, + [223] = {15, 5, "DEV_DCC6_BUS_DCC_CLKSRC1_CLK", "Input clock"}, + [224] = {15, 6, "DEV_DCC6_BUS_DCC_INPUT01_CLK", "Input clock"}, + [225] = {15, 7, "DEV_DCC6_BUS_DCC_CLKSRC5_CLK", "Input clock"}, + [226] = {15, 8, "DEV_DCC6_BUS_DCC_INPUT02_CLK", "Input clock"}, + [227] = {15, 9, "DEV_DCC6_BUS_DCC_CLKSRC0_CLK", "Input clock"}, + [228] = {15, 10, "DEV_DCC6_BUS_DCC_CLKSRC6_CLK", "Input clock"}, + [229] = {15, 11, "DEV_DCC6_BUS_DCC_INPUT10_CLK", "Input clock"}, + [230] = {15, 12, "DEV_DCC6_BUS_DCC_CLKSRC2_CLK", "Input clock"}, + [231] = {16, 1, "DEV_DCC7_BUS_DCC_CLKSRC7_CLK", "Input clock"}, + [232] = {16, 2, "DEV_DCC7_BUS_DCC_CLKSRC4_CLK", "Input clock"}, + [233] = {16, 3, "DEV_DCC7_BUS_DCC_CLKSRC3_CLK", "Input clock"}, + [234] = {16, 4, "DEV_DCC7_BUS_VBUS_CLK", "Input clock"}, + [235] = {16, 5, "DEV_DCC7_BUS_DCC_CLKSRC1_CLK", "Input clock"}, + [236] = {16, 6, "DEV_DCC7_BUS_DCC_INPUT01_CLK", "Input clock"}, + [237] = {16, 7, "DEV_DCC7_BUS_DCC_CLKSRC5_CLK", "Input clock"}, + [238] = {16, 8, "DEV_DCC7_BUS_DCC_INPUT02_CLK", "Input clock"}, + [239] = {16, 9, "DEV_DCC7_BUS_DCC_CLKSRC0_CLK", "Input clock"}, + [240] = {16, 10, "DEV_DCC7_BUS_DCC_CLKSRC6_CLK", "Input clock"}, + [241] = {16, 11, "DEV_DCC7_BUS_DCC_INPUT10_CLK", "Input clock"}, + [242] = {16, 12, "DEV_DCC7_BUS_DCC_CLKSRC2_CLK", "Input clock"}, + [243] = {20, 1, "DEV_DDRSS0_BUS_DDRSS_BYP_4X_CLK", "Input clock"}, + [244] = {20, 2, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, + [245] = {20, 3, "DEV_DDRSS0_BUS_DDRSS_TCLK", "Input clock"}, + [246] = {20, 4, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, + [247] = {20, 5, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, + [248] = {20, 6, "DEV_DDRSS0_BUS_DDRSS_CFG_CLK", "Input clock"}, + [249] = {20, 7, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, + [250] = {20, 8, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, + [251] = {20, 9, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, + [252] = {68, 1, "DEV_DEBUGSS0_BUS_ATB5_CLK", "Input clock"}, + [253] = {68, 2, "DEV_DEBUGSS0_BUS_ATB0_CLK", "Input clock"}, + [254] = {68, 3, "DEV_DEBUGSS0_BUS_SYS_CLK", "Input clock"}, + [255] = {68, 4, "DEV_DEBUGSS0_BUS_ATB4_CLK", "Input clock"}, + [256] = {68, 5, "DEV_DEBUGSS0_BUS_CFG_CLK", "Input clock"}, + [257] = {68, 6, "DEV_DEBUGSS0_BUS_ATB2_CLK", "Input clock"}, + [258] = {68, 7, "DEV_DEBUGSS0_BUS_DBG_CLK", "Input clock"}, + [259] = {68, 8, "DEV_DEBUGSS0_BUS_ATB3_CLK", "Input clock"}, + [260] = {21, 1, "DEV_DEBUGSS_WRAP0_BUS_ATB_CLK", "Input clock"}, + [261] = {21, 2, "DEV_DEBUGSS_WRAP0_BUS_TREXPT_CLK", "Input clock"}, + [262] = {21, 3, "DEV_DEBUGSS_WRAP0_BUS_CORE_CLK", "Input clock"}, + [263] = {67, 1, "DEV_DSS0_BUS_DSS_FUNC_CLK", "Input clock"}, + [264] = {67, 2, "DEV_DSS0_BUS_DPI_1_IN_CLK", "Input muxed clock"}, + [265] = {67, 3, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_CLOCKDIVIDER_DSS_BUS_OUT07", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"}, + [266] = {67, 4, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_BOARD_0_BUS_DSS0EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"}, + [267] = {67, 5, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_CLOCKDIVIDER_DSS_BUS_OUT1", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"}, + [268] = {67, 6, "DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN0_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"}, + [269] = {67, 7, "DEV_DSS0_BUS_DPI_1_OUT_CLK", "Output clock"}, + [270] = {69, 1, "DEV_EFUSE0_BUS_EFC1_CTL_FCLK", "Output clock"}, + [271] = {69, 2, "DEV_EFUSE0_BUS_EFC0_CTL_FCLK", "Output clock"}, + [272] = {60, 1, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"}, + [273] = {60, 2, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK3", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"}, + [274] = {60, 3, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK2", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"}, + [275] = {60, 4, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"}, + [276] = {60, 5, "DEV_GPMC0_BUS_PI_GPMC_RET_CLK", "Input clock"}, + [277] = {60, 6, "DEV_GPMC0_BUS_VBUSP_CLK", "Input clock"}, + [278] = {60, 7, "DEV_GPMC0_BUS_PO_GPMC_DEV_CLK", "Output clock"}, + [279] = {65, 1, "DEV_GPU0_BUS_HYD_CORE_CLK", "Input clock"}, + [280] = {65, 2, "DEV_GPU0_BUS_SGX_CORE_CLK", "Input clock"}, + [281] = {65, 3, "DEV_GPU0_BUS_SYS_CLK", "Input clock"}, + [282] = {232, 1, "DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_CLK", "Input clock"}, + [283] = {231, 1, "DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_CLK", "Input clock"}, + [284] = {61, 1, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, + [285] = {61, 2, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, + [286] = {61, 3, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, + [287] = {61, 4, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, + [288] = {61, 5, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, + [289] = {61, 6, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, + [290] = {61, 7, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, + [291] = {61, 8, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, + [292] = {110, 1, "DEV_I2C0_BUS_PISYS_CLK", "Input clock"}, + [293] = {110, 2, "DEV_I2C0_BUS_PISCL", "Output clock"}, + [294] = {111, 1, "DEV_I2C1_BUS_PISYS_CLK", "Input clock"}, + [295] = {111, 2, "DEV_I2C1_BUS_PISCL", "Output clock"}, + [296] = {112, 1, "DEV_I2C2_BUS_PISYS_CLK", "Input clock"}, + [297] = {112, 2, "DEV_I2C2_BUS_PISCL", "Output clock"}, + [298] = {113, 1, "DEV_I2C3_BUS_PISYS_CLK", "Input clock"}, + [299] = {113, 2, "DEV_I2C3_BUS_PISCL", "Output clock"}, + [300] = {104, 1, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, + [301] = {104, 2, "DEV_MCASP0_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, + [302] = {104, 3, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, + [303] = {104, 4, "DEV_MCASP0_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, + [304] = {104, 5, "DEV_MCASP0_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, + [305] = {104, 6, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, + [306] = {104, 7, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, + [307] = {104, 8, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, + [308] = {104, 9, "DEV_MCASP0_BUS_VBUSP_CLK", "Input clock"}, + [309] = {104, 10, "DEV_MCASP0_BUS_MCASP_AHCLKX_PIN", "Input clock"}, + [310] = {104, 11, "DEV_MCASP0_BUS_MCASP_AHCLKR_PIN", "Input clock"}, + [311] = {105, 1, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, + [312] = {105, 2, "DEV_MCASP1_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, + [313] = {105, 3, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, + [314] = {105, 4, "DEV_MCASP1_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, + [315] = {105, 5, "DEV_MCASP1_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, + [316] = {105, 6, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, + [317] = {105, 7, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, + [318] = {105, 8, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, + [319] = {105, 9, "DEV_MCASP1_BUS_VBUSP_CLK", "Input clock"}, + [320] = {105, 10, "DEV_MCASP1_BUS_MCASP_AHCLKX_PIN", "Input clock"}, + [321] = {105, 11, "DEV_MCASP1_BUS_MCASP_AHCLKR_PIN", "Input clock"}, + [322] = {106, 1, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, + [323] = {106, 2, "DEV_MCASP2_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, + [324] = {106, 3, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, + [325] = {106, 4, "DEV_MCASP2_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, + [326] = {106, 5, "DEV_MCASP2_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT2", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, + [327] = {106, 6, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, + [328] = {106, 7, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, + [329] = {106, 8, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, + [330] = {106, 9, "DEV_MCASP2_BUS_VBUSP_CLK", "Input clock"}, + [331] = {106, 10, "DEV_MCASP2_BUS_MCASP_AHCLKX_PIN", "Input clock"}, + [332] = {106, 11, "DEV_MCASP2_BUS_MCASP_AHCLKR_PIN", "Input clock"}, + [333] = {137, 1, "DEV_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"}, + [334] = {137, 2, "DEV_MCSPI0_BUS_VBUSP_CLK", "Input clock"}, + [335] = {137, 3, "DEV_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"}, + [336] = {138, 1, "DEV_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"}, + [337] = {138, 2, "DEV_MCSPI1_BUS_VBUSP_CLK", "Input clock"}, + [338] = {138, 3, "DEV_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"}, + [339] = {139, 1, "DEV_MCSPI2_BUS_CLKSPIREF_CLK", "Input clock"}, + [340] = {139, 2, "DEV_MCSPI2_BUS_VBUSP_CLK", "Input clock"}, + [341] = {139, 3, "DEV_MCSPI2_BUS_IO_CLKSPIO_CLK", "Output clock"}, + [342] = {140, 1, "DEV_MCSPI3_BUS_CLKSPIREF_CLK", "Input clock"}, + [343] = {140, 2, "DEV_MCSPI3_BUS_VBUSP_CLK", "Input clock"}, + [344] = {140, 3, "DEV_MCSPI3_BUS_IO_CLKSPIO_CLK", "Output clock"}, + [345] = {141, 1, "DEV_MCSPI4_BUS_VBUSP_CLK", "Input clock"}, + [346] = {0, 1, "DEV_MCU_ADC0_BUS_SYS_CLK", "Input clock"}, + [347] = {0, 2, "DEV_MCU_ADC0_BUS_ADC_CLK", "Input muxed clock"}, + [348] = {0, 3, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"}, + [349] = {0, 4, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"}, + [350] = {0, 5, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"}, + [351] = {0, 6, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"}, + [352] = {1, 1, "DEV_MCU_ADC1_BUS_SYS_CLK", "Input clock"}, + [353] = {1, 2, "DEV_MCU_ADC1_BUS_ADC_CLK", "Input muxed clock"}, + [354] = {1, 3, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"}, + [355] = {1, 4, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"}, + [356] = {1, 5, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"}, + [357] = {1, 6, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"}, + [358] = {159, 1, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE", "Input muxed clock"}, + [359] = {159, 2, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE"}, + [360] = {159, 3, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK", "Input muxed clock"}, + [361] = {159, 4, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"}, + [362] = {159, 5, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"}, + [363] = {245, 1, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE", "Input muxed clock"}, + [364] = {245, 2, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE"}, + [365] = {245, 3, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK", "Input muxed clock"}, + [366] = {245, 4, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"}, + [367] = {245, 5, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"}, + [368] = {89, 1, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_4_CLK", "Input clock"}, + [369] = {89, 2, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"}, + [370] = {91, 1, "DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"}, + [371] = {5, 1, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_250_CLK", "Input clock"}, + [372] = {5, 2, "DEV_MCU_CPSW0_BUS_CPTS_RFT_CLK", "Input clock"}, + [373] = {5, 3, "DEV_MCU_CPSW0_BUS_GMII1_MT_CLK", "Input clock"}, + [374] = {5, 4, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_5_CLK", "Input clock"}, + [375] = {5, 5, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_50_CLK", "Input clock"}, + [376] = {5, 6, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK", "Input muxed clock"}, + [377] = {5, 7, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"}, + [378] = {5, 8, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_BOARD_0_BUS_MCU_RMII1_REFCLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"}, + [379] = {5, 9, "DEV_MCU_CPSW0_BUS_GMII_RFT_CLK", "Input clock"}, + [380] = {5, 10, "DEV_MCU_CPSW0_BUS_CPPI_CLK_CLK", "Input clock"}, + [381] = {5, 11, "DEV_MCU_CPSW0_BUS_CPTS_GENF0_0", "Output clock"}, + [382] = {17, 1, "DEV_MCU_DCC0_BUS_DCC_CLKSRC7_CLK", "Input clock"}, + [383] = {17, 2, "DEV_MCU_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"}, + [384] = {17, 3, "DEV_MCU_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"}, + [385] = {17, 4, "DEV_MCU_DCC0_BUS_VBUS_CLK", "Input clock"}, + [386] = {17, 5, "DEV_MCU_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"}, + [387] = {17, 6, "DEV_MCU_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"}, + [388] = {17, 7, "DEV_MCU_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"}, + [389] = {17, 8, "DEV_MCU_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"}, + [390] = {17, 9, "DEV_MCU_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"}, + [391] = {17, 10, "DEV_MCU_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"}, + [392] = {17, 11, "DEV_MCU_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"}, + [393] = {17, 12, "DEV_MCU_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"}, + [394] = {18, 1, "DEV_MCU_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"}, + [395] = {18, 2, "DEV_MCU_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"}, + [396] = {18, 3, "DEV_MCU_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"}, + [397] = {18, 4, "DEV_MCU_DCC1_BUS_VBUS_CLK", "Input clock"}, + [398] = {18, 5, "DEV_MCU_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"}, + [399] = {18, 6, "DEV_MCU_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"}, + [400] = {18, 7, "DEV_MCU_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"}, + [401] = {18, 8, "DEV_MCU_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"}, + [402] = {18, 9, "DEV_MCU_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"}, + [403] = {18, 10, "DEV_MCU_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"}, + [404] = {18, 11, "DEV_MCU_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"}, + [405] = {18, 12, "DEV_MCU_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"}, + [406] = {19, 1, "DEV_MCU_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"}, + [407] = {19, 2, "DEV_MCU_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"}, + [408] = {19, 3, "DEV_MCU_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"}, + [409] = {19, 4, "DEV_MCU_DCC2_BUS_VBUS_CLK", "Input clock"}, + [410] = {19, 5, "DEV_MCU_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"}, + [411] = {19, 6, "DEV_MCU_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"}, + [412] = {19, 7, "DEV_MCU_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"}, + [413] = {19, 8, "DEV_MCU_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"}, + [414] = {19, 9, "DEV_MCU_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"}, + [415] = {19, 10, "DEV_MCU_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"}, + [416] = {19, 11, "DEV_MCU_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"}, + [417] = {19, 12, "DEV_MCU_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"}, + [418] = {71, 1, "DEV_MCU_DEBUGSS0_BUS_ATB0_CLK", "Input clock"}, + [419] = {71, 2, "DEV_MCU_DEBUGSS0_BUS_SYS_CLK", "Input clock"}, + [420] = {71, 3, "DEV_MCU_DEBUGSS0_BUS_CFG_CLK", "Input clock"}, + [421] = {71, 4, "DEV_MCU_DEBUGSS0_BUS_ATB2_CLK", "Input clock"}, + [422] = {71, 5, "DEV_MCU_DEBUGSS0_BUS_DBG_CLK", "Input clock"}, + [423] = {71, 6, "DEV_MCU_DEBUGSS0_BUS_ATB3_CLK", "Input clock"}, + [424] = {72, 1, "DEV_MCU_EFUSE0_BUS_EFC3_CTL_FCLK", "Output clock"}, + [425] = {72, 2, "DEV_MCU_EFUSE0_BUS_EFC0_CTL_FCLK", "Output clock"}, + [426] = {72, 3, "DEV_MCU_EFUSE0_BUS_EFC1_CTL_FCLK", "Output clock"}, + [427] = {72, 4, "DEV_MCU_EFUSE0_BUS_EFC2_CTL_FCLK", "Output clock"}, + [428] = {247, 1, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_CLK", "Input clock"}, + [429] = {247, 2, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX2_CLK", "Input clock"}, + [430] = {247, 3, "DEV_MCU_FSS0_HYPERBUS0_BUS_CBA_CLK", "Input clock"}, + [431] = {247, 4, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX2_INV_CLK", "Input clock"}, + [432] = {247, 5, "DEV_MCU_FSS0_HYPERBUS0_HPB_OUT_CLK_N", "Output clock"}, + [433] = {247, 6, "DEV_MCU_FSS0_HYPERBUS0_HPB_OUT_CLK_P", "Output clock"}, + [434] = {248, 1, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK"}, + [435] = {248, 2, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK"}, + [436] = {248, 3, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK", "Input muxed clock"}, + [437] = {248, 4, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI0DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK"}, + [438] = {248, 5, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_BUS_OSPI0_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK"}, + [439] = {248, 6, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_PCLK_CLK", "Input clock"}, + [440] = {248, 7, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_DQS_CLK", "Input clock"}, + [441] = {248, 8, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_HCLK_CLK", "Input clock"}, + [442] = {248, 9, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_OCLK_CLK", "Output clock"}, + [443] = {249, 1, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK", "Input muxed clock"}, + [444] = {249, 2, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI1DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK"}, + [445] = {249, 3, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_BUS_OSPI1_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK"}, + [446] = {249, 4, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_HCLK_CLK", "Input clock"}, + [447] = {249, 5, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_DQS_CLK", "Input clock"}, + [448] = {249, 6, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK", "Input muxed clock"}, + [449] = {249, 7, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK"}, + [450] = {249, 8, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK"}, + [451] = {249, 9, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_OCLK_CLK", "Output clock"}, + [452] = {114, 1, "DEV_MCU_I2C0_BUS_PISYS_CLK", "Input clock"}, + [453] = {114, 2, "DEV_MCU_I2C0_BUS_PISCL", "Output clock"}, + [454] = {102, 1, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"}, + [455] = {102, 2, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"}, + [456] = {102, 3, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"}, + [457] = {102, 4, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"}, + [458] = {102, 5, "DEV_MCU_MCAN0_BUS_MCANSS_HCLK_CLK", "Input clock"}, + [459] = {103, 1, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"}, + [460] = {103, 2, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"}, + [461] = {103, 3, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"}, + [462] = {103, 4, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"}, + [463] = {103, 5, "DEV_MCU_MCAN1_BUS_MCANSS_HCLK_CLK", "Input clock"}, + [464] = {142, 1, "DEV_MCU_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"}, + [465] = {142, 2, "DEV_MCU_MCSPI0_BUS_VBUSP_CLK", "Input clock"}, + [466] = {142, 3, "DEV_MCU_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"}, + [467] = {143, 1, "DEV_MCU_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"}, + [468] = {143, 2, "DEV_MCU_MCSPI1_BUS_VBUSP_CLK", "Input clock"}, + [469] = {143, 3, "DEV_MCU_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"}, + [470] = {144, 1, "DEV_MCU_MCSPI2_BUS_VBUSP_CLK", "Input clock"}, + [471] = {116, 1, "DEV_MCU_MSRAM0_BUS_VCLK_CLK", "Input clock"}, + [472] = {119, 1, "DEV_MCU_NAVSS0_BUS_CPSW0CLK", "Input clock"}, + [473] = {119, 2, "DEV_MCU_NAVSS0_BUS_MODSS_VD2CLK", "Input clock"}, + [474] = {119, 3, "DEV_MCU_NAVSS0_BUS_PDMA_MCU1CLK", "Input clock"}, + [475] = {75, 1, "DEV_MCU_PBIST0_BUS_CLK4_CLK", "Input clock"}, + [476] = {75, 2, "DEV_MCU_PBIST0_BUS_CLK2_CLK", "Input clock"}, + [477] = {134, 1, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"}, + [478] = {134, 2, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"}, + [479] = {134, 3, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"}, + [480] = {134, 4, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"}, + [481] = {134, 5, "DEV_MCU_RTI0_BUS_VBUSP_CLK", "Input clock"}, + [482] = {135, 1, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"}, + [483] = {135, 2, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"}, + [484] = {135, 3, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"}, + [485] = {135, 4, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"}, + [486] = {135, 5, "DEV_MCU_RTI1_BUS_VBUSP_CLK", "Input clock"}, + [487] = {35, 1, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, + [488] = {35, 2, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, + [489] = {35, 3, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, + [490] = {35, 4, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, + [491] = {35, 5, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, + [492] = {35, 6, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, + [493] = {35, 7, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, + [494] = {35, 8, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, + [495] = {35, 9, "DEV_MCU_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"}, + [496] = {36, 1, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, + [497] = {36, 2, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, + [498] = {36, 3, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, + [499] = {36, 4, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, + [500] = {36, 5, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, + [501] = {36, 6, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, + [502] = {36, 7, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, + [503] = {36, 8, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, + [504] = {36, 9, "DEV_MCU_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"}, + [505] = {37, 1, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, + [506] = {37, 2, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, + [507] = {37, 3, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, + [508] = {37, 4, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, + [509] = {37, 5, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, + [510] = {37, 6, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, + [511] = {37, 7, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, + [512] = {37, 8, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, + [513] = {37, 9, "DEV_MCU_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"}, + [514] = {38, 1, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, + [515] = {38, 2, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, + [516] = {38, 3, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, + [517] = {38, 4, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, + [518] = {38, 5, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, + [519] = {38, 6, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, + [520] = {38, 7, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, + [521] = {38, 8, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, + [522] = {38, 9, "DEV_MCU_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"}, + [523] = {149, 1, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"}, + [524] = {149, 2, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"}, + [525] = {149, 3, "DEV_MCU_UART0_BUS_VBUSP_CLK", "Input clock"}, + [526] = {47, 1, "DEV_MMCSD0_BUS_EMMCSDSS_XIN_CLK", "Input clock"}, + [527] = {48, 1, "DEV_MMCSD1_BUS_EMMCSDSS_XIN_CLK", "Input clock"}, + [528] = {234, 1, "DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0_BUS_UNDEFINEDCHAIN0_FCLK", "Input clock"}, + [529] = {235, 1, "DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN0_FCLK", "Input clock"}, + [530] = {235, 2, "DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN2_FCLK", "Input clock"}, + [531] = {118, 1, "DEV_NAVSS0_BUS_ICSS_G2CLK", "Input clock"}, + [532] = {118, 2, "DEV_NAVSS0_BUS_ICSS_G0CLK", "Input clock"}, + [533] = {118, 3, "DEV_NAVSS0_BUS_RCLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"}, + [534] = {118, 4, "DEV_NAVSS0_BUS_MSMC0CLK", "Input clock"}, + [535] = {118, 5, "DEV_NAVSS0_BUS_RCLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"}, + [536] = {118, 6, "DEV_NAVSS0_BUS_RCLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"}, + [537] = {118, 7, "DEV_NAVSS0_BUS_MODSS_VD2CLK", "Input clock"}, + [538] = {118, 8, "DEV_NAVSS0_BUS_RCLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"}, + [539] = {118, 9, "DEV_NAVSS0_BUS_PDMA_MAIN1CLK", "Input clock"}, + [540] = {118, 10, "DEV_NAVSS0_BUS_NBSS_VCLK", "Input clock"}, + [541] = {118, 11, "DEV_NAVSS0_BUS_RCLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"}, + [542] = {118, 12, "DEV_NAVSS0_BUS_NBSS_VD2CLK", "Input clock"}, + [543] = {118, 13, "DEV_NAVSS0_BUS_ICSS_G1CLK", "Input clock"}, + [544] = {118, 14, "DEV_NAVSS0_BUS_RCLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"}, + [545] = {118, 15, "DEV_NAVSS0_BUS_CPTS0_GENF4_0", "Output clock"}, + [546] = {118, 16, "DEV_NAVSS0_BUS_CPTS0_GENF5_0", "Output clock"}, + [547] = {118, 17, "DEV_NAVSS0_BUS_CPTS0_GENF2_0", "Output clock"}, + [548] = {118, 18, "DEV_NAVSS0_BUS_CPTS0_GENF3_0", "Output clock"}, + [549] = {216, 1, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN1_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"}, + [550] = {216, 2, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN0_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"}, + [551] = {73, 1, "DEV_PBIST0_BUS_CLK4_CLK", "Input clock"}, + [552] = {73, 2, "DEV_PBIST0_BUS_CLK2_CLK", "Input clock"}, + [553] = {74, 1, "DEV_PBIST1_BUS_CLK4_CLK", "Input clock"}, + [554] = {74, 2, "DEV_PBIST1_BUS_CLK2_CLK", "Input clock"}, + [555] = {120, 1, "DEV_PCIE0_BUS_PCIE_CBA_CLK", "Input clock"}, + [556] = {120, 2, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"}, + [557] = {120, 3, "DEV_PCIE0_BUS_PCIE_TXI0_CLK", "Input clock"}, + [558] = {120, 4, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"}, + [559] = {120, 5, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"}, + [560] = {120, 6, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"}, + [561] = {120, 7, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"}, + [562] = {120, 8, "DEV_PCIE0_BUS_PCIE_TXR1_CLK", "Output clock"}, + [563] = {120, 9, "DEV_PCIE0_BUS_PCIE_TXR0_CLK", "Output clock"}, + [564] = {121, 1, "DEV_PCIE1_BUS_PCIE_CBA_CLK", "Input clock"}, + [565] = {121, 2, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"}, + [566] = {121, 3, "DEV_PCIE1_BUS_PCIE_TXI0_CLK", "Input clock"}, + [567] = {121, 4, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"}, + [568] = {121, 5, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"}, + [569] = {121, 6, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"}, + [570] = {121, 7, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"}, + [571] = {121, 8, "DEV_PCIE1_BUS_PCIE_TXR0_CLK", "Output clock"}, + [572] = {76, 1, "DEV_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"}, + [573] = {76, 2, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input muxed clock"}, + [574] = {76, 3, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"}, + [575] = {76, 4, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"}, + [576] = {62, 1, "DEV_PRU_ICSSG0_BUS_WIZ1_TX_SLV_CLK", "Input clock"}, + [577] = {62, 2, "DEV_PRU_ICSSG0_BUS_WIZ0_RX_SLV_CLK", "Input clock"}, + [578] = {62, 3, "DEV_PRU_ICSSG0_BUS_VCLK_CLK", "Input clock"}, + [579] = {62, 4, "DEV_PRU_ICSSG0_BUS_UCLK_CLK", "Input clock"}, + [580] = {62, 5, "DEV_PRU_ICSSG0_BUS_WIZ0_TX_SLV_CLK", "Input clock"}, + [581] = {62, 6, "DEV_PRU_ICSSG0_BUS_WIZ1_RX_SLV_CLK", "Input clock"}, + [582] = {62, 7, "DEV_PRU_ICSSG0_BUS_PR1_RGMII1_RXC_I", "Input clock"}, + [583] = {62, 8, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_250_CLK", "Input clock"}, + [584] = {62, 9, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_50_CLK", "Input clock"}, + [585] = {62, 10, "DEV_PRU_ICSSG0_BUS_IEP_CLK", "Input muxed clock"}, + [586] = {62, 11, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, + [587] = {62, 12, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, + [588] = {62, 13, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, + [589] = {62, 14, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, + [590] = {62, 15, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, + [591] = {62, 16, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, + [592] = {62, 17, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, + [593] = {62, 18, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, + [594] = {62, 19, "DEV_PRU_ICSSG0_BUS_CORE_CLK", "Input muxed clock"}, + [595] = {62, 20, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"}, + [596] = {62, 21, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"}, + [597] = {62, 22, "DEV_PRU_ICSSG0_BUS_PR1_RGMII0_RXC_I", "Input clock"}, + [598] = {62, 23, "DEV_PRU_ICSSG0_BUS_PR1_RGMII1_TXC_I", "Output clock"}, + [599] = {62, 24, "DEV_PRU_ICSSG0_BUS_PR1_RGMII0_TXC_I", "Output clock"}, + [600] = {63, 1, "DEV_PRU_ICSSG1_BUS_WIZ1_TX_SLV_CLK", "Input clock"}, + [601] = {63, 2, "DEV_PRU_ICSSG1_BUS_WIZ0_RX_SLV_CLK", "Input clock"}, + [602] = {63, 3, "DEV_PRU_ICSSG1_BUS_VCLK_CLK", "Input clock"}, + [603] = {63, 4, "DEV_PRU_ICSSG1_BUS_UCLK_CLK", "Input clock"}, + [604] = {63, 5, "DEV_PRU_ICSSG1_BUS_WIZ0_TX_SLV_CLK", "Input clock"}, + [605] = {63, 6, "DEV_PRU_ICSSG1_BUS_WIZ1_RX_SLV_CLK", "Input clock"}, + [606] = {63, 7, "DEV_PRU_ICSSG1_BUS_PR1_RGMII1_RXC_I", "Input clock"}, + [607] = {63, 8, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_250_CLK", "Input clock"}, + [608] = {63, 9, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_50_CLK", "Input clock"}, + [609] = {63, 10, "DEV_PRU_ICSSG1_BUS_IEP_CLK", "Input muxed clock"}, + [610] = {63, 11, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, + [611] = {63, 12, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, + [612] = {63, 13, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, + [613] = {63, 14, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, + [614] = {63, 15, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, + [615] = {63, 16, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, + [616] = {63, 17, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, + [617] = {63, 18, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, + [618] = {63, 19, "DEV_PRU_ICSSG1_BUS_CORE_CLK", "Input muxed clock"}, + [619] = {63, 20, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"}, + [620] = {63, 21, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"}, + [621] = {63, 22, "DEV_PRU_ICSSG1_BUS_PR1_RGMII0_RXC_I", "Input clock"}, + [622] = {63, 23, "DEV_PRU_ICSSG1_BUS_PR1_RGMII1_TXC_I", "Output clock"}, + [623] = {63, 24, "DEV_PRU_ICSSG1_BUS_PR1_RGMII0_TXC_I", "Output clock"}, + [624] = {64, 1, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_SLV_CLK", "Input clock"}, + [625] = {64, 2, "DEV_PRU_ICSSG2_BUS_WIZ0_RX_SLV_CLK", "Input clock"}, + [626] = {64, 3, "DEV_PRU_ICSSG2_BUS_VCLK_CLK", "Input clock"}, + [627] = {64, 4, "DEV_PRU_ICSSG2_BUS_UCLK_CLK", "Input clock"}, + [628] = {64, 5, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_SLV_CLK", "Input clock"}, + [629] = {64, 6, "DEV_PRU_ICSSG2_BUS_WIZ1_RX_SLV_CLK", "Input clock"}, + [630] = {64, 7, "DEV_PRU_ICSSG2_BUS_PR1_RGMII1_RXC_I", "Input clock"}, + [631] = {64, 8, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_250_CLK", "Input clock"}, + [632] = {64, 9, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_50_CLK", "Input clock"}, + [633] = {64, 10, "DEV_PRU_ICSSG2_BUS_IEP_CLK", "Input muxed clock"}, + [634] = {64, 11, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, + [635] = {64, 12, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, + [636] = {64, 13, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, + [637] = {64, 14, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, + [638] = {64, 15, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, + [639] = {64, 16, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, + [640] = {64, 17, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, + [641] = {64, 18, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, + [642] = {64, 19, "DEV_PRU_ICSSG2_BUS_CORE_CLK", "Input muxed clock"}, + [643] = {64, 20, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"}, + [644] = {64, 21, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"}, + [645] = {64, 22, "DEV_PRU_ICSSG2_BUS_PR1_RGMII0_RXC_I", "Input clock"}, + [646] = {64, 23, "DEV_PRU_ICSSG2_BUS_PR1_RGMII1_TXC_I", "Output clock"}, + [647] = {64, 24, "DEV_PRU_ICSSG2_BUS_PR1_RGMII0_TXC_I", "Output clock"}, + [648] = {64, 25, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_MST_CLK", "Output clock"}, + [649] = {64, 26, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_MST_CLK", "Output clock"}, + [650] = {70, 1, "DEV_PSC0_BUS_SLOW_CLK", "Input clock"}, + [651] = {130, 1, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, + [652] = {130, 2, "DEV_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, + [653] = {130, 3, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, + [654] = {130, 4, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, + [655] = {130, 5, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, + [656] = {130, 6, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, + [657] = {130, 7, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, + [658] = {130, 8, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, + [659] = {130, 9, "DEV_RTI0_BUS_VBUSP_CLK", "Input clock"}, + [660] = {131, 1, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, + [661] = {131, 2, "DEV_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, + [662] = {131, 3, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, + [663] = {131, 4, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, + [664] = {131, 5, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, + [665] = {131, 6, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, + [666] = {131, 7, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, + [667] = {131, 8, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, + [668] = {131, 9, "DEV_RTI1_BUS_VBUSP_CLK", "Input clock"}, + [669] = {132, 1, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, + [670] = {132, 2, "DEV_RTI2_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, + [671] = {132, 3, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, + [672] = {132, 4, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, + [673] = {132, 5, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, + [674] = {132, 6, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, + [675] = {132, 7, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, + [676] = {132, 8, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, + [677] = {132, 9, "DEV_RTI2_BUS_VBUSP_CLK", "Input clock"}, + [678] = {133, 1, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, + [679] = {133, 2, "DEV_RTI3_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, + [680] = {133, 3, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, + [681] = {133, 4, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, + [682] = {133, 5, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, + [683] = {133, 6, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, + [684] = {133, 7, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, + [685] = {133, 8, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, + [686] = {133, 9, "DEV_RTI3_BUS_VBUSP_CLK", "Input clock"}, + [687] = {136, 1, "DEV_SA2_UL0_BUS_X1_CLK", "Input clock"}, + [688] = {136, 2, "DEV_SA2_UL0_BUS_X2_CLK", "Input clock"}, + [689] = {153, 1, "DEV_SERDES0_BUS_REFCLKPP", "Input clock"}, + [690] = {153, 2, "DEV_SERDES0_BUS_CLK", "Input clock"}, + [691] = {153, 3, "DEV_SERDES0_BUS_IP2_LN0_TXRCLK", "Input clock"}, + [692] = {153, 4, "DEV_SERDES0_BUS_LI_REFCLK", "Input muxed clock"}, + [693] = {153, 5, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"}, + [694] = {153, 6, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"}, + [695] = {153, 7, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"}, + [696] = {153, 8, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"}, + [697] = {153, 9, "DEV_SERDES0_BUS_REFCLKPN", "Input clock"}, + [698] = {153, 10, "DEV_SERDES0_BUS_LN0_TXCLK", "Output clock"}, + [699] = {153, 11, "DEV_SERDES0_BUS_LN0_RXCLK", "Output clock"}, + [700] = {154, 1, "DEV_SERDES1_BUS_REFCLKPP", "Input clock"}, + [701] = {154, 2, "DEV_SERDES1_BUS_CLK", "Input clock"}, + [702] = {154, 3, "DEV_SERDES1_BUS_IP1_LN0_TXRCLK", "Input clock"}, + [703] = {154, 4, "DEV_SERDES1_BUS_IP2_LN0_TXRCLK", "Input clock"}, + [704] = {154, 5, "DEV_SERDES1_BUS_RI_REFCLK", "Input muxed clock"}, + [705] = {154, 6, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"}, + [706] = {154, 7, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"}, + [707] = {154, 8, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"}, + [708] = {154, 9, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"}, + [709] = {154, 10, "DEV_SERDES1_BUS_REFCLKPN", "Input clock"}, + [710] = {154, 11, "DEV_SERDES1_BUS_LN0_TXCLK", "Output clock"}, + [711] = {154, 12, "DEV_SERDES1_BUS_LN0_RXCLK", "Output clock"}, + [712] = {8, 1, "DEV_STM0_BUS_ATB_CLK", "Input clock"}, + [713] = {8, 2, "DEV_STM0_BUS_VBUSP_CLK", "Input clock"}, + [714] = {23, 1, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, + [715] = {23, 2, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, + [716] = {23, 3, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, + [717] = {23, 4, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, + [718] = {23, 5, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, + [719] = {23, 6, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, + [720] = {23, 7, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, + [721] = {23, 8, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, + [722] = {23, 9, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, + [723] = {23, 10, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, + [724] = {23, 11, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, + [725] = {23, 12, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, + [726] = {23, 13, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, + [727] = {23, 14, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, + [728] = {23, 15, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, + [729] = {23, 16, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, + [730] = {23, 17, "DEV_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"}, + [731] = {24, 1, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, + [732] = {24, 2, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, + [733] = {24, 3, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, + [734] = {24, 4, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, + [735] = {24, 5, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, + [736] = {24, 6, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, + [737] = {24, 7, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, + [738] = {24, 8, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, + [739] = {24, 9, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, + [740] = {24, 10, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, + [741] = {24, 11, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, + [742] = {24, 12, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, + [743] = {24, 13, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, + [744] = {24, 14, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, + [745] = {24, 15, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, + [746] = {24, 16, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, + [747] = {24, 17, "DEV_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"}, + [748] = {25, 1, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, + [749] = {25, 2, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, + [750] = {25, 3, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, + [751] = {25, 4, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, + [752] = {25, 5, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, + [753] = {25, 6, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, + [754] = {25, 7, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, + [755] = {25, 8, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, + [756] = {25, 9, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, + [757] = {25, 10, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, + [758] = {25, 11, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, + [759] = {25, 12, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, + [760] = {25, 13, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, + [761] = {25, 14, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, + [762] = {25, 15, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, + [763] = {25, 16, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, + [764] = {25, 17, "DEV_TIMER10_BUS_TIMER_HCLK_CLK", "Input clock"}, + [765] = {26, 1, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, + [766] = {26, 2, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, + [767] = {26, 3, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, + [768] = {26, 4, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, + [769] = {26, 5, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, + [770] = {26, 6, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, + [771] = {26, 7, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, + [772] = {26, 8, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, + [773] = {26, 9, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, + [774] = {26, 10, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, + [775] = {26, 11, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, + [776] = {26, 12, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, + [777] = {26, 13, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, + [778] = {26, 14, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, + [779] = {26, 15, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, + [780] = {26, 16, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, + [781] = {26, 17, "DEV_TIMER11_BUS_TIMER_HCLK_CLK", "Input clock"}, + [782] = {27, 1, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, + [783] = {27, 2, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, + [784] = {27, 3, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, + [785] = {27, 4, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, + [786] = {27, 5, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, + [787] = {27, 6, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, + [788] = {27, 7, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, + [789] = {27, 8, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, + [790] = {27, 9, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, + [791] = {27, 10, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, + [792] = {27, 11, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, + [793] = {27, 12, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, + [794] = {27, 13, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, + [795] = {27, 14, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, + [796] = {27, 15, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, + [797] = {27, 16, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, + [798] = {27, 17, "DEV_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"}, + [799] = {28, 1, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, + [800] = {28, 2, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, + [801] = {28, 3, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, + [802] = {28, 4, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, + [803] = {28, 5, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, + [804] = {28, 6, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, + [805] = {28, 7, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, + [806] = {28, 8, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, + [807] = {28, 9, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, + [808] = {28, 10, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, + [809] = {28, 11, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, + [810] = {28, 12, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, + [811] = {28, 13, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, + [812] = {28, 14, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, + [813] = {28, 15, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, + [814] = {28, 16, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, + [815] = {28, 17, "DEV_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"}, + [816] = {29, 1, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, + [817] = {29, 2, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, + [818] = {29, 3, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, + [819] = {29, 4, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, + [820] = {29, 5, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, + [821] = {29, 6, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, + [822] = {29, 7, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, + [823] = {29, 8, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, + [824] = {29, 9, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, + [825] = {29, 10, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, + [826] = {29, 11, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, + [827] = {29, 12, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, + [828] = {29, 13, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, + [829] = {29, 14, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, + [830] = {29, 15, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, + [831] = {29, 16, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, + [832] = {29, 17, "DEV_TIMER4_BUS_TIMER_HCLK_CLK", "Input clock"}, + [833] = {30, 1, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, + [834] = {30, 2, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, + [835] = {30, 3, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, + [836] = {30, 4, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, + [837] = {30, 5, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, + [838] = {30, 6, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, + [839] = {30, 7, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, + [840] = {30, 8, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, + [841] = {30, 9, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, + [842] = {30, 10, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, + [843] = {30, 11, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, + [844] = {30, 12, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, + [845] = {30, 13, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, + [846] = {30, 14, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, + [847] = {30, 15, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, + [848] = {30, 16, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, + [849] = {30, 17, "DEV_TIMER5_BUS_TIMER_HCLK_CLK", "Input clock"}, + [850] = {31, 1, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, + [851] = {31, 2, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, + [852] = {31, 3, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, + [853] = {31, 4, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, + [854] = {31, 5, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, + [855] = {31, 6, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, + [856] = {31, 7, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, + [857] = {31, 8, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, + [858] = {31, 9, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, + [859] = {31, 10, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, + [860] = {31, 11, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, + [861] = {31, 12, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, + [862] = {31, 13, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, + [863] = {31, 14, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, + [864] = {31, 15, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, + [865] = {31, 16, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, + [866] = {31, 17, "DEV_TIMER6_BUS_TIMER_HCLK_CLK", "Input clock"}, + [867] = {32, 1, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, + [868] = {32, 2, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, + [869] = {32, 3, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, + [870] = {32, 4, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, + [871] = {32, 5, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, + [872] = {32, 6, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, + [873] = {32, 7, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, + [874] = {32, 8, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, + [875] = {32, 9, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, + [876] = {32, 10, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, + [877] = {32, 11, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, + [878] = {32, 12, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, + [879] = {32, 13, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, + [880] = {32, 14, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, + [881] = {32, 15, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, + [882] = {32, 16, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, + [883] = {32, 17, "DEV_TIMER7_BUS_TIMER_HCLK_CLK", "Input clock"}, + [884] = {33, 1, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, + [885] = {33, 2, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, + [886] = {33, 3, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, + [887] = {33, 4, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, + [888] = {33, 5, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, + [889] = {33, 6, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, + [890] = {33, 7, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, + [891] = {33, 8, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, + [892] = {33, 9, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, + [893] = {33, 10, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, + [894] = {33, 11, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, + [895] = {33, 12, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, + [896] = {33, 13, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, + [897] = {33, 14, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, + [898] = {33, 15, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, + [899] = {33, 16, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, + [900] = {33, 17, "DEV_TIMER8_BUS_TIMER_HCLK_CLK", "Input clock"}, + [901] = {34, 1, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, + [902] = {34, 2, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, + [903] = {34, 3, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, + [904] = {34, 4, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, + [905] = {34, 5, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, + [906] = {34, 6, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, + [907] = {34, 7, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, + [908] = {34, 8, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, + [909] = {34, 9, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, + [910] = {34, 10, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, + [911] = {34, 11, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, + [912] = {34, 12, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, + [913] = {34, 13, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, + [914] = {34, 14, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, + [915] = {34, 15, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, + [916] = {34, 16, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, + [917] = {34, 17, "DEV_TIMER9_BUS_TIMER_HCLK_CLK", "Input clock"}, + [918] = {146, 1, "DEV_UART0_BUS_VBUSP_CLK", "Input clock"}, + [919] = {147, 1, "DEV_UART1_BUS_VBUSP_CLK", "Input clock"}, + [920] = {148, 1, "DEV_UART2_BUS_VBUSP_CLK", "Input clock"}, + [921] = {151, 1, "DEV_USB3SS0_BUS_PHY2_REFCLK960M_CLK", "Input clock"}, + [922] = {151, 2, "DEV_USB3SS0_BUS_REF_CLK", "Input muxed clock"}, + [923] = {151, 3, "DEV_USB3SS0_BUS_REF_CLK_PARENT_CLOCKMUX_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"}, + [924] = {151, 4, "DEV_USB3SS0_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"}, + [925] = {151, 5, "DEV_USB3SS0_BUS_HSIC_CLK_CLK", "Input clock"}, + [926] = {151, 6, "DEV_USB3SS0_BUS_BUS_CLK", "Input clock"}, + [927] = {151, 7, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK", "Input muxed clock"}, + [928] = {151, 8, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"}, + [929] = {151, 9, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_CLOCKMUX_USB0_PIPE3_CLK_SEL_DIV_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"}, + [930] = {151, 10, "DEV_USB3SS0_BUS_UTMI_CLK_CLK", "Input clock"}, + [931] = {152, 1, "DEV_USB3SS1_BUS_PHY2_REFCLK960M_CLK", "Input clock"}, + [932] = {152, 2, "DEV_USB3SS1_BUS_REF_CLK", "Input muxed clock"}, + [933] = {152, 3, "DEV_USB3SS1_BUS_REF_CLK_PARENT_CLOCKMUX_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"}, + [934] = {152, 4, "DEV_USB3SS1_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"}, + [935] = {152, 5, "DEV_USB3SS1_BUS_HSIC_CLK_CLK", "Input clock"}, + [936] = {152, 6, "DEV_USB3SS1_BUS_BUS_CLK", "Input clock"}, + [937] = {152, 7, "DEV_USB3SS1_BUS_PIPE3_TXB_CLK", "Input clock"}, + [938] = {152, 8, "DEV_USB3SS1_BUS_UTMI_CLK_CLK", "Input clock"}, + [939] = {94, 1, "DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_4_CLK", "Input clock"}, + [940] = {22, 1, "DEV_WKUP_DMSC0_BUS_FUNC_MOSC_CLK", "Input clock"}, + [941] = {22, 2, "DEV_WKUP_DMSC0_BUS_VBUS_CLK", "Input clock"}, + [942] = {22, 3, "DEV_WKUP_DMSC0_BUS_FUNC_32K_RC_CLK", "Input clock"}, + [943] = {22, 4, "DEV_WKUP_DMSC0_BUS_SEC_EFC_FCLK", "Input clock"}, + [944] = {22, 5, "DEV_WKUP_DMSC0_BUS_DAP_CLK", "Input clock"}, + [945] = {22, 6, "DEV_WKUP_DMSC0_BUS_EXT_CLK", "Input clock"}, + [946] = {59, 1, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"}, + [947] = {59, 2, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4_DUP0", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"}, + [948] = {59, 3, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"}, + [949] = {59, 4, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"}, + [950] = {115, 1, "DEV_WKUP_I2C0_BUS_PISYS_CLK", "Input muxed clock"}, + [951] = {115, 2, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"}, + [952] = {115, 3, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"}, + [953] = {115, 4, "DEV_WKUP_I2C0_BUS_PISCL", "Output clock"}, + [954] = {77, 1, "DEV_WKUP_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"}, + [955] = {77, 2, "DEV_WKUP_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input clock"}, + [956] = {79, 1, "DEV_WKUP_PSC0_BUS_SLOW_CLK", "Input clock"}, + [957] = {150, 1, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_CLOCKMUX_WKUPUSART_CLK_SEL_BUS_OUT0", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"}, + [958] = {150, 2, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"}, + [959] = {150, 3, "DEV_WKUP_UART0_BUS_VBUSP_CLK", "Input clock"}, + [960] = {80, 1, "DEV_WKUP_VTM0_BUS_VBUSP_CLK", "Input clock"}, }; diff --git a/soc/am65x/am65x_clocks_info.h b/soc/am65x/am65x_clocks_info.h new file mode 100644 index 0000000..dcabfeb --- /dev/null +++ b/soc/am65x/am65x_clocks_info.h @@ -0,0 +1,42 @@ +/* + * AM65X Clocks Info + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __AM65X_CLOCKS_INFO_H +#define __AM65X_CLOCKS_INFO_H + +#define AM65X_MAX_CLOCKS 961 + +extern struct ti_sci_clocks_info am65x_clocks_info[]; + +#endif /* __AM65X_CLOCKS_INFO_H */ \ No newline at end of file diff --git a/soc/am65x/am65x_devices_info.c b/soc/am65x/am65x_devices_info.c index 533708d..393150a 100644 --- a/soc/am65x/am65x_devices_info.c +++ b/soc/am65x/am65x_devices_info.c @@ -1,7 +1,7 @@ /* - * SoC Device Info + * AM65X Devices Info * - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -36,247 +36,247 @@ #include struct ti_sci_devices_info am65x_devices_info[] = { - [0] = {0, "AM6_DEV_MCU_ADC0"}, - [1] = {1, "AM6_DEV_MCU_ADC1"}, - [2] = {2, "AM6_DEV_CAL0"}, - [3] = {3, "AM6_DEV_CMPEVENT_INTRTR0"}, - [4] = {5, "AM6_DEV_MCU_CPSW0"}, - [5] = {6, "AM6_DEV_CPT2_AGGR0"}, - [6] = {7, "AM6_DEV_MCU_CPT2_AGGR0"}, - [7] = {8, "AM6_DEV_STM0"}, - [8] = {9, "AM6_DEV_DCC0"}, - [9] = {10, "AM6_DEV_DCC1"}, - [10] = {11, "AM6_DEV_DCC2"}, - [11] = {12, "AM6_DEV_DCC3"}, - [12] = {13, "AM6_DEV_DCC4"}, - [13] = {14, "AM6_DEV_DCC5"}, - [14] = {15, "AM6_DEV_DCC6"}, - [15] = {16, "AM6_DEV_DCC7"}, - [16] = {17, "AM6_DEV_MCU_DCC0"}, - [17] = {18, "AM6_DEV_MCU_DCC1"}, - [18] = {19, "AM6_DEV_MCU_DCC2"}, - [19] = {20, "AM6_DEV_DDRSS0"}, - [20] = {21, "AM6_DEV_DEBUGSS_WRAP0"}, - [21] = {22, "AM6_DEV_WKUP_DMSC0"}, - [22] = {23, "AM6_DEV_TIMER0"}, - [23] = {24, "AM6_DEV_TIMER1"}, - [24] = {25, "AM6_DEV_TIMER10"}, - [25] = {26, "AM6_DEV_TIMER11"}, - [26] = {27, "AM6_DEV_TIMER2"}, - [27] = {28, "AM6_DEV_TIMER3"}, - [28] = {29, "AM6_DEV_TIMER4"}, - [29] = {30, "AM6_DEV_TIMER5"}, - [30] = {31, "AM6_DEV_TIMER6"}, - [31] = {32, "AM6_DEV_TIMER7"}, - [32] = {33, "AM6_DEV_TIMER8"}, - [33] = {34, "AM6_DEV_TIMER9"}, - [34] = {35, "AM6_DEV_MCU_TIMER0"}, - [35] = {36, "AM6_DEV_MCU_TIMER1"}, - [36] = {37, "AM6_DEV_MCU_TIMER2"}, - [37] = {38, "AM6_DEV_MCU_TIMER3"}, - [38] = {39, "AM6_DEV_ECAP0"}, - [39] = {40, "AM6_DEV_EHRPWM0"}, - [40] = {41, "AM6_DEV_EHRPWM1"}, - [41] = {42, "AM6_DEV_EHRPWM2"}, - [42] = {43, "AM6_DEV_EHRPWM3"}, - [43] = {44, "AM6_DEV_EHRPWM4"}, - [44] = {45, "AM6_DEV_EHRPWM5"}, - [45] = {46, "AM6_DEV_ELM0"}, - [46] = {47, "AM6_DEV_MMCSD0"}, - [47] = {48, "AM6_DEV_MMCSD1"}, - [48] = {49, "AM6_DEV_EQEP0"}, - [49] = {50, "AM6_DEV_EQEP1"}, - [50] = {51, "AM6_DEV_EQEP2"}, - [51] = {52, "AM6_DEV_ESM0"}, - [52] = {53, "AM6_DEV_MCU_ESM0"}, - [53] = {54, "AM6_DEV_WKUP_ESM0"}, - [54] = {55, "AM6_DEV_MCU_FSS0"}, - [55] = {56, "AM6_DEV_GIC0"}, - [56] = {57, "AM6_DEV_GPIO0"}, - [57] = {58, "AM6_DEV_GPIO1"}, - [58] = {59, "AM6_DEV_WKUP_GPIO0"}, - [59] = {60, "AM6_DEV_GPMC0"}, - [60] = {61, "AM6_DEV_GTC0"}, - [61] = {62, "AM6_DEV_PRU_ICSSG0"}, - [62] = {63, "AM6_DEV_PRU_ICSSG1"}, - [63] = {64, "AM6_DEV_PRU_ICSSG2"}, - [64] = {65, "AM6_DEV_GPU0"}, - [65] = {66, "AM6_DEV_CCDEBUGSS0"}, - [66] = {67, "AM6_DEV_DSS0"}, - [67] = {68, "AM6_DEV_DEBUGSS0"}, - [68] = {69, "AM6_DEV_EFUSE0"}, - [69] = {70, "AM6_DEV_PSC0"}, - [70] = {71, "AM6_DEV_MCU_DEBUGSS0"}, - [71] = {72, "AM6_DEV_MCU_EFUSE0"}, - [72] = {73, "AM6_DEV_PBIST0"}, - [73] = {74, "AM6_DEV_PBIST1"}, - [74] = {75, "AM6_DEV_MCU_PBIST0"}, - [75] = {76, "AM6_DEV_PLLCTRL0"}, - [76] = {77, "AM6_DEV_WKUP_PLLCTRL0"}, - [77] = {78, "AM6_DEV_MCU_ROM0"}, - [78] = {79, "AM6_DEV_WKUP_PSC0"}, - [79] = {80, "AM6_DEV_WKUP_VTM0"}, - [80] = {81, "AM6_DEV_DEBUGSUSPENDRTR0"}, - [81] = {82, "AM6_DEV_CBASS0"}, - [82] = {83, "AM6_DEV_CBASS_DEBUG0"}, - [83] = {84, "AM6_DEV_CBASS_FW0"}, - [84] = {85, "AM6_DEV_CBASS_INFRA0"}, - [85] = {86, "AM6_DEV_ECC_AGGR0"}, - [86] = {87, "AM6_DEV_ECC_AGGR1"}, - [87] = {88, "AM6_DEV_ECC_AGGR2"}, - [88] = {89, "AM6_DEV_MCU_CBASS0"}, - [89] = {90, "AM6_DEV_MCU_CBASS_DEBUG0"}, - [90] = {91, "AM6_DEV_MCU_CBASS_FW0"}, - [91] = {92, "AM6_DEV_MCU_ECC_AGGR0"}, - [92] = {93, "AM6_DEV_MCU_ECC_AGGR1"}, - [93] = {94, "AM6_DEV_WKUP_CBASS0"}, - [94] = {95, "AM6_DEV_WKUP_ECC_AGGR0"}, - [95] = {96, "AM6_DEV_WKUP_CBASS_FW0"}, - [96] = {97, "AM6_DEV_MAIN2MCU_LVL_INTRTR0"}, - [97] = {98, "AM6_DEV_MAIN2MCU_PLS_INTRTR0"}, - [98] = {99, "AM6_DEV_CTRL_MMR0"}, - [99] = {100, "AM6_DEV_GPIOMUX_INTRTR0"}, - [100] = {101, "AM6_DEV_PLL_MMR0"}, - [101] = {102, "AM6_DEV_MCU_MCAN0"}, - [102] = {103, "AM6_DEV_MCU_MCAN1"}, - [103] = {104, "AM6_DEV_MCASP0"}, - [104] = {105, "AM6_DEV_MCASP1"}, - [105] = {106, "AM6_DEV_MCASP2"}, - [106] = {107, "AM6_DEV_MCU_CTRL_MMR0"}, - [107] = {108, "AM6_DEV_MCU_PLL_MMR0"}, - [108] = {109, "AM6_DEV_MCU_SEC_MMR0"}, - [109] = {110, "AM6_DEV_I2C0"}, - [110] = {111, "AM6_DEV_I2C1"}, - [111] = {112, "AM6_DEV_I2C2"}, - [112] = {113, "AM6_DEV_I2C3"}, - [113] = {114, "AM6_DEV_MCU_I2C0"}, - [114] = {115, "AM6_DEV_WKUP_I2C0"}, - [115] = {116, "AM6_DEV_MCU_MSRAM0"}, - [116] = {117, "AM6_DEV_DFTSS0"}, - [117] = {118, "AM6_DEV_NAVSS0"}, - [118] = {119, "AM6_DEV_MCU_NAVSS0"}, - [119] = {120, "AM6_DEV_PCIE0"}, - [120] = {121, "AM6_DEV_PCIE1"}, - [121] = {122, "AM6_DEV_PDMA_DEBUG0"}, - [122] = {123, "AM6_DEV_PDMA0"}, - [123] = {124, "AM6_DEV_PDMA1"}, - [124] = {125, "AM6_DEV_MCU_PDMA0"}, - [125] = {126, "AM6_DEV_MCU_PDMA1"}, - [126] = {127, "AM6_DEV_MCU_PSRAM0"}, - [127] = {128, "AM6_DEV_PSRAMECC0"}, - [128] = {129, "AM6_DEV_MCU_ARMSS0"}, - [129] = {130, "AM6_DEV_RTI0"}, - [130] = {131, "AM6_DEV_RTI1"}, - [131] = {132, "AM6_DEV_RTI2"}, - [132] = {133, "AM6_DEV_RTI3"}, - [133] = {134, "AM6_DEV_MCU_RTI0"}, - [134] = {135, "AM6_DEV_MCU_RTI1"}, - [135] = {136, "AM6_DEV_SA2_UL0"}, - [136] = {137, "AM6_DEV_MCSPI0"}, - [137] = {138, "AM6_DEV_MCSPI1"}, - [138] = {139, "AM6_DEV_MCSPI2"}, - [139] = {140, "AM6_DEV_MCSPI3"}, - [140] = {141, "AM6_DEV_MCSPI4"}, - [141] = {142, "AM6_DEV_MCU_MCSPI0"}, - [142] = {143, "AM6_DEV_MCU_MCSPI1"}, - [143] = {144, "AM6_DEV_MCU_MCSPI2"}, - [144] = {145, "AM6_DEV_TIMESYNC_INTRTR0"}, - [145] = {146, "AM6_DEV_UART0"}, - [146] = {147, "AM6_DEV_UART1"}, - [147] = {148, "AM6_DEV_UART2"}, - [148] = {149, "AM6_DEV_MCU_UART0"}, - [149] = {150, "AM6_DEV_WKUP_UART0"}, - [150] = {151, "AM6_DEV_USB3SS0"}, - [151] = {152, "AM6_DEV_USB3SS1"}, - [152] = {153, "AM6_DEV_SERDES0"}, - [153] = {154, "AM6_DEV_SERDES1"}, - [154] = {155, "AM6_DEV_WKUP_CTRL_MMR0"}, - [155] = {156, "AM6_DEV_WKUP_GPIOMUX_INTRTR0"}, - [156] = {157, "AM6_DEV_BOARD0"}, - [157] = {159, "AM6_DEV_MCU_ARMSS0_CPU0"}, - [158] = {161, "AM6_DEV_WKUP_DMSC0_CORTEX_M3_0"}, - [159] = {162, "AM6_DEV_WKUP_DMSC0_INTR_AGGR_0"}, - [160] = {163, "AM6_DEV_NAVSS0_CPTS0"}, - [161] = {164, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0"}, - [162] = {165, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1"}, - [163] = {166, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2"}, - [164] = {167, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER3"}, - [165] = {168, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER4"}, - [166] = {169, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER5"}, - [167] = {170, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER6"}, - [168] = {171, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER7"}, - [169] = {172, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER8"}, - [170] = {173, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER9"}, - [171] = {174, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10"}, - [172] = {175, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11"}, - [173] = {176, "AM6_DEV_NAVSS0_MCRC0"}, - [174] = {177, "AM6_DEV_NAVSS0_PVU0"}, - [175] = {178, "AM6_DEV_NAVSS0_PVU1"}, - [176] = {179, "AM6_DEV_NAVSS0_UDMASS_INTA0"}, - [177] = {180, "AM6_DEV_NAVSS0_MODSS_INTA0"}, - [178] = {181, "AM6_DEV_NAVSS0_MODSS_INTA1"}, - [179] = {182, "AM6_DEV_NAVSS0_INTR_ROUTER_0"}, - [180] = {183, "AM6_DEV_NAVSS0_TIMER_MGR0"}, - [181] = {184, "AM6_DEV_NAVSS0_TIMER_MGR1"}, - [182] = {185, "AM6_DEV_NAVSS0_PROXY0"}, - [183] = {186, "AM6_DEV_NAVSS0_SEC_PROXY0"}, - [184] = {187, "AM6_DEV_NAVSS0_RINGACC0"}, - [185] = {188, "AM6_DEV_NAVSS0_UDMAP0"}, - [186] = {189, "AM6_DEV_MCU_NAVSS0_INTR_AGGR_0"}, - [187] = {190, "AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0"}, - [188] = {191, "AM6_DEV_MCU_NAVSS0_PROXY0"}, - [189] = {192, "AM6_DEV_MCU_NAVSS0_SEC_PROXY0"}, - [190] = {193, "AM6_DEV_MCU_NAVSS0_MCRC0"}, - [191] = {194, "AM6_DEV_MCU_NAVSS0_UDMAP0"}, - [192] = {195, "AM6_DEV_MCU_NAVSS0_RINGACC0"}, - [193] = {196, "AM6_DEV_COMPUTE_CLUSTER_MSMC0"}, - [194] = {197, "AM6_DEV_COMPUTE_CLUSTER_PBIST0"}, - [195] = {198, "AM6_DEV_COMPUTE_CLUSTER_CPAC0"}, - [196] = {199, "AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST0"}, - [197] = {200, "AM6_DEV_COMPUTE_CLUSTER_CPAC1"}, - [198] = {201, "AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST1"}, - [199] = {202, "AM6_DEV_COMPUTE_CLUSTER_A53_0"}, - [200] = {203, "AM6_DEV_COMPUTE_CLUSTER_A53_1"}, - [201] = {204, "AM6_DEV_COMPUTE_CLUSTER_A53_2"}, - [202] = {205, "AM6_DEV_COMPUTE_CLUSTER_A53_3"}, - [203] = {206, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4"}, - [204] = {207, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3"}, - [205] = {208, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0"}, - [206] = {209, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3"}, - [207] = {210, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1"}, - [208] = {211, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5"}, - [209] = {212, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6"}, - [210] = {213, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0"}, - [211] = {214, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2"}, - [212] = {215, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2"}, - [213] = {216, "AM6_DEV_OLDI_TX_CORE_MAIN_0"}, - [214] = {217, "AM6_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0"}, - [215] = {218, "AM6_DEV_ICEMELTER_WKUP_0"}, - [216] = {219, "AM6_DEV_K3_LED_MAIN_0"}, - [217] = {220, "AM6_DEV_VDC_DATA_VBUSM_32B_REF_WKUP2MCU"}, - [218] = {221, "AM6_DEV_VDC_DATA_VBUSM_32B_REF_MCU2WKUP"}, - [219] = {222, "AM6_DEV_VDC_DATA_VBUSM_64B_REF_MAIN2MCU"}, - [220] = {223, "AM6_DEV_VDC_DATA_VBUSM_64B_REF_MCU2MAIN"}, - [221] = {224, "AM6_DEV_VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC"}, - [222] = {225, "AM6_DEV_VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA"}, - [223] = {226, "AM6_DEV_VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA"}, - [224] = {227, "AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU"}, - [225] = {228, "AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN"}, - [226] = {229, "AM6_DEV_VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU"}, - [227] = {230, "AM6_DEV_VDC_NAV_PSIL_128B_REF_MAIN2MCU"}, - [228] = {231, "AM6_DEV_GS80PRG_SOC_WRAP_WKUP_0"}, - [229] = {232, "AM6_DEV_GS80PRG_MCU_WRAP_WKUP_0"}, - [230] = {233, "AM6_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0"}, - [231] = {234, "AM6_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0"}, - [232] = {235, "AM6_DEV_MX_EFUSE_MCU_CHAIN_MCU_0"}, - [233] = {236, "AM6_DEV_DUMMY_IP_LPSC_WKUP2MCU"}, - [234] = {237, "AM6_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA"}, - [235] = {238, "AM6_DEV_DUMMY_IP_LPSC_DEBUG2DMSC"}, - [236] = {239, "AM6_DEV_DUMMY_IP_LPSC_DMSC"}, - [237] = {240, "AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA"}, - [238] = {241, "AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN"}, - [239] = {242, "AM6_DEV_DUMMY_IP_LPSC_MCU2WKUP"}, - [240] = {243, "AM6_DEV_DUMMY_IP_LPSC_MAIN2MCU"}, - [241] = {244, "AM6_DEV_DUMMY_IP_LPSC_EMIF_DATA"}, - [242] = {245, "AM6_DEV_MCU_ARMSS0_CPU1"}, + [0] = {0, "AM6_DEV_MCU_ADC0"}, + [1] = {1, "AM6_DEV_MCU_ADC1"}, + [2] = {2, "AM6_DEV_CAL0"}, + [3] = {3, "AM6_DEV_CMPEVENT_INTRTR0"}, + [4] = {5, "AM6_DEV_MCU_CPSW0"}, + [5] = {6, "AM6_DEV_CPT2_AGGR0"}, + [6] = {7, "AM6_DEV_MCU_CPT2_AGGR0"}, + [7] = {8, "AM6_DEV_STM0"}, + [8] = {9, "AM6_DEV_DCC0"}, + [9] = {10, "AM6_DEV_DCC1"}, + [10] = {11, "AM6_DEV_DCC2"}, + [11] = {12, "AM6_DEV_DCC3"}, + [12] = {13, "AM6_DEV_DCC4"}, + [13] = {14, "AM6_DEV_DCC5"}, + [14] = {15, "AM6_DEV_DCC6"}, + [15] = {16, "AM6_DEV_DCC7"}, + [16] = {17, "AM6_DEV_MCU_DCC0"}, + [17] = {18, "AM6_DEV_MCU_DCC1"}, + [18] = {19, "AM6_DEV_MCU_DCC2"}, + [19] = {20, "AM6_DEV_DDRSS0"}, + [20] = {21, "AM6_DEV_DEBUGSS_WRAP0"}, + [21] = {22, "AM6_DEV_WKUP_DMSC0"}, + [22] = {23, "AM6_DEV_TIMER0"}, + [23] = {24, "AM6_DEV_TIMER1"}, + [24] = {25, "AM6_DEV_TIMER10"}, + [25] = {26, "AM6_DEV_TIMER11"}, + [26] = {27, "AM6_DEV_TIMER2"}, + [27] = {28, "AM6_DEV_TIMER3"}, + [28] = {29, "AM6_DEV_TIMER4"}, + [29] = {30, "AM6_DEV_TIMER5"}, + [30] = {31, "AM6_DEV_TIMER6"}, + [31] = {32, "AM6_DEV_TIMER7"}, + [32] = {33, "AM6_DEV_TIMER8"}, + [33] = {34, "AM6_DEV_TIMER9"}, + [34] = {35, "AM6_DEV_MCU_TIMER0"}, + [35] = {36, "AM6_DEV_MCU_TIMER1"}, + [36] = {37, "AM6_DEV_MCU_TIMER2"}, + [37] = {38, "AM6_DEV_MCU_TIMER3"}, + [38] = {39, "AM6_DEV_ECAP0"}, + [39] = {40, "AM6_DEV_EHRPWM0"}, + [40] = {41, "AM6_DEV_EHRPWM1"}, + [41] = {42, "AM6_DEV_EHRPWM2"}, + [42] = {43, "AM6_DEV_EHRPWM3"}, + [43] = {44, "AM6_DEV_EHRPWM4"}, + [44] = {45, "AM6_DEV_EHRPWM5"}, + [45] = {46, "AM6_DEV_ELM0"}, + [46] = {47, "AM6_DEV_MMCSD0"}, + [47] = {48, "AM6_DEV_MMCSD1"}, + [48] = {49, "AM6_DEV_EQEP0"}, + [49] = {50, "AM6_DEV_EQEP1"}, + [50] = {51, "AM6_DEV_EQEP2"}, + [51] = {52, "AM6_DEV_ESM0"}, + [52] = {53, "AM6_DEV_MCU_ESM0"}, + [53] = {54, "AM6_DEV_WKUP_ESM0"}, + [54] = {56, "AM6_DEV_GIC0"}, + [55] = {57, "AM6_DEV_GPIO0"}, + [56] = {58, "AM6_DEV_GPIO1"}, + [57] = {59, "AM6_DEV_WKUP_GPIO0"}, + [58] = {60, "AM6_DEV_GPMC0"}, + [59] = {61, "AM6_DEV_GTC0"}, + [60] = {62, "AM6_DEV_PRU_ICSSG0"}, + [61] = {63, "AM6_DEV_PRU_ICSSG1"}, + [62] = {64, "AM6_DEV_PRU_ICSSG2"}, + [63] = {65, "AM6_DEV_GPU0"}, + [64] = {66, "AM6_DEV_CCDEBUGSS0"}, + [65] = {67, "AM6_DEV_DSS0"}, + [66] = {68, "AM6_DEV_DEBUGSS0"}, + [67] = {69, "AM6_DEV_EFUSE0"}, + [68] = {70, "AM6_DEV_PSC0"}, + [69] = {71, "AM6_DEV_MCU_DEBUGSS0"}, + [70] = {72, "AM6_DEV_MCU_EFUSE0"}, + [71] = {73, "AM6_DEV_PBIST0"}, + [72] = {74, "AM6_DEV_PBIST1"}, + [73] = {75, "AM6_DEV_MCU_PBIST0"}, + [74] = {76, "AM6_DEV_PLLCTRL0"}, + [75] = {77, "AM6_DEV_WKUP_PLLCTRL0"}, + [76] = {78, "AM6_DEV_MCU_ROM0"}, + [77] = {79, "AM6_DEV_WKUP_PSC0"}, + [78] = {80, "AM6_DEV_WKUP_VTM0"}, + [79] = {81, "AM6_DEV_DEBUGSUSPENDRTR0"}, + [80] = {82, "AM6_DEV_CBASS0"}, + [81] = {83, "AM6_DEV_CBASS_DEBUG0"}, + [82] = {84, "AM6_DEV_CBASS_FW0"}, + [83] = {85, "AM6_DEV_CBASS_INFRA0"}, + [84] = {86, "AM6_DEV_ECC_AGGR0"}, + [85] = {87, "AM6_DEV_ECC_AGGR1"}, + [86] = {88, "AM6_DEV_ECC_AGGR2"}, + [87] = {89, "AM6_DEV_MCU_CBASS0"}, + [88] = {90, "AM6_DEV_MCU_CBASS_DEBUG0"}, + [89] = {91, "AM6_DEV_MCU_CBASS_FW0"}, + [90] = {92, "AM6_DEV_MCU_ECC_AGGR0"}, + [91] = {93, "AM6_DEV_MCU_ECC_AGGR1"}, + [92] = {94, "AM6_DEV_WKUP_CBASS0"}, + [93] = {95, "AM6_DEV_WKUP_ECC_AGGR0"}, + [94] = {96, "AM6_DEV_WKUP_CBASS_FW0"}, + [95] = {97, "AM6_DEV_MAIN2MCU_LVL_INTRTR0"}, + [96] = {98, "AM6_DEV_MAIN2MCU_PLS_INTRTR0"}, + [97] = {99, "AM6_DEV_CTRL_MMR0"}, + [98] = {100, "AM6_DEV_GPIOMUX_INTRTR0"}, + [99] = {101, "AM6_DEV_PLL_MMR0"}, + [100] = {102, "AM6_DEV_MCU_MCAN0"}, + [101] = {103, "AM6_DEV_MCU_MCAN1"}, + [102] = {104, "AM6_DEV_MCASP0"}, + [103] = {105, "AM6_DEV_MCASP1"}, + [104] = {106, "AM6_DEV_MCASP2"}, + [105] = {107, "AM6_DEV_MCU_CTRL_MMR0"}, + [106] = {108, "AM6_DEV_MCU_PLL_MMR0"}, + [107] = {109, "AM6_DEV_MCU_SEC_MMR0"}, + [108] = {110, "AM6_DEV_I2C0"}, + [109] = {111, "AM6_DEV_I2C1"}, + [110] = {112, "AM6_DEV_I2C2"}, + [111] = {113, "AM6_DEV_I2C3"}, + [112] = {114, "AM6_DEV_MCU_I2C0"}, + [113] = {115, "AM6_DEV_WKUP_I2C0"}, + [114] = {116, "AM6_DEV_MCU_MSRAM0"}, + [115] = {117, "AM6_DEV_DFTSS0"}, + [116] = {118, "AM6_DEV_NAVSS0"}, + [117] = {119, "AM6_DEV_MCU_NAVSS0"}, + [118] = {120, "AM6_DEV_PCIE0"}, + [119] = {121, "AM6_DEV_PCIE1"}, + [120] = {122, "AM6_DEV_PDMA_DEBUG0"}, + [121] = {123, "AM6_DEV_PDMA0"}, + [122] = {124, "AM6_DEV_PDMA1"}, + [123] = {125, "AM6_DEV_MCU_PDMA0"}, + [124] = {126, "AM6_DEV_MCU_PDMA1"}, + [125] = {127, "AM6_DEV_MCU_PSRAM0"}, + [126] = {128, "AM6_DEV_PSRAMECC0"}, + [127] = {129, "AM6_DEV_MCU_ARMSS0"}, + [128] = {130, "AM6_DEV_RTI0"}, + [129] = {131, "AM6_DEV_RTI1"}, + [130] = {132, "AM6_DEV_RTI2"}, + [131] = {133, "AM6_DEV_RTI3"}, + [132] = {134, "AM6_DEV_MCU_RTI0"}, + [133] = {135, "AM6_DEV_MCU_RTI1"}, + [134] = {136, "AM6_DEV_SA2_UL0"}, + [135] = {137, "AM6_DEV_MCSPI0"}, + [136] = {138, "AM6_DEV_MCSPI1"}, + [137] = {139, "AM6_DEV_MCSPI2"}, + [138] = {140, "AM6_DEV_MCSPI3"}, + [139] = {141, "AM6_DEV_MCSPI4"}, + [140] = {142, "AM6_DEV_MCU_MCSPI0"}, + [141] = {143, "AM6_DEV_MCU_MCSPI1"}, + [142] = {144, "AM6_DEV_MCU_MCSPI2"}, + [143] = {145, "AM6_DEV_TIMESYNC_INTRTR0"}, + [144] = {146, "AM6_DEV_UART0"}, + [145] = {147, "AM6_DEV_UART1"}, + [146] = {148, "AM6_DEV_UART2"}, + [147] = {149, "AM6_DEV_MCU_UART0"}, + [148] = {150, "AM6_DEV_WKUP_UART0"}, + [149] = {151, "AM6_DEV_USB3SS0"}, + [150] = {152, "AM6_DEV_USB3SS1"}, + [151] = {153, "AM6_DEV_SERDES0"}, + [152] = {154, "AM6_DEV_SERDES1"}, + [153] = {155, "AM6_DEV_WKUP_CTRL_MMR0"}, + [154] = {156, "AM6_DEV_WKUP_GPIOMUX_INTRTR0"}, + [155] = {157, "AM6_DEV_BOARD0"}, + [156] = {159, "AM6_DEV_MCU_ARMSS0_CPU0"}, + [157] = {161, "AM6_DEV_WKUP_DMSC0_CORTEX_M3_0"}, + [158] = {163, "AM6_DEV_NAVSS0_CPTS0"}, + [159] = {164, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0"}, + [160] = {165, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1"}, + [161] = {166, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2"}, + [162] = {167, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER3"}, + [163] = {168, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER4"}, + [164] = {169, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER5"}, + [165] = {170, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER6"}, + [166] = {171, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER7"}, + [167] = {172, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER8"}, + [168] = {173, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER9"}, + [169] = {174, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10"}, + [170] = {175, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11"}, + [171] = {176, "AM6_DEV_NAVSS0_MCRC0"}, + [172] = {177, "AM6_DEV_NAVSS0_PVU0"}, + [173] = {178, "AM6_DEV_NAVSS0_PVU1"}, + [174] = {179, "AM6_DEV_NAVSS0_UDMASS_INTA0"}, + [175] = {180, "AM6_DEV_NAVSS0_MODSS_INTA0"}, + [176] = {181, "AM6_DEV_NAVSS0_MODSS_INTA1"}, + [177] = {182, "AM6_DEV_NAVSS0_INTR_ROUTER_0"}, + [178] = {183, "AM6_DEV_NAVSS0_TIMER_MGR0"}, + [179] = {184, "AM6_DEV_NAVSS0_TIMER_MGR1"}, + [180] = {185, "AM6_DEV_NAVSS0_PROXY0"}, + [181] = {187, "AM6_DEV_NAVSS0_RINGACC0"}, + [182] = {188, "AM6_DEV_NAVSS0_UDMAP0"}, + [183] = {189, "AM6_DEV_MCU_NAVSS0_INTR_AGGR_0"}, + [184] = {190, "AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0"}, + [185] = {191, "AM6_DEV_MCU_NAVSS0_PROXY0"}, + [186] = {193, "AM6_DEV_MCU_NAVSS0_MCRC0"}, + [187] = {194, "AM6_DEV_MCU_NAVSS0_UDMAP0"}, + [188] = {195, "AM6_DEV_MCU_NAVSS0_RINGACC0"}, + [189] = {196, "AM6_DEV_COMPUTE_CLUSTER_MSMC0"}, + [190] = {197, "AM6_DEV_COMPUTE_CLUSTER_PBIST0"}, + [191] = {198, "AM6_DEV_COMPUTE_CLUSTER_CPAC0"}, + [192] = {199, "AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST0"}, + [193] = {200, "AM6_DEV_COMPUTE_CLUSTER_CPAC1"}, + [194] = {201, "AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST1"}, + [195] = {202, "AM6_DEV_COMPUTE_CLUSTER_A53_0"}, + [196] = {203, "AM6_DEV_COMPUTE_CLUSTER_A53_1"}, + [197] = {204, "AM6_DEV_COMPUTE_CLUSTER_A53_2"}, + [198] = {205, "AM6_DEV_COMPUTE_CLUSTER_A53_3"}, + [199] = {206, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4"}, + [200] = {207, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3"}, + [201] = {208, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0"}, + [202] = {209, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3"}, + [203] = {210, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1"}, + [204] = {211, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5"}, + [205] = {212, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6"}, + [206] = {213, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0"}, + [207] = {214, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2"}, + [208] = {215, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2"}, + [209] = {216, "AM6_DEV_OLDI_TX_CORE_MAIN_0"}, + [210] = {217, "AM6_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0"}, + [211] = {218, "AM6_DEV_ICEMELTER_WKUP_0"}, + [212] = {219, "AM6_DEV_K3_LED_MAIN_0"}, + [213] = {220, "AM6_DEV_VDC_DATA_VBUSM_32B_REF_WKUP2MCU"}, + [214] = {221, "AM6_DEV_VDC_DATA_VBUSM_32B_REF_MCU2WKUP"}, + [215] = {222, "AM6_DEV_VDC_DATA_VBUSM_64B_REF_MAIN2MCU"}, + [216] = {223, "AM6_DEV_VDC_DATA_VBUSM_64B_REF_MCU2MAIN"}, + [217] = {224, "AM6_DEV_VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC"}, + [218] = {225, "AM6_DEV_VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA"}, + [219] = {226, "AM6_DEV_VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA"}, + [220] = {227, "AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU"}, + [221] = {228, "AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN"}, + [222] = {229, "AM6_DEV_VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU"}, + [223] = {230, "AM6_DEV_VDC_NAV_PSIL_128B_REF_MAIN2MCU"}, + [224] = {231, "AM6_DEV_GS80PRG_SOC_WRAP_WKUP_0"}, + [225] = {232, "AM6_DEV_GS80PRG_MCU_WRAP_WKUP_0"}, + [226] = {233, "AM6_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0"}, + [227] = {234, "AM6_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0"}, + [228] = {235, "AM6_DEV_MX_EFUSE_MCU_CHAIN_MCU_0"}, + [229] = {236, "AM6_DEV_DUMMY_IP_LPSC_WKUP2MCU_VD"}, + [230] = {237, "AM6_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA_VD"}, + [231] = {238, "AM6_DEV_DUMMY_IP_LPSC_DEBUG2DMSC_VD"}, + [232] = {239, "AM6_DEV_DUMMY_IP_LPSC_DMSC_VD"}, + [233] = {240, "AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA_VD"}, + [234] = {241, "AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_VD"}, + [235] = {242, "AM6_DEV_DUMMY_IP_LPSC_MCU2WKUP_VD"}, + [236] = {243, "AM6_DEV_DUMMY_IP_LPSC_MAIN2MCU_VD"}, + [237] = {244, "AM6_DEV_DUMMY_IP_LPSC_EMIF_DATA_VD"}, + [238] = {245, "AM6_DEV_MCU_ARMSS0_CPU1"}, + [239] = {246, "AM6_DEV_MCU_FSS0_FSAS_0"}, + [240] = {247, "AM6_DEV_MCU_FSS0_HYPERBUS0"}, + [241] = {248, "AM6_DEV_MCU_FSS0_OSPI_0"}, + [242] = {249, "AM6_DEV_MCU_FSS0_OSPI_1"}, }; diff --git a/soc/am65x/am65x_devices_info.h b/soc/am65x/am65x_devices_info.h new file mode 100644 index 0000000..28caf30 --- /dev/null +++ b/soc/am65x/am65x_devices_info.h @@ -0,0 +1,42 @@ +/* + * AM65X Devices Info + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __AM65X_DEVICES_INFO_H +#define __AM65X_DEVICES_INFO_H + +#define AM65X_MAX_DEVICES 243 + +extern struct ti_sci_devices_info am65x_devices_info[]; + +#endif /* __AM65X_DEVICES_INFO_H */ \ No newline at end of file diff --git a/soc/am65x/am65x_host_info.c b/soc/am65x/am65x_host_info.c index 47684d2..25a23b4 100644 --- a/soc/am65x/am65x_host_info.c +++ b/soc/am65x/am65x_host_info.c @@ -1,7 +1,7 @@ /* - * SoC Host Info + * AM65X Hosts Info * - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -54,4 +54,4 @@ struct ti_sci_host_info am65x_host_info[] = { [15] = {50, "ICSSG_0", "Non Secure", "ICSS Context 0 on Main island"}, [16] = {51, "ICSSG_1", "Non Secure", "ICSS Context 1 on Main island"}, [17] = {52, "ICSSG_2", "Non Secure", "ICSS Context 2 on Main island"}, -}; \ No newline at end of file +}; diff --git a/soc/am65x/am65x_host_info.h b/soc/am65x/am65x_host_info.h new file mode 100644 index 0000000..9f6e196 --- /dev/null +++ b/soc/am65x/am65x_host_info.h @@ -0,0 +1,61 @@ +/* + * AM65X Host Info + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __AM65X_HOST_INFO_H +#define __AM65X_HOST_INFO_H + +#define AM65X_HOST_ID_DMSC 0 +#define AM65X_HOST_ID_R5_0 3 +#define AM65X_HOST_ID_R5_1 4 +#define AM65X_HOST_ID_R5_2 5 +#define AM65X_HOST_ID_R5_3 6 +#define AM65X_HOST_ID_A53_0 10 +#define AM65X_HOST_ID_A53_1 11 +#define AM65X_HOST_ID_A53_2 12 +#define AM65X_HOST_ID_A53_3 13 +#define AM65X_HOST_ID_A53_4 14 +#define AM65X_HOST_ID_A53_5 15 +#define AM65X_HOST_ID_A53_6 16 +#define AM65X_HOST_ID_A53_7 17 +#define AM65X_HOST_ID_GPU_0 30 +#define AM65X_HOST_ID_GPU_1 31 +#define AM65X_HOST_ID_ICSSG_0 50 +#define AM65X_HOST_ID_ICSSG_1 51 +#define AM65X_HOST_ID_ICSSG_2 52 + +#define AM65X_MAX_HOST_IDS 18 + +extern struct ti_sci_host_info am65x_host_info[]; + +#endif /* __AM65X_HOST_INFO_H */ \ No newline at end of file diff --git a/soc/am65x/am65x_processors_info.h b/soc/am65x/am65x_processors_info.h new file mode 100644 index 0000000..59cd6d5 --- /dev/null +++ b/soc/am65x/am65x_processors_info.h @@ -0,0 +1,41 @@ +/* + * AM65X Processor Info + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __AM65X_PROCESSOR_INFO_H +#define __AM65X_PROCESSOR_INFO_H + +#define AM65X_MAX_PROCESSORS_IDS 6 +extern struct ti_sci_processors_info am65x_processors_info[]; + +#endif /* __AM65X_PROCESSOR_INFO_H */ \ No newline at end of file diff --git a/soc/am65x/am65x_sec_proxy_info.c b/soc/am65x/am65x_sec_proxy_info.c index a21f65d..f93a371 100644 --- a/soc/am65x/am65x_sec_proxy_info.c +++ b/soc/am65x/am65x_sec_proxy_info.c @@ -1,7 +1,7 @@ /* - * SoC Sec Proxy Info + * AM65X Sec Proxy Info * - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -36,92 +36,92 @@ #include struct ti_sci_sec_proxy_info am65x_main_sp_info[] = { - [0] = {0, "read", 2, "A53_0", "notify"}, - [1] = {1, "read", 30, "A53_0", "response"}, - [2] = {2, "write", 10, "A53_0", "high_priority"}, - [3] = {3, "write", 20, "A53_0", "low_priority"}, - [4] = {4, "write", 2, "A53_0", "notify_resp"}, - [5] = {5, "read", 2, "A53_1", "notify"}, - [6] = {6, "read", 30, "A53_1", "response"}, - [7] = {7, "write", 10, "A53_1", "high_priority"}, - [8] = {8, "write", 20, "A53_1", "low_priority"}, - [9] = {9, "write", 2, "A53_1", "notify_resp"}, - [10] = {10, "read", 2, "A53_2", "notify"}, - [11] = {11, "read", 22, "A53_2", "response"}, - [12] = {12, "write", 2, "A53_2", "high_priority"}, - [13] = {13, "write", 20, "A53_2", "low_priority"}, - [14] = {14, "write", 2, "A53_2", "notify_resp"}, - [15] = {15, "read", 2, "A53_3", "notify"}, - [16] = {16, "read", 7, "A53_3", "response"}, - [17] = {17, "write", 2, "A53_3", "high_priority"}, - [18] = {18, "write", 5, "A53_3", "low_priority"}, - [19] = {19, "write", 2, "A53_3", "notify_resp"}, - [20] = {20, "read", 2, "A53_4", "notify"}, - [21] = {21, "read", 5, "A53_4", "response"}, - [22] = {22, "write", 2, "A53_4", "high_priority"}, - [23] = {23, "write", 5, "A53_4", "low_priority"}, - [24] = {24, "write", 2, "A53_4", "notify_resp"}, - [25] = {25, "read", 2, "A53_5", "notify"}, - [26] = {26, "read", 5, "A53_5", "response"}, - [27] = {27, "write", 2, "A53_5", "high_priority"}, - [28] = {28, "write", 5, "A53_5", "low_priority"}, - [29] = {29, "write", 2, "A53_5", "notify_resp"}, - [30] = {30, "read", 2, "A53_6", "notify"}, - [31] = {31, "read", 5, "A53_6", "response"}, - [32] = {32, "write", 2, "A53_6", "high_priority"}, - [33] = {33, "write", 5, "A53_6", "low_priority"}, - [34] = {34, "write", 2, "A53_6", "notify_resp"}, - [35] = {35, "read", 2, "A53_7", "notify"}, - [36] = {36, "read", 5, "A53_7", "response"}, - [37] = {37, "write", 2, "A53_7", "high_priority"}, - [38] = {38, "write", 5, "A53_7", "low_priority"}, - [39] = {39, "write", 2, "A53_7", "notify_resp"}, - [40] = {40, "read", 2, "ICSSG_0", "notify"}, - [41] = {41, "read", 7, "ICSSG_0", "response"}, - [42] = {42, "write", 2, "ICSSG_0", "high_priority"}, - [43] = {43, "write", 5, "ICSSG_0", "low_priority"}, - [44] = {44, "write", 2, "ICSSG_0", "notify_resp"}, - [45] = {45, "read", 2, "ICSSG_1", "notify"}, - [46] = {46, "read", 4, "ICSSG_1", "response"}, - [47] = {47, "write", 2, "ICSSG_1", "high_priority"}, - [48] = {48, "write", 2, "ICSSG_1", "low_priority"}, - [49] = {49, "write", 2, "ICSSG_1", "notify_resp"}, - [50] = {50, "read", 2, "ICSSG_2", "notify"}, - [51] = {51, "read", 4, "ICSSG_2", "response"}, - [52] = {52, "write", 2, "ICSSG_2", "high_priority"}, - [53] = {53, "write", 2, "ICSSG_2", "low_priority"}, - [54] = {54, "write", 2, "ICSSG_2", "notify_resp"}, - [55] = {55, "read", 2, "GPU_0", "notify"}, - [56] = {56, "read", 7, "GPU_0", "response"}, - [57] = {57, "write", 2, "GPU_0", "high_priority"}, - [58] = {58, "write", 5, "GPU_0", "low_priority"}, - [59] = {59, "write", 2, "GPU_0", "notify_resp"}, - [60] = {60, "read", 2, "GPU_1", "notify"}, - [61] = {61, "read", 5, "GPU_1", "response"}, - [62] = {62, "write", 2, "GPU_1", "high_priority"}, - [63] = {63, "write", 3, "GPU_1", "low_priority"}, - [64] = {64, "write", 2, "GPU_1", "notify_resp"}, + [0] = {0, "read", 2, "A53_0", "notify"}, + [1] = {1, "read", 30, "A53_0", "response"}, + [2] = {2, "write", 10, "A53_0", "high_priority"}, + [3] = {3, "write", 20, "A53_0", "low_priority"}, + [4] = {4, "write", 2, "A53_0", "notify_resp"}, + [5] = {5, "read", 2, "A53_1", "notify"}, + [6] = {6, "read", 30, "A53_1", "response"}, + [7] = {7, "write", 10, "A53_1", "high_priority"}, + [8] = {8, "write", 20, "A53_1", "low_priority"}, + [9] = {9, "write", 2, "A53_1", "notify_resp"}, + [10] = {10, "read", 2, "A53_2", "notify"}, + [11] = {11, "read", 22, "A53_2", "response"}, + [12] = {12, "write", 2, "A53_2", "high_priority"}, + [13] = {13, "write", 20, "A53_2", "low_priority"}, + [14] = {14, "write", 2, "A53_2", "notify_resp"}, + [15] = {15, "read", 2, "A53_3", "notify"}, + [16] = {16, "read", 7, "A53_3", "response"}, + [17] = {17, "write", 2, "A53_3", "high_priority"}, + [18] = {18, "write", 5, "A53_3", "low_priority"}, + [19] = {19, "write", 2, "A53_3", "notify_resp"}, + [20] = {20, "read", 2, "A53_4", "notify"}, + [21] = {21, "read", 5, "A53_4", "response"}, + [22] = {22, "write", 2, "A53_4", "high_priority"}, + [23] = {23, "write", 5, "A53_4", "low_priority"}, + [24] = {24, "write", 2, "A53_4", "notify_resp"}, + [25] = {25, "read", 2, "A53_5", "notify"}, + [26] = {26, "read", 5, "A53_5", "response"}, + [27] = {27, "write", 2, "A53_5", "high_priority"}, + [28] = {28, "write", 5, "A53_5", "low_priority"}, + [29] = {29, "write", 2, "A53_5", "notify_resp"}, + [30] = {30, "read", 2, "A53_6", "notify"}, + [31] = {31, "read", 5, "A53_6", "response"}, + [32] = {32, "write", 2, "A53_6", "high_priority"}, + [33] = {33, "write", 5, "A53_6", "low_priority"}, + [34] = {34, "write", 2, "A53_6", "notify_resp"}, + [35] = {35, "read", 2, "A53_7", "notify"}, + [36] = {36, "read", 5, "A53_7", "response"}, + [37] = {37, "write", 2, "A53_7", "high_priority"}, + [38] = {38, "write", 5, "A53_7", "low_priority"}, + [39] = {39, "write", 2, "A53_7", "notify_resp"}, + [40] = {40, "read", 2, "ICSSG_0", "notify"}, + [41] = {41, "read", 7, "ICSSG_0", "response"}, + [42] = {42, "write", 2, "ICSSG_0", "high_priority"}, + [43] = {43, "write", 5, "ICSSG_0", "low_priority"}, + [44] = {44, "write", 2, "ICSSG_0", "notify_resp"}, + [45] = {45, "read", 2, "ICSSG_1", "notify"}, + [46] = {46, "read", 4, "ICSSG_1", "response"}, + [47] = {47, "write", 2, "ICSSG_1", "high_priority"}, + [48] = {48, "write", 2, "ICSSG_1", "low_priority"}, + [49] = {49, "write", 2, "ICSSG_1", "notify_resp"}, + [50] = {50, "read", 2, "ICSSG_2", "notify"}, + [51] = {51, "read", 4, "ICSSG_2", "response"}, + [52] = {52, "write", 2, "ICSSG_2", "high_priority"}, + [53] = {53, "write", 2, "ICSSG_2", "low_priority"}, + [54] = {54, "write", 2, "ICSSG_2", "notify_resp"}, + [55] = {55, "read", 2, "GPU_0", "notify"}, + [56] = {56, "read", 7, "GPU_0", "response"}, + [57] = {57, "write", 2, "GPU_0", "high_priority"}, + [58] = {58, "write", 5, "GPU_0", "low_priority"}, + [59] = {59, "write", 2, "GPU_0", "notify_resp"}, + [60] = {60, "read", 2, "GPU_1", "notify"}, + [61] = {61, "read", 5, "GPU_1", "response"}, + [62] = {62, "write", 2, "GPU_1", "high_priority"}, + [63] = {63, "write", 3, "GPU_1", "low_priority"}, + [64] = {64, "write", 2, "GPU_1", "notify_resp"}, }; struct ti_sci_sec_proxy_info am65x_mcu_sp_info[] = { - [0] = {0, "read", 2, "R5_0", "notify"}, - [1] = {1, "read", 7, "R5_0", "response"}, - [2] = {2, "write", 2, "R5_0", "high_priority"}, - [3] = {3, "write", 5, "R5_0", "low_priority"}, - [4] = {4, "write", 2, "R5_0", "notify_resp"}, - [5] = {5, "read", 2, "R5_1", "notify"}, - [6] = {6, "read", 7, "R5_1", "response"}, - [7] = {7, "write", 2, "R5_1", "high_priority"}, - [8] = {8, "write", 5, "R5_1", "low_priority"}, - [9] = {9, "write", 2, "R5_1", "notify_resp"}, - [10] = {10, "read", 1, "R5_2", "notify"}, - [11] = {11, "read", 2, "R5_2", "response"}, - [12] = {12, "write", 1, "R5_2", "high_priority"}, - [13] = {13, "write", 1, "R5_2", "low_priority"}, - [14] = {14, "write", 1, "R5_2", "notify_resp"}, - [15] = {15, "read", 1, "R5_3", "notify"}, - [16] = {16, "read", 2, "R5_3", "response"}, - [17] = {17, "write", 1, "R5_3", "high_priority"}, - [18] = {18, "write", 1, "R5_3", "low_priority"}, - [19] = {19, "write", 1, "R5_3", "notify_resp"}, + [0] = {0, "read", 2, "R5_0", "notify"}, + [1] = {1, "read", 7, "R5_0", "response"}, + [2] = {2, "write", 2, "R5_0", "high_priority"}, + [3] = {3, "write", 5, "R5_0", "low_priority"}, + [4] = {4, "write", 2, "R5_0", "notify_resp"}, + [5] = {5, "read", 2, "R5_1", "notify"}, + [6] = {6, "read", 7, "R5_1", "response"}, + [7] = {7, "write", 2, "R5_1", "high_priority"}, + [8] = {8, "write", 5, "R5_1", "low_priority"}, + [9] = {9, "write", 2, "R5_1", "notify_resp"}, + [10] = {10, "read", 1, "R5_2", "notify"}, + [11] = {11, "read", 2, "R5_2", "response"}, + [12] = {12, "write", 1, "R5_2", "high_priority"}, + [13] = {13, "write", 1, "R5_2", "low_priority"}, + [14] = {14, "write", 1, "R5_2", "notify_resp"}, + [15] = {15, "read", 1, "R5_3", "notify"}, + [16] = {16, "read", 2, "R5_3", "response"}, + [17] = {17, "write", 1, "R5_3", "high_priority"}, + [18] = {18, "write", 1, "R5_3", "low_priority"}, + [19] = {19, "write", 1, "R5_3", "notify_resp"}, }; diff --git a/soc/am65x/am65x_sec_proxy_info.h b/soc/am65x/am65x_sec_proxy_info.h new file mode 100644 index 0000000..df956af --- /dev/null +++ b/soc/am65x/am65x_sec_proxy_info.h @@ -0,0 +1,44 @@ +/* + * AM65X Sec Proxy Info + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __AM65X_SEC_PROXY_INFO_H +#define __AM65X_SEC_PROXY_INFO_H + +#define AM65X_MAIN_SEC_PROXY_THREADS 65 +#define AM65X_MCU_SEC_PROXY_THREADS 20 + +extern struct ti_sci_sec_proxy_info am65x_main_sp_info[]; +extern struct ti_sci_sec_proxy_info am65x_mcu_sp_info[]; + +#endif /* __AM65X_SEC_PROXY_INFO_H */ \ No newline at end of file