From: Lokesh Vutla Date: Wed, 11 Nov 2020 15:34:19 +0000 (+0530) Subject: soc: am64x: Add clocks info X-Git-Tag: v0.2~3 X-Git-Url: https://git.ti.com/gitweb?p=k3conf%2Fk3conf.git;a=commitdiff_plain;h=a431db20940583528f15dbc34f0fee23efd27ff5;ds=sidebyside soc: am64x: Add clocks info Add TISCI Clocks info for AM64x devices. Data based on sysfw v2020.08b. Also assign this data to sci_info based on SoC detection. Signed-off-by: Lokesh Vutla --- diff --git a/Makefile b/Makefile index 39131a8..c532dd5 100644 --- a/Makefile +++ b/Makefile @@ -107,6 +107,7 @@ AM64XSOURCES =\ soc/am64x/am64x_sec_proxy_info.c \ soc/am64x/am64x_processors_info.c \ soc/am64x/am64x_devices_info.c \ + soc/am64x/am64x_clocks_info.c \ COMMONOBJECTS= $(COMMONSOURCES:.c=.o) AM65XOBJECTS= $(AM65XSOURCES:.c=.o) diff --git a/common/socinfo.c b/common/socinfo.c index 5a57f11..e74e5eb 100644 --- a/common/socinfo.c +++ b/common/socinfo.c @@ -65,6 +65,7 @@ #include #include #include +#include /* Assuming these addresses and definitions stay common across K3 devices */ #define CTRLMMR_WKUP_JTAG_DEVICE_ID 0x43000018 @@ -200,6 +201,8 @@ static void am64x_init(void) sci_info->num_processors = AM64X_MAX_PROCESSORS_IDS; sci_info->devices_info = am64x_devices_info; sci_info->num_devices = AM64X_MAX_DEVICES; + sci_info->clocks_info = am64x_clocks_info; + sci_info->num_clocks = AM64X_MAX_CLOCKS; soc_info.host_id = 13; soc_info.sec_proxy = &k3_lite_sec_proxy_base; } diff --git a/soc/am64x/am64x_clocks_info.c b/soc/am64x/am64x_clocks_info.c new file mode 100644 index 0000000..2916d3e --- /dev/null +++ b/soc/am64x/am64x_clocks_info.c @@ -0,0 +1,989 @@ +/* + * AM64X Clocks Info + * + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +struct ti_sci_clocks_info am64x_clocks_info[] = { + [0] = {137, 0, "DEV_A53SS0_COREPAC_ARM_CLK_CLK", "Input clock"}, + [1] = {137, 1, "DEV_A53SS0_PLL_CTRL_CLK", "Input clock"}, + [2] = {137, 2, "DEV_A53SS0_A53_DIVH_CLK4_OBSCLK_OUT_CLK", "Output clock"}, + [3] = {135, 0, "DEV_A53SS0_CORE_0_A53_CORE0_ARM_CLK_CLK", "Input clock"}, + [4] = {136, 0, "DEV_A53SS0_CORE_1_A53_CORE1_ARM_CLK_CLK", "Input clock"}, + [5] = {0, 0, "DEV_ADC0_ADC_CLK", "Input muxed clock"}, + [6] = {0, 1, "DEV_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_ADC0_ADC_CLK"}, + [7] = {0, 2, "DEV_ADC0_ADC_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_ADC0_ADC_CLK"}, + [8] = {0, 3, "DEV_ADC0_ADC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_ADC0_ADC_CLK"}, + [9] = {0, 4, "DEV_ADC0_ADC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ADC0_ADC_CLK"}, + [10] = {0, 5, "DEV_ADC0_SYS_CLK", "Input clock"}, + [11] = {0, 6, "DEV_ADC0_VBUS_CLK", "Input clock"}, + [12] = {157, 0, "DEV_BOARD0_FSI_TX0_CLK_IN", "Input clock"}, + [13] = {157, 1, "DEV_BOARD0_FSI_TX1_CLK_IN", "Input clock"}, + [14] = {157, 2, "DEV_BOARD0_GPMC0_CLKLB_IN", "Input clock"}, + [15] = {157, 3, "DEV_BOARD0_GPMC0_CLK_IN", "Input clock"}, + [16] = {157, 4, "DEV_BOARD0_GPMC0_FCLK_MUX_IN", "Input muxed clock"}, + [17] = {157, 5, "DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_BOARD0_GPMC0_FCLK_MUX_IN"}, + [18] = {157, 6, "DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK", "Parent input clock option to DEV_BOARD0_GPMC0_FCLK_MUX_IN"}, + [19] = {157, 7, "DEV_BOARD0_I2C0_SCL_IN", "Input clock"}, + [20] = {157, 8, "DEV_BOARD0_I2C1_SCL_IN", "Input clock"}, + [21] = {157, 9, "DEV_BOARD0_I2C2_SCL_IN", "Input clock"}, + [22] = {157, 10, "DEV_BOARD0_I2C3_SCL_IN", "Input clock"}, + [23] = {157, 11, "DEV_BOARD0_MCU_I2C0_SCL_IN", "Input clock"}, + [24] = {157, 12, "DEV_BOARD0_MCU_I2C1_SCL_IN", "Input clock"}, + [25] = {157, 13, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"}, + [26] = {157, 14, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, + [27] = {157, 15, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, + [28] = {157, 16, "DEV_BOARD0_MCU_SPI0_CLK_IN", "Input clock"}, + [29] = {157, 17, "DEV_BOARD0_MCU_SPI1_CLK_IN", "Input clock"}, + [30] = {157, 18, "DEV_BOARD0_MCU_SYSCLKOUT0_IN", "Input clock"}, + [31] = {157, 19, "DEV_BOARD0_MCU_TIMER_IO0_IN", "Input clock"}, + [32] = {157, 20, "DEV_BOARD0_MCU_TIMER_IO1_IN", "Input clock"}, + [33] = {157, 21, "DEV_BOARD0_MCU_TIMER_IO2_IN", "Input clock"}, + [34] = {157, 22, "DEV_BOARD0_MCU_TIMER_IO3_IN", "Input clock"}, + [35] = {157, 23, "DEV_BOARD0_MMC1_CLK_IN", "Input clock"}, + [36] = {157, 24, "DEV_BOARD0_OBSCLK0_IN", "Input clock"}, + [37] = {157, 25, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, + [38] = {157, 26, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, + [39] = {157, 27, "DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, + [40] = {157, 28, "DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, + [41] = {157, 29, "DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, + [42] = {157, 30, "DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, + [43] = {157, 31, "DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, + [44] = {157, 32, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, + [45] = {157, 33, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, + [46] = {157, 34, "DEV_BOARD0_OBSCLK0_IN_PARENT_SAM64_A53_256KB_WRAP_MAIN_0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSCLK_OUT_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, + [47] = {157, 35, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, + [48] = {157, 36, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, + [49] = {157, 37, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, + [50] = {157, 38, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, + [51] = {157, 39, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, + [52] = {157, 40, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, + [53] = {157, 41, "DEV_BOARD0_OSPI0_LBCLKO_IN", "Input clock"}, + [54] = {157, 42, "DEV_BOARD0_PRG0_MDIO0_MDC_IN", "Input clock"}, + [55] = {157, 43, "DEV_BOARD0_PRG0_RGMII1_TXC_IN", "Input clock"}, + [56] = {157, 44, "DEV_BOARD0_PRG0_RGMII2_TXC_IN", "Input clock"}, + [57] = {157, 45, "DEV_BOARD0_PRG1_MDIO0_MDC_IN", "Input clock"}, + [58] = {157, 46, "DEV_BOARD0_PRG1_RGMII1_TXC_IN", "Input clock"}, + [59] = {157, 47, "DEV_BOARD0_PRG1_RGMII2_TXC_IN", "Input clock"}, + [60] = {157, 48, "DEV_BOARD0_RGMII1_TXC_IN", "Input clock"}, + [61] = {157, 49, "DEV_BOARD0_RGMII2_TXC_IN", "Input clock"}, + [62] = {157, 50, "DEV_BOARD0_SPI0_CLK_IN", "Input clock"}, + [63] = {157, 51, "DEV_BOARD0_SPI1_CLK_IN", "Input clock"}, + [64] = {157, 52, "DEV_BOARD0_SPI2_CLK_IN", "Input clock"}, + [65] = {157, 53, "DEV_BOARD0_SPI3_CLK_IN", "Input clock"}, + [66] = {157, 54, "DEV_BOARD0_SPI4_CLK_IN", "Input clock"}, + [67] = {157, 55, "DEV_BOARD0_SYSCLKOUT0_IN", "Input clock"}, + [68] = {157, 56, "DEV_BOARD0_TIMER_IO0_IN", "Input clock"}, + [69] = {157, 57, "DEV_BOARD0_TIMER_IO10_IN", "Input clock"}, + [70] = {157, 58, "DEV_BOARD0_TIMER_IO11_IN", "Input clock"}, + [71] = {157, 59, "DEV_BOARD0_TIMER_IO1_IN", "Input clock"}, + [72] = {157, 60, "DEV_BOARD0_TIMER_IO2_IN", "Input clock"}, + [73] = {157, 61, "DEV_BOARD0_TIMER_IO3_IN", "Input clock"}, + [74] = {157, 62, "DEV_BOARD0_TIMER_IO4_IN", "Input clock"}, + [75] = {157, 63, "DEV_BOARD0_TIMER_IO5_IN", "Input clock"}, + [76] = {157, 64, "DEV_BOARD0_TIMER_IO6_IN", "Input clock"}, + [77] = {157, 65, "DEV_BOARD0_TIMER_IO7_IN", "Input clock"}, + [78] = {157, 66, "DEV_BOARD0_TIMER_IO8_IN", "Input clock"}, + [79] = {157, 67, "DEV_BOARD0_TIMER_IO9_IN", "Input clock"}, + [80] = {157, 68, "DEV_BOARD0_CPTS0_RFT_CLK_OUT", "Output clock"}, + [81] = {157, 69, "DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Output clock"}, + [82] = {157, 70, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"}, + [83] = {157, 71, "DEV_BOARD0_FSI_RX0_CLK_OUT", "Output clock"}, + [84] = {157, 72, "DEV_BOARD0_FSI_RX1_CLK_OUT", "Output clock"}, + [85] = {157, 73, "DEV_BOARD0_FSI_RX2_CLK_OUT", "Output clock"}, + [86] = {157, 74, "DEV_BOARD0_FSI_RX3_CLK_OUT", "Output clock"}, + [87] = {157, 75, "DEV_BOARD0_FSI_RX4_CLK_OUT", "Output clock"}, + [88] = {157, 76, "DEV_BOARD0_FSI_RX5_CLK_OUT", "Output clock"}, + [89] = {157, 77, "DEV_BOARD0_GPMC0_CLKLB_OUT", "Output clock"}, + [90] = {157, 78, "DEV_BOARD0_I2C0_SCL_OUT", "Output clock"}, + [91] = {157, 79, "DEV_BOARD0_I2C1_SCL_OUT", "Output clock"}, + [92] = {157, 80, "DEV_BOARD0_I2C2_SCL_OUT", "Output clock"}, + [93] = {157, 81, "DEV_BOARD0_I2C3_SCL_OUT", "Output clock"}, + [94] = {157, 82, "DEV_BOARD0_LED_CLK_OUT", "Output clock"}, + [95] = {157, 83, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"}, + [96] = {157, 84, "DEV_BOARD0_MCU_I2C0_SCL_OUT", "Output clock"}, + [97] = {157, 85, "DEV_BOARD0_MCU_I2C1_SCL_OUT", "Output clock"}, + [98] = {157, 86, "DEV_BOARD0_MCU_SPI0_CLK_OUT", "Output clock"}, + [99] = {157, 87, "DEV_BOARD0_MCU_SPI1_CLK_OUT", "Output clock"}, + [100] = {157, 88, "DEV_BOARD0_MMC1_CLKLB_OUT", "Output clock"}, + [101] = {157, 89, "DEV_BOARD0_OSPI0_DQS_OUT", "Output clock"}, + [102] = {157, 90, "DEV_BOARD0_OSPI0_LBCLKO_OUT", "Output clock"}, + [103] = {157, 91, "DEV_BOARD0_PRG0_RGMII1_RXC_OUT", "Output clock"}, + [104] = {157, 92, "DEV_BOARD0_PRG0_RGMII1_TXC_OUT", "Output clock"}, + [105] = {157, 93, "DEV_BOARD0_PRG0_RGMII2_RXC_OUT", "Output clock"}, + [106] = {157, 94, "DEV_BOARD0_PRG0_RGMII2_TXC_OUT", "Output clock"}, + [107] = {157, 95, "DEV_BOARD0_PRG1_RGMII1_RXC_OUT", "Output clock"}, + [108] = {157, 96, "DEV_BOARD0_PRG1_RGMII1_TXC_OUT", "Output clock"}, + [109] = {157, 97, "DEV_BOARD0_PRG1_RGMII2_RXC_OUT", "Output clock"}, + [110] = {157, 98, "DEV_BOARD0_PRG1_RGMII2_TXC_OUT", "Output clock"}, + [111] = {157, 99, "DEV_BOARD0_RGMII1_RXC_OUT", "Output clock"}, + [112] = {157, 100, "DEV_BOARD0_RGMII1_TXC_OUT", "Output clock"}, + [113] = {157, 101, "DEV_BOARD0_RGMII2_RXC_OUT", "Output clock"}, + [114] = {157, 102, "DEV_BOARD0_RGMII2_TXC_OUT", "Output clock"}, + [115] = {157, 103, "DEV_BOARD0_RMII_REF_CLK_OUT", "Output clock"}, + [116] = {157, 104, "DEV_BOARD0_SPI0_CLK_OUT", "Output clock"}, + [117] = {157, 105, "DEV_BOARD0_SPI1_CLK_OUT", "Output clock"}, + [118] = {157, 106, "DEV_BOARD0_SPI2_CLK_OUT", "Output clock"}, + [119] = {157, 107, "DEV_BOARD0_SPI3_CLK_OUT", "Output clock"}, + [120] = {157, 108, "DEV_BOARD0_SPI4_CLK_OUT", "Output clock"}, + [121] = {157, 109, "DEV_BOARD0_TCK_OUT", "Output clock"}, + [122] = {1, 0, "DEV_CMP_EVENT_INTROUTER0_INTR_CLK", "Input clock"}, + [123] = {13, 0, "DEV_CPSW0_CPPI_CLK_CLK", "Input clock"}, + [124] = {13, 1, "DEV_CPSW0_CPTS_RFT_CLK", "Input muxed clock"}, + [125] = {13, 2, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [126] = {13, 3, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [127] = {13, 4, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [128] = {13, 5, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [129] = {13, 6, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [130] = {13, 7, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [131] = {13, 8, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [132] = {13, 9, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [133] = {13, 10, "DEV_CPSW0_GMII1_MR_CLK", "Input clock"}, + [134] = {13, 11, "DEV_CPSW0_GMII1_MT_CLK", "Input clock"}, + [135] = {13, 12, "DEV_CPSW0_GMII2_MR_CLK", "Input clock"}, + [136] = {13, 13, "DEV_CPSW0_GMII2_MT_CLK", "Input clock"}, + [137] = {13, 14, "DEV_CPSW0_GMII_RFT_CLK", "Input clock"}, + [138] = {13, 15, "DEV_CPSW0_RGMII1_RXC_I", "Input clock"}, + [139] = {13, 16, "DEV_CPSW0_RGMII1_TXC_I", "Input clock"}, + [140] = {13, 17, "DEV_CPSW0_RGMII2_RXC_I", "Input clock"}, + [141] = {13, 18, "DEV_CPSW0_RGMII2_TXC_I", "Input clock"}, + [142] = {13, 19, "DEV_CPSW0_RGMII_MHZ_250_CLK", "Input clock"}, + [143] = {13, 20, "DEV_CPSW0_RGMII_MHZ_50_CLK", "Input clock"}, + [144] = {13, 21, "DEV_CPSW0_RGMII_MHZ_5_CLK", "Input clock"}, + [145] = {13, 22, "DEV_CPSW0_RMII_MHZ_50_CLK", "Input clock"}, + [146] = {13, 23, "DEV_CPSW0_CPTS_GENF0", "Output clock"}, + [147] = {13, 24, "DEV_CPSW0_CPTS_GENF1", "Output clock"}, + [148] = {13, 25, "DEV_CPSW0_RGMII1_TXC_O", "Output clock"}, + [149] = {13, 26, "DEV_CPSW0_RGMII2_TXC_O", "Output clock"}, + [150] = {14, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"}, + [151] = {84, 0, "DEV_CPTS0_CPTS_RFT_CLK", "Input muxed clock"}, + [152] = {84, 1, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"}, + [153] = {84, 2, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"}, + [154] = {84, 3, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"}, + [155] = {84, 4, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"}, + [156] = {84, 5, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"}, + [157] = {84, 6, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"}, + [158] = {84, 7, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"}, + [159] = {84, 8, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"}, + [160] = {84, 9, "DEV_CPTS0_VBUSP_CLK", "Input clock"}, + [161] = {84, 10, "DEV_CPTS0_CPTS_GENF1", "Output clock"}, + [162] = {84, 11, "DEV_CPTS0_CPTS_GENF2", "Output clock"}, + [163] = {84, 12, "DEV_CPTS0_CPTS_GENF3", "Output clock"}, + [164] = {84, 13, "DEV_CPTS0_CPTS_GENF4", "Output clock"}, + [165] = {2, 0, "DEV_DBGSUSPENDROUTER0_INTR_CLK", "Input clock"}, + [166] = {16, 0, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, + [167] = {16, 1, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, + [168] = {16, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, + [169] = {16, 3, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, + [170] = {16, 4, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, + [171] = {16, 5, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, + [172] = {16, 6, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, + [173] = {16, 7, "DEV_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, + [174] = {16, 8, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"}, + [175] = {16, 9, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"}, + [176] = {16, 10, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"}, + [177] = {16, 11, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"}, + [178] = {16, 12, "DEV_DCC0_VBUS_CLK", "Input clock"}, + [179] = {17, 0, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"}, + [180] = {17, 1, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"}, + [181] = {17, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"}, + [182] = {17, 3, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"}, + [183] = {17, 4, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"}, + [184] = {17, 5, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"}, + [185] = {17, 6, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"}, + [186] = {17, 7, "DEV_DCC1_DCC_CLKSRC7_CLK", "Input clock"}, + [187] = {17, 8, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"}, + [188] = {17, 9, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"}, + [189] = {17, 10, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"}, + [190] = {17, 11, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"}, + [191] = {17, 12, "DEV_DCC1_VBUS_CLK", "Input clock"}, + [192] = {18, 0, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"}, + [193] = {18, 1, "DEV_DCC2_DCC_CLKSRC1_CLK", "Input clock"}, + [194] = {18, 2, "DEV_DCC2_DCC_CLKSRC2_CLK", "Input clock"}, + [195] = {18, 3, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"}, + [196] = {18, 4, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"}, + [197] = {18, 5, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"}, + [198] = {18, 6, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"}, + [199] = {18, 7, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"}, + [200] = {18, 8, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"}, + [201] = {18, 9, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"}, + [202] = {18, 10, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"}, + [203] = {18, 11, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"}, + [204] = {18, 12, "DEV_DCC2_VBUS_CLK", "Input clock"}, + [205] = {19, 0, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"}, + [206] = {19, 1, "DEV_DCC3_DCC_CLKSRC1_CLK", "Input clock"}, + [207] = {19, 2, "DEV_DCC3_DCC_CLKSRC2_CLK", "Input clock"}, + [208] = {19, 3, "DEV_DCC3_DCC_CLKSRC3_CLK", "Input clock"}, + [209] = {19, 4, "DEV_DCC3_DCC_CLKSRC4_CLK", "Input clock"}, + [210] = {19, 5, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"}, + [211] = {19, 6, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"}, + [212] = {19, 7, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"}, + [213] = {19, 8, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"}, + [214] = {19, 9, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"}, + [215] = {19, 10, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"}, + [216] = {19, 11, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"}, + [217] = {19, 12, "DEV_DCC3_VBUS_CLK", "Input clock"}, + [218] = {20, 0, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input muxed clock"}, + [219] = {20, 1, "DEV_DCC4_DCC_CLKSRC0_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_DCC4_DCC_CLKSRC0_CLK"}, + [220] = {20, 2, "DEV_DCC4_DCC_CLKSRC0_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK", "Parent input clock option to DEV_DCC4_DCC_CLKSRC0_CLK"}, + [221] = {20, 3, "DEV_DCC4_DCC_CLKSRC1_CLK", "Input clock"}, + [222] = {20, 4, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"}, + [223] = {20, 5, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"}, + [224] = {20, 6, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"}, + [225] = {20, 7, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"}, + [226] = {20, 8, "DEV_DCC4_DCC_CLKSRC6_CLK", "Input clock"}, + [227] = {20, 9, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"}, + [228] = {20, 10, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"}, + [229] = {20, 11, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"}, + [230] = {20, 12, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"}, + [231] = {20, 13, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"}, + [232] = {20, 14, "DEV_DCC4_VBUS_CLK", "Input clock"}, + [233] = {21, 0, "DEV_DCC5_DCC_CLKSRC0_CLK", "Input clock"}, + [234] = {21, 1, "DEV_DCC5_DCC_CLKSRC1_CLK", "Input clock"}, + [235] = {21, 2, "DEV_DCC5_DCC_CLKSRC2_CLK", "Input clock"}, + [236] = {21, 3, "DEV_DCC5_DCC_CLKSRC3_CLK", "Input clock"}, + [237] = {21, 4, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"}, + [238] = {21, 5, "DEV_DCC5_DCC_CLKSRC5_CLK", "Input clock"}, + [239] = {21, 6, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"}, + [240] = {21, 7, "DEV_DCC5_DCC_CLKSRC7_CLK", "Input clock"}, + [241] = {21, 8, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"}, + [242] = {21, 9, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"}, + [243] = {21, 10, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"}, + [244] = {21, 11, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"}, + [245] = {21, 12, "DEV_DCC5_VBUS_CLK", "Input clock"}, + [246] = {85, 0, "DEV_DDPA0_DDPA_CLK", "Input clock"}, + [247] = {138, 0, "DEV_DDR16SS0_DDRSS_DDR_PLL_CLK", "Input clock"}, + [248] = {138, 1, "DEV_DDR16SS0_PLL_CTRL_CLK", "Input clock"}, + [249] = {24, 0, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"}, + [250] = {24, 1, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"}, + [251] = {24, 2, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"}, + [252] = {24, 3, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"}, + [253] = {26, 0, "DEV_DMASS0_BCDMA_0_CLK", "Input clock"}, + [254] = {27, 0, "DEV_DMASS0_CBASS_0_CLK", "Input clock"}, + [255] = {28, 0, "DEV_DMASS0_INTAGGR_0_CLK", "Input clock"}, + [256] = {29, 0, "DEV_DMASS0_IPCSS_0_CLK", "Input clock"}, + [257] = {30, 0, "DEV_DMASS0_PKTDMA_0_CLK", "Input clock"}, + [258] = {31, 0, "DEV_DMASS0_PSILCFG_0_CLK", "Input clock"}, + [259] = {32, 0, "DEV_DMASS0_PSILSS_0_PDMA_MAIN0_CLK", "Input clock"}, + [260] = {32, 1, "DEV_DMASS0_PSILSS_0_PDMA_MAIN1_CLK", "Input clock"}, + [261] = {32, 2, "DEV_DMASS0_PSILSS_0_VD2CLK", "Input clock"}, + [262] = {33, 0, "DEV_DMASS0_RINGACC_0_CLK", "Input clock"}, + [263] = {51, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"}, + [264] = {52, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"}, + [265] = {53, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"}, + [266] = {54, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"}, + [267] = {86, 0, "DEV_EPWM0_VBUSP_CLK", "Input clock"}, + [268] = {87, 0, "DEV_EPWM1_VBUSP_CLK", "Input clock"}, + [269] = {88, 0, "DEV_EPWM2_VBUSP_CLK", "Input clock"}, + [270] = {89, 0, "DEV_EPWM3_VBUSP_CLK", "Input clock"}, + [271] = {90, 0, "DEV_EPWM4_VBUSP_CLK", "Input clock"}, + [272] = {91, 0, "DEV_EPWM5_VBUSP_CLK", "Input clock"}, + [273] = {92, 0, "DEV_EPWM6_VBUSP_CLK", "Input clock"}, + [274] = {93, 0, "DEV_EPWM7_VBUSP_CLK", "Input clock"}, + [275] = {94, 0, "DEV_EPWM8_VBUSP_CLK", "Input clock"}, + [276] = {59, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"}, + [277] = {60, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"}, + [278] = {62, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"}, + [279] = {63, 0, "DEV_ESM0_CLK", "Input clock"}, + [280] = {65, 0, "DEV_FSIRX0_FSI_RX_CK", "Input clock"}, + [281] = {65, 1, "DEV_FSIRX0_FSI_RX_LPBK_CK", "Input clock"}, + [282] = {65, 2, "DEV_FSIRX0_FSI_RX_VBUS_CLK", "Input clock"}, + [283] = {66, 0, "DEV_FSIRX1_FSI_RX_CK", "Input clock"}, + [284] = {66, 1, "DEV_FSIRX1_FSI_RX_LPBK_CK", "Input clock"}, + [285] = {66, 2, "DEV_FSIRX1_FSI_RX_VBUS_CLK", "Input clock"}, + [286] = {67, 0, "DEV_FSIRX2_FSI_RX_CK", "Input clock"}, + [287] = {67, 1, "DEV_FSIRX2_FSI_RX_LPBK_CK", "Input clock"}, + [288] = {67, 2, "DEV_FSIRX2_FSI_RX_VBUS_CLK", "Input clock"}, + [289] = {68, 0, "DEV_FSIRX3_FSI_RX_CK", "Input clock"}, + [290] = {68, 1, "DEV_FSIRX3_FSI_RX_LPBK_CK", "Input clock"}, + [291] = {68, 2, "DEV_FSIRX3_FSI_RX_VBUS_CLK", "Input clock"}, + [292] = {69, 0, "DEV_FSIRX4_FSI_RX_CK", "Input clock"}, + [293] = {69, 1, "DEV_FSIRX4_FSI_RX_LPBK_CK", "Input clock"}, + [294] = {69, 2, "DEV_FSIRX4_FSI_RX_VBUS_CLK", "Input clock"}, + [295] = {70, 0, "DEV_FSIRX5_FSI_RX_CK", "Input clock"}, + [296] = {70, 1, "DEV_FSIRX5_FSI_RX_LPBK_CK", "Input clock"}, + [297] = {70, 2, "DEV_FSIRX5_FSI_RX_VBUS_CLK", "Input clock"}, + [298] = {71, 0, "DEV_FSITX0_FSI_TX_PLL_CLK", "Input clock"}, + [299] = {71, 1, "DEV_FSITX0_FSI_TX_VBUS_CLK", "Input clock"}, + [300] = {71, 2, "DEV_FSITX0_FSI_TX_CK", "Output clock"}, + [301] = {72, 0, "DEV_FSITX1_FSI_TX_PLL_CLK", "Input clock"}, + [302] = {72, 1, "DEV_FSITX1_FSI_TX_VBUS_CLK", "Input clock"}, + [303] = {72, 2, "DEV_FSITX1_FSI_TX_CK", "Output clock"}, + [304] = {74, 0, "DEV_FSS0_FSAS_0_GCLK", "Input clock"}, + [305] = {75, 0, "DEV_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"}, + [306] = {75, 1, "DEV_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"}, + [307] = {75, 2, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"}, + [308] = {75, 3, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_ICLK_CLK"}, + [309] = {75, 4, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_ICLK_CLK"}, + [310] = {75, 5, "DEV_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"}, + [311] = {75, 6, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK", "Input muxed clock"}, + [312] = {75, 7, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_RCLK_CLK"}, + [313] = {75, 8, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_RCLK_CLK"}, + [314] = {75, 9, "DEV_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"}, + [315] = {76, 0, "DEV_GICSS0_VCLK_CLK", "Input clock"}, + [316] = {77, 0, "DEV_GPIO0_MMR_CLK", "Input clock"}, + [317] = {78, 0, "DEV_GPIO1_MMR_CLK", "Input clock"}, + [318] = {80, 0, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"}, + [319] = {80, 1, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, + [320] = {80, 2, "DEV_GPMC0_FUNC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, + [321] = {80, 3, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"}, + [322] = {80, 4, "DEV_GPMC0_VBUSM_CLK", "Input clock"}, + [323] = {80, 5, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"}, + [324] = {61, 0, "DEV_GTC0_GTC_CLK", "Input muxed clock"}, + [325] = {61, 1, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [326] = {61, 2, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [327] = {61, 3, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [328] = {61, 4, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [329] = {61, 5, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [330] = {61, 6, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [331] = {61, 7, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [332] = {61, 8, "DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [333] = {61, 9, "DEV_GTC0_VBUSP_CLK", "Input clock"}, + [334] = {102, 0, "DEV_I2C0_CLK", "Input clock"}, + [335] = {102, 1, "DEV_I2C0_PISCL", "Input clock"}, + [336] = {102, 2, "DEV_I2C0_PISYS_CLK", "Input clock"}, + [337] = {102, 3, "DEV_I2C0_PORSCL", "Output clock"}, + [338] = {103, 0, "DEV_I2C1_CLK", "Input clock"}, + [339] = {103, 1, "DEV_I2C1_PISCL", "Input clock"}, + [340] = {103, 2, "DEV_I2C1_PISYS_CLK", "Input clock"}, + [341] = {103, 3, "DEV_I2C1_PORSCL", "Output clock"}, + [342] = {104, 0, "DEV_I2C2_CLK", "Input clock"}, + [343] = {104, 1, "DEV_I2C2_PISCL", "Input clock"}, + [344] = {104, 2, "DEV_I2C2_PISYS_CLK", "Input clock"}, + [345] = {104, 3, "DEV_I2C2_PORSCL", "Output clock"}, + [346] = {105, 0, "DEV_I2C3_CLK", "Input clock"}, + [347] = {105, 1, "DEV_I2C3_PISCL", "Input clock"}, + [348] = {105, 2, "DEV_I2C3_PISYS_CLK", "Input clock"}, + [349] = {105, 3, "DEV_I2C3_PORSCL", "Output clock"}, + [350] = {83, 0, "DEV_LED0_LED_CLK", "Input clock"}, + [351] = {83, 1, "DEV_LED0_VBUSP_CLK", "Input clock"}, + [352] = {3, 0, "DEV_MAIN_GPIOMUX_INTROUTER0_INTR_CLK", "Input clock"}, + [353] = {98, 0, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, + [354] = {98, 1, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, + [355] = {98, 2, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, + [356] = {98, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, + [357] = {98, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, + [358] = {98, 5, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, + [359] = {99, 0, "DEV_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"}, + [360] = {99, 1, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, + [361] = {99, 2, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, + [362] = {99, 3, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, + [363] = {99, 4, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, + [364] = {99, 5, "DEV_MCAN1_MCANSS_HCLK_CLK", "Input clock"}, + [365] = {141, 0, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"}, + [366] = {141, 1, "DEV_MCSPI0_IO_CLKSPII_CLK", "Input muxed clock"}, + [367] = {141, 2, "DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT", "Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK"}, + [368] = {141, 3, "DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK"}, + [369] = {141, 4, "DEV_MCSPI0_VBUSP_CLK", "Input clock"}, + [370] = {141, 5, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, + [371] = {142, 0, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"}, + [372] = {142, 1, "DEV_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"}, + [373] = {142, 2, "DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT", "Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK"}, + [374] = {142, 3, "DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK"}, + [375] = {142, 4, "DEV_MCSPI1_VBUSP_CLK", "Input clock"}, + [376] = {142, 5, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, + [377] = {143, 0, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"}, + [378] = {143, 1, "DEV_MCSPI2_IO_CLKSPII_CLK", "Input muxed clock"}, + [379] = {143, 2, "DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT", "Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK"}, + [380] = {143, 3, "DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK"}, + [381] = {143, 4, "DEV_MCSPI2_VBUSP_CLK", "Input clock"}, + [382] = {143, 5, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"}, + [383] = {144, 0, "DEV_MCSPI3_CLKSPIREF_CLK", "Input clock"}, + [384] = {144, 1, "DEV_MCSPI3_IO_CLKSPII_CLK", "Input muxed clock"}, + [385] = {144, 2, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI3_CLK_OUT", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"}, + [386] = {144, 3, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"}, + [387] = {144, 4, "DEV_MCSPI3_VBUSP_CLK", "Input clock"}, + [388] = {144, 5, "DEV_MCSPI3_IO_CLKSPIO_CLK", "Output clock"}, + [389] = {145, 0, "DEV_MCSPI4_CLKSPIREF_CLK", "Input clock"}, + [390] = {145, 1, "DEV_MCSPI4_IO_CLKSPII_CLK", "Input muxed clock"}, + [391] = {145, 2, "DEV_MCSPI4_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI4_CLK_OUT", "Parent input clock option to DEV_MCSPI4_IO_CLKSPII_CLK"}, + [392] = {145, 3, "DEV_MCSPI4_IO_CLKSPII_CLK_PARENT_SPI_MAIN_4_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI4_IO_CLKSPII_CLK"}, + [393] = {145, 4, "DEV_MCSPI4_VBUSP_CLK", "Input clock"}, + [394] = {145, 5, "DEV_MCSPI4_IO_CLKSPIO_CLK", "Output clock"}, + [395] = {23, 0, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, + [396] = {23, 1, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, + [397] = {23, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, + [398] = {23, 3, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, + [399] = {23, 4, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, + [400] = {23, 5, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, + [401] = {23, 6, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, + [402] = {23, 7, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, + [403] = {23, 8, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"}, + [404] = {23, 9, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"}, + [405] = {23, 10, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"}, + [406] = {23, 11, "DEV_MCU_DCC0_DCC_INPUT10_CLK", "Input clock"}, + [407] = {23, 12, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"}, + [408] = {64, 0, "DEV_MCU_ESM0_CLK", "Input clock"}, + [409] = {79, 0, "DEV_MCU_GPIO0_MMR_CLK", "Input clock"}, + [410] = {106, 0, "DEV_MCU_I2C0_CLK", "Input clock"}, + [411] = {106, 1, "DEV_MCU_I2C0_PISCL", "Input clock"}, + [412] = {106, 2, "DEV_MCU_I2C0_PISYS_CLK", "Input clock"}, + [413] = {106, 3, "DEV_MCU_I2C0_PORSCL", "Output clock"}, + [414] = {107, 0, "DEV_MCU_I2C1_CLK", "Input clock"}, + [415] = {107, 1, "DEV_MCU_I2C1_PISCL", "Input clock"}, + [416] = {107, 2, "DEV_MCU_I2C1_PISYS_CLK", "Input clock"}, + [417] = {107, 3, "DEV_MCU_I2C1_PORSCL", "Output clock"}, + [418] = {9, 0, "DEV_MCU_M4FSS0_CORE0_DAP_CLK", "Input clock"}, + [419] = {9, 1, "DEV_MCU_M4FSS0_CORE0_VBUS_CLK", "Input muxed clock"}, + [420] = {9, 2, "DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_M4FSS0_CORE0_VBUS_CLK"}, + [421] = {9, 3, "DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_M4FSS0_CORE0_VBUS_CLK"}, + [422] = {100, 0, "DEV_MCU_MCRC64_0_CLK", "Input clock"}, + [423] = {147, 0, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"}, + [424] = {147, 1, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK", "Input muxed clock"}, + [425] = {147, 2, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT", "Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK"}, + [426] = {147, 3, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK"}, + [427] = {147, 4, "DEV_MCU_MCSPI0_VBUSP_CLK", "Input clock"}, + [428] = {147, 5, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, + [429] = {148, 0, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"}, + [430] = {148, 1, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"}, + [431] = {148, 2, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI1_CLK_OUT", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"}, + [432] = {148, 3, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MCU_1_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"}, + [433] = {148, 4, "DEV_MCU_MCSPI1_VBUSP_CLK", "Input clock"}, + [434] = {148, 5, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, + [435] = {5, 0, "DEV_MCU_MCU_GPIOMUX_INTROUTER0_INTR_CLK", "Input clock"}, + [436] = {140, 0, "DEV_MCU_PSC0_CLK", "Input clock"}, + [437] = {140, 1, "DEV_MCU_PSC0_SLOW_CLK", "Input clock"}, + [438] = {132, 0, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"}, + [439] = {132, 1, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, + [440] = {132, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, + [441] = {132, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, + [442] = {132, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, + [443] = {132, 5, "DEV_MCU_RTI0_VBUSP_CLK", "Input clock"}, + [444] = {35, 0, "DEV_MCU_TIMER0_TIMER_HCLK_CLK", "Input clock"}, + [445] = {35, 1, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, + [446] = {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, + [447] = {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, + [448] = {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, + [449] = {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, + [450] = {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, + [451] = {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, + [452] = {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, + [453] = {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, + [454] = {35, 10, "DEV_MCU_TIMER0_TIMER_PWM", "Output clock"}, + [455] = {48, 0, "DEV_MCU_TIMER1_TIMER_HCLK_CLK", "Input clock"}, + [456] = {48, 1, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, + [457] = {48, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, + [458] = {48, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, + [459] = {48, 4, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, + [460] = {48, 5, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, + [461] = {48, 6, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, + [462] = {48, 7, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, + [463] = {48, 8, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, + [464] = {48, 9, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, + [465] = {48, 10, "DEV_MCU_TIMER1_TIMER_PWM", "Output clock"}, + [466] = {49, 0, "DEV_MCU_TIMER2_TIMER_HCLK_CLK", "Input clock"}, + [467] = {49, 1, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, + [468] = {49, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, + [469] = {49, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, + [470] = {49, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, + [471] = {49, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, + [472] = {49, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, + [473] = {49, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, + [474] = {49, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, + [475] = {49, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, + [476] = {49, 10, "DEV_MCU_TIMER2_TIMER_PWM", "Output clock"}, + [477] = {50, 0, "DEV_MCU_TIMER3_TIMER_HCLK_CLK", "Input clock"}, + [478] = {50, 1, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, + [479] = {50, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, + [480] = {50, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, + [481] = {50, 4, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, + [482] = {50, 5, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, + [483] = {50, 6, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, + [484] = {50, 7, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, + [485] = {50, 8, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, + [486] = {50, 9, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, + [487] = {50, 10, "DEV_MCU_TIMER3_TIMER_PWM", "Output clock"}, + [488] = {149, 0, "DEV_MCU_UART0_FCLK_CLK", "Input clock"}, + [489] = {149, 1, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"}, + [490] = {160, 0, "DEV_MCU_UART1_FCLK_CLK", "Input clock"}, + [491] = {160, 1, "DEV_MCU_UART1_VBUSP_CLK", "Input clock"}, + [492] = {57, 0, "DEV_MMCSD0_EMMCSS_VBUS_CLK", "Input clock"}, + [493] = {57, 1, "DEV_MMCSD0_EMMCSS_XIN_CLK", "Input muxed clock"}, + [494] = {57, 2, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, + [495] = {57, 3, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, + [496] = {58, 0, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I", "Input muxed clock"}, + [497] = {58, 1, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLKLB_OUT", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_IO_CLK_I"}, + [498] = {58, 2, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_EMMCSD4SS_MAIN_0_EMMCSDSS_IO_CLK_O", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_IO_CLK_I"}, + [499] = {58, 3, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"}, + [500] = {58, 4, "DEV_MMCSD1_EMMCSDSS_XIN_CLK", "Input muxed clock"}, + [501] = {58, 5, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, + [502] = {58, 6, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, + [503] = {58, 7, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O", "Output clock"}, + [504] = {108, 0, "DEV_MSRAM_256K0_CCLK_CLK", "Input clock"}, + [505] = {108, 1, "DEV_MSRAM_256K0_VCLK_CLK", "Input clock"}, + [506] = {109, 0, "DEV_MSRAM_256K1_CCLK_CLK", "Input clock"}, + [507] = {109, 1, "DEV_MSRAM_256K1_VCLK_CLK", "Input clock"}, + [508] = {110, 0, "DEV_MSRAM_256K2_CCLK_CLK", "Input clock"}, + [509] = {110, 1, "DEV_MSRAM_256K2_VCLK_CLK", "Input clock"}, + [510] = {111, 0, "DEV_MSRAM_256K3_CCLK_CLK", "Input clock"}, + [511] = {111, 1, "DEV_MSRAM_256K3_VCLK_CLK", "Input clock"}, + [512] = {112, 0, "DEV_MSRAM_256K4_CCLK_CLK", "Input clock"}, + [513] = {112, 1, "DEV_MSRAM_256K4_VCLK_CLK", "Input clock"}, + [514] = {113, 0, "DEV_MSRAM_256K5_CCLK_CLK", "Input clock"}, + [515] = {113, 1, "DEV_MSRAM_256K5_VCLK_CLK", "Input clock"}, + [516] = {163, 0, "DEV_PBIST0_CLK8_CLK", "Input clock"}, + [517] = {164, 0, "DEV_PBIST1_CLK8_CLK", "Input clock"}, + [518] = {165, 0, "DEV_PBIST2_CLK8_CLK", "Input clock"}, + [519] = {166, 0, "DEV_PBIST3_CLK8_CLK", "Input clock"}, + [520] = {114, 0, "DEV_PCIE0_PCIE_CBA_CLK", "Input clock"}, + [521] = {114, 1, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, + [522] = {114, 2, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [523] = {114, 3, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [524] = {114, 4, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [525] = {114, 5, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [526] = {114, 6, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [527] = {114, 7, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [528] = {114, 8, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [529] = {114, 9, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [530] = {114, 10, "DEV_PCIE0_PCIE_LANE0_REFCLK", "Input clock"}, + [531] = {114, 11, "DEV_PCIE0_PCIE_LANE0_RXCLK", "Input clock"}, + [532] = {114, 12, "DEV_PCIE0_PCIE_LANE0_RXFCLK", "Input clock"}, + [533] = {114, 13, "DEV_PCIE0_PCIE_LANE0_TXFCLK", "Input clock"}, + [534] = {114, 14, "DEV_PCIE0_PCIE_LANE0_TXMCLK", "Input clock"}, + [535] = {114, 15, "DEV_PCIE0_PCIE_PM_CLK", "Input clock"}, + [536] = {114, 16, "DEV_PCIE0_PCIE_LANE0_TXCLK", "Output clock"}, + [537] = {115, 0, "DEV_POSTDIV1_16FFT1_FREF_CLK", "Input clock"}, + [538] = {115, 1, "DEV_POSTDIV1_16FFT1_POSTDIV_CLKIN_CLK", "Input clock"}, + [539] = {115, 2, "DEV_POSTDIV1_16FFT1_HSDIVOUT5_CLK", "Output clock"}, + [540] = {115, 3, "DEV_POSTDIV1_16FFT1_HSDIVOUT6_CLK", "Output clock"}, + [541] = {116, 0, "DEV_POSTDIV4_16FF0_FREF_CLK", "Input clock"}, + [542] = {116, 1, "DEV_POSTDIV4_16FF0_POSTDIV_CLKIN_CLK", "Input clock"}, + [543] = {116, 2, "DEV_POSTDIV4_16FF0_HSDIVOUT5_CLK", "Output clock"}, + [544] = {116, 3, "DEV_POSTDIV4_16FF0_HSDIVOUT6_CLK", "Output clock"}, + [545] = {116, 4, "DEV_POSTDIV4_16FF0_HSDIVOUT7_CLK", "Output clock"}, + [546] = {116, 5, "DEV_POSTDIV4_16FF0_HSDIVOUT8_CLK", "Output clock"}, + [547] = {116, 6, "DEV_POSTDIV4_16FF0_HSDIVOUT9_CLK", "Output clock"}, + [548] = {117, 0, "DEV_POSTDIV4_16FF2_FREF_CLK", "Input clock"}, + [549] = {117, 1, "DEV_POSTDIV4_16FF2_POSTDIV_CLKIN_CLK", "Input clock"}, + [550] = {117, 2, "DEV_POSTDIV4_16FF2_HSDIVOUT5_CLK", "Output clock"}, + [551] = {117, 3, "DEV_POSTDIV4_16FF2_HSDIVOUT6_CLK", "Output clock"}, + [552] = {117, 4, "DEV_POSTDIV4_16FF2_HSDIVOUT7_CLK", "Output clock"}, + [553] = {117, 5, "DEV_POSTDIV4_16FF2_HSDIVOUT8_CLK", "Output clock"}, + [554] = {117, 6, "DEV_POSTDIV4_16FF2_HSDIVOUT9_CLK", "Output clock"}, + [555] = {81, 0, "DEV_PRU_ICSSG0_CORE_CLK", "Input muxed clock"}, + [556] = {81, 1, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"}, + [557] = {81, 2, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"}, + [558] = {81, 3, "DEV_PRU_ICSSG0_IEP_CLK", "Input muxed clock"}, + [559] = {81, 4, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [560] = {81, 5, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [561] = {81, 6, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [562] = {81, 7, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [563] = {81, 8, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [564] = {81, 9, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [565] = {81, 10, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [566] = {81, 11, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [567] = {81, 12, "DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I", "Input clock"}, + [568] = {81, 13, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I", "Input clock"}, + [569] = {81, 14, "DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I", "Input clock"}, + [570] = {81, 15, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I", "Input clock"}, + [571] = {81, 16, "DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK", "Input clock"}, + [572] = {81, 17, "DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK", "Input clock"}, + [573] = {81, 18, "DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK", "Input clock"}, + [574] = {81, 19, "DEV_PRU_ICSSG0_UCLK_CLK", "Input clock"}, + [575] = {81, 20, "DEV_PRU_ICSSG0_VCLK_CLK", "Input clock"}, + [576] = {81, 21, "DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O", "Output clock"}, + [577] = {81, 22, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O", "Output clock"}, + [578] = {81, 23, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O", "Output clock"}, + [579] = {82, 0, "DEV_PRU_ICSSG1_CORE_CLK", "Input muxed clock"}, + [580] = {82, 1, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"}, + [581] = {82, 2, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"}, + [582] = {82, 3, "DEV_PRU_ICSSG1_IEP_CLK", "Input muxed clock"}, + [583] = {82, 4, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [584] = {82, 5, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [585] = {82, 6, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [586] = {82, 7, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [587] = {82, 8, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [588] = {82, 9, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [589] = {82, 10, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [590] = {82, 11, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [591] = {82, 12, "DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I", "Input clock"}, + [592] = {82, 13, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I", "Input clock"}, + [593] = {82, 14, "DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I", "Input clock"}, + [594] = {82, 15, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I", "Input clock"}, + [595] = {82, 16, "DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK", "Input clock"}, + [596] = {82, 17, "DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK", "Input clock"}, + [597] = {82, 18, "DEV_PRU_ICSSG1_RGMII_MHZ_5_CLK", "Input clock"}, + [598] = {82, 19, "DEV_PRU_ICSSG1_UCLK_CLK", "Input clock"}, + [599] = {82, 20, "DEV_PRU_ICSSG1_VCLK_CLK", "Input clock"}, + [600] = {82, 21, "DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O", "Output clock"}, + [601] = {82, 22, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O", "Output clock"}, + [602] = {82, 23, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O", "Output clock"}, + [603] = {139, 0, "DEV_PSC0_CLK", "Input clock"}, + [604] = {139, 1, "DEV_PSC0_SLOW_CLK", "Input clock"}, + [605] = {118, 0, "DEV_PSRAMECC0_CLK_CLK", "Input clock"}, + [606] = {121, 0, "DEV_R5FSS0_CORE0_CPU_CLK", "Input clock"}, + [607] = {121, 1, "DEV_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"}, + [608] = {122, 0, "DEV_R5FSS0_CORE1_CPU_CLK", "Input clock"}, + [609] = {122, 1, "DEV_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"}, + [610] = {123, 0, "DEV_R5FSS1_CORE0_CPU_CLK", "Input clock"}, + [611] = {123, 1, "DEV_R5FSS1_CORE0_INTERFACE_CLK", "Input clock"}, + [612] = {124, 0, "DEV_R5FSS1_CORE1_CPU_CLK", "Input clock"}, + [613] = {124, 1, "DEV_R5FSS1_CORE1_INTERFACE_CLK", "Input clock"}, + [614] = {125, 0, "DEV_RTI0_RTI_CLK", "Input muxed clock"}, + [615] = {125, 1, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, + [616] = {125, 2, "DEV_RTI0_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_RTI0_RTI_CLK"}, + [617] = {125, 3, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, + [618] = {125, 4, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI0_RTI_CLK"}, + [619] = {125, 5, "DEV_RTI0_VBUSP_CLK", "Input clock"}, + [620] = {126, 0, "DEV_RTI1_RTI_CLK", "Input muxed clock"}, + [621] = {126, 1, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, + [622] = {126, 2, "DEV_RTI1_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_RTI1_RTI_CLK"}, + [623] = {126, 3, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, + [624] = {126, 4, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI1_RTI_CLK"}, + [625] = {126, 5, "DEV_RTI1_VBUSP_CLK", "Input clock"}, + [626] = {130, 0, "DEV_RTI10_RTI_CLK", "Input muxed clock"}, + [627] = {130, 1, "DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI10_RTI_CLK"}, + [628] = {130, 2, "DEV_RTI10_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_RTI10_RTI_CLK"}, + [629] = {130, 3, "DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI10_RTI_CLK"}, + [630] = {130, 4, "DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI10_RTI_CLK"}, + [631] = {130, 5, "DEV_RTI10_VBUSP_CLK", "Input clock"}, + [632] = {131, 0, "DEV_RTI11_RTI_CLK", "Input muxed clock"}, + [633] = {131, 1, "DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI11_RTI_CLK"}, + [634] = {131, 2, "DEV_RTI11_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_RTI11_RTI_CLK"}, + [635] = {131, 3, "DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI11_RTI_CLK"}, + [636] = {131, 4, "DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI11_RTI_CLK"}, + [637] = {131, 5, "DEV_RTI11_VBUSP_CLK", "Input clock"}, + [638] = {127, 0, "DEV_RTI8_RTI_CLK", "Input muxed clock"}, + [639] = {127, 1, "DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI8_RTI_CLK"}, + [640] = {127, 2, "DEV_RTI8_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_RTI8_RTI_CLK"}, + [641] = {127, 3, "DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI8_RTI_CLK"}, + [642] = {127, 4, "DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI8_RTI_CLK"}, + [643] = {127, 5, "DEV_RTI8_VBUSP_CLK", "Input clock"}, + [644] = {128, 0, "DEV_RTI9_RTI_CLK", "Input muxed clock"}, + [645] = {128, 1, "DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI9_RTI_CLK"}, + [646] = {128, 2, "DEV_RTI9_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_RTI9_RTI_CLK"}, + [647] = {128, 3, "DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI9_RTI_CLK"}, + [648] = {128, 4, "DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI9_RTI_CLK"}, + [649] = {128, 5, "DEV_RTI9_VBUSP_CLK", "Input clock"}, + [650] = {133, 0, "DEV_SA2_UL0_PKA_IN_CLK", "Input clock"}, + [651] = {133, 1, "DEV_SA2_UL0_X1_CLK", "Input clock"}, + [652] = {133, 2, "DEV_SA2_UL0_X2_CLK", "Input clock"}, + [653] = {162, 0, "DEV_SERDES_10G0_CLK", "Input clock"}, + [654] = {162, 1, "DEV_SERDES_10G0_CORE_REF_CLK", "Input muxed clock"}, + [655] = {162, 2, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, + [656] = {162, 3, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, + [657] = {162, 4, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, + [658] = {162, 5, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, + [659] = {162, 6, "DEV_SERDES_10G0_IP1_LN0_TXCLK", "Input clock"}, + [660] = {162, 7, "DEV_SERDES_10G0_IP2_LN0_TXCLK", "Input clock"}, + [661] = {162, 8, "DEV_SERDES_10G0_IP1_LN0_REFCLK", "Output clock"}, + [662] = {162, 9, "DEV_SERDES_10G0_IP1_LN0_RXCLK", "Output clock"}, + [663] = {162, 10, "DEV_SERDES_10G0_IP1_LN0_RXFCLK", "Output clock"}, + [664] = {162, 11, "DEV_SERDES_10G0_IP1_LN0_TXFCLK", "Output clock"}, + [665] = {162, 12, "DEV_SERDES_10G0_IP1_LN0_TXMCLK", "Output clock"}, + [666] = {162, 13, "DEV_SERDES_10G0_IP2_LN0_REFCLK", "Output clock"}, + [667] = {162, 14, "DEV_SERDES_10G0_IP2_LN0_RXCLK", "Output clock"}, + [668] = {162, 15, "DEV_SERDES_10G0_IP2_LN0_RXFCLK", "Output clock"}, + [669] = {162, 16, "DEV_SERDES_10G0_IP2_LN0_TXFCLK", "Output clock"}, + [670] = {162, 17, "DEV_SERDES_10G0_IP2_LN0_TXMCLK", "Output clock"}, + [671] = {162, 18, "DEV_SERDES_10G0_REF_OUT_CLK", "Output clock"}, + [672] = {150, 0, "DEV_SPINLOCK0_VCLK_CLK", "Input clock"}, + [673] = {15, 0, "DEV_STM0_ATB_CLK", "Input clock"}, + [674] = {15, 1, "DEV_STM0_CORE_CLK", "Input clock"}, + [675] = {15, 2, "DEV_STM0_VBUSP_CLK", "Input clock"}, + [676] = {36, 0, "DEV_TIMER0_TIMER_HCLK_CLK", "Input clock"}, + [677] = {36, 1, "DEV_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, + [678] = {36, 2, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, + [679] = {36, 3, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, + [680] = {36, 4, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, + [681] = {36, 5, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, + [682] = {36, 6, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, + [683] = {36, 7, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, + [684] = {36, 8, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, + [685] = {36, 9, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, + [686] = {36, 10, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, + [687] = {36, 11, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, + [688] = {36, 12, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, + [689] = {36, 13, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, + [690] = {36, 14, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, + [691] = {36, 15, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, + [692] = {36, 16, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, + [693] = {36, 17, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, + [694] = {36, 18, "DEV_TIMER0_TIMER_PWM", "Output clock"}, + [695] = {37, 0, "DEV_TIMER1_TIMER_HCLK_CLK", "Input clock"}, + [696] = {37, 1, "DEV_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, + [697] = {37, 2, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, + [698] = {37, 3, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, + [699] = {37, 4, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, + [700] = {37, 5, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, + [701] = {37, 6, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, + [702] = {37, 7, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, + [703] = {37, 8, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, + [704] = {37, 9, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, + [705] = {37, 10, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, + [706] = {37, 11, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, + [707] = {37, 12, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, + [708] = {37, 13, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, + [709] = {37, 14, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, + [710] = {37, 15, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, + [711] = {37, 16, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, + [712] = {37, 17, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, + [713] = {37, 18, "DEV_TIMER1_TIMER_PWM", "Output clock"}, + [714] = {46, 0, "DEV_TIMER10_TIMER_HCLK_CLK", "Input clock"}, + [715] = {46, 1, "DEV_TIMER10_TIMER_TCLK_CLK", "Input muxed clock"}, + [716] = {46, 2, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, + [717] = {46, 3, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, + [718] = {46, 4, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, + [719] = {46, 5, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, + [720] = {46, 6, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, + [721] = {46, 7, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, + [722] = {46, 8, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, + [723] = {46, 9, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, + [724] = {46, 10, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, + [725] = {46, 11, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, + [726] = {46, 12, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, + [727] = {46, 13, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, + [728] = {46, 14, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, + [729] = {46, 15, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, + [730] = {46, 16, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, + [731] = {46, 17, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, + [732] = {46, 18, "DEV_TIMER10_TIMER_PWM", "Output clock"}, + [733] = {47, 0, "DEV_TIMER11_TIMER_HCLK_CLK", "Input clock"}, + [734] = {47, 1, "DEV_TIMER11_TIMER_TCLK_CLK", "Input muxed clock"}, + [735] = {47, 2, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, + [736] = {47, 3, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, + [737] = {47, 4, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, + [738] = {47, 5, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, + [739] = {47, 6, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, + [740] = {47, 7, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, + [741] = {47, 8, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, + [742] = {47, 9, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, + [743] = {47, 10, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, + [744] = {47, 11, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, + [745] = {47, 12, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, + [746] = {47, 13, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, + [747] = {47, 14, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, + [748] = {47, 15, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, + [749] = {47, 16, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, + [750] = {47, 17, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, + [751] = {47, 18, "DEV_TIMER11_TIMER_PWM", "Output clock"}, + [752] = {38, 0, "DEV_TIMER2_TIMER_HCLK_CLK", "Input clock"}, + [753] = {38, 1, "DEV_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, + [754] = {38, 2, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, + [755] = {38, 3, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, + [756] = {38, 4, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, + [757] = {38, 5, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, + [758] = {38, 6, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, + [759] = {38, 7, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, + [760] = {38, 8, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, + [761] = {38, 9, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, + [762] = {38, 10, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, + [763] = {38, 11, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, + [764] = {38, 12, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, + [765] = {38, 13, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, + [766] = {38, 14, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, + [767] = {38, 15, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, + [768] = {38, 16, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, + [769] = {38, 17, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, + [770] = {38, 18, "DEV_TIMER2_TIMER_PWM", "Output clock"}, + [771] = {39, 0, "DEV_TIMER3_TIMER_HCLK_CLK", "Input clock"}, + [772] = {39, 1, "DEV_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, + [773] = {39, 2, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, + [774] = {39, 3, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, + [775] = {39, 4, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, + [776] = {39, 5, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, + [777] = {39, 6, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, + [778] = {39, 7, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, + [779] = {39, 8, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, + [780] = {39, 9, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, + [781] = {39, 10, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, + [782] = {39, 11, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, + [783] = {39, 12, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, + [784] = {39, 13, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, + [785] = {39, 14, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, + [786] = {39, 15, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, + [787] = {39, 16, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, + [788] = {39, 17, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, + [789] = {39, 18, "DEV_TIMER3_TIMER_PWM", "Output clock"}, + [790] = {40, 0, "DEV_TIMER4_TIMER_HCLK_CLK", "Input clock"}, + [791] = {40, 1, "DEV_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"}, + [792] = {40, 2, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, + [793] = {40, 3, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, + [794] = {40, 4, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, + [795] = {40, 5, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, + [796] = {40, 6, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, + [797] = {40, 7, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, + [798] = {40, 8, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, + [799] = {40, 9, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, + [800] = {40, 10, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, + [801] = {40, 11, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, + [802] = {40, 12, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, + [803] = {40, 13, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, + [804] = {40, 14, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, + [805] = {40, 15, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, + [806] = {40, 16, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, + [807] = {40, 17, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, + [808] = {40, 18, "DEV_TIMER4_TIMER_PWM", "Output clock"}, + [809] = {41, 0, "DEV_TIMER5_TIMER_HCLK_CLK", "Input clock"}, + [810] = {41, 1, "DEV_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"}, + [811] = {41, 2, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, + [812] = {41, 3, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, + [813] = {41, 4, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, + [814] = {41, 5, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, + [815] = {41, 6, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, + [816] = {41, 7, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, + [817] = {41, 8, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, + [818] = {41, 9, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, + [819] = {41, 10, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, + [820] = {41, 11, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, + [821] = {41, 12, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, + [822] = {41, 13, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, + [823] = {41, 14, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, + [824] = {41, 15, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, + [825] = {41, 16, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, + [826] = {41, 17, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, + [827] = {41, 18, "DEV_TIMER5_TIMER_PWM", "Output clock"}, + [828] = {42, 0, "DEV_TIMER6_TIMER_HCLK_CLK", "Input clock"}, + [829] = {42, 1, "DEV_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"}, + [830] = {42, 2, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, + [831] = {42, 3, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, + [832] = {42, 4, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, + [833] = {42, 5, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, + [834] = {42, 6, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, + [835] = {42, 7, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, + [836] = {42, 8, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, + [837] = {42, 9, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, + [838] = {42, 10, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, + [839] = {42, 11, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, + [840] = {42, 12, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, + [841] = {42, 13, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, + [842] = {42, 14, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, + [843] = {42, 15, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, + [844] = {42, 16, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, + [845] = {42, 17, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, + [846] = {42, 18, "DEV_TIMER6_TIMER_PWM", "Output clock"}, + [847] = {43, 0, "DEV_TIMER7_TIMER_HCLK_CLK", "Input clock"}, + [848] = {43, 1, "DEV_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"}, + [849] = {43, 2, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, + [850] = {43, 3, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, + [851] = {43, 4, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, + [852] = {43, 5, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, + [853] = {43, 6, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, + [854] = {43, 7, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, + [855] = {43, 8, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, + [856] = {43, 9, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, + [857] = {43, 10, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, + [858] = {43, 11, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, + [859] = {43, 12, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, + [860] = {43, 13, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, + [861] = {43, 14, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, + [862] = {43, 15, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, + [863] = {43, 16, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, + [864] = {43, 17, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, + [865] = {43, 18, "DEV_TIMER7_TIMER_PWM", "Output clock"}, + [866] = {44, 0, "DEV_TIMER8_TIMER_HCLK_CLK", "Input clock"}, + [867] = {44, 1, "DEV_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"}, + [868] = {44, 2, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, + [869] = {44, 3, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, + [870] = {44, 4, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, + [871] = {44, 5, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, + [872] = {44, 6, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, + [873] = {44, 7, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, + [874] = {44, 8, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, + [875] = {44, 9, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, + [876] = {44, 10, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, + [877] = {44, 11, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, + [878] = {44, 12, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, + [879] = {44, 13, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, + [880] = {44, 14, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, + [881] = {44, 15, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, + [882] = {44, 16, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, + [883] = {44, 17, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, + [884] = {44, 18, "DEV_TIMER8_TIMER_PWM", "Output clock"}, + [885] = {45, 0, "DEV_TIMER9_TIMER_HCLK_CLK", "Input clock"}, + [886] = {45, 1, "DEV_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"}, + [887] = {45, 2, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, + [888] = {45, 3, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, + [889] = {45, 4, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, + [890] = {45, 5, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, + [891] = {45, 6, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, + [892] = {45, 7, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, + [893] = {45, 8, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, + [894] = {45, 9, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, + [895] = {45, 10, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, + [896] = {45, 11, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, + [897] = {45, 12, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, + [898] = {45, 13, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, + [899] = {45, 14, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, + [900] = {45, 15, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, + [901] = {45, 16, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, + [902] = {45, 17, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, + [903] = {45, 18, "DEV_TIMER9_TIMER_PWM", "Output clock"}, + [904] = {151, 0, "DEV_TIMERMGR0_VCLK_CLK", "Input clock"}, + [905] = {6, 0, "DEV_TIMESYNC_EVENT_INTROUTER0_INTR_CLK", "Input clock"}, + [906] = {146, 0, "DEV_UART0_FCLK_CLK", "Input muxed clock"}, + [907] = {146, 1, "DEV_UART0_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT0", "Parent input clock option to DEV_UART0_FCLK_CLK"}, + [908] = {146, 2, "DEV_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART0_FCLK_CLK"}, + [909] = {146, 3, "DEV_UART0_VBUSP_CLK", "Input clock"}, + [910] = {152, 0, "DEV_UART1_FCLK_CLK", "Input muxed clock"}, + [911] = {152, 1, "DEV_UART1_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT1", "Parent input clock option to DEV_UART1_FCLK_CLK"}, + [912] = {152, 2, "DEV_UART1_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART1_FCLK_CLK"}, + [913] = {152, 3, "DEV_UART1_VBUSP_CLK", "Input clock"}, + [914] = {153, 0, "DEV_UART2_FCLK_CLK", "Input muxed clock"}, + [915] = {153, 1, "DEV_UART2_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT2", "Parent input clock option to DEV_UART2_FCLK_CLK"}, + [916] = {153, 2, "DEV_UART2_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART2_FCLK_CLK"}, + [917] = {153, 3, "DEV_UART2_VBUSP_CLK", "Input clock"}, + [918] = {154, 0, "DEV_UART3_FCLK_CLK", "Input muxed clock"}, + [919] = {154, 1, "DEV_UART3_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT3", "Parent input clock option to DEV_UART3_FCLK_CLK"}, + [920] = {154, 2, "DEV_UART3_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART3_FCLK_CLK"}, + [921] = {154, 3, "DEV_UART3_VBUSP_CLK", "Input clock"}, + [922] = {155, 0, "DEV_UART4_FCLK_CLK", "Input muxed clock"}, + [923] = {155, 1, "DEV_UART4_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT4", "Parent input clock option to DEV_UART4_FCLK_CLK"}, + [924] = {155, 2, "DEV_UART4_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART4_FCLK_CLK"}, + [925] = {155, 3, "DEV_UART4_VBUSP_CLK", "Input clock"}, + [926] = {156, 0, "DEV_UART5_FCLK_CLK", "Input muxed clock"}, + [927] = {156, 1, "DEV_UART5_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT5", "Parent input clock option to DEV_UART5_FCLK_CLK"}, + [928] = {156, 2, "DEV_UART5_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART5_FCLK_CLK"}, + [929] = {156, 3, "DEV_UART5_VBUSP_CLK", "Input clock"}, + [930] = {158, 0, "DEV_UART6_FCLK_CLK", "Input muxed clock"}, + [931] = {158, 1, "DEV_UART6_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT6", "Parent input clock option to DEV_UART6_FCLK_CLK"}, + [932] = {158, 2, "DEV_UART6_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART6_FCLK_CLK"}, + [933] = {158, 3, "DEV_UART6_VBUSP_CLK", "Input clock"}, + [934] = {161, 0, "DEV_USB0_ACLK_CLK", "Input clock"}, + [935] = {161, 1, "DEV_USB0_CLK_LPM_CLK", "Input clock"}, + [936] = {161, 2, "DEV_USB0_PCLK_CLK", "Input clock"}, + [937] = {161, 3, "DEV_USB0_PIPE_REFCLK", "Input clock"}, + [938] = {161, 4, "DEV_USB0_PIPE_RXCLK", "Input clock"}, + [939] = {161, 5, "DEV_USB0_PIPE_RXFCLK", "Input clock"}, + [940] = {161, 6, "DEV_USB0_PIPE_TXFCLK", "Input clock"}, + [941] = {161, 7, "DEV_USB0_PIPE_TXMCLK", "Input clock"}, + [942] = {161, 8, "DEV_USB0_USB2_APB_PCLK_CLK", "Input clock"}, + [943] = {161, 9, "DEV_USB0_USB2_REFCLOCK_CLK", "Input muxed clock"}, + [944] = {161, 10, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"}, + [945] = {161, 11, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"}, + [946] = {161, 12, "DEV_USB0_PIPE_TXCLK", "Output clock"}, + [947] = {95, 0, "DEV_VTM0_FIX_REF2_CLK", "Input clock"}, + [948] = {95, 1, "DEV_VTM0_FIX_REF_CLK", "Input clock"}, + [949] = {95, 2, "DEV_VTM0_VBUSP_CLK", "Input clock"}, +}; diff --git a/soc/am64x/am64x_clocks_info.h b/soc/am64x/am64x_clocks_info.h new file mode 100644 index 0000000..4415701 --- /dev/null +++ b/soc/am64x/am64x_clocks_info.h @@ -0,0 +1,42 @@ +/* + * AM64X Clocks Info + * + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __AM64X_CLOCKS_INFO_H +#define __AM64X_CLOCKS_INFO_H + +#define AM64X_MAX_CLOCKS 950 + +extern struct ti_sci_clocks_info am64x_clocks_info[]; + +#endif /* __AM64X_CLOCKS_INFO_H */ \ No newline at end of file