From f25b10cb71059c88cc8bfec39bb3190a3b6cfbe3 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Wed, 11 Nov 2020 20:39:26 +0530 Subject: [PATCH] soc: j721e: Update sysfw data corresponding to v2020.08b Update the sysfw data that corresponds to v2020.08b. Also fix the TI link in Copyright headers. Signed-off-by: Lokesh Vutla --- soc/j721e/j721e_clocks_info.c | 4270 ++++++++++++++--------------- soc/j721e/j721e_devices_info.c | 38 +- soc/j721e/j721e_host_info.c | 55 +- soc/j721e/j721e_host_info.h | 5 +- soc/j721e/j721e_processors_info.c | 2 +- soc/j721e/j721e_sec_proxy_info.c | 296 +- soc/j721e/j721e_sec_proxy_info.h | 4 +- 7 files changed, 2361 insertions(+), 2309 deletions(-) diff --git a/soc/j721e/j721e_clocks_info.c b/soc/j721e/j721e_clocks_info.c index d6ebaf2..e971426 100644 --- a/soc/j721e/j721e_clocks_info.c +++ b/soc/j721e/j721e_clocks_info.c @@ -36,309 +36,309 @@ #include struct ti_sci_clocks_info j721e_clocks_info[] = { - [0] = {4, 0, "DEV_A72SS0_CLUSTER_CLK", "Input clock"}, - [1] = {202, 0, "DEV_A72SS0_CORE0_PLL_CTRL_CLK", "Input clock"}, - [2] = {202, 1, "DEV_A72SS0_CORE0_MSMC_CLK", "Input clock"}, + [0] = {4, 0, "DEV_A72SS0_PLL_CTRL_CLK", "Input clock"}, + [1] = {4, 1, "DEV_A72SS0_MSMC_CLK", "Input clock"}, + [2] = {4, 2, "DEV_A72SS0_ARM_CLK_CLK", "Input clock"}, [3] = {202, 2, "DEV_A72SS0_CORE0_ARM_CLK_CLK", "Input clock"}, [4] = {203, 0, "DEV_A72SS0_CORE1_ARM_CLK_CLK", "Input clock"}, [5] = {139, 0, "DEV_AASRC0_SYS_CLK", "Input clock"}, [6] = {139, 1, "DEV_AASRC0_VBUSP_CLK", "Input clock"}, - [7] = {139, 2, "DEV_AASRC0_RX0_SYNC_0", "Input muxed clock"}, - [8] = {139, 3, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [9] = {139, 4, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [10] = {139, 5, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [11] = {139, 6, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [12] = {139, 7, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [13] = {139, 8, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [14] = {139, 9, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [15] = {139, 10, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [16] = {139, 11, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [17] = {139, 12, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [18] = {139, 13, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [19] = {139, 14, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [20] = {139, 15, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [21] = {139, 16, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [22] = {139, 17, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [23] = {139, 18, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [24] = {139, 19, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [25] = {139, 20, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [26] = {139, 21, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [27] = {139, 22, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [28] = {139, 23, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [29] = {139, 24, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [30] = {139, 25, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [31] = {139, 26, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [32] = {139, 27, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [33] = {139, 28, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [34] = {139, 29, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [35] = {139, 30, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [36] = {139, 31, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [37] = {139, 32, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [38] = {139, 33, "DEV_AASRC0_RX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [39] = {139, 34, "DEV_AASRC0_RX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [40] = {139, 35, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [41] = {139, 36, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [42] = {139, 37, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [43] = {139, 38, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"}, - [44] = {139, 39, "DEV_AASRC0_RX1_SYNC_0", "Input muxed clock"}, - [45] = {139, 40, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [46] = {139, 41, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [47] = {139, 42, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [48] = {139, 43, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [49] = {139, 44, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [50] = {139, 45, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [51] = {139, 46, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [52] = {139, 47, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [53] = {139, 48, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [54] = {139, 49, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [55] = {139, 50, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [56] = {139, 51, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [57] = {139, 52, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [58] = {139, 53, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [59] = {139, 54, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [60] = {139, 55, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [61] = {139, 56, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [62] = {139, 57, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [63] = {139, 58, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [64] = {139, 59, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [65] = {139, 60, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [66] = {139, 61, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [67] = {139, 62, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [68] = {139, 63, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [69] = {139, 64, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [70] = {139, 65, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [71] = {139, 66, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [72] = {139, 67, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [73] = {139, 68, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [74] = {139, 69, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [75] = {139, 70, "DEV_AASRC0_RX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [76] = {139, 71, "DEV_AASRC0_RX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [77] = {139, 72, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [78] = {139, 73, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [79] = {139, 74, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [80] = {139, 75, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"}, - [81] = {139, 76, "DEV_AASRC0_RX2_SYNC_0", "Input muxed clock"}, - [82] = {139, 77, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [83] = {139, 78, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [84] = {139, 79, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [85] = {139, 80, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [86] = {139, 81, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [87] = {139, 82, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [88] = {139, 83, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [89] = {139, 84, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [90] = {139, 85, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [91] = {139, 86, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [92] = {139, 87, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [93] = {139, 88, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [94] = {139, 89, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [95] = {139, 90, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [96] = {139, 91, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [97] = {139, 92, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [98] = {139, 93, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [99] = {139, 94, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [100] = {139, 95, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [101] = {139, 96, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [102] = {139, 97, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [103] = {139, 98, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [104] = {139, 99, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [105] = {139, 100, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [106] = {139, 101, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [107] = {139, 102, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [108] = {139, 103, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [109] = {139, 104, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [110] = {139, 105, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [111] = {139, 106, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [112] = {139, 107, "DEV_AASRC0_RX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [113] = {139, 108, "DEV_AASRC0_RX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [114] = {139, 109, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [115] = {139, 110, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [116] = {139, 111, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [117] = {139, 112, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"}, - [118] = {139, 113, "DEV_AASRC0_RX3_SYNC_0", "Input muxed clock"}, - [119] = {139, 114, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [120] = {139, 115, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [121] = {139, 116, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [122] = {139, 117, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [123] = {139, 118, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [124] = {139, 119, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [125] = {139, 120, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [126] = {139, 121, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [127] = {139, 122, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [128] = {139, 123, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [129] = {139, 124, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [130] = {139, 125, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [131] = {139, 126, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [132] = {139, 127, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [133] = {139, 128, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [134] = {139, 129, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [135] = {139, 130, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [136] = {139, 131, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [137] = {139, 132, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [138] = {139, 133, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [139] = {139, 134, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [140] = {139, 135, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [141] = {139, 136, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [142] = {139, 137, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [143] = {139, 138, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [144] = {139, 139, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [145] = {139, 140, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [146] = {139, 141, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [147] = {139, 142, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [148] = {139, 143, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [149] = {139, 144, "DEV_AASRC0_RX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [150] = {139, 145, "DEV_AASRC0_RX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [151] = {139, 146, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [152] = {139, 147, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [153] = {139, 148, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [154] = {139, 149, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"}, - [155] = {139, 150, "DEV_AASRC0_TX0_SYNC_0", "Input muxed clock"}, - [156] = {139, 151, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [157] = {139, 152, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [158] = {139, 153, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [159] = {139, 154, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [160] = {139, 155, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [161] = {139, 156, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [162] = {139, 157, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [163] = {139, 158, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [164] = {139, 159, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [165] = {139, 160, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [166] = {139, 161, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [167] = {139, 162, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [168] = {139, 163, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [169] = {139, 164, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [170] = {139, 165, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [171] = {139, 166, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [172] = {139, 167, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [173] = {139, 168, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [174] = {139, 169, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [175] = {139, 170, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [176] = {139, 171, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [177] = {139, 172, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [178] = {139, 173, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [179] = {139, 174, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [180] = {139, 175, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [181] = {139, 176, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [182] = {139, 177, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [183] = {139, 178, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [184] = {139, 179, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [185] = {139, 180, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [186] = {139, 181, "DEV_AASRC0_TX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [187] = {139, 182, "DEV_AASRC0_TX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [188] = {139, 183, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [189] = {139, 184, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [190] = {139, 185, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [191] = {139, 186, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"}, - [192] = {139, 187, "DEV_AASRC0_TX1_SYNC_0", "Input muxed clock"}, - [193] = {139, 188, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [194] = {139, 189, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [195] = {139, 190, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [196] = {139, 191, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [197] = {139, 192, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [198] = {139, 193, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [199] = {139, 194, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [200] = {139, 195, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [201] = {139, 196, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [202] = {139, 197, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [203] = {139, 198, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [204] = {139, 199, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [205] = {139, 200, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [206] = {139, 201, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [207] = {139, 202, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [208] = {139, 203, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [209] = {139, 204, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [210] = {139, 205, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [211] = {139, 206, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [212] = {139, 207, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [213] = {139, 208, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [214] = {139, 209, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [215] = {139, 210, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [216] = {139, 211, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [217] = {139, 212, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [218] = {139, 213, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [219] = {139, 214, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [220] = {139, 215, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [221] = {139, 216, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [222] = {139, 217, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [223] = {139, 218, "DEV_AASRC0_TX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [224] = {139, 219, "DEV_AASRC0_TX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [225] = {139, 220, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [226] = {139, 221, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [227] = {139, 222, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [228] = {139, 223, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"}, - [229] = {139, 224, "DEV_AASRC0_TX2_SYNC_0", "Input muxed clock"}, - [230] = {139, 225, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [231] = {139, 226, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [232] = {139, 227, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [233] = {139, 228, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [234] = {139, 229, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [235] = {139, 230, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [236] = {139, 231, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [237] = {139, 232, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [238] = {139, 233, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [239] = {139, 234, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [240] = {139, 235, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [241] = {139, 236, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [242] = {139, 237, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [243] = {139, 238, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [244] = {139, 239, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [245] = {139, 240, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [246] = {139, 241, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [247] = {139, 242, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [248] = {139, 243, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [249] = {139, 244, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [250] = {139, 245, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [251] = {139, 246, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [252] = {139, 247, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [253] = {139, 248, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [254] = {139, 249, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [255] = {139, 250, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [256] = {139, 251, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [257] = {139, 252, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [258] = {139, 253, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [259] = {139, 254, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [260] = {139, 255, "DEV_AASRC0_TX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [261] = {139, 256, "DEV_AASRC0_TX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [262] = {139, 257, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [263] = {139, 258, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [264] = {139, 259, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [265] = {139, 260, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"}, - [266] = {139, 261, "DEV_AASRC0_TX3_SYNC_0", "Input muxed clock"}, - [267] = {139, 262, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [268] = {139, 263, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [269] = {139, 264, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [270] = {139, 265, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [271] = {139, 266, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [272] = {139, 267, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [273] = {139, 268, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [274] = {139, 269, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [275] = {139, 270, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [276] = {139, 271, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [277] = {139, 272, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [278] = {139, 273, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [279] = {139, 274, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [280] = {139, 275, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [281] = {139, 276, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [282] = {139, 277, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [283] = {139, 278, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [284] = {139, 279, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [285] = {139, 280, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [286] = {139, 281, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [287] = {139, 282, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [288] = {139, 283, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [289] = {139, 284, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [290] = {139, 285, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [291] = {139, 286, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [292] = {139, 287, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [293] = {139, 288, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [294] = {139, 289, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [295] = {139, 290, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [296] = {139, 291, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [297] = {139, 292, "DEV_AASRC0_TX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [298] = {139, 293, "DEV_AASRC0_TX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [299] = {139, 294, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [300] = {139, 295, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [301] = {139, 296, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, - [302] = {139, 297, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"}, + [7] = {139, 2, "DEV_AASRC0_RX0_SYNC", "Input muxed clock"}, + [8] = {139, 3, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [9] = {139, 4, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [10] = {139, 5, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [11] = {139, 6, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [12] = {139, 7, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [13] = {139, 8, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [14] = {139, 9, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [15] = {139, 10, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [16] = {139, 11, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [17] = {139, 12, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [18] = {139, 13, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [19] = {139, 14, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [20] = {139, 15, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [21] = {139, 16, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [22] = {139, 17, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [23] = {139, 18, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [24] = {139, 19, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [25] = {139, 20, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [26] = {139, 21, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [27] = {139, 22, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [28] = {139, 23, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [29] = {139, 24, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [30] = {139, 25, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [31] = {139, 26, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [32] = {139, 27, "DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [33] = {139, 28, "DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [34] = {139, 29, "DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [35] = {139, 30, "DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [36] = {139, 31, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [37] = {139, 32, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [38] = {139, 33, "DEV_AASRC0_RX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [39] = {139, 34, "DEV_AASRC0_RX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [40] = {139, 35, "DEV_AASRC0_RX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [41] = {139, 36, "DEV_AASRC0_RX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [42] = {139, 37, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [43] = {139, 38, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, + [44] = {139, 39, "DEV_AASRC0_RX1_SYNC", "Input muxed clock"}, + [45] = {139, 40, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [46] = {139, 41, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [47] = {139, 42, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [48] = {139, 43, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [49] = {139, 44, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [50] = {139, 45, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [51] = {139, 46, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [52] = {139, 47, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [53] = {139, 48, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [54] = {139, 49, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [55] = {139, 50, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [56] = {139, 51, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [57] = {139, 52, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [58] = {139, 53, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [59] = {139, 54, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [60] = {139, 55, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [61] = {139, 56, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [62] = {139, 57, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [63] = {139, 58, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [64] = {139, 59, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [65] = {139, 60, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [66] = {139, 61, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [67] = {139, 62, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [68] = {139, 63, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [69] = {139, 64, "DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [70] = {139, 65, "DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [71] = {139, 66, "DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [72] = {139, 67, "DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [73] = {139, 68, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [74] = {139, 69, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [75] = {139, 70, "DEV_AASRC0_RX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [76] = {139, 71, "DEV_AASRC0_RX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [77] = {139, 72, "DEV_AASRC0_RX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [78] = {139, 73, "DEV_AASRC0_RX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [79] = {139, 74, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [80] = {139, 75, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, + [81] = {139, 76, "DEV_AASRC0_RX2_SYNC", "Input muxed clock"}, + [82] = {139, 77, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [83] = {139, 78, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [84] = {139, 79, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [85] = {139, 80, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [86] = {139, 81, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [87] = {139, 82, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [88] = {139, 83, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [89] = {139, 84, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [90] = {139, 85, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [91] = {139, 86, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [92] = {139, 87, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [93] = {139, 88, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [94] = {139, 89, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [95] = {139, 90, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [96] = {139, 91, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [97] = {139, 92, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [98] = {139, 93, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [99] = {139, 94, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [100] = {139, 95, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [101] = {139, 96, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [102] = {139, 97, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [103] = {139, 98, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [104] = {139, 99, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [105] = {139, 100, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [106] = {139, 101, "DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [107] = {139, 102, "DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [108] = {139, 103, "DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [109] = {139, 104, "DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [110] = {139, 105, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [111] = {139, 106, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [112] = {139, 107, "DEV_AASRC0_RX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [113] = {139, 108, "DEV_AASRC0_RX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [114] = {139, 109, "DEV_AASRC0_RX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [115] = {139, 110, "DEV_AASRC0_RX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [116] = {139, 111, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [117] = {139, 112, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, + [118] = {139, 113, "DEV_AASRC0_RX3_SYNC", "Input muxed clock"}, + [119] = {139, 114, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [120] = {139, 115, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [121] = {139, 116, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [122] = {139, 117, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [123] = {139, 118, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [124] = {139, 119, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [125] = {139, 120, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [126] = {139, 121, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [127] = {139, 122, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [128] = {139, 123, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [129] = {139, 124, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [130] = {139, 125, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [131] = {139, 126, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [132] = {139, 127, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [133] = {139, 128, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [134] = {139, 129, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [135] = {139, 130, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [136] = {139, 131, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [137] = {139, 132, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [138] = {139, 133, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [139] = {139, 134, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [140] = {139, 135, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [141] = {139, 136, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [142] = {139, 137, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [143] = {139, 138, "DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [144] = {139, 139, "DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [145] = {139, 140, "DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [146] = {139, 141, "DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [147] = {139, 142, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [148] = {139, 143, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [149] = {139, 144, "DEV_AASRC0_RX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [150] = {139, 145, "DEV_AASRC0_RX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [151] = {139, 146, "DEV_AASRC0_RX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [152] = {139, 147, "DEV_AASRC0_RX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [153] = {139, 148, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [154] = {139, 149, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, + [155] = {139, 150, "DEV_AASRC0_TX0_SYNC", "Input muxed clock"}, + [156] = {139, 151, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [157] = {139, 152, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [158] = {139, 153, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [159] = {139, 154, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [160] = {139, 155, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [161] = {139, 156, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [162] = {139, 157, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [163] = {139, 158, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [164] = {139, 159, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [165] = {139, 160, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [166] = {139, 161, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [167] = {139, 162, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [168] = {139, 163, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [169] = {139, 164, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [170] = {139, 165, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [171] = {139, 166, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [172] = {139, 167, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [173] = {139, 168, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [174] = {139, 169, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [175] = {139, 170, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [176] = {139, 171, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [177] = {139, 172, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [178] = {139, 173, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [179] = {139, 174, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [180] = {139, 175, "DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [181] = {139, 176, "DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [182] = {139, 177, "DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [183] = {139, 178, "DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [184] = {139, 179, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [185] = {139, 180, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [186] = {139, 181, "DEV_AASRC0_TX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [187] = {139, 182, "DEV_AASRC0_TX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [188] = {139, 183, "DEV_AASRC0_TX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [189] = {139, 184, "DEV_AASRC0_TX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [190] = {139, 185, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [191] = {139, 186, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, + [192] = {139, 187, "DEV_AASRC0_TX1_SYNC", "Input muxed clock"}, + [193] = {139, 188, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [194] = {139, 189, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [195] = {139, 190, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [196] = {139, 191, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [197] = {139, 192, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [198] = {139, 193, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [199] = {139, 194, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [200] = {139, 195, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [201] = {139, 196, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [202] = {139, 197, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [203] = {139, 198, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [204] = {139, 199, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [205] = {139, 200, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [206] = {139, 201, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [207] = {139, 202, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [208] = {139, 203, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [209] = {139, 204, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [210] = {139, 205, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [211] = {139, 206, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [212] = {139, 207, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [213] = {139, 208, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [214] = {139, 209, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [215] = {139, 210, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [216] = {139, 211, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [217] = {139, 212, "DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [218] = {139, 213, "DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [219] = {139, 214, "DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [220] = {139, 215, "DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [221] = {139, 216, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [222] = {139, 217, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [223] = {139, 218, "DEV_AASRC0_TX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [224] = {139, 219, "DEV_AASRC0_TX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [225] = {139, 220, "DEV_AASRC0_TX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [226] = {139, 221, "DEV_AASRC0_TX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [227] = {139, 222, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [228] = {139, 223, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, + [229] = {139, 224, "DEV_AASRC0_TX2_SYNC", "Input muxed clock"}, + [230] = {139, 225, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [231] = {139, 226, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [232] = {139, 227, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [233] = {139, 228, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [234] = {139, 229, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [235] = {139, 230, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [236] = {139, 231, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [237] = {139, 232, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [238] = {139, 233, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [239] = {139, 234, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [240] = {139, 235, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [241] = {139, 236, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [242] = {139, 237, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [243] = {139, 238, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [244] = {139, 239, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [245] = {139, 240, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [246] = {139, 241, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [247] = {139, 242, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [248] = {139, 243, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [249] = {139, 244, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [250] = {139, 245, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [251] = {139, 246, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [252] = {139, 247, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [253] = {139, 248, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [254] = {139, 249, "DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [255] = {139, 250, "DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [256] = {139, 251, "DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [257] = {139, 252, "DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [258] = {139, 253, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [259] = {139, 254, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [260] = {139, 255, "DEV_AASRC0_TX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [261] = {139, 256, "DEV_AASRC0_TX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [262] = {139, 257, "DEV_AASRC0_TX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [263] = {139, 258, "DEV_AASRC0_TX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [264] = {139, 259, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [265] = {139, 260, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, + [266] = {139, 261, "DEV_AASRC0_TX3_SYNC", "Input muxed clock"}, + [267] = {139, 262, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [268] = {139, 263, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [269] = {139, 264, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [270] = {139, 265, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [271] = {139, 266, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [272] = {139, 267, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [273] = {139, 268, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [274] = {139, 269, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [275] = {139, 270, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [276] = {139, 271, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [277] = {139, 272, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [278] = {139, 273, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [279] = {139, 274, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [280] = {139, 275, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [281] = {139, 276, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [282] = {139, 277, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [283] = {139, 278, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [284] = {139, 279, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [285] = {139, 280, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [286] = {139, 281, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [287] = {139, 282, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [288] = {139, 283, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [289] = {139, 284, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [290] = {139, 285, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [291] = {139, 286, "DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [292] = {139, 287, "DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [293] = {139, 288, "DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [294] = {139, 289, "DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [295] = {139, 290, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [296] = {139, 291, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [297] = {139, 292, "DEV_AASRC0_TX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [298] = {139, 293, "DEV_AASRC0_TX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [299] = {139, 294, "DEV_AASRC0_TX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [300] = {139, 295, "DEV_AASRC0_TX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [301] = {139, 296, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, + [302] = {139, 297, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, [303] = {2, 0, "DEV_ATL0_VBUS_CLK", "Input clock"}, [304] = {2, 1, "DEV_ATL0_ATL_CLK", "Input muxed clock"}, [305] = {2, 2, "DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT1_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"}, @@ -348,7 +348,7 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [309] = {2, 6, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"}, [310] = {2, 7, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"}, [311] = {2, 8, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1", "Output clock"}, - [312] = {2, 9, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_0", "Output clock"}, + [312] = {2, 9, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT", "Output clock"}, [313] = {2, 10, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3", "Output clock"}, [314] = {2, 11, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2", "Output clock"}, [315] = {157, 0, "DEV_BOARD0_SPI0_CLK_IN", "Input clock"}, @@ -452,16 +452,16 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [413] = {157, 137, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, [414] = {157, 138, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_24_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, [415] = {157, 139, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, - [416] = {157, 140, "DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, + [416] = {157, 140, "DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, [417] = {157, 141, "DEV_BOARD0_OBSCLK0_IN_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, [418] = {157, 142, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, [419] = {157, 143, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, [420] = {157, 144, "DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, [421] = {157, 145, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, [422] = {157, 146, "DEV_BOARD0_OBSCLK1_IN", "Input muxed clock"}, - [423] = {157, 147, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_7_HSDIVOUT0_CLK3", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, - [424] = {157, 148, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK7", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, - [425] = {157, 149, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_13_HSDIVOUT0_CLK3", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, + [423] = {157, 147, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_7_HSDIVOUT0_CLK4", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, + [424] = {157, 148, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK8", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, + [425] = {157, 149, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_13_HSDIVOUT0_CLK4", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, [426] = {157, 152, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"}, [427] = {157, 153, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, [428] = {157, 154, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, @@ -472,8 +472,8 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [433] = {157, 173, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"}, [434] = {157, 174, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"}, [435] = {157, 175, "DEV_BOARD0_MCU_CLKOUT0_IN", "Input muxed clock"}, - [436] = {157, 176, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK4", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"}, - [437] = {157, 177, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK9", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"}, + [436] = {157, 176, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"}, + [437] = {157, 177, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"}, [438] = {157, 178, "DEV_BOARD0_LED_CLK_OUT", "Output clock"}, [439] = {157, 179, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"}, [440] = {157, 180, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"}, @@ -561,31 +561,31 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [522] = {157, 290, "DEV_BOARD0_MCASP11_AFSX_OUT", "Output clock"}, [523] = {157, 300, "DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT", "Output clock"}, [524] = {157, 301, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN", "Input muxed clock"}, - [525] = {157, 302, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [526] = {157, 303, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [527] = {157, 304, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [528] = {157, 305, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [529] = {157, 306, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [530] = {157, 307, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [531] = {157, 308, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [532] = {157, 309, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [533] = {157, 310, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [534] = {157, 311, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [535] = {157, 312, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [536] = {157, 313, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [537] = {157, 314, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [538] = {157, 315, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [539] = {157, 316, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [540] = {157, 317, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [541] = {157, 318, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [542] = {157, 319, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [543] = {157, 320, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [544] = {157, 321, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [545] = {157, 322, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [546] = {157, 323, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [547] = {157, 324, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [548] = {157, 325, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, - [549] = {157, 326, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [525] = {157, 302, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [526] = {157, 303, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [527] = {157, 304, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [528] = {157, 305, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [529] = {157, 306, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [530] = {157, 307, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [531] = {157, 308, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [532] = {157, 309, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [533] = {157, 310, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [534] = {157, 311, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [535] = {157, 312, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [536] = {157, 313, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [537] = {157, 314, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [538] = {157, 315, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [539] = {157, 316, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [540] = {157, 317, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [541] = {157, 318, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [542] = {157, 319, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [543] = {157, 320, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [544] = {157, 321, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [545] = {157, 322, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [546] = {157, 323, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [547] = {157, 324, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [548] = {157, 325, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, + [549] = {157, 326, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, [550] = {157, 327, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, [551] = {157, 328, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, [552] = {157, 329, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, @@ -594,31 +594,31 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [555] = {157, 334, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, [556] = {157, 335, "DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT", "Output clock"}, [557] = {157, 336, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN", "Input muxed clock"}, - [558] = {157, 337, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [559] = {157, 338, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [560] = {157, 339, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [561] = {157, 340, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [562] = {157, 341, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [563] = {157, 342, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [564] = {157, 343, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [565] = {157, 344, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [566] = {157, 345, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [567] = {157, 346, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [568] = {157, 347, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [569] = {157, 348, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [570] = {157, 349, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [571] = {157, 350, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [572] = {157, 351, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [573] = {157, 352, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [574] = {157, 353, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [575] = {157, 354, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [576] = {157, 355, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [577] = {157, 356, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [578] = {157, 357, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [579] = {157, 358, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [580] = {157, 359, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [581] = {157, 360, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, - [582] = {157, 361, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [558] = {157, 337, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [559] = {157, 338, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [560] = {157, 339, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [561] = {157, 340, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [562] = {157, 341, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [563] = {157, 342, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [564] = {157, 343, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [565] = {157, 344, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [566] = {157, 345, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [567] = {157, 346, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [568] = {157, 347, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [569] = {157, 348, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [570] = {157, 349, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [571] = {157, 350, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [572] = {157, 351, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [573] = {157, 352, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [574] = {157, 353, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [575] = {157, 354, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [576] = {157, 355, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [577] = {157, 356, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [578] = {157, 357, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [579] = {157, 358, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [580] = {157, 359, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [581] = {157, 360, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, + [582] = {157, 361, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, [583] = {157, 362, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, [584] = {157, 363, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, [585] = {157, 364, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, @@ -627,31 +627,31 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [588] = {157, 369, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, [589] = {157, 370, "DEV_BOARD0_AUDIO_EXT_REFCLK2_OUT", "Output clock"}, [590] = {157, 371, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN", "Input muxed clock"}, - [591] = {157, 372, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [592] = {157, 373, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [593] = {157, 374, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [594] = {157, 375, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [595] = {157, 376, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [596] = {157, 377, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [597] = {157, 378, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [598] = {157, 379, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [599] = {157, 380, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [600] = {157, 381, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [601] = {157, 382, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [602] = {157, 383, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [603] = {157, 384, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [604] = {157, 385, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [605] = {157, 386, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [606] = {157, 387, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [607] = {157, 388, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [608] = {157, 389, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [609] = {157, 390, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [610] = {157, 391, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [611] = {157, 392, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [612] = {157, 393, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [613] = {157, 394, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [614] = {157, 395, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, - [615] = {157, 396, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [591] = {157, 372, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [592] = {157, 373, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [593] = {157, 374, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [594] = {157, 375, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [595] = {157, 376, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [596] = {157, 377, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [597] = {157, 378, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [598] = {157, 379, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [599] = {157, 380, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [600] = {157, 381, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [601] = {157, 382, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [602] = {157, 383, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [603] = {157, 384, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [604] = {157, 385, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [605] = {157, 386, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [606] = {157, 387, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [607] = {157, 388, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [608] = {157, 389, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [609] = {157, 390, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [610] = {157, 391, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [611] = {157, 392, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [612] = {157, 393, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [613] = {157, 394, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [614] = {157, 395, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, + [615] = {157, 396, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, [616] = {157, 397, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, [617] = {157, 398, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, [618] = {157, 399, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, @@ -660,31 +660,31 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [621] = {157, 404, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, [622] = {157, 405, "DEV_BOARD0_AUDIO_EXT_REFCLK3_OUT", "Output clock"}, [623] = {157, 406, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN", "Input muxed clock"}, - [624] = {157, 407, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [625] = {157, 408, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [626] = {157, 409, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [627] = {157, 410, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [628] = {157, 411, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [629] = {157, 412, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [630] = {157, 413, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [631] = {157, 414, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [632] = {157, 415, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [633] = {157, 416, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [634] = {157, 417, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [635] = {157, 418, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [636] = {157, 419, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [637] = {157, 420, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [638] = {157, 421, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [639] = {157, 422, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [640] = {157, 423, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [641] = {157, 424, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [642] = {157, 425, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [643] = {157, 426, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [644] = {157, 427, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [645] = {157, 428, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [646] = {157, 429, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [647] = {157, 430, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, - [648] = {157, 431, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [624] = {157, 407, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [625] = {157, 408, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [626] = {157, 409, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [627] = {157, 410, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [628] = {157, 411, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [629] = {157, 412, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [630] = {157, 413, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [631] = {157, 414, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [632] = {157, 415, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [633] = {157, 416, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [634] = {157, 417, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [635] = {157, 418, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [636] = {157, 419, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [637] = {157, 420, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [638] = {157, 421, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [639] = {157, 422, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [640] = {157, 423, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [641] = {157, 424, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [642] = {157, 425, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [643] = {157, 426, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [644] = {157, 427, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [645] = {157, 428, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [646] = {157, 429, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [647] = {157, 430, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, + [648] = {157, 431, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, [649] = {157, 432, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, [650] = {157, 433, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, [651] = {157, 434, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, @@ -694,1672 +694,1672 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [655] = {142, 0, "DEV_C66SS0_CORE0_GEM_TRC_CLK", "Input clock"}, [656] = {142, 1, "DEV_C66SS0_CORE0_GEM_CLK2_OUT_CLK", "Output clock"}, [657] = {142, 4, "DEV_C66SS0_CORE0_GEM_PBIST_ROM_CLK", "Output clock"}, - [658] = {121, 0, "DEV_C66SS0_INTROUTER0_INTR_CLK", "Input clock"}, - [659] = {143, 0, "DEV_C66SS1_CORE0_GEM_TRC_CLK", "Input clock"}, - [660] = {143, 1, "DEV_C66SS1_CORE0_GEM_CLK2_OUT_CLK", "Output clock"}, - [661] = {143, 4, "DEV_C66SS1_CORE0_GEM_PBIST_ROM_CLK", "Output clock"}, - [662] = {122, 0, "DEV_C66SS1_INTROUTER0_INTR_CLK", "Input clock"}, - [663] = {15, 0, "DEV_C71SS0_C7X_CLK", "Input clock"}, - [664] = {15, 1, "DEV_C71SS0_PLL_CTRL_CLK", "Input clock"}, - [665] = {16, 0, "DEV_C71SS0_MMA_PLL_CTRL_CLK", "Input clock"}, - [666] = {16, 1, "DEV_C71SS0_MMA_MMA_CLK", "Input clock"}, - [667] = {123, 0, "DEV_CMPEVENT_INTRTR0_INTR_CLK", "Input clock"}, - [668] = {5, 0, "DEV_COMPUTE_CLUSTER0_CFG_WRAP_CLK4_CLK", "Input clock"}, - [669] = {6, 0, "DEV_COMPUTE_CLUSTER0_CLEC_CLK4_CLK", "Input clock"}, - [670] = {6, 1, "DEV_COMPUTE_CLUSTER0_CLEC_CLK1_CLK", "Input clock"}, - [671] = {7, 0, "DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK", "Input clock"}, - [672] = {7, 1, "DEV_COMPUTE_CLUSTER0_CORE_CORE_CLK1_CLK", "Input clock"}, - [673] = {8, 0, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_PLL_CTRL_CLK", "Input clock"}, - [674] = {8, 1, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_DDRSS_DDR_PLL_CLK", "Input clock"}, - [675] = {9, 0, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK1_CLK_CLK", "Input clock"}, - [676] = {9, 1, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK2_CLK_CLK", "Input clock"}, - [677] = {12, 0, "DEV_COMPUTE_CLUSTER0_DMSC_WRAP_CLK4_CLK_CLK", "Input clock"}, - [678] = {13, 0, "DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_MSMC_CLK1_CLK", "Input clock"}, - [679] = {14, 0, "DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK", "Input clock"}, - [680] = {17, 0, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVP_CLK1_CLK_CLK", "Input clock"}, - [681] = {17, 1, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK4_CLK_CLK", "Input clock"}, - [682] = {17, 2, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK2_CLK_CLK", "Input clock"}, - [683] = {19, 0, "DEV_CPSW0_GMII3_MT_CLK", "Input clock"}, - [684] = {19, 1, "DEV_CPSW0_SERDES6_TXFCLK", "Input clock"}, - [685] = {19, 2, "DEV_CPSW0_SERDES8_TXMCLK", "Input clock"}, - [686] = {19, 3, "DEV_CPSW0_GMII2_MR_CLK", "Input clock"}, - [687] = {19, 4, "DEV_CPSW0_SERDES2_TXFCLK", "Input clock"}, - [688] = {19, 5, "DEV_CPSW0_SERDES4_RXCLK", "Input clock"}, - [689] = {19, 6, "DEV_CPSW0_SERDES7_TXMCLK", "Input clock"}, - [690] = {19, 7, "DEV_CPSW0_SERDES7_RXCLK", "Input clock"}, - [691] = {19, 8, "DEV_CPSW0_SERDES6_REFCLK", "Input clock"}, - [692] = {19, 9, "DEV_CPSW0_SERDES5_TXFCLK", "Input clock"}, - [693] = {19, 10, "DEV_CPSW0_SERDES5_RXCLK", "Input clock"}, - [694] = {19, 11, "DEV_CPSW0_GMII4_MT_CLK", "Input clock"}, - [695] = {19, 12, "DEV_CPSW0_SERDES3_TXFCLK", "Input clock"}, - [696] = {19, 13, "DEV_CPSW0_SERDES2_REFCLK", "Input clock"}, - [697] = {19, 14, "DEV_CPSW0_SERDES4_RXFCLK", "Input clock"}, - [698] = {19, 15, "DEV_CPSW0_SERDES6_RXFCLK", "Input clock"}, - [699] = {19, 16, "DEV_CPSW0_CPTS_RFT_CLK", "Input muxed clock"}, - [700] = {19, 17, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, - [701] = {19, 18, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, - [702] = {19, 19, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, - [703] = {19, 20, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, - [704] = {19, 21, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, - [705] = {19, 22, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, - [706] = {19, 23, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, - [707] = {19, 24, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, - [708] = {19, 25, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, - [709] = {19, 26, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, - [710] = {19, 27, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, - [711] = {19, 28, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, - [712] = {19, 29, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, - [713] = {19, 30, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, - [714] = {19, 31, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, - [715] = {19, 32, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, - [716] = {19, 33, "DEV_CPSW0_SERDES5_RXFCLK", "Input clock"}, - [717] = {19, 34, "DEV_CPSW0_SERDES5_TXMCLK", "Input clock"}, - [718] = {19, 35, "DEV_CPSW0_GMII5_MT_CLK", "Input clock"}, - [719] = {19, 36, "DEV_CPSW0_SERDES2_RXCLK", "Input clock"}, - [720] = {19, 37, "DEV_CPSW0_SERDES8_RXFCLK", "Input clock"}, - [721] = {19, 38, "DEV_CPSW0_SERDES1_RXFCLK", "Input clock"}, - [722] = {19, 39, "DEV_CPSW0_SERDES8_RXCLK", "Input clock"}, - [723] = {19, 40, "DEV_CPSW0_GMII_RFT_CLK", "Input clock"}, - [724] = {19, 41, "DEV_CPSW0_SERDES3_REFCLK", "Input clock"}, - [725] = {19, 42, "DEV_CPSW0_RGMII_MHZ_250_CLK", "Input clock"}, - [726] = {19, 43, "DEV_CPSW0_SERDES7_REFCLK", "Input clock"}, - [727] = {19, 44, "DEV_CPSW0_GMII6_MT_CLK", "Input clock"}, - [728] = {19, 45, "DEV_CPSW0_SERDES6_TXMCLK", "Input clock"}, - [729] = {19, 46, "DEV_CPSW0_RMII_MHZ_50_CLK", "Input clock"}, - [730] = {19, 47, "DEV_CPSW0_GMII4_MR_CLK", "Input clock"}, - [731] = {19, 48, "DEV_CPSW0_SERDES2_TXMCLK", "Input clock"}, - [732] = {19, 49, "DEV_CPSW0_RGMII_MHZ_50_CLK", "Input clock"}, - [733] = {19, 50, "DEV_CPSW0_SERDES4_TXMCLK", "Input clock"}, - [734] = {19, 51, "DEV_CPSW0_SERDES3_RXFCLK", "Input clock"}, - [735] = {19, 52, "DEV_CPSW0_GMII8_MT_CLK", "Input clock"}, - [736] = {19, 53, "DEV_CPSW0_SERDES7_TXFCLK", "Input clock"}, - [737] = {19, 54, "DEV_CPSW0_GMII7_MT_CLK", "Input clock"}, - [738] = {19, 55, "DEV_CPSW0_GMII7_MR_CLK", "Input clock"}, - [739] = {19, 56, "DEV_CPSW0_SERDES6_RXCLK", "Input clock"}, - [740] = {19, 57, "DEV_CPSW0_SERDES3_RXCLK", "Input clock"}, - [741] = {19, 58, "DEV_CPSW0_SERDES4_REFCLK", "Input clock"}, - [742] = {19, 59, "DEV_CPSW0_SERDES1_RXCLK", "Input clock"}, - [743] = {19, 60, "DEV_CPSW0_SERDES1_TXFCLK", "Input clock"}, - [744] = {19, 61, "DEV_CPSW0_GMII6_MR_CLK", "Input clock"}, - [745] = {19, 62, "DEV_CPSW0_SERDES1_REFCLK", "Input clock"}, - [746] = {19, 63, "DEV_CPSW0_RGMII_MHZ_5_CLK", "Input clock"}, - [747] = {19, 64, "DEV_CPSW0_SERDES5_REFCLK", "Input clock"}, - [748] = {19, 65, "DEV_CPSW0_GMII2_MT_CLK", "Input clock"}, - [749] = {19, 66, "DEV_CPSW0_SERDES8_TXFCLK", "Input clock"}, - [750] = {19, 67, "DEV_CPSW0_GMII8_MR_CLK", "Input clock"}, - [751] = {19, 68, "DEV_CPSW0_GMII1_MR_CLK", "Input clock"}, - [752] = {19, 69, "DEV_CPSW0_SERDES8_REFCLK", "Input clock"}, - [753] = {19, 70, "DEV_CPSW0_SERDES3_TXMCLK", "Input clock"}, - [754] = {19, 71, "DEV_CPSW0_GMII3_MR_CLK", "Input clock"}, - [755] = {19, 72, "DEV_CPSW0_SERDES1_TXMCLK", "Input clock"}, - [756] = {19, 73, "DEV_CPSW0_SERDES7_RXFCLK", "Input clock"}, - [757] = {19, 74, "DEV_CPSW0_GMII5_MR_CLK", "Input clock"}, - [758] = {19, 75, "DEV_CPSW0_GMII1_MT_CLK", "Input clock"}, - [759] = {19, 76, "DEV_CPSW0_SERDES2_RXFCLK", "Input clock"}, - [760] = {19, 77, "DEV_CPSW0_SERDES4_TXFCLK", "Input clock"}, - [761] = {19, 78, "DEV_CPSW0_SERDES3_TXCLK", "Output clock"}, - [762] = {19, 79, "DEV_CPSW0_CPTS_GENF0_0", "Output clock"}, - [763] = {19, 80, "DEV_CPSW0_SERDES5_TXCLK", "Output clock"}, - [764] = {19, 81, "DEV_CPSW0_SERDES6_TXCLK", "Output clock"}, - [765] = {19, 82, "DEV_CPSW0_SERDES8_TXCLK", "Output clock"}, - [766] = {19, 83, "DEV_CPSW0_SERDES1_TXCLK", "Output clock"}, - [767] = {19, 84, "DEV_CPSW0_SERDES4_TXCLK", "Output clock"}, - [768] = {19, 85, "DEV_CPSW0_SERDES2_TXCLK", "Output clock"}, - [769] = {19, 86, "DEV_CPSW0_SERDES7_TXCLK", "Output clock"}, - [770] = {19, 87, "DEV_CPSW0_MDIO_MDCLK_O_0", "Output clock"}, - [771] = {19, 89, "DEV_CPSW0_CPPI_CLK_CLK", "Input clock"}, - [772] = {20, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"}, - [773] = {21, 0, "DEV_CPT2_AGGR1_VCLK_CLK", "Input clock"}, - [774] = {23, 0, "DEV_CPT2_AGGR2_VCLK_CLK", "Input clock"}, - [775] = {25, 0, "DEV_CSI_PSILSS0_MAIN_CLK", "Input clock"}, - [776] = {26, 0, "DEV_CSI_RX_IF0_VBUS_CLK_CLK", "Input clock"}, - [777] = {26, 1, "DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK", "Input clock"}, - [778] = {26, 2, "DEV_CSI_RX_IF0_MAIN_CLK_CLK", "Input clock"}, - [779] = {26, 3, "DEV_CSI_RX_IF0_VP_CLK_CLK", "Input clock"}, - [780] = {27, 0, "DEV_CSI_RX_IF1_VBUS_CLK_CLK", "Input clock"}, - [781] = {27, 1, "DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK", "Input clock"}, - [782] = {27, 2, "DEV_CSI_RX_IF1_MAIN_CLK_CLK", "Input clock"}, - [783] = {27, 3, "DEV_CSI_RX_IF1_VP_CLK_CLK", "Input clock"}, - [784] = {28, 0, "DEV_CSI_TX_IF0_ESC_CLK_CLK", "Input clock"}, - [785] = {28, 1, "DEV_CSI_TX_IF0_DPHY_TXBYTECLKHS_CL_CLK", "Input clock"}, - [786] = {28, 2, "DEV_CSI_TX_IF0_VBUS_CLK_CLK", "Input clock"}, - [787] = {28, 3, "DEV_CSI_TX_IF0_MAIN_CLK_CLK", "Input clock"}, - [788] = {30, 0, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"}, - [789] = {30, 1, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"}, - [790] = {30, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, - [791] = {30, 3, "DEV_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, - [792] = {30, 4, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, - [793] = {30, 5, "DEV_DCC0_VBUS_CLK", "Input clock"}, - [794] = {30, 6, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, - [795] = {30, 7, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, - [796] = {30, 8, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, - [797] = {30, 9, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"}, - [798] = {30, 10, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, - [799] = {30, 11, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, - [800] = {30, 12, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"}, - [801] = {31, 0, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"}, - [802] = {31, 1, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"}, - [803] = {31, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"}, - [804] = {31, 3, "DEV_DCC1_DCC_CLKSRC7_CLK", "Input clock"}, - [805] = {31, 4, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"}, - [806] = {31, 5, "DEV_DCC1_VBUS_CLK", "Input clock"}, - [807] = {31, 6, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"}, - [808] = {31, 7, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"}, - [809] = {31, 8, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"}, - [810] = {31, 9, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"}, - [811] = {31, 10, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"}, - [812] = {31, 11, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"}, - [813] = {31, 12, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"}, - [814] = {41, 0, "DEV_DCC10_DCC_INPUT10_CLK", "Input clock"}, - [815] = {41, 1, "DEV_DCC10_DCC_INPUT01_CLK", "Input clock"}, - [816] = {41, 2, "DEV_DCC10_DCC_CLKSRC2_CLK", "Input clock"}, - [817] = {41, 3, "DEV_DCC10_DCC_CLKSRC7_CLK", "Input clock"}, - [818] = {41, 4, "DEV_DCC10_DCC_CLKSRC0_CLK", "Input clock"}, - [819] = {41, 5, "DEV_DCC10_VBUS_CLK", "Input clock"}, - [820] = {41, 6, "DEV_DCC10_DCC_CLKSRC4_CLK", "Input clock"}, - [821] = {41, 7, "DEV_DCC10_DCC_CLKSRC1_CLK", "Input clock"}, - [822] = {41, 8, "DEV_DCC10_DCC_CLKSRC3_CLK", "Input clock"}, - [823] = {41, 9, "DEV_DCC10_DCC_INPUT00_CLK", "Input clock"}, - [824] = {41, 10, "DEV_DCC10_DCC_CLKSRC5_CLK", "Input clock"}, - [825] = {41, 11, "DEV_DCC10_DCC_CLKSRC6_CLK", "Input clock"}, - [826] = {41, 12, "DEV_DCC10_DCC_INPUT02_CLK", "Input clock"}, - [827] = {42, 0, "DEV_DCC11_DCC_INPUT10_CLK", "Input clock"}, - [828] = {42, 1, "DEV_DCC11_DCC_INPUT01_CLK", "Input clock"}, - [829] = {42, 2, "DEV_DCC11_DCC_CLKSRC2_CLK", "Input clock"}, - [830] = {42, 3, "DEV_DCC11_DCC_CLKSRC7_CLK", "Input clock"}, - [831] = {42, 4, "DEV_DCC11_DCC_CLKSRC0_CLK", "Input clock"}, - [832] = {42, 5, "DEV_DCC11_VBUS_CLK", "Input clock"}, - [833] = {42, 6, "DEV_DCC11_DCC_CLKSRC4_CLK", "Input clock"}, - [834] = {42, 7, "DEV_DCC11_DCC_CLKSRC1_CLK", "Input clock"}, - [835] = {42, 8, "DEV_DCC11_DCC_CLKSRC3_CLK", "Input clock"}, - [836] = {42, 9, "DEV_DCC11_DCC_INPUT00_CLK", "Input clock"}, - [837] = {42, 10, "DEV_DCC11_DCC_CLKSRC5_CLK", "Input clock"}, - [838] = {42, 11, "DEV_DCC11_DCC_CLKSRC6_CLK", "Input clock"}, - [839] = {42, 12, "DEV_DCC11_DCC_INPUT02_CLK", "Input clock"}, - [840] = {43, 0, "DEV_DCC12_DCC_INPUT10_CLK", "Input clock"}, - [841] = {43, 1, "DEV_DCC12_DCC_INPUT01_CLK", "Input clock"}, - [842] = {43, 2, "DEV_DCC12_DCC_CLKSRC2_CLK", "Input clock"}, - [843] = {43, 3, "DEV_DCC12_DCC_CLKSRC7_CLK", "Input clock"}, - [844] = {43, 4, "DEV_DCC12_DCC_CLKSRC0_CLK", "Input clock"}, - [845] = {43, 5, "DEV_DCC12_VBUS_CLK", "Input clock"}, - [846] = {43, 6, "DEV_DCC12_DCC_CLKSRC4_CLK", "Input clock"}, - [847] = {43, 7, "DEV_DCC12_DCC_CLKSRC1_CLK", "Input clock"}, - [848] = {43, 8, "DEV_DCC12_DCC_CLKSRC3_CLK", "Input clock"}, - [849] = {43, 9, "DEV_DCC12_DCC_INPUT00_CLK", "Input clock"}, - [850] = {43, 10, "DEV_DCC12_DCC_CLKSRC5_CLK", "Input clock"}, - [851] = {43, 11, "DEV_DCC12_DCC_CLKSRC6_CLK", "Input clock"}, - [852] = {43, 12, "DEV_DCC12_DCC_INPUT02_CLK", "Input clock"}, - [853] = {32, 0, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"}, - [854] = {32, 1, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"}, - [855] = {32, 2, "DEV_DCC2_DCC_CLKSRC2_CLK", "Input clock"}, - [856] = {32, 3, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"}, - [857] = {32, 4, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"}, - [858] = {32, 5, "DEV_DCC2_VBUS_CLK", "Input clock"}, - [859] = {32, 6, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"}, - [860] = {32, 7, "DEV_DCC2_DCC_CLKSRC1_CLK", "Input clock"}, - [861] = {32, 8, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"}, - [862] = {32, 9, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"}, - [863] = {32, 10, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"}, - [864] = {32, 11, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"}, - [865] = {32, 12, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"}, - [866] = {33, 0, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"}, - [867] = {33, 1, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"}, - [868] = {33, 2, "DEV_DCC3_DCC_CLKSRC2_CLK", "Input clock"}, - [869] = {33, 3, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"}, - [870] = {33, 4, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"}, - [871] = {33, 5, "DEV_DCC3_VBUS_CLK", "Input clock"}, - [872] = {33, 6, "DEV_DCC3_DCC_CLKSRC4_CLK", "Input clock"}, - [873] = {33, 7, "DEV_DCC3_DCC_CLKSRC1_CLK", "Input clock"}, - [874] = {33, 8, "DEV_DCC3_DCC_CLKSRC3_CLK", "Input clock"}, - [875] = {33, 9, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"}, - [876] = {33, 10, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"}, - [877] = {33, 11, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"}, - [878] = {33, 12, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"}, - [879] = {34, 0, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"}, - [880] = {34, 1, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"}, - [881] = {34, 2, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"}, - [882] = {34, 3, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"}, - [883] = {34, 4, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input clock"}, - [884] = {34, 5, "DEV_DCC4_VBUS_CLK", "Input clock"}, - [885] = {34, 6, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"}, - [886] = {34, 7, "DEV_DCC4_DCC_CLKSRC1_CLK", "Input clock"}, - [887] = {34, 8, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"}, - [888] = {34, 9, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"}, - [889] = {34, 10, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"}, - [890] = {34, 11, "DEV_DCC4_DCC_CLKSRC6_CLK", "Input clock"}, - [891] = {34, 12, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"}, - [892] = {36, 0, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"}, - [893] = {36, 1, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"}, - [894] = {36, 2, "DEV_DCC5_DCC_CLKSRC2_CLK", "Input clock"}, - [895] = {36, 3, "DEV_DCC5_DCC_CLKSRC7_CLK", "Input clock"}, - [896] = {36, 4, "DEV_DCC5_DCC_CLKSRC0_CLK", "Input clock"}, - [897] = {36, 5, "DEV_DCC5_VBUS_CLK", "Input clock"}, - [898] = {36, 6, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"}, - [899] = {36, 7, "DEV_DCC5_DCC_CLKSRC1_CLK", "Input clock"}, - [900] = {36, 8, "DEV_DCC5_DCC_CLKSRC3_CLK", "Input clock"}, - [901] = {36, 9, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"}, - [902] = {36, 10, "DEV_DCC5_DCC_CLKSRC5_CLK", "Input clock"}, - [903] = {36, 11, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"}, - [904] = {36, 12, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"}, - [905] = {37, 0, "DEV_DCC6_DCC_INPUT10_CLK", "Input clock"}, - [906] = {37, 1, "DEV_DCC6_DCC_INPUT01_CLK", "Input clock"}, - [907] = {37, 2, "DEV_DCC6_DCC_CLKSRC2_CLK", "Input clock"}, - [908] = {37, 3, "DEV_DCC6_DCC_CLKSRC7_CLK", "Input clock"}, - [909] = {37, 4, "DEV_DCC6_DCC_CLKSRC0_CLK", "Input clock"}, - [910] = {37, 5, "DEV_DCC6_VBUS_CLK", "Input clock"}, - [911] = {37, 6, "DEV_DCC6_DCC_CLKSRC4_CLK", "Input clock"}, - [912] = {37, 7, "DEV_DCC6_DCC_CLKSRC1_CLK", "Input clock"}, - [913] = {37, 8, "DEV_DCC6_DCC_CLKSRC3_CLK", "Input clock"}, - [914] = {37, 9, "DEV_DCC6_DCC_INPUT00_CLK", "Input clock"}, - [915] = {37, 10, "DEV_DCC6_DCC_CLKSRC5_CLK", "Input clock"}, - [916] = {37, 11, "DEV_DCC6_DCC_CLKSRC6_CLK", "Input clock"}, - [917] = {37, 12, "DEV_DCC6_DCC_INPUT02_CLK", "Input clock"}, - [918] = {38, 0, "DEV_DCC7_DCC_INPUT10_CLK", "Input clock"}, - [919] = {38, 1, "DEV_DCC7_DCC_INPUT01_CLK", "Input clock"}, - [920] = {38, 2, "DEV_DCC7_DCC_CLKSRC2_CLK", "Input clock"}, - [921] = {38, 3, "DEV_DCC7_DCC_CLKSRC7_CLK", "Input clock"}, - [922] = {38, 4, "DEV_DCC7_DCC_CLKSRC0_CLK", "Input clock"}, - [923] = {38, 5, "DEV_DCC7_VBUS_CLK", "Input clock"}, - [924] = {38, 6, "DEV_DCC7_DCC_CLKSRC4_CLK", "Input clock"}, - [925] = {38, 7, "DEV_DCC7_DCC_CLKSRC1_CLK", "Input clock"}, - [926] = {38, 8, "DEV_DCC7_DCC_CLKSRC3_CLK", "Input clock"}, - [927] = {38, 9, "DEV_DCC7_DCC_INPUT00_CLK", "Input clock"}, - [928] = {38, 10, "DEV_DCC7_DCC_CLKSRC5_CLK", "Input clock"}, - [929] = {38, 11, "DEV_DCC7_DCC_CLKSRC6_CLK", "Input clock"}, - [930] = {38, 12, "DEV_DCC7_DCC_INPUT02_CLK", "Input clock"}, - [931] = {39, 0, "DEV_DCC8_DCC_INPUT10_CLK", "Input clock"}, - [932] = {39, 1, "DEV_DCC8_DCC_INPUT01_CLK", "Input clock"}, - [933] = {39, 2, "DEV_DCC8_DCC_CLKSRC2_CLK", "Input clock"}, - [934] = {39, 3, "DEV_DCC8_DCC_CLKSRC7_CLK", "Input clock"}, - [935] = {39, 4, "DEV_DCC8_DCC_CLKSRC0_CLK", "Input clock"}, - [936] = {39, 5, "DEV_DCC8_VBUS_CLK", "Input clock"}, - [937] = {39, 6, "DEV_DCC8_DCC_CLKSRC4_CLK", "Input clock"}, - [938] = {39, 7, "DEV_DCC8_DCC_CLKSRC1_CLK", "Input clock"}, - [939] = {39, 8, "DEV_DCC8_DCC_CLKSRC3_CLK", "Input clock"}, - [940] = {39, 9, "DEV_DCC8_DCC_INPUT00_CLK", "Input clock"}, - [941] = {39, 10, "DEV_DCC8_DCC_CLKSRC5_CLK", "Input clock"}, - [942] = {39, 11, "DEV_DCC8_DCC_CLKSRC6_CLK", "Input clock"}, - [943] = {39, 12, "DEV_DCC8_DCC_INPUT02_CLK", "Input clock"}, - [944] = {40, 0, "DEV_DCC9_DCC_INPUT10_CLK", "Input clock"}, - [945] = {40, 1, "DEV_DCC9_DCC_INPUT01_CLK", "Input clock"}, - [946] = {40, 2, "DEV_DCC9_DCC_CLKSRC2_CLK", "Input clock"}, - [947] = {40, 3, "DEV_DCC9_DCC_CLKSRC7_CLK", "Input clock"}, - [948] = {40, 4, "DEV_DCC9_DCC_CLKSRC0_CLK", "Input clock"}, - [949] = {40, 5, "DEV_DCC9_VBUS_CLK", "Input clock"}, - [950] = {40, 6, "DEV_DCC9_DCC_CLKSRC4_CLK", "Input clock"}, - [951] = {40, 7, "DEV_DCC9_DCC_CLKSRC1_CLK", "Input clock"}, - [952] = {40, 8, "DEV_DCC9_DCC_CLKSRC3_CLK", "Input clock"}, - [953] = {40, 9, "DEV_DCC9_DCC_INPUT00_CLK", "Input clock"}, - [954] = {40, 10, "DEV_DCC9_DCC_CLKSRC5_CLK", "Input clock"}, - [955] = {40, 11, "DEV_DCC9_DCC_CLKSRC6_CLK", "Input clock"}, - [956] = {40, 12, "DEV_DCC9_DCC_INPUT02_CLK", "Input clock"}, - [957] = {47, 0, "DEV_DDR0_DDRSS_VBUS_CLK", "Input clock"}, - [958] = {47, 1, "DEV_DDR0_PLL_CTRL_CLK", "Input clock"}, - [959] = {47, 2, "DEV_DDR0_DDRSS_DDR_PLL_CLK", "Input clock"}, - [960] = {47, 3, "DEV_DDR0_DDRSS_CFG_CLK", "Input clock"}, - [961] = {47, 4, "DEV_DDR0_DDRSS_IO_CK_N_0", "Output clock"}, - [962] = {47, 5, "DEV_DDR0_DDRSS_IO_CK_0", "Output clock"}, - [963] = {304, 5, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"}, - [964] = {304, 9, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"}, - [965] = {304, 25, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"}, - [966] = {304, 32, "DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK_0", "Output clock"}, - [967] = {304, 35, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"}, - [968] = {144, 0, "DEV_DECODER0_SYS_CLK", "Input clock"}, - [969] = {305, 0, "DEV_DMPAC0_SDE_0_CLK", "Input clock"}, - [970] = {48, 0, "DEV_DMPAC_TOP_MAIN_0_CLK", "Input clock"}, - [971] = {48, 1, "DEV_DMPAC_TOP_MAIN_0_PLL_DCO_CLK", "Input clock"}, - [972] = {147, 0, "DEV_DPHY_RX0_MAIN_CLK_CLK", "Input clock"}, - [973] = {147, 1, "DEV_DPHY_RX0_PPI_RX_BYTE_CLK", "Output clock"}, - [974] = {148, 0, "DEV_DPHY_RX1_MAIN_CLK_CLK", "Input clock"}, - [975] = {148, 1, "DEV_DPHY_RX1_PPI_RX_BYTE_CLK", "Output clock"}, - [976] = {296, 0, "DEV_DPHY_TX0_CLK", "Input clock"}, - [977] = {296, 1, "DEV_DPHY_TX0_PSM_CLK", "Input clock"}, - [978] = {296, 2, "DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK", "Input clock"}, - [979] = {296, 3, "DEV_DPHY_TX0_DPHY_REF_CLK", "Input muxed clock"}, - [980] = {296, 4, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, - [981] = {296, 5, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, - [982] = {296, 6, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, - [983] = {296, 7, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, - [984] = {296, 8, "DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK", "Output clock"}, - [985] = {296, 9, "DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK", "Output clock"}, - [986] = {296, 10, "DEV_DPHY_TX0_CK_P_0", "Output clock"}, - [987] = {296, 11, "DEV_DPHY_TX0_CK_M_0", "Output clock"}, - [988] = {296, 12, "DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK", "Output clock"}, - [989] = {152, 0, "DEV_DSS0_DSS_FUNC_CLK", "Input clock"}, - [990] = {152, 1, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK", "Input muxed clock"}, - [991] = {152, 2, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"}, - [992] = {152, 3, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"}, - [993] = {152, 4, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK", "Input muxed clock"}, - [994] = {152, 5, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, - [995] = {152, 6, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, - [996] = {152, 7, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, - [997] = {152, 8, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, - [998] = {152, 9, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK", "Input muxed clock"}, - [999] = {152, 10, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"}, - [1000] = {152, 11, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"}, - [1001] = {152, 12, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"}, - [1002] = {152, 13, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK", "Input muxed clock"}, - [1003] = {152, 14, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, - [1004] = {152, 15, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, - [1005] = {152, 16, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, - [1006] = {152, 17, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, - [1007] = {152, 18, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, - [1008] = {152, 23, "DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK", "Output clock"}, - [1009] = {152, 24, "DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK", "Output clock"}, - [1010] = {152, 25, "DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK", "Output clock"}, - [1011] = {152, 27, "DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK", "Output clock"}, - [1012] = {152, 29, "DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK", "Output clock"}, - [1013] = {152, 31, "DEV_DSS0_DPI0_EXT_CLKSEL", "Input muxed clock"}, - [1014] = {152, 32, "DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL"}, - [1015] = {152, 33, "DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_BOARD_0_VOUT1_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL"}, - [1016] = {152, 34, "DEV_DSS0_DPI1_EXT_CLKSEL", "Input muxed clock"}, - [1017] = {152, 35, "DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL"}, - [1018] = {152, 36, "DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_BOARD_0_VOUT2_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL"}, - [1019] = {150, 0, "DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK", "Input clock"}, - [1020] = {150, 1, "DEV_DSS_DSI0_DPI_0_CLK", "Input clock"}, - [1021] = {150, 2, "DEV_DSS_DSI0_PLL_CTRL_CLK", "Input clock"}, - [1022] = {150, 3, "DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK", "Input clock"}, - [1023] = {150, 4, "DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK", "Input clock"}, - [1024] = {150, 5, "DEV_DSS_DSI0_SYS_CLK", "Input clock"}, - [1025] = {151, 0, "DEV_DSS_EDP0_PHY_LN1_TXFCLK", "Input clock"}, - [1026] = {151, 1, "DEV_DSS_EDP0_DPI_2_CLK", "Input clock"}, - [1027] = {151, 2, "DEV_DSS_EDP0_PHY_LN2_TXFCLK", "Input clock"}, - [1028] = {151, 3, "DEV_DSS_EDP0_PHY_LN0_RXCLK", "Input clock"}, - [1029] = {151, 4, "DEV_DSS_EDP0_PHY_LN2_TXMCLK", "Input clock"}, - [1030] = {151, 5, "DEV_DSS_EDP0_PHY_LN0_RXFCLK", "Input clock"}, - [1031] = {151, 6, "DEV_DSS_EDP0_PHY_LN0_REFCLK", "Input clock"}, - [1032] = {151, 7, "DEV_DSS_EDP0_PHY_LN1_RXCLK", "Input clock"}, - [1033] = {151, 8, "DEV_DSS_EDP0_PHY_LN2_RXFCLK", "Input clock"}, - [1034] = {151, 9, "DEV_DSS_EDP0_DPI_4_CLK", "Input clock"}, - [1035] = {151, 10, "DEV_DSS_EDP0_DPI_2_2X_CLK", "Input clock"}, - [1036] = {151, 11, "DEV_DSS_EDP0_PHY_LN0_TXFCLK", "Input clock"}, - [1037] = {151, 12, "DEV_DSS_EDP0_PHY_LN2_RXCLK", "Input clock"}, - [1038] = {151, 13, "DEV_DSS_EDP0_PHY_LN2_REFCLK", "Input clock"}, - [1039] = {151, 14, "DEV_DSS_EDP0_PHY_LN3_REFCLK", "Input clock"}, - [1040] = {151, 15, "DEV_DSS_EDP0_DPI_5_CLK", "Input clock"}, - [1041] = {151, 16, "DEV_DSS_EDP0_PHY_LN3_RXCLK", "Input clock"}, - [1042] = {151, 17, "DEV_DSS_EDP0_PHY_LN1_REFCLK", "Input clock"}, - [1043] = {151, 18, "DEV_DSS_EDP0_AIF_I2S_CLK", "Input clock"}, - [1044] = {151, 19, "DEV_DSS_EDP0_PHY_LN3_TXFCLK", "Input clock"}, - [1045] = {151, 20, "DEV_DSS_EDP0_DPI_3_CLK", "Input clock"}, - [1046] = {151, 21, "DEV_DSS_EDP0_PHY_LN1_RXFCLK", "Input clock"}, - [1047] = {151, 22, "DEV_DSS_EDP0_PHY_LN1_TXMCLK", "Input clock"}, - [1048] = {151, 23, "DEV_DSS_EDP0_PLL_CTRL_CLK", "Input clock"}, - [1049] = {151, 24, "DEV_DSS_EDP0_PHY_LN3_TXMCLK", "Input clock"}, - [1050] = {151, 25, "DEV_DSS_EDP0_PHY_LN3_RXFCLK", "Input clock"}, - [1051] = {151, 26, "DEV_DSS_EDP0_PHY_LN0_TXMCLK", "Input clock"}, - [1052] = {151, 27, "DEV_DSS_EDP0_PHY_LN2_TXCLK", "Output clock"}, - [1053] = {151, 28, "DEV_DSS_EDP0_PHY_LN3_TXCLK", "Output clock"}, - [1054] = {151, 29, "DEV_DSS_EDP0_PHY_LN0_TXCLK", "Output clock"}, - [1055] = {151, 30, "DEV_DSS_EDP0_PHY_LN1_TXCLK", "Output clock"}, - [1056] = {151, 36, "DEV_DSS_EDP0_DPTX_MOD_CLK", "Input clock"}, - [1057] = {80, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"}, - [1058] = {81, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"}, - [1059] = {82, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"}, - [1060] = {83, 0, "DEV_EHRPWM0_VBUSP_CLK", "Input clock"}, - [1061] = {84, 0, "DEV_EHRPWM1_VBUSP_CLK", "Input clock"}, - [1062] = {85, 0, "DEV_EHRPWM2_VBUSP_CLK", "Input clock"}, - [1063] = {86, 0, "DEV_EHRPWM3_VBUSP_CLK", "Input clock"}, - [1064] = {87, 0, "DEV_EHRPWM4_VBUSP_CLK", "Input clock"}, - [1065] = {88, 0, "DEV_EHRPWM5_VBUSP_CLK", "Input clock"}, - [1066] = {89, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"}, - [1067] = {153, 0, "DEV_ENCODER0_SYS_CLK", "Input clock"}, - [1068] = {94, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"}, - [1069] = {95, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"}, - [1070] = {96, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"}, - [1071] = {97, 0, "DEV_ESM0_CLK", "Input clock"}, - [1072] = {105, 0, "DEV_GPIO0_MMR_CLK", "Input clock"}, - [1073] = {106, 0, "DEV_GPIO1_MMR_CLK", "Input clock"}, - [1074] = {107, 0, "DEV_GPIO2_MMR_CLK", "Input clock"}, - [1075] = {108, 0, "DEV_GPIO3_MMR_CLK", "Input clock"}, - [1076] = {109, 0, "DEV_GPIO4_MMR_CLK", "Input clock"}, - [1077] = {110, 0, "DEV_GPIO5_MMR_CLK", "Input clock"}, - [1078] = {111, 0, "DEV_GPIO6_MMR_CLK", "Input clock"}, - [1079] = {112, 0, "DEV_GPIO7_MMR_CLK", "Input clock"}, - [1080] = {131, 0, "DEV_GPIOMUX_INTRTR0_INTR_CLK", "Input clock"}, - [1081] = {115, 0, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"}, - [1082] = {115, 1, "DEV_GPMC0_VBUSP_CLK", "Input clock"}, - [1083] = {115, 2, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"}, - [1084] = {115, 3, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, - [1085] = {115, 4, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, - [1086] = {115, 5, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK3", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, - [1087] = {115, 6, "DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, - [1088] = {115, 7, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"}, - [1089] = {125, 0, "DEV_GPU0_GPU_0_GPU_PLL_CLK", "Input clock"}, - [1090] = {61, 0, "DEV_GTC0_VBUSP_CLK", "Input clock"}, - [1091] = {61, 1, "DEV_GTC0_GTC_CLK", "Input muxed clock"}, - [1092] = {61, 2, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, - [1093] = {61, 3, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, - [1094] = {61, 4, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, - [1095] = {61, 5, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, - [1096] = {61, 6, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, - [1097] = {61, 7, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, - [1098] = {61, 8, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, - [1099] = {61, 9, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, - [1100] = {61, 10, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, - [1101] = {61, 11, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, - [1102] = {61, 12, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, - [1103] = {61, 13, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, - [1104] = {61, 14, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, - [1105] = {61, 15, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, - [1106] = {61, 16, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, - [1107] = {61, 17, "DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, - [1108] = {187, 0, "DEV_I2C0_PISYS_CLK", "Input clock"}, - [1109] = {187, 1, "DEV_I2C0_PISCL_0", "Input clock"}, - [1110] = {187, 2, "DEV_I2C0_CLK", "Input clock"}, - [1111] = {188, 0, "DEV_I2C1_PISYS_CLK", "Input clock"}, - [1112] = {188, 1, "DEV_I2C1_PISCL_0", "Input clock"}, - [1113] = {188, 2, "DEV_I2C1_CLK", "Input clock"}, - [1114] = {189, 0, "DEV_I2C2_PISYS_CLK", "Input clock"}, - [1115] = {189, 1, "DEV_I2C2_PISCL_0", "Input clock"}, - [1116] = {189, 2, "DEV_I2C2_CLK", "Input clock"}, - [1117] = {190, 0, "DEV_I2C3_PISYS_CLK", "Input clock"}, - [1118] = {190, 1, "DEV_I2C3_PISCL_0", "Input clock"}, - [1119] = {190, 2, "DEV_I2C3_CLK", "Input clock"}, - [1120] = {191, 0, "DEV_I2C4_PISYS_CLK", "Input clock"}, - [1121] = {191, 1, "DEV_I2C4_PISCL_0", "Input clock"}, - [1122] = {191, 2, "DEV_I2C4_CLK", "Input clock"}, - [1123] = {192, 0, "DEV_I2C5_PISYS_CLK", "Input clock"}, - [1124] = {192, 1, "DEV_I2C5_PISCL_0", "Input clock"}, - [1125] = {192, 2, "DEV_I2C5_CLK", "Input clock"}, - [1126] = {193, 0, "DEV_I2C6_PISYS_CLK", "Input clock"}, - [1127] = {193, 1, "DEV_I2C6_PISCL_0", "Input clock"}, - [1128] = {193, 2, "DEV_I2C6_CLK", "Input clock"}, - [1129] = {116, 0, "DEV_I3C0_I3C_PCLK_CLK", "Input clock"}, - [1130] = {116, 1, "DEV_I3C0_I3C_SCL_DI", "Input clock"}, - [1131] = {116, 2, "DEV_I3C0_I3C_SCLK_CLK", "Input clock"}, - [1132] = {116, 3, "DEV_I3C0_I3C_SCL_DO_0", "Output clock"}, - [1133] = {127, 0, "DEV_LED0_LED_CLK", "Input clock"}, - [1134] = {127, 1, "DEV_LED0_VBUS_CLK", "Input clock"}, - [1135] = {128, 0, "DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK", "Input clock"}, - [1136] = {130, 0, "DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK", "Input clock"}, - [1137] = {156, 0, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, - [1138] = {156, 1, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, - [1139] = {156, 2, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, - [1140] = {156, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, - [1141] = {156, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, - [1142] = {156, 5, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, - [1143] = {158, 0, "DEV_MCAN1_MCANSS_HCLK_CLK", "Input clock"}, - [1144] = {158, 1, "DEV_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"}, - [1145] = {158, 2, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, - [1146] = {158, 3, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, - [1147] = {158, 4, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, - [1148] = {158, 5, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, - [1149] = {168, 0, "DEV_MCAN10_MCANSS_HCLK_CLK", "Input clock"}, - [1150] = {168, 1, "DEV_MCAN10_MCANSS_CCLK_CLK", "Input muxed clock"}, - [1151] = {168, 2, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, - [1152] = {168, 3, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, - [1153] = {168, 4, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, - [1154] = {168, 5, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, - [1155] = {169, 0, "DEV_MCAN11_MCANSS_HCLK_CLK", "Input clock"}, - [1156] = {169, 1, "DEV_MCAN11_MCANSS_CCLK_CLK", "Input muxed clock"}, - [1157] = {169, 2, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, - [1158] = {169, 3, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, - [1159] = {169, 4, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, - [1160] = {169, 5, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, - [1161] = {170, 0, "DEV_MCAN12_MCANSS_HCLK_CLK", "Input clock"}, - [1162] = {170, 1, "DEV_MCAN12_MCANSS_CCLK_CLK", "Input muxed clock"}, - [1163] = {170, 2, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, - [1164] = {170, 3, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, - [1165] = {170, 4, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, - [1166] = {170, 5, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, - [1167] = {171, 0, "DEV_MCAN13_MCANSS_HCLK_CLK", "Input clock"}, - [1168] = {171, 1, "DEV_MCAN13_MCANSS_CCLK_CLK", "Input muxed clock"}, - [1169] = {171, 2, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, - [1170] = {171, 3, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, - [1171] = {171, 4, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, - [1172] = {171, 5, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, - [1173] = {160, 0, "DEV_MCAN2_MCANSS_HCLK_CLK", "Input clock"}, - [1174] = {160, 1, "DEV_MCAN2_MCANSS_CCLK_CLK", "Input muxed clock"}, - [1175] = {160, 2, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, - [1176] = {160, 3, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, - [1177] = {160, 4, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, - [1178] = {160, 5, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, - [1179] = {161, 0, "DEV_MCAN3_MCANSS_HCLK_CLK", "Input clock"}, - [1180] = {161, 1, "DEV_MCAN3_MCANSS_CCLK_CLK", "Input muxed clock"}, - [1181] = {161, 2, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, - [1182] = {161, 3, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, - [1183] = {161, 4, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, - [1184] = {161, 5, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, - [1185] = {162, 0, "DEV_MCAN4_MCANSS_HCLK_CLK", "Input clock"}, - [1186] = {162, 1, "DEV_MCAN4_MCANSS_CCLK_CLK", "Input muxed clock"}, - [1187] = {162, 2, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, - [1188] = {162, 3, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, - [1189] = {162, 4, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, - [1190] = {162, 5, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, - [1191] = {163, 0, "DEV_MCAN5_MCANSS_HCLK_CLK", "Input clock"}, - [1192] = {163, 1, "DEV_MCAN5_MCANSS_CCLK_CLK", "Input muxed clock"}, - [1193] = {163, 2, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, - [1194] = {163, 3, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, - [1195] = {163, 4, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, - [1196] = {163, 5, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, - [1197] = {164, 0, "DEV_MCAN6_MCANSS_HCLK_CLK", "Input clock"}, - [1198] = {164, 1, "DEV_MCAN6_MCANSS_CCLK_CLK", "Input muxed clock"}, - [1199] = {164, 2, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, - [1200] = {164, 3, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, - [1201] = {164, 4, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, - [1202] = {164, 5, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, - [1203] = {165, 0, "DEV_MCAN7_MCANSS_HCLK_CLK", "Input clock"}, - [1204] = {165, 1, "DEV_MCAN7_MCANSS_CCLK_CLK", "Input muxed clock"}, - [1205] = {165, 2, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, - [1206] = {165, 3, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, - [1207] = {165, 4, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, - [1208] = {165, 5, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, - [1209] = {166, 0, "DEV_MCAN8_MCANSS_HCLK_CLK", "Input clock"}, - [1210] = {166, 1, "DEV_MCAN8_MCANSS_CCLK_CLK", "Input muxed clock"}, - [1211] = {166, 2, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, - [1212] = {166, 3, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, - [1213] = {166, 4, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, - [1214] = {166, 5, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, - [1215] = {167, 0, "DEV_MCAN9_MCANSS_HCLK_CLK", "Input clock"}, - [1216] = {167, 1, "DEV_MCAN9_MCANSS_CCLK_CLK", "Input muxed clock"}, - [1217] = {167, 2, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, - [1218] = {167, 3, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, - [1219] = {167, 4, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, - [1220] = {167, 5, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, - [1221] = {174, 0, "DEV_MCASP0_VBUSP_CLK", "Input clock"}, - [1222] = {174, 1, "DEV_MCASP0_AUX_CLK", "Input muxed clock"}, - [1223] = {174, 2, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, - [1224] = {174, 3, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, - [1225] = {174, 4, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, - [1226] = {174, 6, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, - [1227] = {174, 7, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, - [1228] = {174, 8, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, - [1229] = {174, 9, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, - [1230] = {174, 10, "DEV_MCASP0_MCASP_ACLKX_POUT_0", "Output clock"}, - [1231] = {174, 11, "DEV_MCASP0_MCASP_ACLKX_PIN_0", "Input clock"}, - [1232] = {174, 12, "DEV_MCASP0_MCASP_ACLKR_POUT_0", "Output clock"}, - [1233] = {174, 13, "DEV_MCASP0_MCASP_ACLKR_PIN_0", "Input clock"}, - [1234] = {174, 14, "DEV_MCASP0_MCASP_AHCLKX_POUT_0", "Output clock"}, - [1235] = {174, 15, "DEV_MCASP0_MCASP_AHCLKX_PIN_0", "Input muxed clock"}, - [1236] = {174, 16, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"}, - [1237] = {174, 17, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"}, - [1238] = {174, 18, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"}, - [1239] = {174, 19, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"}, - [1240] = {174, 20, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"}, - [1241] = {174, 21, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"}, - [1242] = {174, 22, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"}, - [1243] = {174, 23, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"}, - [1244] = {174, 24, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"}, - [1245] = {174, 25, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"}, - [1246] = {174, 26, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"}, - [1247] = {174, 27, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"}, - [1248] = {174, 28, "DEV_MCASP0_MCASP_AHCLKR_POUT_0", "Output clock"}, - [1249] = {174, 29, "DEV_MCASP0_MCASP_AHCLKR_PIN_0", "Input muxed clock"}, - [1250] = {174, 30, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"}, - [1251] = {174, 31, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"}, - [1252] = {174, 32, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"}, - [1253] = {174, 33, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"}, - [1254] = {174, 34, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"}, - [1255] = {174, 35, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"}, - [1256] = {174, 36, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"}, - [1257] = {174, 37, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"}, - [1258] = {174, 38, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"}, - [1259] = {174, 39, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"}, - [1260] = {174, 40, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"}, - [1261] = {174, 41, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"}, - [1262] = {175, 0, "DEV_MCASP1_VBUSP_CLK", "Input clock"}, - [1263] = {175, 1, "DEV_MCASP1_AUX_CLK", "Input muxed clock"}, - [1264] = {175, 2, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, - [1265] = {175, 3, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, - [1266] = {175, 4, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, - [1267] = {175, 6, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, - [1268] = {175, 7, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, - [1269] = {175, 8, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, - [1270] = {175, 9, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, - [1271] = {175, 10, "DEV_MCASP1_MCASP_ACLKX_POUT_0", "Output clock"}, - [1272] = {175, 11, "DEV_MCASP1_MCASP_ACLKX_PIN_0", "Input clock"}, - [1273] = {175, 12, "DEV_MCASP1_MCASP_ACLKR_POUT_0", "Output clock"}, - [1274] = {175, 13, "DEV_MCASP1_MCASP_ACLKR_PIN_0", "Input clock"}, - [1275] = {175, 14, "DEV_MCASP1_MCASP_AHCLKX_POUT_0", "Output clock"}, - [1276] = {175, 15, "DEV_MCASP1_MCASP_AHCLKX_PIN_0", "Input muxed clock"}, - [1277] = {175, 16, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"}, - [1278] = {175, 17, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"}, - [1279] = {175, 18, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"}, - [1280] = {175, 19, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"}, - [1281] = {175, 20, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"}, - [1282] = {175, 21, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"}, - [1283] = {175, 22, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"}, - [1284] = {175, 23, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"}, - [1285] = {175, 24, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"}, - [1286] = {175, 25, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"}, - [1287] = {175, 26, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"}, - [1288] = {175, 27, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"}, - [1289] = {175, 28, "DEV_MCASP1_MCASP_AHCLKR_POUT_0", "Output clock"}, - [1290] = {175, 29, "DEV_MCASP1_MCASP_AHCLKR_PIN_0", "Input muxed clock"}, - [1291] = {175, 30, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"}, - [1292] = {175, 31, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"}, - [1293] = {175, 32, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"}, - [1294] = {175, 33, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"}, - [1295] = {175, 34, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"}, - [1296] = {175, 35, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"}, - [1297] = {175, 36, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"}, - [1298] = {175, 37, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"}, - [1299] = {175, 38, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"}, - [1300] = {175, 39, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"}, - [1301] = {175, 40, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"}, - [1302] = {175, 41, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"}, - [1303] = {184, 0, "DEV_MCASP10_VBUSP_CLK", "Input clock"}, - [1304] = {184, 1, "DEV_MCASP10_AUX_CLK", "Input muxed clock"}, - [1305] = {184, 2, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, - [1306] = {184, 3, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, - [1307] = {184, 4, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, - [1308] = {184, 6, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, - [1309] = {184, 7, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, - [1310] = {184, 8, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, - [1311] = {184, 9, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, - [1312] = {184, 10, "DEV_MCASP10_MCASP_ACLKX_POUT_0", "Output clock"}, - [1313] = {184, 11, "DEV_MCASP10_MCASP_ACLKX_PIN_0", "Input clock"}, - [1314] = {184, 12, "DEV_MCASP10_MCASP_ACLKR_POUT_0", "Output clock"}, - [1315] = {184, 13, "DEV_MCASP10_MCASP_ACLKR_PIN_0", "Input clock"}, - [1316] = {184, 14, "DEV_MCASP10_MCASP_AHCLKX_POUT_0", "Output clock"}, - [1317] = {184, 15, "DEV_MCASP10_MCASP_AHCLKX_PIN_0", "Input muxed clock"}, - [1318] = {184, 16, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"}, - [1319] = {184, 17, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"}, - [1320] = {184, 18, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"}, - [1321] = {184, 19, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"}, - [1322] = {184, 20, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"}, - [1323] = {184, 21, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"}, - [1324] = {184, 22, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"}, - [1325] = {184, 23, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"}, - [1326] = {184, 24, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"}, - [1327] = {184, 25, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"}, - [1328] = {184, 26, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"}, - [1329] = {184, 27, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"}, - [1330] = {184, 28, "DEV_MCASP10_MCASP_AHCLKR_POUT_0", "Output clock"}, - [1331] = {184, 29, "DEV_MCASP10_MCASP_AHCLKR_PIN_0", "Input muxed clock"}, - [1332] = {184, 30, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"}, - [1333] = {184, 31, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"}, - [1334] = {184, 32, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"}, - [1335] = {184, 33, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"}, - [1336] = {184, 34, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"}, - [1337] = {184, 35, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"}, - [1338] = {184, 36, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"}, - [1339] = {184, 37, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"}, - [1340] = {184, 38, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"}, - [1341] = {184, 39, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"}, - [1342] = {184, 40, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"}, - [1343] = {184, 41, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"}, - [1344] = {185, 0, "DEV_MCASP11_VBUSP_CLK", "Input clock"}, - [1345] = {185, 1, "DEV_MCASP11_AUX_CLK", "Input muxed clock"}, - [1346] = {185, 2, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, - [1347] = {185, 3, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, - [1348] = {185, 4, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, - [1349] = {185, 6, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, - [1350] = {185, 7, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, - [1351] = {185, 8, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, - [1352] = {185, 9, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, - [1353] = {185, 10, "DEV_MCASP11_MCASP_ACLKX_POUT_0", "Output clock"}, - [1354] = {185, 11, "DEV_MCASP11_MCASP_ACLKX_PIN_0", "Input clock"}, - [1355] = {185, 12, "DEV_MCASP11_MCASP_ACLKR_POUT_0", "Output clock"}, - [1356] = {185, 13, "DEV_MCASP11_MCASP_ACLKR_PIN_0", "Input clock"}, - [1357] = {185, 14, "DEV_MCASP11_MCASP_AHCLKX_POUT_0", "Output clock"}, - [1358] = {185, 15, "DEV_MCASP11_MCASP_AHCLKX_PIN_0", "Input muxed clock"}, - [1359] = {185, 16, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"}, - [1360] = {185, 17, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"}, - [1361] = {185, 18, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"}, - [1362] = {185, 19, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"}, - [1363] = {185, 20, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"}, - [1364] = {185, 21, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"}, - [1365] = {185, 22, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"}, - [1366] = {185, 23, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"}, - [1367] = {185, 24, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"}, - [1368] = {185, 25, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"}, - [1369] = {185, 26, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"}, - [1370] = {185, 27, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"}, - [1371] = {185, 28, "DEV_MCASP11_MCASP_AHCLKR_POUT_0", "Output clock"}, - [1372] = {185, 29, "DEV_MCASP11_MCASP_AHCLKR_PIN_0", "Input muxed clock"}, - [1373] = {185, 30, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"}, - [1374] = {185, 31, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"}, - [1375] = {185, 32, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"}, - [1376] = {185, 33, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"}, - [1377] = {185, 34, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"}, - [1378] = {185, 35, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"}, - [1379] = {185, 36, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"}, - [1380] = {185, 37, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"}, - [1381] = {185, 38, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"}, - [1382] = {185, 39, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"}, - [1383] = {185, 40, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"}, - [1384] = {185, 41, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"}, - [1385] = {176, 0, "DEV_MCASP2_VBUSP_CLK", "Input clock"}, - [1386] = {176, 1, "DEV_MCASP2_AUX_CLK", "Input muxed clock"}, - [1387] = {176, 2, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, - [1388] = {176, 3, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, - [1389] = {176, 4, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, - [1390] = {176, 6, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, - [1391] = {176, 7, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, - [1392] = {176, 8, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, - [1393] = {176, 9, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, - [1394] = {176, 10, "DEV_MCASP2_MCASP_ACLKX_POUT_0", "Output clock"}, - [1395] = {176, 11, "DEV_MCASP2_MCASP_ACLKX_PIN_0", "Input clock"}, - [1396] = {176, 12, "DEV_MCASP2_MCASP_ACLKR_POUT_0", "Output clock"}, - [1397] = {176, 13, "DEV_MCASP2_MCASP_ACLKR_PIN_0", "Input clock"}, - [1398] = {176, 14, "DEV_MCASP2_MCASP_AHCLKX_POUT_0", "Output clock"}, - [1399] = {176, 15, "DEV_MCASP2_MCASP_AHCLKX_PIN_0", "Input muxed clock"}, - [1400] = {176, 16, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"}, - [1401] = {176, 17, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"}, - [1402] = {176, 18, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"}, - [1403] = {176, 19, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"}, - [1404] = {176, 20, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"}, - [1405] = {176, 21, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"}, - [1406] = {176, 22, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"}, - [1407] = {176, 23, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"}, - [1408] = {176, 24, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"}, - [1409] = {176, 25, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"}, - [1410] = {176, 26, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"}, - [1411] = {176, 27, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"}, - [1412] = {176, 28, "DEV_MCASP2_MCASP_AHCLKR_POUT_0", "Output clock"}, - [1413] = {176, 29, "DEV_MCASP2_MCASP_AHCLKR_PIN_0", "Input muxed clock"}, - [1414] = {176, 30, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"}, - [1415] = {176, 31, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"}, - [1416] = {176, 32, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"}, - [1417] = {176, 33, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"}, - [1418] = {176, 34, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"}, - [1419] = {176, 35, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"}, - [1420] = {176, 36, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"}, - [1421] = {176, 37, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"}, - [1422] = {176, 38, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"}, - [1423] = {176, 39, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"}, - [1424] = {176, 40, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"}, - [1425] = {176, 41, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"}, - [1426] = {177, 0, "DEV_MCASP3_VBUSP_CLK", "Input clock"}, - [1427] = {177, 1, "DEV_MCASP3_AUX_CLK", "Input muxed clock"}, - [1428] = {177, 2, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, - [1429] = {177, 3, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, - [1430] = {177, 4, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, - [1431] = {177, 6, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, - [1432] = {177, 7, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, - [1433] = {177, 8, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, - [1434] = {177, 9, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, - [1435] = {177, 10, "DEV_MCASP3_MCASP_ACLKX_POUT_0", "Output clock"}, - [1436] = {177, 11, "DEV_MCASP3_MCASP_ACLKX_PIN_0", "Input clock"}, - [1437] = {177, 12, "DEV_MCASP3_MCASP_ACLKR_POUT_0", "Output clock"}, - [1438] = {177, 13, "DEV_MCASP3_MCASP_ACLKR_PIN_0", "Input clock"}, - [1439] = {177, 14, "DEV_MCASP3_MCASP_AHCLKX_POUT_0", "Output clock"}, - [1440] = {177, 15, "DEV_MCASP3_MCASP_AHCLKX_PIN_0", "Input muxed clock"}, - [1441] = {177, 16, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"}, - [1442] = {177, 17, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"}, - [1443] = {177, 18, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"}, - [1444] = {177, 19, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"}, - [1445] = {177, 20, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"}, - [1446] = {177, 21, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"}, - [1447] = {177, 22, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"}, - [1448] = {177, 23, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"}, - [1449] = {177, 24, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"}, - [1450] = {177, 25, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"}, - [1451] = {177, 26, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"}, - [1452] = {177, 27, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"}, - [1453] = {177, 28, "DEV_MCASP3_MCASP_AHCLKR_POUT_0", "Output clock"}, - [1454] = {177, 29, "DEV_MCASP3_MCASP_AHCLKR_PIN_0", "Input muxed clock"}, - [1455] = {177, 30, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"}, - [1456] = {177, 31, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"}, - [1457] = {177, 32, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"}, - [1458] = {177, 33, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"}, - [1459] = {177, 34, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"}, - [1460] = {177, 35, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"}, - [1461] = {177, 36, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"}, - [1462] = {177, 37, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"}, - [1463] = {177, 38, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"}, - [1464] = {177, 39, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"}, - [1465] = {177, 40, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"}, - [1466] = {177, 41, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"}, - [1467] = {178, 0, "DEV_MCASP4_VBUSP_CLK", "Input clock"}, - [1468] = {178, 1, "DEV_MCASP4_AUX_CLK", "Input muxed clock"}, - [1469] = {178, 2, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, - [1470] = {178, 3, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, - [1471] = {178, 4, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, - [1472] = {178, 6, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, - [1473] = {178, 7, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, - [1474] = {178, 8, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, - [1475] = {178, 9, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, - [1476] = {178, 10, "DEV_MCASP4_MCASP_ACLKX_POUT_0", "Output clock"}, - [1477] = {178, 11, "DEV_MCASP4_MCASP_ACLKX_PIN_0", "Input clock"}, - [1478] = {178, 12, "DEV_MCASP4_MCASP_ACLKR_POUT_0", "Output clock"}, - [1479] = {178, 13, "DEV_MCASP4_MCASP_ACLKR_PIN_0", "Input clock"}, - [1480] = {178, 14, "DEV_MCASP4_MCASP_AHCLKX_POUT_0", "Output clock"}, - [1481] = {178, 15, "DEV_MCASP4_MCASP_AHCLKX_PIN_0", "Input muxed clock"}, - [1482] = {178, 16, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"}, - [1483] = {178, 17, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"}, - [1484] = {178, 18, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"}, - [1485] = {178, 19, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"}, - [1486] = {178, 20, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"}, - [1487] = {178, 21, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"}, - [1488] = {178, 22, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"}, - [1489] = {178, 23, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"}, - [1490] = {178, 24, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"}, - [1491] = {178, 25, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"}, - [1492] = {178, 26, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"}, - [1493] = {178, 27, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"}, - [1494] = {178, 28, "DEV_MCASP4_MCASP_AHCLKR_POUT_0", "Output clock"}, - [1495] = {178, 29, "DEV_MCASP4_MCASP_AHCLKR_PIN_0", "Input muxed clock"}, - [1496] = {178, 30, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"}, - [1497] = {178, 31, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"}, - [1498] = {178, 32, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"}, - [1499] = {178, 33, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"}, - [1500] = {178, 34, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"}, - [1501] = {178, 35, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"}, - [1502] = {178, 36, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"}, - [1503] = {178, 37, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"}, - [1504] = {178, 38, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"}, - [1505] = {178, 39, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"}, - [1506] = {178, 40, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"}, - [1507] = {178, 41, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"}, - [1508] = {179, 0, "DEV_MCASP5_VBUSP_CLK", "Input clock"}, - [1509] = {179, 1, "DEV_MCASP5_AUX_CLK", "Input muxed clock"}, - [1510] = {179, 2, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, - [1511] = {179, 3, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, - [1512] = {179, 4, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, - [1513] = {179, 6, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, - [1514] = {179, 7, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, - [1515] = {179, 8, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, - [1516] = {179, 9, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, - [1517] = {179, 10, "DEV_MCASP5_MCASP_ACLKX_POUT_0", "Output clock"}, - [1518] = {179, 11, "DEV_MCASP5_MCASP_ACLKX_PIN_0", "Input clock"}, - [1519] = {179, 12, "DEV_MCASP5_MCASP_ACLKR_POUT_0", "Output clock"}, - [1520] = {179, 13, "DEV_MCASP5_MCASP_ACLKR_PIN_0", "Input clock"}, - [1521] = {179, 14, "DEV_MCASP5_MCASP_AHCLKX_POUT_0", "Output clock"}, - [1522] = {179, 15, "DEV_MCASP5_MCASP_AHCLKX_PIN_0", "Input muxed clock"}, - [1523] = {179, 16, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"}, - [1524] = {179, 17, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"}, - [1525] = {179, 18, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"}, - [1526] = {179, 19, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"}, - [1527] = {179, 20, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"}, - [1528] = {179, 21, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"}, - [1529] = {179, 22, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"}, - [1530] = {179, 23, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"}, - [1531] = {179, 24, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"}, - [1532] = {179, 25, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"}, - [1533] = {179, 26, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"}, - [1534] = {179, 27, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"}, - [1535] = {179, 28, "DEV_MCASP5_MCASP_AHCLKR_POUT_0", "Output clock"}, - [1536] = {179, 29, "DEV_MCASP5_MCASP_AHCLKR_PIN_0", "Input muxed clock"}, - [1537] = {179, 30, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"}, - [1538] = {179, 31, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"}, - [1539] = {179, 32, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"}, - [1540] = {179, 33, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"}, - [1541] = {179, 34, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"}, - [1542] = {179, 35, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"}, - [1543] = {179, 36, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"}, - [1544] = {179, 37, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"}, - [1545] = {179, 38, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"}, - [1546] = {179, 39, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"}, - [1547] = {179, 40, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"}, - [1548] = {179, 41, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"}, - [1549] = {180, 0, "DEV_MCASP6_VBUSP_CLK", "Input clock"}, - [1550] = {180, 1, "DEV_MCASP6_AUX_CLK", "Input muxed clock"}, - [1551] = {180, 2, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, - [1552] = {180, 3, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, - [1553] = {180, 4, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, - [1554] = {180, 6, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, - [1555] = {180, 7, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, - [1556] = {180, 8, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, - [1557] = {180, 9, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, - [1558] = {180, 10, "DEV_MCASP6_MCASP_ACLKX_POUT_0", "Output clock"}, - [1559] = {180, 11, "DEV_MCASP6_MCASP_ACLKX_PIN_0", "Input clock"}, - [1560] = {180, 12, "DEV_MCASP6_MCASP_ACLKR_POUT_0", "Output clock"}, - [1561] = {180, 13, "DEV_MCASP6_MCASP_ACLKR_PIN_0", "Input clock"}, - [1562] = {180, 14, "DEV_MCASP6_MCASP_AHCLKX_POUT_0", "Output clock"}, - [1563] = {180, 15, "DEV_MCASP6_MCASP_AHCLKX_PIN_0", "Input muxed clock"}, - [1564] = {180, 16, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"}, - [1565] = {180, 17, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"}, - [1566] = {180, 18, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"}, - [1567] = {180, 19, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"}, - [1568] = {180, 20, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"}, - [1569] = {180, 21, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"}, - [1570] = {180, 22, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"}, - [1571] = {180, 23, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"}, - [1572] = {180, 24, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"}, - [1573] = {180, 25, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"}, - [1574] = {180, 26, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"}, - [1575] = {180, 27, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"}, - [1576] = {180, 28, "DEV_MCASP6_MCASP_AHCLKR_POUT_0", "Output clock"}, - [1577] = {180, 29, "DEV_MCASP6_MCASP_AHCLKR_PIN_0", "Input muxed clock"}, - [1578] = {180, 30, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"}, - [1579] = {180, 31, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"}, - [1580] = {180, 32, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"}, - [1581] = {180, 33, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"}, - [1582] = {180, 34, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"}, - [1583] = {180, 35, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"}, - [1584] = {180, 36, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"}, - [1585] = {180, 37, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"}, - [1586] = {180, 38, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"}, - [1587] = {180, 39, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"}, - [1588] = {180, 40, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"}, - [1589] = {180, 41, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"}, - [1590] = {181, 0, "DEV_MCASP7_VBUSP_CLK", "Input clock"}, - [1591] = {181, 1, "DEV_MCASP7_AUX_CLK", "Input muxed clock"}, - [1592] = {181, 2, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, - [1593] = {181, 3, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, - [1594] = {181, 4, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, - [1595] = {181, 6, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, - [1596] = {181, 7, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, - [1597] = {181, 8, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, - [1598] = {181, 9, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, - [1599] = {181, 10, "DEV_MCASP7_MCASP_ACLKX_POUT_0", "Output clock"}, - [1600] = {181, 11, "DEV_MCASP7_MCASP_ACLKX_PIN_0", "Input clock"}, - [1601] = {181, 12, "DEV_MCASP7_MCASP_ACLKR_POUT_0", "Output clock"}, - [1602] = {181, 13, "DEV_MCASP7_MCASP_ACLKR_PIN_0", "Input clock"}, - [1603] = {181, 14, "DEV_MCASP7_MCASP_AHCLKX_POUT_0", "Output clock"}, - [1604] = {181, 15, "DEV_MCASP7_MCASP_AHCLKX_PIN_0", "Input muxed clock"}, - [1605] = {181, 16, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"}, - [1606] = {181, 17, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"}, - [1607] = {181, 18, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"}, - [1608] = {181, 19, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"}, - [1609] = {181, 20, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"}, - [1610] = {181, 21, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"}, - [1611] = {181, 22, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"}, - [1612] = {181, 23, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"}, - [1613] = {181, 24, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"}, - [1614] = {181, 25, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"}, - [1615] = {181, 26, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"}, - [1616] = {181, 27, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"}, - [1617] = {181, 28, "DEV_MCASP7_MCASP_AHCLKR_POUT_0", "Output clock"}, - [1618] = {181, 29, "DEV_MCASP7_MCASP_AHCLKR_PIN_0", "Input muxed clock"}, - [1619] = {181, 30, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"}, - [1620] = {181, 31, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"}, - [1621] = {181, 32, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"}, - [1622] = {181, 33, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"}, - [1623] = {181, 34, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"}, - [1624] = {181, 35, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"}, - [1625] = {181, 36, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"}, - [1626] = {181, 37, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"}, - [1627] = {181, 38, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"}, - [1628] = {181, 39, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"}, - [1629] = {181, 40, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"}, - [1630] = {181, 41, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"}, - [1631] = {182, 0, "DEV_MCASP8_VBUSP_CLK", "Input clock"}, - [1632] = {182, 1, "DEV_MCASP8_AUX_CLK", "Input muxed clock"}, - [1633] = {182, 2, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, - [1634] = {182, 3, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, - [1635] = {182, 4, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, - [1636] = {182, 6, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, - [1637] = {182, 7, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, - [1638] = {182, 8, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, - [1639] = {182, 9, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, - [1640] = {182, 10, "DEV_MCASP8_MCASP_ACLKX_POUT_0", "Output clock"}, - [1641] = {182, 11, "DEV_MCASP8_MCASP_ACLKX_PIN_0", "Input clock"}, - [1642] = {182, 12, "DEV_MCASP8_MCASP_ACLKR_POUT_0", "Output clock"}, - [1643] = {182, 13, "DEV_MCASP8_MCASP_ACLKR_PIN_0", "Input clock"}, - [1644] = {182, 14, "DEV_MCASP8_MCASP_AHCLKX_POUT_0", "Output clock"}, - [1645] = {182, 15, "DEV_MCASP8_MCASP_AHCLKX_PIN_0", "Input muxed clock"}, - [1646] = {182, 16, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"}, - [1647] = {182, 17, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"}, - [1648] = {182, 18, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"}, - [1649] = {182, 19, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"}, - [1650] = {182, 20, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"}, - [1651] = {182, 21, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"}, - [1652] = {182, 22, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"}, - [1653] = {182, 23, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"}, - [1654] = {182, 24, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"}, - [1655] = {182, 25, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"}, - [1656] = {182, 26, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"}, - [1657] = {182, 27, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"}, - [1658] = {182, 28, "DEV_MCASP8_MCASP_AHCLKR_POUT_0", "Output clock"}, - [1659] = {182, 29, "DEV_MCASP8_MCASP_AHCLKR_PIN_0", "Input muxed clock"}, - [1660] = {182, 30, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"}, - [1661] = {182, 31, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"}, - [1662] = {182, 32, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"}, - [1663] = {182, 33, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"}, - [1664] = {182, 34, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"}, - [1665] = {182, 35, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"}, - [1666] = {182, 36, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"}, - [1667] = {182, 37, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"}, - [1668] = {182, 38, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"}, - [1669] = {182, 39, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"}, - [1670] = {182, 40, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"}, - [1671] = {182, 41, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"}, - [1672] = {183, 0, "DEV_MCASP9_VBUSP_CLK", "Input clock"}, - [1673] = {183, 1, "DEV_MCASP9_AUX_CLK", "Input muxed clock"}, - [1674] = {183, 2, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, - [1675] = {183, 3, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, - [1676] = {183, 4, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, - [1677] = {183, 6, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, - [1678] = {183, 7, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, - [1679] = {183, 8, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, - [1680] = {183, 9, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, - [1681] = {183, 10, "DEV_MCASP9_MCASP_ACLKX_POUT_0", "Output clock"}, - [1682] = {183, 11, "DEV_MCASP9_MCASP_ACLKX_PIN_0", "Input clock"}, - [1683] = {183, 12, "DEV_MCASP9_MCASP_ACLKR_POUT_0", "Output clock"}, - [1684] = {183, 13, "DEV_MCASP9_MCASP_ACLKR_PIN_0", "Input clock"}, - [1685] = {183, 14, "DEV_MCASP9_MCASP_AHCLKX_POUT_0", "Output clock"}, - [1686] = {183, 15, "DEV_MCASP9_MCASP_AHCLKX_PIN_0", "Input muxed clock"}, - [1687] = {183, 16, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"}, - [1688] = {183, 17, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"}, - [1689] = {183, 18, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"}, - [1690] = {183, 19, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"}, - [1691] = {183, 20, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"}, - [1692] = {183, 21, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"}, - [1693] = {183, 22, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"}, - [1694] = {183, 23, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"}, - [1695] = {183, 24, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"}, - [1696] = {183, 25, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"}, - [1697] = {183, 26, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"}, - [1698] = {183, 27, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"}, - [1699] = {183, 28, "DEV_MCASP9_MCASP_AHCLKR_POUT_0", "Output clock"}, - [1700] = {183, 29, "DEV_MCASP9_MCASP_AHCLKR_PIN_0", "Input muxed clock"}, - [1701] = {183, 30, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"}, - [1702] = {183, 31, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"}, - [1703] = {183, 32, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"}, - [1704] = {183, 33, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"}, - [1705] = {183, 34, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"}, - [1706] = {183, 35, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"}, - [1707] = {183, 36, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"}, - [1708] = {183, 37, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"}, - [1709] = {183, 38, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"}, - [1710] = {183, 39, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"}, - [1711] = {183, 40, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"}, - [1712] = {183, 41, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"}, - [1713] = {266, 0, "DEV_MCSPI0_VBUSP_CLK", "Input clock"}, - [1714] = {266, 1, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"}, - [1715] = {266, 2, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, - [1716] = {267, 0, "DEV_MCSPI1_VBUSP_CLK", "Input clock"}, - [1717] = {267, 1, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"}, - [1718] = {267, 2, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, - [1719] = {268, 0, "DEV_MCSPI2_VBUSP_CLK", "Input clock"}, - [1720] = {268, 1, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"}, - [1721] = {268, 2, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"}, - [1722] = {269, 0, "DEV_MCSPI3_VBUSP_CLK", "Input clock"}, - [1723] = {269, 1, "DEV_MCSPI3_CLKSPIREF_CLK", "Input clock"}, - [1724] = {269, 2, "DEV_MCSPI3_IO_CLKSPII_CLK", "Input muxed clock"}, - [1725] = {269, 3, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"}, - [1726] = {269, 4, "DEV_MCSPI3_IO_CLKSPIO_CLK", "Output clock"}, - [1727] = {270, 0, "DEV_MCSPI4_VBUSP_CLK", "Input clock"}, - [1728] = {270, 1, "DEV_MCSPI4_CLKSPIREF_CLK", "Input clock"}, - [1729] = {270, 2, "DEV_MCSPI4_IO_CLKSPII_CLK", "Input clock"}, - [1730] = {270, 3, "DEV_MCSPI4_IO_CLKSPIO_CLK", "Output clock"}, - [1731] = {271, 0, "DEV_MCSPI5_VBUSP_CLK", "Input clock"}, - [1732] = {271, 1, "DEV_MCSPI5_CLKSPIREF_CLK", "Input clock"}, - [1733] = {271, 2, "DEV_MCSPI5_IO_CLKSPIO_CLK", "Output clock"}, - [1734] = {272, 0, "DEV_MCSPI6_VBUSP_CLK", "Input clock"}, - [1735] = {272, 1, "DEV_MCSPI6_CLKSPIREF_CLK", "Input clock"}, - [1736] = {272, 2, "DEV_MCSPI6_IO_CLKSPIO_CLK", "Output clock"}, - [1737] = {273, 0, "DEV_MCSPI7_VBUSP_CLK", "Input clock"}, - [1738] = {273, 1, "DEV_MCSPI7_CLKSPIREF_CLK", "Input clock"}, - [1739] = {273, 2, "DEV_MCSPI7_IO_CLKSPIO_CLK", "Output clock"}, - [1740] = {0, 0, "DEV_MCU_ADC0_SYS_CLK", "Input clock"}, - [1741] = {0, 1, "DEV_MCU_ADC0_ADC_CLK", "Input muxed clock"}, - [1742] = {0, 2, "DEV_MCU_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"}, - [1743] = {0, 3, "DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"}, - [1744] = {0, 4, "DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"}, - [1745] = {0, 5, "DEV_MCU_ADC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"}, - [1746] = {0, 6, "DEV_MCU_ADC0_VBUS_CLK", "Input clock"}, - [1747] = {1, 0, "DEV_MCU_ADC1_SYS_CLK", "Input clock"}, - [1748] = {1, 1, "DEV_MCU_ADC1_ADC_CLK", "Input muxed clock"}, - [1749] = {1, 2, "DEV_MCU_ADC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"}, - [1750] = {1, 3, "DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"}, - [1751] = {1, 4, "DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"}, - [1752] = {1, 5, "DEV_MCU_ADC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"}, - [1753] = {1, 6, "DEV_MCU_ADC1_VBUS_CLK", "Input clock"}, - [1754] = {18, 0, "DEV_MCU_CPSW0_RGMII1_RXC_I", "Input clock"}, - [1755] = {18, 1, "DEV_MCU_CPSW0_RGMII_MHZ_250_CLK", "Input clock"}, - [1756] = {18, 2, "DEV_MCU_CPSW0_CPTS_RFT_CLK", "Input muxed clock"}, - [1757] = {18, 3, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, - [1758] = {18, 4, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, - [1759] = {18, 5, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, - [1760] = {18, 6, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, - [1761] = {18, 7, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, - [1762] = {18, 8, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, - [1763] = {18, 9, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, - [1764] = {18, 10, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, - [1765] = {18, 11, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, - [1766] = {18, 12, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, - [1767] = {18, 13, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, - [1768] = {18, 14, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, - [1769] = {18, 15, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, - [1770] = {18, 16, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, - [1771] = {18, 17, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, - [1772] = {18, 18, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, - [1773] = {18, 19, "DEV_MCU_CPSW0_GMII_RFT_CLK", "Input clock"}, - [1774] = {18, 20, "DEV_MCU_CPSW0_RMII_MHZ_50_CLK", "Input clock"}, - [1775] = {18, 21, "DEV_MCU_CPSW0_RGMII_MHZ_50_CLK", "Input clock"}, - [1776] = {18, 22, "DEV_MCU_CPSW0_CPPI_CLK_CLK", "Input clock"}, - [1777] = {18, 23, "DEV_MCU_CPSW0_RGMII_MHZ_5_CLK", "Input clock"}, - [1778] = {18, 24, "DEV_MCU_CPSW0_GMII1_MR_CLK", "Input clock"}, - [1779] = {18, 25, "DEV_MCU_CPSW0_GMII1_MT_CLK", "Input clock"}, - [1780] = {18, 26, "DEV_MCU_CPSW0_RGMII1_TXC_I", "Input clock"}, - [1781] = {18, 27, "DEV_MCU_CPSW0_RGMII1_TXC_O", "Output clock"}, - [1782] = {18, 28, "DEV_MCU_CPSW0_CPTS_GENF0_0", "Output clock"}, - [1783] = {18, 29, "DEV_MCU_CPSW0_MDIO_MDCLK_O_0", "Output clock"}, - [1784] = {24, 0, "DEV_MCU_CPT2_AGGR0_VCLK_CLK", "Input clock"}, - [1785] = {44, 0, "DEV_MCU_DCC0_DCC_INPUT10_CLK", "Input clock"}, - [1786] = {44, 1, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"}, - [1787] = {44, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, - [1788] = {44, 3, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, - [1789] = {44, 4, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, - [1790] = {44, 5, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"}, - [1791] = {44, 6, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, - [1792] = {44, 7, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, - [1793] = {44, 8, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, - [1794] = {44, 9, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"}, - [1795] = {44, 10, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, - [1796] = {44, 11, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, - [1797] = {44, 12, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"}, - [1798] = {45, 0, "DEV_MCU_DCC1_DCC_INPUT10_CLK", "Input clock"}, - [1799] = {45, 1, "DEV_MCU_DCC1_DCC_INPUT01_CLK", "Input clock"}, - [1800] = {45, 2, "DEV_MCU_DCC1_DCC_CLKSRC2_CLK", "Input clock"}, - [1801] = {45, 3, "DEV_MCU_DCC1_DCC_CLKSRC7_CLK", "Input clock"}, - [1802] = {45, 4, "DEV_MCU_DCC1_DCC_CLKSRC0_CLK", "Input clock"}, - [1803] = {45, 5, "DEV_MCU_DCC1_VBUS_CLK", "Input clock"}, - [1804] = {45, 6, "DEV_MCU_DCC1_DCC_CLKSRC4_CLK", "Input clock"}, - [1805] = {45, 7, "DEV_MCU_DCC1_DCC_CLKSRC1_CLK", "Input clock"}, - [1806] = {45, 8, "DEV_MCU_DCC1_DCC_CLKSRC3_CLK", "Input clock"}, - [1807] = {45, 9, "DEV_MCU_DCC1_DCC_INPUT00_CLK", "Input clock"}, - [1808] = {45, 10, "DEV_MCU_DCC1_DCC_CLKSRC5_CLK", "Input clock"}, - [1809] = {45, 11, "DEV_MCU_DCC1_DCC_CLKSRC6_CLK", "Input clock"}, - [1810] = {45, 12, "DEV_MCU_DCC1_DCC_INPUT02_CLK", "Input clock"}, - [1811] = {46, 0, "DEV_MCU_DCC2_DCC_INPUT10_CLK", "Input clock"}, - [1812] = {46, 1, "DEV_MCU_DCC2_DCC_INPUT01_CLK", "Input clock"}, - [1813] = {46, 2, "DEV_MCU_DCC2_DCC_CLKSRC7_CLK", "Input clock"}, - [1814] = {46, 3, "DEV_MCU_DCC2_DCC_CLKSRC0_CLK", "Input clock"}, - [1815] = {46, 4, "DEV_MCU_DCC2_VBUS_CLK", "Input clock"}, - [1816] = {46, 5, "DEV_MCU_DCC2_DCC_CLKSRC4_CLK", "Input clock"}, - [1817] = {46, 6, "DEV_MCU_DCC2_DCC_CLKSRC1_CLK", "Input clock"}, - [1818] = {46, 7, "DEV_MCU_DCC2_DCC_CLKSRC3_CLK", "Input clock"}, - [1819] = {46, 8, "DEV_MCU_DCC2_DCC_INPUT00_CLK", "Input clock"}, - [1820] = {46, 9, "DEV_MCU_DCC2_DCC_CLKSRC6_CLK", "Input clock"}, - [1821] = {46, 10, "DEV_MCU_DCC2_DCC_INPUT02_CLK", "Input clock"}, - [1822] = {98, 0, "DEV_MCU_ESM0_CLK", "Input clock"}, - [1823] = {101, 0, "DEV_MCU_FSS0_FSAS_0_GCLK", "Input clock"}, - [1824] = {102, 0, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK", "Input clock"}, - [1825] = {102, 1, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK", "Input clock"}, - [1826] = {102, 2, "DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK", "Input clock"}, - [1827] = {102, 3, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK", "Input clock"}, - [1828] = {102, 4, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK", "Input clock"}, - [1829] = {102, 5, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N", "Output clock"}, - [1830] = {102, 6, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P", "Output clock"}, - [1831] = {103, 0, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK", "Input muxed clock"}, - [1832] = {103, 1, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"}, - [1833] = {103, 2, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"}, - [1834] = {103, 3, "DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"}, - [1835] = {103, 4, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"}, - [1836] = {103, 5, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"}, - [1837] = {103, 6, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"}, - [1838] = {103, 7, "DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"}, - [1839] = {103, 8, "DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"}, - [1840] = {103, 9, "DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"}, - [1841] = {104, 0, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK", "Input muxed clock"}, - [1842] = {104, 1, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"}, - [1843] = {104, 2, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"}, - [1844] = {104, 3, "DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK", "Input clock"}, - [1845] = {104, 4, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK", "Input muxed clock"}, - [1846] = {104, 5, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"}, - [1847] = {104, 6, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"}, - [1848] = {104, 7, "DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK", "Input clock"}, - [1849] = {104, 8, "DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK", "Input clock"}, - [1850] = {104, 9, "DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK", "Output clock"}, - [1851] = {194, 0, "DEV_MCU_I2C0_PISYS_CLK", "Input clock"}, - [1852] = {194, 1, "DEV_MCU_I2C0_PISCL_0", "Input clock"}, - [1853] = {194, 2, "DEV_MCU_I2C0_CLK", "Input clock"}, - [1854] = {194, 3, "DEV_MCU_I2C0_PORSCL_0", "Output clock"}, - [1855] = {195, 0, "DEV_MCU_I2C1_PISYS_CLK", "Input clock"}, - [1856] = {195, 1, "DEV_MCU_I2C1_PISCL_0", "Input clock"}, - [1857] = {195, 2, "DEV_MCU_I2C1_CLK", "Input clock"}, - [1858] = {117, 0, "DEV_MCU_I3C0_I3C_PCLK_CLK", "Input clock"}, - [1859] = {117, 1, "DEV_MCU_I3C0_I3C_SCL_DI", "Input clock"}, - [1860] = {117, 2, "DEV_MCU_I3C0_I3C_SCLK_CLK", "Input clock"}, - [1861] = {117, 3, "DEV_MCU_I3C0_I3C_SCL_DO_0", "Output clock"}, - [1862] = {118, 0, "DEV_MCU_I3C1_I3C_PCLK_CLK", "Input clock"}, - [1863] = {118, 1, "DEV_MCU_I3C1_I3C_SCL_DI", "Input clock"}, - [1864] = {118, 2, "DEV_MCU_I3C1_I3C_SCLK_CLK", "Input clock"}, - [1865] = {118, 3, "DEV_MCU_I3C1_I3C_SCL_DO_0", "Output clock"}, - [1866] = {172, 0, "DEV_MCU_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, - [1867] = {172, 1, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, - [1868] = {172, 2, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, - [1869] = {172, 3, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, - [1870] = {172, 4, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, - [1871] = {172, 5, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, - [1872] = {173, 0, "DEV_MCU_MCAN1_MCANSS_HCLK_CLK", "Input clock"}, - [1873] = {173, 1, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"}, - [1874] = {173, 2, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, - [1875] = {173, 3, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, - [1876] = {173, 4, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, - [1877] = {173, 5, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, - [1878] = {274, 0, "DEV_MCU_MCSPI0_VBUSP_CLK", "Input clock"}, - [1879] = {274, 1, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"}, - [1880] = {274, 2, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, - [1881] = {275, 0, "DEV_MCU_MCSPI1_VBUSP_CLK", "Input clock"}, - [1882] = {275, 1, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"}, - [1883] = {275, 2, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"}, - [1884] = {275, 3, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"}, - [1885] = {275, 4, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, - [1886] = {276, 0, "DEV_MCU_MCSPI2_VBUSP_CLK", "Input clock"}, - [1887] = {276, 1, "DEV_MCU_MCSPI2_CLKSPIREF_CLK", "Input clock"}, - [1888] = {276, 2, "DEV_MCU_MCSPI2_IO_CLKSPII_CLK", "Input clock"}, - [1889] = {276, 3, "DEV_MCU_MCSPI2_IO_CLKSPIO_CLK", "Output clock"}, - [1890] = {233, 0, "DEV_MCU_NAVSS0_INTAGGR_0_SYS_CLK", "Input clock"}, - [1891] = {237, 0, "DEV_MCU_NAVSS0_INTR_ROUTER_0_INTR_CLK", "Input clock"}, - [1892] = {238, 0, "DEV_MCU_NAVSS0_MCRC_0_CLK", "Input clock"}, - [1893] = {302, 0, "DEV_MCU_NAVSS0_MODSS_VD2CLK", "Input clock"}, - [1894] = {234, 0, "DEV_MCU_NAVSS0_PROXY_0_CLK_CLK", "Input clock"}, - [1895] = {235, 0, "DEV_MCU_NAVSS0_RINGACC_0_SYS_CLK", "Input clock"}, - [1896] = {236, 0, "DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"}, - [1897] = {303, 0, "DEV_MCU_NAVSS0_UDMASS_VD2CLK", "Input clock"}, - [1898] = {250, 0, "DEV_MCU_R5FSS0_CORE0_CPU_CLK", "Input muxed clock"}, - [1899] = {250, 1, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"}, - [1900] = {250, 2, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"}, - [1901] = {250, 3, "DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"}, - [1902] = {251, 0, "DEV_MCU_R5FSS0_CORE1_CPU_CLK", "Input muxed clock"}, - [1903] = {251, 1, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"}, - [1904] = {251, 2, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"}, - [1905] = {251, 3, "DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"}, - [1906] = {262, 0, "DEV_MCU_RTI0_VBUSP_CLK", "Input clock"}, - [1907] = {262, 1, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"}, - [1908] = {262, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, - [1909] = {262, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, - [1910] = {262, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, - [1911] = {262, 5, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, - [1912] = {263, 0, "DEV_MCU_RTI1_VBUSP_CLK", "Input clock"}, - [1913] = {263, 1, "DEV_MCU_RTI1_RTI_CLK", "Input muxed clock"}, - [1914] = {263, 2, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, - [1915] = {263, 3, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, - [1916] = {263, 4, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, - [1917] = {263, 5, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, - [1918] = {265, 0, "DEV_MCU_SA2_UL0_X2_CLK", "Input clock"}, - [1919] = {265, 1, "DEV_MCU_SA2_UL0_PKA_IN_CLK", "Input clock"}, - [1920] = {265, 2, "DEV_MCU_SA2_UL0_X1_CLK", "Input clock"}, - [1921] = {35, 0, "DEV_MCU_TIMER0_TIMER_HCLK_CLK", "Input clock"}, - [1922] = {35, 1, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, - [1923] = {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, - [1924] = {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK5", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, - [1925] = {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, - [1926] = {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, - [1927] = {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, - [1928] = {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, - [1929] = {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, - [1930] = {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, - [1931] = {35, 10, "DEV_MCU_TIMER0_TIMER_PWM_0", "Output clock"}, - [1932] = {71, 0, "DEV_MCU_TIMER1_TIMER_HCLK_CLK", "Input clock"}, - [1933] = {71, 1, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, - [1934] = {71, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, - [1935] = {71, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM_0", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, - [1936] = {72, 0, "DEV_MCU_TIMER2_TIMER_HCLK_CLK", "Input clock"}, - [1937] = {72, 1, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, - [1938] = {72, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, - [1939] = {72, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK5", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, - [1940] = {72, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, - [1941] = {72, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, - [1942] = {72, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, - [1943] = {72, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, - [1944] = {72, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, - [1945] = {72, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, - [1946] = {72, 10, "DEV_MCU_TIMER2_TIMER_PWM_0", "Output clock"}, - [1947] = {73, 0, "DEV_MCU_TIMER3_TIMER_HCLK_CLK", "Input clock"}, - [1948] = {73, 1, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, - [1949] = {73, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, - [1950] = {73, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM_0", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, - [1951] = {74, 0, "DEV_MCU_TIMER4_TIMER_HCLK_CLK", "Input clock"}, - [1952] = {74, 1, "DEV_MCU_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"}, - [1953] = {74, 2, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, - [1954] = {74, 3, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK5", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, - [1955] = {74, 4, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, - [1956] = {74, 5, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, - [1957] = {74, 6, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, - [1958] = {74, 7, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, - [1959] = {74, 8, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, - [1960] = {74, 9, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, - [1961] = {74, 10, "DEV_MCU_TIMER4_TIMER_PWM_0", "Output clock"}, - [1962] = {75, 0, "DEV_MCU_TIMER5_TIMER_HCLK_CLK", "Input clock"}, - [1963] = {75, 1, "DEV_MCU_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"}, - [1964] = {75, 2, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"}, - [1965] = {75, 3, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM_0", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"}, - [1966] = {76, 0, "DEV_MCU_TIMER6_TIMER_HCLK_CLK", "Input clock"}, - [1967] = {76, 1, "DEV_MCU_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"}, - [1968] = {76, 2, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, - [1969] = {76, 3, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK5", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, - [1970] = {76, 4, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, - [1971] = {76, 5, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, - [1972] = {76, 6, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, - [1973] = {76, 7, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, - [1974] = {76, 8, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, - [1975] = {76, 9, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, - [1976] = {76, 10, "DEV_MCU_TIMER6_TIMER_PWM_0", "Output clock"}, - [1977] = {77, 0, "DEV_MCU_TIMER7_TIMER_HCLK_CLK", "Input clock"}, - [1978] = {77, 1, "DEV_MCU_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"}, - [1979] = {77, 2, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"}, - [1980] = {77, 3, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM_0", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"}, - [1981] = {78, 0, "DEV_MCU_TIMER8_TIMER_HCLK_CLK", "Input clock"}, - [1982] = {78, 1, "DEV_MCU_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"}, - [1983] = {78, 2, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, - [1984] = {78, 3, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK5", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, - [1985] = {78, 4, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, - [1986] = {78, 5, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, - [1987] = {78, 6, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, - [1988] = {78, 7, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, - [1989] = {78, 8, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, - [1990] = {78, 9, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, - [1991] = {78, 10, "DEV_MCU_TIMER8_TIMER_PWM_0", "Output clock"}, - [1992] = {79, 0, "DEV_MCU_TIMER9_TIMER_HCLK_CLK", "Input clock"}, - [1993] = {79, 1, "DEV_MCU_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"}, - [1994] = {79, 2, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"}, - [1995] = {79, 3, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM_0", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"}, - [1996] = {149, 0, "DEV_MCU_UART0_FCLK_CLK", "Input muxed clock"}, - [1997] = {149, 1, "DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"}, - [1998] = {149, 2, "DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"}, - [1999] = {149, 3, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"}, - [2000] = {186, 0, "DEV_MLB0_MLBSS_MLB_CLK", "Input clock"}, - [2001] = {186, 1, "DEV_MLB0_MLBSS_SCLK_CLK", "Input clock"}, - [2002] = {186, 2, "DEV_MLB0_MLBSS_HCLK_CLK", "Input clock"}, - [2003] = {186, 3, "DEV_MLB0_MLBSS_PCLK_CLK", "Input clock"}, - [2004] = {186, 4, "DEV_MLB0_MLBSS_AMLB_CLK", "Input clock"}, - [2005] = {91, 0, "DEV_MMCSD0_EMMCSS_VBUS_CLK", "Input clock"}, - [2006] = {91, 1, "DEV_MMCSD0_EMMCSS_XIN_CLK", "Input muxed clock"}, - [2007] = {91, 2, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, - [2008] = {91, 3, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, - [2009] = {91, 4, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, - [2010] = {91, 5, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, - [2011] = {91, 6, "DEV_MMCSD0_EMMCSS_IO_CLK_0", "Output clock"}, - [2012] = {92, 0, "DEV_MMCSD1_EMMCSDSS_XIN_CLK", "Input muxed clock"}, - [2013] = {92, 1, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, - [2014] = {92, 2, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, - [2015] = {92, 3, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, - [2016] = {92, 4, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, - [2017] = {92, 5, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"}, - [2018] = {92, 6, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I_0", "Input clock"}, - [2019] = {92, 7, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O_0", "Output clock"}, - [2020] = {93, 0, "DEV_MMCSD2_EMMCSDSS_XIN_CLK", "Input muxed clock"}, - [2021] = {93, 1, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"}, - [2022] = {93, 2, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"}, - [2023] = {93, 3, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"}, - [2024] = {93, 4, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"}, - [2025] = {93, 5, "DEV_MMCSD2_EMMCSDSS_VBUS_CLK", "Input clock"}, - [2026] = {93, 6, "DEV_MMCSD2_EMMCSDSS_IO_CLK_I_0", "Input clock"}, - [2027] = {93, 7, "DEV_MMCSD2_EMMCSDSS_IO_CLK_O_0", "Output clock"}, - [2028] = {201, 0, "DEV_NAVSS0_CPTS_0_VBUSP_GCLK", "Input clock"}, - [2029] = {201, 1, "DEV_NAVSS0_CPTS_0_RCLK", "Input muxed clock"}, - [2030] = {201, 2, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, - [2031] = {201, 3, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, - [2032] = {201, 4, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, - [2033] = {201, 5, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, - [2034] = {201, 6, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, - [2035] = {201, 7, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, - [2036] = {201, 8, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, - [2037] = {201, 9, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, - [2038] = {201, 10, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, - [2039] = {201, 11, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, - [2040] = {201, 12, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, - [2041] = {201, 13, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, - [2042] = {201, 14, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, - [2043] = {201, 15, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, - [2044] = {201, 16, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, - [2045] = {201, 17, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, - [2046] = {201, 18, "DEV_NAVSS0_CPTS_0_TS_GENF0", "Output clock"}, - [2047] = {201, 19, "DEV_NAVSS0_CPTS_0_TS_GENF1", "Output clock"}, - [2048] = {206, 0, "DEV_NAVSS0_DTI_0_CLK_CLK", "Input clock"}, - [2049] = {206, 1, "DEV_NAVSS0_DTI_0_EXT0_DTI_CLK_CLK", "Input clock"}, - [2050] = {206, 2, "DEV_NAVSS0_DTI_0_EXT3_DTI_CLK_CLK", "Input clock"}, - [2051] = {206, 3, "DEV_NAVSS0_DTI_0_EXT1_DTI_CLK_CLK", "Input clock"}, - [2052] = {206, 4, "DEV_NAVSS0_DTI_0_EXT2_DTI_CLK_CLK", "Input clock"}, - [2053] = {213, 0, "DEV_NAVSS0_INTR_ROUTER_0_INTR_CLK", "Input clock"}, - [2054] = {214, 0, "DEV_NAVSS0_MAILBOX_0_VCLK_CLK", "Input clock"}, - [2055] = {215, 0, "DEV_NAVSS0_MAILBOX_1_VCLK_CLK", "Input clock"}, - [2056] = {224, 0, "DEV_NAVSS0_MAILBOX_10_VCLK_CLK", "Input clock"}, - [2057] = {225, 0, "DEV_NAVSS0_MAILBOX_11_VCLK_CLK", "Input clock"}, - [2058] = {216, 0, "DEV_NAVSS0_MAILBOX_2_VCLK_CLK", "Input clock"}, - [2059] = {217, 0, "DEV_NAVSS0_MAILBOX_3_VCLK_CLK", "Input clock"}, - [2060] = {218, 0, "DEV_NAVSS0_MAILBOX_4_VCLK_CLK", "Input clock"}, - [2061] = {219, 0, "DEV_NAVSS0_MAILBOX_5_VCLK_CLK", "Input clock"}, - [2062] = {220, 0, "DEV_NAVSS0_MAILBOX_6_VCLK_CLK", "Input clock"}, - [2063] = {221, 0, "DEV_NAVSS0_MAILBOX_7_VCLK_CLK", "Input clock"}, - [2064] = {222, 0, "DEV_NAVSS0_MAILBOX_8_VCLK_CLK", "Input clock"}, - [2065] = {223, 0, "DEV_NAVSS0_MAILBOX_9_VCLK_CLK", "Input clock"}, - [2066] = {227, 0, "DEV_NAVSS0_MCRC_0_CLK", "Input clock"}, - [2067] = {299, 0, "DEV_NAVSS0_MODSS_VD2CLK", "Input clock"}, - [2068] = {207, 0, "DEV_NAVSS0_MODSS_INTAGGR_0_SYS_CLK", "Input clock"}, - [2069] = {208, 0, "DEV_NAVSS0_MODSS_INTAGGR_1_SYS_CLK", "Input clock"}, - [2070] = {210, 0, "DEV_NAVSS0_PROXY_0_CLK_CLK", "Input clock"}, - [2071] = {211, 0, "DEV_NAVSS0_RINGACC_0_SYS_CLK", "Input clock"}, - [2072] = {226, 0, "DEV_NAVSS0_SPINLOCK_0_CLK", "Input clock"}, - [2073] = {228, 0, "DEV_NAVSS0_TBU_0_CLK_CLK", "Input clock"}, - [2074] = {229, 0, "DEV_NAVSS0_TCU_0_CLK_CLK", "Input clock"}, - [2075] = {230, 0, "DEV_NAVSS0_TIMERMGR_0_VCLK_CLK", "Input clock"}, - [2076] = {230, 1, "DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT", "Input clock"}, - [2077] = {231, 0, "DEV_NAVSS0_TIMERMGR_1_VCLK_CLK", "Input clock"}, - [2078] = {231, 1, "DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT", "Input clock"}, - [2079] = {212, 0, "DEV_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"}, - [2080] = {300, 0, "DEV_NAVSS0_UDMASS_VD2CLK", "Input clock"}, - [2081] = {209, 0, "DEV_NAVSS0_UDMASS_INTAGGR_0_SYS_CLK", "Input clock"}, - [2082] = {301, 0, "DEV_NAVSS0_VIRTSS_VD2CLK", "Input clock"}, - [2083] = {199, 0, "DEV_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Output clock"}, - [2084] = {199, 1, "DEV_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Output clock"}, - [2085] = {239, 0, "DEV_PCIE0_PCIE_LANE1_TXMCLK", "Input clock"}, - [2086] = {239, 1, "DEV_PCIE0_PCIE_CBA_CLK", "Input clock"}, - [2087] = {239, 2, "DEV_PCIE0_PCIE_LANE1_RXCLK", "Input clock"}, - [2088] = {239, 3, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, - [2089] = {239, 4, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, - [2090] = {239, 5, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, - [2091] = {239, 6, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, - [2092] = {239, 7, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, - [2093] = {239, 8, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, - [2094] = {239, 9, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, - [2095] = {239, 10, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, - [2096] = {239, 11, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, - [2097] = {239, 12, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, - [2098] = {239, 13, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, - [2099] = {239, 14, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, - [2100] = {239, 15, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, - [2101] = {239, 16, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, - [2102] = {239, 17, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, - [2103] = {239, 18, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, - [2104] = {239, 19, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, - [2105] = {239, 20, "DEV_PCIE0_PCIE_LANE1_TXFCLK", "Input clock"}, - [2106] = {239, 21, "DEV_PCIE0_PCIE_LANE1_REFCLK", "Input clock"}, - [2107] = {239, 22, "DEV_PCIE0_PCIE_LANE0_REFCLK", "Input clock"}, - [2108] = {239, 23, "DEV_PCIE0_PCIE_LANE0_TXMCLK", "Input clock"}, - [2109] = {239, 24, "DEV_PCIE0_PCIE_LANE0_TXFCLK", "Input clock"}, - [2110] = {239, 25, "DEV_PCIE0_PCIE_PM_CLK", "Input clock"}, - [2111] = {239, 26, "DEV_PCIE0_PCIE_LANE0_RXFCLK", "Input clock"}, - [2112] = {239, 27, "DEV_PCIE0_PCIE_LANE1_RXFCLK", "Input clock"}, - [2113] = {239, 28, "DEV_PCIE0_PCIE_LANE0_RXCLK", "Input clock"}, - [2114] = {239, 29, "DEV_PCIE0_PCIE_LANE1_TXCLK", "Output clock"}, - [2115] = {239, 30, "DEV_PCIE0_PCIE_LANE0_TXCLK", "Output clock"}, - [2116] = {240, 0, "DEV_PCIE1_PCIE_LANE1_TXMCLK", "Input clock"}, - [2117] = {240, 1, "DEV_PCIE1_PCIE_CBA_CLK", "Input clock"}, - [2118] = {240, 2, "DEV_PCIE1_PCIE_LANE1_RXCLK", "Input clock"}, - [2119] = {240, 3, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, - [2120] = {240, 4, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, - [2121] = {240, 5, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, - [2122] = {240, 6, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, - [2123] = {240, 7, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, - [2124] = {240, 8, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, - [2125] = {240, 9, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, - [2126] = {240, 10, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, - [2127] = {240, 11, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, - [2128] = {240, 12, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, - [2129] = {240, 13, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, - [2130] = {240, 14, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, - [2131] = {240, 15, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, - [2132] = {240, 16, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, - [2133] = {240, 17, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, - [2134] = {240, 18, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, - [2135] = {240, 19, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, - [2136] = {240, 20, "DEV_PCIE1_PCIE_LANE1_TXFCLK", "Input clock"}, - [2137] = {240, 21, "DEV_PCIE1_PCIE_LANE1_REFCLK", "Input clock"}, - [2138] = {240, 22, "DEV_PCIE1_PCIE_LANE0_REFCLK", "Input clock"}, - [2139] = {240, 23, "DEV_PCIE1_PCIE_LANE0_TXMCLK", "Input clock"}, - [2140] = {240, 24, "DEV_PCIE1_PCIE_LANE0_TXFCLK", "Input clock"}, - [2141] = {240, 25, "DEV_PCIE1_PCIE_PM_CLK", "Input clock"}, - [2142] = {240, 26, "DEV_PCIE1_PCIE_LANE0_RXFCLK", "Input clock"}, - [2143] = {240, 27, "DEV_PCIE1_PCIE_LANE1_RXFCLK", "Input clock"}, - [2144] = {240, 28, "DEV_PCIE1_PCIE_LANE0_RXCLK", "Input clock"}, - [2145] = {240, 29, "DEV_PCIE1_PCIE_LANE1_TXCLK", "Output clock"}, - [2146] = {240, 30, "DEV_PCIE1_PCIE_LANE0_TXCLK", "Output clock"}, - [2147] = {241, 0, "DEV_PCIE2_PCIE_LANE1_TXMCLK", "Input clock"}, - [2148] = {241, 1, "DEV_PCIE2_PCIE_CBA_CLK", "Input clock"}, - [2149] = {241, 2, "DEV_PCIE2_PCIE_LANE1_RXCLK", "Input clock"}, - [2150] = {241, 3, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, - [2151] = {241, 4, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, - [2152] = {241, 5, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, - [2153] = {241, 6, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, - [2154] = {241, 7, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, - [2155] = {241, 8, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, - [2156] = {241, 9, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, - [2157] = {241, 10, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, - [2158] = {241, 11, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, - [2159] = {241, 12, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, - [2160] = {241, 13, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, - [2161] = {241, 14, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, - [2162] = {241, 15, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, - [2163] = {241, 16, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, - [2164] = {241, 17, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, - [2165] = {241, 18, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, - [2166] = {241, 19, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, - [2167] = {241, 20, "DEV_PCIE2_PCIE_LANE1_TXFCLK", "Input clock"}, - [2168] = {241, 21, "DEV_PCIE2_PCIE_LANE1_REFCLK", "Input clock"}, - [2169] = {241, 22, "DEV_PCIE2_PCIE_LANE0_REFCLK", "Input clock"}, - [2170] = {241, 23, "DEV_PCIE2_PCIE_LANE0_TXMCLK", "Input clock"}, - [2171] = {241, 24, "DEV_PCIE2_PCIE_LANE0_TXFCLK", "Input clock"}, - [2172] = {241, 25, "DEV_PCIE2_PCIE_PM_CLK", "Input clock"}, - [2173] = {241, 26, "DEV_PCIE2_PCIE_LANE0_RXFCLK", "Input clock"}, - [2174] = {241, 27, "DEV_PCIE2_PCIE_LANE1_RXFCLK", "Input clock"}, - [2175] = {241, 28, "DEV_PCIE2_PCIE_LANE0_RXCLK", "Input clock"}, - [2176] = {241, 29, "DEV_PCIE2_PCIE_LANE1_TXCLK", "Output clock"}, - [2177] = {241, 30, "DEV_PCIE2_PCIE_LANE0_TXCLK", "Output clock"}, - [2178] = {242, 0, "DEV_PCIE3_PCIE_LANE1_TXMCLK", "Input clock"}, - [2179] = {242, 1, "DEV_PCIE3_PCIE_CBA_CLK", "Input clock"}, - [2180] = {242, 2, "DEV_PCIE3_PCIE_LANE1_RXCLK", "Input clock"}, - [2181] = {242, 3, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, - [2182] = {242, 4, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, - [2183] = {242, 5, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, - [2184] = {242, 6, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, - [2185] = {242, 7, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, - [2186] = {242, 8, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, - [2187] = {242, 9, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, - [2188] = {242, 10, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, - [2189] = {242, 11, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, - [2190] = {242, 12, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, - [2191] = {242, 13, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, - [2192] = {242, 14, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, - [2193] = {242, 15, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, - [2194] = {242, 16, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, - [2195] = {242, 17, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, - [2196] = {242, 18, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, - [2197] = {242, 19, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, - [2198] = {242, 20, "DEV_PCIE3_PCIE_LANE1_TXFCLK", "Input clock"}, - [2199] = {242, 21, "DEV_PCIE3_PCIE_LANE1_REFCLK", "Input clock"}, - [2200] = {242, 22, "DEV_PCIE3_PCIE_LANE0_REFCLK", "Input clock"}, - [2201] = {242, 23, "DEV_PCIE3_PCIE_LANE0_TXMCLK", "Input clock"}, - [2202] = {242, 24, "DEV_PCIE3_PCIE_LANE0_TXFCLK", "Input clock"}, - [2203] = {242, 25, "DEV_PCIE3_PCIE_PM_CLK", "Input clock"}, - [2204] = {242, 26, "DEV_PCIE3_PCIE_LANE0_RXFCLK", "Input clock"}, - [2205] = {242, 27, "DEV_PCIE3_PCIE_LANE1_RXFCLK", "Input clock"}, - [2206] = {242, 28, "DEV_PCIE3_PCIE_LANE0_RXCLK", "Input clock"}, - [2207] = {242, 29, "DEV_PCIE3_PCIE_LANE1_TXCLK", "Output clock"}, - [2208] = {242, 30, "DEV_PCIE3_PCIE_LANE0_TXCLK", "Output clock"}, - [2209] = {119, 0, "DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I_0", "Input clock"}, - [2210] = {119, 1, "DEV_PRU_ICSSG0_VCLK_CLK", "Input clock"}, - [2211] = {119, 2, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I_0", "Input clock"}, - [2212] = {119, 3, "DEV_PRU_ICSSG0_IEP_CLK", "Input muxed clock"}, - [2213] = {119, 4, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, - [2214] = {119, 5, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, - [2215] = {119, 6, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, - [2216] = {119, 7, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, - [2217] = {119, 8, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, - [2218] = {119, 9, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, - [2219] = {119, 10, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, - [2220] = {119, 11, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, - [2221] = {119, 12, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, - [2222] = {119, 13, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, - [2223] = {119, 14, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, - [2224] = {119, 15, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, - [2225] = {119, 16, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, - [2226] = {119, 17, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, - [2227] = {119, 18, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, - [2228] = {119, 19, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, - [2229] = {119, 20, "DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK", "Input clock"}, - [2230] = {119, 21, "DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I_0", "Input clock"}, - [2231] = {119, 22, "DEV_PRU_ICSSG0_UCLK_CLK", "Input clock"}, - [2232] = {119, 23, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I_0", "Input clock"}, - [2233] = {119, 24, "DEV_PRU_ICSSG0_CORE_CLK", "Input muxed clock"}, - [2234] = {119, 25, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"}, - [2235] = {119, 26, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"}, - [2236] = {119, 27, "DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK", "Input clock"}, - [2237] = {119, 28, "DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK", "Input clock"}, - [2238] = {119, 29, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O_0", "Output clock"}, - [2239] = {119, 30, "DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O_0", "Output clock"}, - [2240] = {119, 31, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O_0", "Output clock"}, - [2241] = {120, 0, "DEV_PRU_ICSSG1_SERDES0_RXCLK", "Input muxed clock"}, - [2242] = {120, 1, "DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK"}, - [2243] = {120, 2, "DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK"}, - [2244] = {120, 3, "DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I_0", "Input clock"}, - [2245] = {120, 4, "DEV_PRU_ICSSG1_VCLK_CLK", "Input clock"}, - [2246] = {120, 5, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I_0", "Input clock"}, - [2247] = {120, 6, "DEV_PRU_ICSSG1_SERDES0_RXFCLK", "Input muxed clock"}, - [2248] = {120, 7, "DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK"}, - [2249] = {120, 8, "DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK"}, - [2250] = {120, 9, "DEV_PRU_ICSSG1_IEP_CLK", "Input muxed clock"}, - [2251] = {120, 10, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, - [2252] = {120, 11, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, - [2253] = {120, 12, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, - [2254] = {120, 13, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, - [2255] = {120, 14, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, - [2256] = {120, 15, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, - [2257] = {120, 16, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, - [2258] = {120, 17, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, - [2259] = {120, 18, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, - [2260] = {120, 19, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, - [2261] = {120, 20, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, - [2262] = {120, 21, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, - [2263] = {120, 22, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, - [2264] = {120, 23, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, - [2265] = {120, 24, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, - [2266] = {120, 25, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, - [2267] = {120, 26, "DEV_PRU_ICSSG1_RGMII_MHZ_5_CLK", "Input clock"}, - [2268] = {120, 27, "DEV_PRU_ICSSG1_SERDES0_TXMCLK", "Input muxed clock"}, - [2269] = {120, 28, "DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK"}, - [2270] = {120, 29, "DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK"}, - [2271] = {120, 30, "DEV_PRU_ICSSG1_SERDES0_REFCLK", "Input muxed clock"}, - [2272] = {120, 31, "DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK"}, - [2273] = {120, 32, "DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK"}, - [2274] = {120, 33, "DEV_PRU_ICSSG1_SERDES1_RXFCLK", "Input muxed clock"}, - [2275] = {120, 34, "DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK"}, - [2276] = {120, 35, "DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK"}, - [2277] = {120, 36, "DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I_0", "Input clock"}, - [2278] = {120, 37, "DEV_PRU_ICSSG1_SERDES1_RXCLK", "Input muxed clock"}, - [2279] = {120, 38, "DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK"}, - [2280] = {120, 39, "DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK"}, - [2281] = {120, 40, "DEV_PRU_ICSSG1_SERDES1_TXFCLK", "Input muxed clock"}, - [2282] = {120, 41, "DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK"}, - [2283] = {120, 42, "DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK"}, - [2284] = {120, 43, "DEV_PRU_ICSSG1_SERDES1_TXMCLK", "Input muxed clock"}, - [2285] = {120, 44, "DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK"}, - [2286] = {120, 45, "DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK"}, - [2287] = {120, 46, "DEV_PRU_ICSSG1_SERDES0_TXFCLK", "Input muxed clock"}, - [2288] = {120, 47, "DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK"}, - [2289] = {120, 48, "DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK"}, - [2290] = {120, 49, "DEV_PRU_ICSSG1_UCLK_CLK", "Input clock"}, - [2291] = {120, 50, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I_0", "Input clock"}, - [2292] = {120, 51, "DEV_PRU_ICSSG1_SERDES1_REFCLK", "Input muxed clock"}, - [2293] = {120, 52, "DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK"}, - [2294] = {120, 53, "DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK"}, - [2295] = {120, 54, "DEV_PRU_ICSSG1_CORE_CLK", "Input muxed clock"}, - [2296] = {120, 55, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"}, - [2297] = {120, 56, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"}, - [2298] = {120, 57, "DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK", "Input clock"}, - [2299] = {120, 58, "DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK", "Input clock"}, - [2300] = {120, 59, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O_0", "Output clock"}, - [2301] = {120, 60, "DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O_0", "Output clock"}, - [2302] = {120, 61, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O_0", "Output clock"}, - [2303] = {120, 62, "DEV_PRU_ICSSG1_SERDES0_TXCLK", "Output clock"}, - [2304] = {120, 63, "DEV_PRU_ICSSG1_SERDES1_TXCLK", "Output clock"}, - [2305] = {133, 0, "DEV_PSC0_SLOW_CLK", "Input clock"}, - [2306] = {133, 1, "DEV_PSC0_CLK", "Input clock"}, - [2307] = {243, 0, "DEV_PULSAR_SL_MAIN_0_INTERFACE0_PHASE_0", "Input clock"}, - [2308] = {243, 1, "DEV_PULSAR_SL_MAIN_0_INTERFACE1_PHASE_0", "Input clock"}, - [2309] = {244, 0, "DEV_PULSAR_SL_MAIN_1_INTERFACE0_PHASE_0", "Input clock"}, - [2310] = {244, 1, "DEV_PULSAR_SL_MAIN_1_INTERFACE1_PHASE_0", "Input clock"}, - [2311] = {249, 0, "DEV_PULSAR_SL_MCU_0_INTERFACE0_PHASE_0", "Input muxed clock"}, - [2312] = {249, 1, "DEV_PULSAR_SL_MCU_0_INTERFACE0_PHASE_0_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_PULSAR_SL_MCU_0_INTERFACE0_PHASE_0"}, - [2313] = {249, 2, "DEV_PULSAR_SL_MCU_0_INTERFACE1_PHASE_0", "Input muxed clock"}, - [2314] = {249, 3, "DEV_PULSAR_SL_MCU_0_INTERFACE1_PHASE_0_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_PULSAR_SL_MCU_0_INTERFACE1_PHASE_0"}, - [2315] = {245, 0, "DEV_R5FSS0_CORE0_CPU_CLK", "Input clock"}, - [2316] = {245, 1, "DEV_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"}, - [2317] = {246, 0, "DEV_R5FSS0_CORE1_CPU_CLK", "Input clock"}, - [2318] = {246, 1, "DEV_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"}, - [2319] = {134, 0, "DEV_R5FSS0_INTROUTER0_INTR_CLK", "Input clock"}, - [2320] = {247, 0, "DEV_R5FSS1_CORE0_CPU_CLK", "Input clock"}, - [2321] = {247, 1, "DEV_R5FSS1_CORE0_INTERFACE_CLK", "Input clock"}, - [2322] = {248, 0, "DEV_R5FSS1_CORE1_CPU_CLK", "Input clock"}, - [2323] = {248, 1, "DEV_R5FSS1_CORE1_INTERFACE_CLK", "Input clock"}, + [658] = {142, 6, "DEV_C66SS0_CORE0_GEM_CLKIN_CLK", "Input clock"}, + [659] = {121, 0, "DEV_C66SS0_INTROUTER0_INTR_CLK", "Input clock"}, + [660] = {143, 0, "DEV_C66SS1_CORE0_GEM_TRC_CLK", "Input clock"}, + [661] = {143, 1, "DEV_C66SS1_CORE0_GEM_CLK2_OUT_CLK", "Output clock"}, + [662] = {143, 4, "DEV_C66SS1_CORE0_GEM_PBIST_ROM_CLK", "Output clock"}, + [663] = {143, 6, "DEV_C66SS1_CORE0_GEM_CLKIN_CLK", "Input clock"}, + [664] = {122, 0, "DEV_C66SS1_INTROUTER0_INTR_CLK", "Input clock"}, + [665] = {15, 0, "DEV_C71SS0_C7X_CLK", "Input clock"}, + [666] = {15, 1, "DEV_C71SS0_PLL_CTRL_CLK", "Input clock"}, + [667] = {16, 0, "DEV_C71SS0_MMA_PLL_CTRL_CLK", "Input clock"}, + [668] = {16, 1, "DEV_C71SS0_MMA_MMA_CLK", "Input clock"}, + [669] = {123, 0, "DEV_CMPEVENT_INTRTR0_INTR_CLK", "Input clock"}, + [670] = {5, 0, "DEV_COMPUTE_CLUSTER0_CFG_WRAP_CLK4_CLK", "Input clock"}, + [671] = {6, 0, "DEV_COMPUTE_CLUSTER0_CLEC_CLK4_CLK", "Input clock"}, + [672] = {6, 1, "DEV_COMPUTE_CLUSTER0_CLEC_CLK1_CLK", "Input clock"}, + [673] = {7, 0, "DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK", "Input clock"}, + [674] = {7, 1, "DEV_COMPUTE_CLUSTER0_CORE_CORE_CLK1_CLK", "Input clock"}, + [675] = {8, 0, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_PLL_CTRL_CLK", "Input clock"}, + [676] = {8, 1, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_DDRSS_DDR_PLL_CLK", "Input clock"}, + [677] = {9, 0, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK1_CLK_CLK", "Input clock"}, + [678] = {9, 1, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK2_CLK_CLK", "Input clock"}, + [679] = {12, 0, "DEV_COMPUTE_CLUSTER0_DMSC_WRAP_CLK4_CLK_CLK", "Input clock"}, + [680] = {13, 0, "DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_MSMC_CLK1_CLK", "Input clock"}, + [681] = {14, 0, "DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK", "Input clock"}, + [682] = {17, 0, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVP_CLK1_CLK_CLK", "Input clock"}, + [683] = {17, 1, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK4_CLK_CLK", "Input clock"}, + [684] = {17, 2, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK2_CLK_CLK", "Input clock"}, + [685] = {19, 0, "DEV_CPSW0_GMII3_MT_CLK", "Input clock"}, + [686] = {19, 1, "DEV_CPSW0_SERDES6_TXFCLK", "Input clock"}, + [687] = {19, 2, "DEV_CPSW0_SERDES8_TXMCLK", "Input clock"}, + [688] = {19, 3, "DEV_CPSW0_GMII2_MR_CLK", "Input clock"}, + [689] = {19, 4, "DEV_CPSW0_SERDES2_TXFCLK", "Input clock"}, + [690] = {19, 5, "DEV_CPSW0_SERDES4_RXCLK", "Input clock"}, + [691] = {19, 6, "DEV_CPSW0_SERDES7_TXMCLK", "Input clock"}, + [692] = {19, 7, "DEV_CPSW0_SERDES7_RXCLK", "Input clock"}, + [693] = {19, 8, "DEV_CPSW0_SERDES6_REFCLK", "Input clock"}, + [694] = {19, 9, "DEV_CPSW0_SERDES5_TXFCLK", "Input clock"}, + [695] = {19, 10, "DEV_CPSW0_SERDES5_RXCLK", "Input clock"}, + [696] = {19, 11, "DEV_CPSW0_GMII4_MT_CLK", "Input clock"}, + [697] = {19, 12, "DEV_CPSW0_SERDES3_TXFCLK", "Input clock"}, + [698] = {19, 13, "DEV_CPSW0_SERDES2_REFCLK", "Input clock"}, + [699] = {19, 14, "DEV_CPSW0_SERDES4_RXFCLK", "Input clock"}, + [700] = {19, 15, "DEV_CPSW0_SERDES6_RXFCLK", "Input clock"}, + [701] = {19, 16, "DEV_CPSW0_CPTS_RFT_CLK", "Input muxed clock"}, + [702] = {19, 17, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [703] = {19, 18, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [704] = {19, 19, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [705] = {19, 20, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [706] = {19, 21, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [707] = {19, 22, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [708] = {19, 23, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [709] = {19, 24, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [710] = {19, 25, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [711] = {19, 26, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [712] = {19, 27, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [713] = {19, 28, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [714] = {19, 29, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [715] = {19, 30, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [716] = {19, 31, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [717] = {19, 32, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, + [718] = {19, 33, "DEV_CPSW0_SERDES5_RXFCLK", "Input clock"}, + [719] = {19, 34, "DEV_CPSW0_SERDES5_TXMCLK", "Input clock"}, + [720] = {19, 35, "DEV_CPSW0_GMII5_MT_CLK", "Input clock"}, + [721] = {19, 36, "DEV_CPSW0_SERDES2_RXCLK", "Input clock"}, + [722] = {19, 37, "DEV_CPSW0_SERDES8_RXFCLK", "Input clock"}, + [723] = {19, 38, "DEV_CPSW0_SERDES1_RXFCLK", "Input clock"}, + [724] = {19, 39, "DEV_CPSW0_SERDES8_RXCLK", "Input clock"}, + [725] = {19, 40, "DEV_CPSW0_GMII_RFT_CLK", "Input clock"}, + [726] = {19, 41, "DEV_CPSW0_SERDES3_REFCLK", "Input clock"}, + [727] = {19, 42, "DEV_CPSW0_RGMII_MHZ_250_CLK", "Input clock"}, + [728] = {19, 43, "DEV_CPSW0_SERDES7_REFCLK", "Input clock"}, + [729] = {19, 44, "DEV_CPSW0_GMII6_MT_CLK", "Input clock"}, + [730] = {19, 45, "DEV_CPSW0_SERDES6_TXMCLK", "Input clock"}, + [731] = {19, 46, "DEV_CPSW0_RMII_MHZ_50_CLK", "Input clock"}, + [732] = {19, 47, "DEV_CPSW0_GMII4_MR_CLK", "Input clock"}, + [733] = {19, 48, "DEV_CPSW0_SERDES2_TXMCLK", "Input clock"}, + [734] = {19, 49, "DEV_CPSW0_RGMII_MHZ_50_CLK", "Input clock"}, + [735] = {19, 50, "DEV_CPSW0_SERDES4_TXMCLK", "Input clock"}, + [736] = {19, 51, "DEV_CPSW0_SERDES3_RXFCLK", "Input clock"}, + [737] = {19, 52, "DEV_CPSW0_GMII8_MT_CLK", "Input clock"}, + [738] = {19, 53, "DEV_CPSW0_SERDES7_TXFCLK", "Input clock"}, + [739] = {19, 54, "DEV_CPSW0_GMII7_MT_CLK", "Input clock"}, + [740] = {19, 55, "DEV_CPSW0_GMII7_MR_CLK", "Input clock"}, + [741] = {19, 56, "DEV_CPSW0_SERDES6_RXCLK", "Input clock"}, + [742] = {19, 57, "DEV_CPSW0_SERDES3_RXCLK", "Input clock"}, + [743] = {19, 58, "DEV_CPSW0_SERDES4_REFCLK", "Input clock"}, + [744] = {19, 59, "DEV_CPSW0_SERDES1_RXCLK", "Input clock"}, + [745] = {19, 60, "DEV_CPSW0_SERDES1_TXFCLK", "Input clock"}, + [746] = {19, 61, "DEV_CPSW0_GMII6_MR_CLK", "Input clock"}, + [747] = {19, 62, "DEV_CPSW0_SERDES1_REFCLK", "Input clock"}, + [748] = {19, 63, "DEV_CPSW0_RGMII_MHZ_5_CLK", "Input clock"}, + [749] = {19, 64, "DEV_CPSW0_SERDES5_REFCLK", "Input clock"}, + [750] = {19, 65, "DEV_CPSW0_GMII2_MT_CLK", "Input clock"}, + [751] = {19, 66, "DEV_CPSW0_SERDES8_TXFCLK", "Input clock"}, + [752] = {19, 67, "DEV_CPSW0_GMII8_MR_CLK", "Input clock"}, + [753] = {19, 68, "DEV_CPSW0_GMII1_MR_CLK", "Input clock"}, + [754] = {19, 69, "DEV_CPSW0_SERDES8_REFCLK", "Input clock"}, + [755] = {19, 70, "DEV_CPSW0_SERDES3_TXMCLK", "Input clock"}, + [756] = {19, 71, "DEV_CPSW0_GMII3_MR_CLK", "Input clock"}, + [757] = {19, 72, "DEV_CPSW0_SERDES1_TXMCLK", "Input clock"}, + [758] = {19, 73, "DEV_CPSW0_SERDES7_RXFCLK", "Input clock"}, + [759] = {19, 74, "DEV_CPSW0_GMII5_MR_CLK", "Input clock"}, + [760] = {19, 75, "DEV_CPSW0_GMII1_MT_CLK", "Input clock"}, + [761] = {19, 76, "DEV_CPSW0_SERDES2_RXFCLK", "Input clock"}, + [762] = {19, 77, "DEV_CPSW0_SERDES4_TXFCLK", "Input clock"}, + [763] = {19, 78, "DEV_CPSW0_SERDES3_TXCLK", "Output clock"}, + [764] = {19, 79, "DEV_CPSW0_CPTS_GENF0", "Output clock"}, + [765] = {19, 80, "DEV_CPSW0_SERDES5_TXCLK", "Output clock"}, + [766] = {19, 81, "DEV_CPSW0_SERDES6_TXCLK", "Output clock"}, + [767] = {19, 82, "DEV_CPSW0_SERDES8_TXCLK", "Output clock"}, + [768] = {19, 83, "DEV_CPSW0_SERDES1_TXCLK", "Output clock"}, + [769] = {19, 84, "DEV_CPSW0_SERDES4_TXCLK", "Output clock"}, + [770] = {19, 85, "DEV_CPSW0_SERDES2_TXCLK", "Output clock"}, + [771] = {19, 86, "DEV_CPSW0_SERDES7_TXCLK", "Output clock"}, + [772] = {19, 87, "DEV_CPSW0_MDIO_MDCLK_O", "Output clock"}, + [773] = {19, 89, "DEV_CPSW0_CPPI_CLK_CLK", "Input clock"}, + [774] = {20, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"}, + [775] = {21, 0, "DEV_CPT2_AGGR1_VCLK_CLK", "Input clock"}, + [776] = {23, 0, "DEV_CPT2_AGGR2_VCLK_CLK", "Input clock"}, + [777] = {25, 0, "DEV_CSI_PSILSS0_MAIN_CLK", "Input clock"}, + [778] = {26, 0, "DEV_CSI_RX_IF0_VBUS_CLK_CLK", "Input clock"}, + [779] = {26, 1, "DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK", "Input clock"}, + [780] = {26, 2, "DEV_CSI_RX_IF0_MAIN_CLK_CLK", "Input clock"}, + [781] = {26, 3, "DEV_CSI_RX_IF0_VP_CLK_CLK", "Input clock"}, + [782] = {27, 0, "DEV_CSI_RX_IF1_VBUS_CLK_CLK", "Input clock"}, + [783] = {27, 1, "DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK", "Input clock"}, + [784] = {27, 2, "DEV_CSI_RX_IF1_MAIN_CLK_CLK", "Input clock"}, + [785] = {27, 3, "DEV_CSI_RX_IF1_VP_CLK_CLK", "Input clock"}, + [786] = {28, 0, "DEV_CSI_TX_IF0_ESC_CLK_CLK", "Input clock"}, + [787] = {28, 1, "DEV_CSI_TX_IF0_DPHY_TXBYTECLKHS_CL_CLK", "Input clock"}, + [788] = {28, 2, "DEV_CSI_TX_IF0_VBUS_CLK_CLK", "Input clock"}, + [789] = {28, 3, "DEV_CSI_TX_IF0_MAIN_CLK_CLK", "Input clock"}, + [790] = {30, 0, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"}, + [791] = {30, 1, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"}, + [792] = {30, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, + [793] = {30, 3, "DEV_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, + [794] = {30, 4, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, + [795] = {30, 5, "DEV_DCC0_VBUS_CLK", "Input clock"}, + [796] = {30, 6, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, + [797] = {30, 7, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, + [798] = {30, 8, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, + [799] = {30, 9, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"}, + [800] = {30, 10, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, + [801] = {30, 11, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, + [802] = {30, 12, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"}, + [803] = {31, 0, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"}, + [804] = {31, 1, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"}, + [805] = {31, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"}, + [806] = {31, 3, "DEV_DCC1_DCC_CLKSRC7_CLK", "Input clock"}, + [807] = {31, 4, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"}, + [808] = {31, 5, "DEV_DCC1_VBUS_CLK", "Input clock"}, + [809] = {31, 6, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"}, + [810] = {31, 7, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"}, + [811] = {31, 8, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"}, + [812] = {31, 9, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"}, + [813] = {31, 10, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"}, + [814] = {31, 11, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"}, + [815] = {31, 12, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"}, + [816] = {41, 0, "DEV_DCC10_DCC_INPUT10_CLK", "Input clock"}, + [817] = {41, 1, "DEV_DCC10_DCC_INPUT01_CLK", "Input clock"}, + [818] = {41, 2, "DEV_DCC10_DCC_CLKSRC2_CLK", "Input clock"}, + [819] = {41, 3, "DEV_DCC10_DCC_CLKSRC7_CLK", "Input clock"}, + [820] = {41, 4, "DEV_DCC10_DCC_CLKSRC0_CLK", "Input clock"}, + [821] = {41, 5, "DEV_DCC10_VBUS_CLK", "Input clock"}, + [822] = {41, 6, "DEV_DCC10_DCC_CLKSRC4_CLK", "Input clock"}, + [823] = {41, 7, "DEV_DCC10_DCC_CLKSRC1_CLK", "Input clock"}, + [824] = {41, 8, "DEV_DCC10_DCC_CLKSRC3_CLK", "Input clock"}, + [825] = {41, 9, "DEV_DCC10_DCC_INPUT00_CLK", "Input clock"}, + [826] = {41, 10, "DEV_DCC10_DCC_CLKSRC5_CLK", "Input clock"}, + [827] = {41, 11, "DEV_DCC10_DCC_CLKSRC6_CLK", "Input clock"}, + [828] = {41, 12, "DEV_DCC10_DCC_INPUT02_CLK", "Input clock"}, + [829] = {42, 0, "DEV_DCC11_DCC_INPUT10_CLK", "Input clock"}, + [830] = {42, 1, "DEV_DCC11_DCC_INPUT01_CLK", "Input clock"}, + [831] = {42, 2, "DEV_DCC11_DCC_CLKSRC2_CLK", "Input clock"}, + [832] = {42, 3, "DEV_DCC11_DCC_CLKSRC7_CLK", "Input clock"}, + [833] = {42, 4, "DEV_DCC11_DCC_CLKSRC0_CLK", "Input clock"}, + [834] = {42, 5, "DEV_DCC11_VBUS_CLK", "Input clock"}, + [835] = {42, 6, "DEV_DCC11_DCC_CLKSRC4_CLK", "Input clock"}, + [836] = {42, 7, "DEV_DCC11_DCC_CLKSRC1_CLK", "Input clock"}, + [837] = {42, 8, "DEV_DCC11_DCC_CLKSRC3_CLK", "Input clock"}, + [838] = {42, 9, "DEV_DCC11_DCC_INPUT00_CLK", "Input clock"}, + [839] = {42, 10, "DEV_DCC11_DCC_CLKSRC5_CLK", "Input clock"}, + [840] = {42, 11, "DEV_DCC11_DCC_CLKSRC6_CLK", "Input clock"}, + [841] = {42, 12, "DEV_DCC11_DCC_INPUT02_CLK", "Input clock"}, + [842] = {43, 0, "DEV_DCC12_DCC_INPUT10_CLK", "Input clock"}, + [843] = {43, 1, "DEV_DCC12_DCC_INPUT01_CLK", "Input clock"}, + [844] = {43, 2, "DEV_DCC12_DCC_CLKSRC2_CLK", "Input clock"}, + [845] = {43, 3, "DEV_DCC12_DCC_CLKSRC7_CLK", "Input clock"}, + [846] = {43, 4, "DEV_DCC12_DCC_CLKSRC0_CLK", "Input clock"}, + [847] = {43, 5, "DEV_DCC12_VBUS_CLK", "Input clock"}, + [848] = {43, 6, "DEV_DCC12_DCC_CLKSRC4_CLK", "Input clock"}, + [849] = {43, 7, "DEV_DCC12_DCC_CLKSRC1_CLK", "Input clock"}, + [850] = {43, 8, "DEV_DCC12_DCC_CLKSRC3_CLK", "Input clock"}, + [851] = {43, 9, "DEV_DCC12_DCC_INPUT00_CLK", "Input clock"}, + [852] = {43, 10, "DEV_DCC12_DCC_CLKSRC5_CLK", "Input clock"}, + [853] = {43, 11, "DEV_DCC12_DCC_CLKSRC6_CLK", "Input clock"}, + [854] = {43, 12, "DEV_DCC12_DCC_INPUT02_CLK", "Input clock"}, + [855] = {32, 0, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"}, + [856] = {32, 1, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"}, + [857] = {32, 2, "DEV_DCC2_DCC_CLKSRC2_CLK", "Input clock"}, + [858] = {32, 3, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"}, + [859] = {32, 4, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"}, + [860] = {32, 5, "DEV_DCC2_VBUS_CLK", "Input clock"}, + [861] = {32, 6, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"}, + [862] = {32, 7, "DEV_DCC2_DCC_CLKSRC1_CLK", "Input clock"}, + [863] = {32, 8, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"}, + [864] = {32, 9, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"}, + [865] = {32, 10, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"}, + [866] = {32, 11, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"}, + [867] = {32, 12, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"}, + [868] = {33, 0, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"}, + [869] = {33, 1, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"}, + [870] = {33, 2, "DEV_DCC3_DCC_CLKSRC2_CLK", "Input clock"}, + [871] = {33, 3, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"}, + [872] = {33, 4, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"}, + [873] = {33, 5, "DEV_DCC3_VBUS_CLK", "Input clock"}, + [874] = {33, 6, "DEV_DCC3_DCC_CLKSRC4_CLK", "Input clock"}, + [875] = {33, 7, "DEV_DCC3_DCC_CLKSRC1_CLK", "Input clock"}, + [876] = {33, 8, "DEV_DCC3_DCC_CLKSRC3_CLK", "Input clock"}, + [877] = {33, 9, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"}, + [878] = {33, 10, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"}, + [879] = {33, 11, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"}, + [880] = {33, 12, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"}, + [881] = {34, 0, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"}, + [882] = {34, 1, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"}, + [883] = {34, 2, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"}, + [884] = {34, 3, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"}, + [885] = {34, 4, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input clock"}, + [886] = {34, 5, "DEV_DCC4_VBUS_CLK", "Input clock"}, + [887] = {34, 6, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"}, + [888] = {34, 7, "DEV_DCC4_DCC_CLKSRC1_CLK", "Input clock"}, + [889] = {34, 8, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"}, + [890] = {34, 9, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"}, + [891] = {34, 10, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"}, + [892] = {34, 11, "DEV_DCC4_DCC_CLKSRC6_CLK", "Input clock"}, + [893] = {34, 12, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"}, + [894] = {36, 0, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"}, + [895] = {36, 1, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"}, + [896] = {36, 2, "DEV_DCC5_DCC_CLKSRC2_CLK", "Input clock"}, + [897] = {36, 3, "DEV_DCC5_DCC_CLKSRC7_CLK", "Input clock"}, + [898] = {36, 4, "DEV_DCC5_DCC_CLKSRC0_CLK", "Input clock"}, + [899] = {36, 5, "DEV_DCC5_VBUS_CLK", "Input clock"}, + [900] = {36, 6, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"}, + [901] = {36, 7, "DEV_DCC5_DCC_CLKSRC1_CLK", "Input clock"}, + [902] = {36, 8, "DEV_DCC5_DCC_CLKSRC3_CLK", "Input clock"}, + [903] = {36, 9, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"}, + [904] = {36, 10, "DEV_DCC5_DCC_CLKSRC5_CLK", "Input clock"}, + [905] = {36, 11, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"}, + [906] = {36, 12, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"}, + [907] = {37, 0, "DEV_DCC6_DCC_INPUT10_CLK", "Input clock"}, + [908] = {37, 1, "DEV_DCC6_DCC_INPUT01_CLK", "Input clock"}, + [909] = {37, 2, "DEV_DCC6_DCC_CLKSRC2_CLK", "Input clock"}, + [910] = {37, 3, "DEV_DCC6_DCC_CLKSRC7_CLK", "Input clock"}, + [911] = {37, 4, "DEV_DCC6_DCC_CLKSRC0_CLK", "Input clock"}, + [912] = {37, 5, "DEV_DCC6_VBUS_CLK", "Input clock"}, + [913] = {37, 6, "DEV_DCC6_DCC_CLKSRC4_CLK", "Input clock"}, + [914] = {37, 7, "DEV_DCC6_DCC_CLKSRC1_CLK", "Input clock"}, + [915] = {37, 8, "DEV_DCC6_DCC_CLKSRC3_CLK", "Input clock"}, + [916] = {37, 9, "DEV_DCC6_DCC_INPUT00_CLK", "Input clock"}, + [917] = {37, 10, "DEV_DCC6_DCC_CLKSRC5_CLK", "Input clock"}, + [918] = {37, 11, "DEV_DCC6_DCC_CLKSRC6_CLK", "Input clock"}, + [919] = {37, 12, "DEV_DCC6_DCC_INPUT02_CLK", "Input clock"}, + [920] = {38, 0, "DEV_DCC7_DCC_INPUT10_CLK", "Input clock"}, + [921] = {38, 1, "DEV_DCC7_DCC_INPUT01_CLK", "Input clock"}, + [922] = {38, 2, "DEV_DCC7_DCC_CLKSRC2_CLK", "Input clock"}, + [923] = {38, 3, "DEV_DCC7_DCC_CLKSRC7_CLK", "Input clock"}, + [924] = {38, 4, "DEV_DCC7_DCC_CLKSRC0_CLK", "Input clock"}, + [925] = {38, 5, "DEV_DCC7_VBUS_CLK", "Input clock"}, + [926] = {38, 6, "DEV_DCC7_DCC_CLKSRC4_CLK", "Input clock"}, + [927] = {38, 7, "DEV_DCC7_DCC_CLKSRC1_CLK", "Input clock"}, + [928] = {38, 8, "DEV_DCC7_DCC_CLKSRC3_CLK", "Input clock"}, + [929] = {38, 9, "DEV_DCC7_DCC_INPUT00_CLK", "Input clock"}, + [930] = {38, 10, "DEV_DCC7_DCC_CLKSRC5_CLK", "Input clock"}, + [931] = {38, 11, "DEV_DCC7_DCC_CLKSRC6_CLK", "Input clock"}, + [932] = {38, 12, "DEV_DCC7_DCC_INPUT02_CLK", "Input clock"}, + [933] = {39, 0, "DEV_DCC8_DCC_INPUT10_CLK", "Input clock"}, + [934] = {39, 1, "DEV_DCC8_DCC_INPUT01_CLK", "Input clock"}, + [935] = {39, 2, "DEV_DCC8_DCC_CLKSRC2_CLK", "Input clock"}, + [936] = {39, 3, "DEV_DCC8_DCC_CLKSRC7_CLK", "Input clock"}, + [937] = {39, 4, "DEV_DCC8_DCC_CLKSRC0_CLK", "Input clock"}, + [938] = {39, 5, "DEV_DCC8_VBUS_CLK", "Input clock"}, + [939] = {39, 6, "DEV_DCC8_DCC_CLKSRC4_CLK", "Input clock"}, + [940] = {39, 7, "DEV_DCC8_DCC_CLKSRC1_CLK", "Input clock"}, + [941] = {39, 8, "DEV_DCC8_DCC_CLKSRC3_CLK", "Input clock"}, + [942] = {39, 9, "DEV_DCC8_DCC_INPUT00_CLK", "Input clock"}, + [943] = {39, 10, "DEV_DCC8_DCC_CLKSRC5_CLK", "Input clock"}, + [944] = {39, 11, "DEV_DCC8_DCC_CLKSRC6_CLK", "Input clock"}, + [945] = {39, 12, "DEV_DCC8_DCC_INPUT02_CLK", "Input clock"}, + [946] = {40, 0, "DEV_DCC9_DCC_INPUT10_CLK", "Input clock"}, + [947] = {40, 1, "DEV_DCC9_DCC_INPUT01_CLK", "Input clock"}, + [948] = {40, 2, "DEV_DCC9_DCC_CLKSRC2_CLK", "Input clock"}, + [949] = {40, 3, "DEV_DCC9_DCC_CLKSRC7_CLK", "Input clock"}, + [950] = {40, 4, "DEV_DCC9_DCC_CLKSRC0_CLK", "Input clock"}, + [951] = {40, 5, "DEV_DCC9_VBUS_CLK", "Input clock"}, + [952] = {40, 6, "DEV_DCC9_DCC_CLKSRC4_CLK", "Input clock"}, + [953] = {40, 7, "DEV_DCC9_DCC_CLKSRC1_CLK", "Input clock"}, + [954] = {40, 8, "DEV_DCC9_DCC_CLKSRC3_CLK", "Input clock"}, + [955] = {40, 9, "DEV_DCC9_DCC_INPUT00_CLK", "Input clock"}, + [956] = {40, 10, "DEV_DCC9_DCC_CLKSRC5_CLK", "Input clock"}, + [957] = {40, 11, "DEV_DCC9_DCC_CLKSRC6_CLK", "Input clock"}, + [958] = {40, 12, "DEV_DCC9_DCC_INPUT02_CLK", "Input clock"}, + [959] = {47, 0, "DEV_DDR0_DDRSS_VBUS_CLK", "Input clock"}, + [960] = {47, 1, "DEV_DDR0_PLL_CTRL_CLK", "Input clock"}, + [961] = {47, 2, "DEV_DDR0_DDRSS_DDR_PLL_CLK", "Input clock"}, + [962] = {47, 3, "DEV_DDR0_DDRSS_CFG_CLK", "Input clock"}, + [963] = {47, 4, "DEV_DDR0_DDRSS_IO_CK_N", "Output clock"}, + [964] = {47, 5, "DEV_DDR0_DDRSS_IO_CK", "Output clock"}, + [965] = {304, 5, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"}, + [966] = {304, 9, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"}, + [967] = {304, 25, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"}, + [968] = {304, 32, "DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK", "Output clock"}, + [969] = {304, 35, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"}, + [970] = {144, 0, "DEV_DECODER0_SYS_CLK", "Input clock"}, + [971] = {48, 0, "DEV_DMPAC0_CLK", "Input clock"}, + [972] = {48, 1, "DEV_DMPAC0_PLL_DCO_CLK", "Input clock"}, + [973] = {305, 0, "DEV_DMPAC0_SDE_0_CLK", "Input clock"}, + [974] = {147, 0, "DEV_DPHY_RX0_MAIN_CLK_CLK", "Input clock"}, + [975] = {147, 1, "DEV_DPHY_RX0_PPI_RX_BYTE_CLK", "Output clock"}, + [976] = {148, 0, "DEV_DPHY_RX1_MAIN_CLK_CLK", "Input clock"}, + [977] = {148, 1, "DEV_DPHY_RX1_PPI_RX_BYTE_CLK", "Output clock"}, + [978] = {296, 0, "DEV_DPHY_TX0_CLK", "Input clock"}, + [979] = {296, 1, "DEV_DPHY_TX0_PSM_CLK", "Input clock"}, + [980] = {296, 2, "DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK", "Input clock"}, + [981] = {296, 3, "DEV_DPHY_TX0_DPHY_REF_CLK", "Input muxed clock"}, + [982] = {296, 4, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, + [983] = {296, 5, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, + [984] = {296, 6, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, + [985] = {296, 7, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, + [986] = {296, 8, "DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK", "Output clock"}, + [987] = {296, 9, "DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK", "Output clock"}, + [988] = {296, 10, "DEV_DPHY_TX0_CK_P", "Output clock"}, + [989] = {296, 11, "DEV_DPHY_TX0_CK_M", "Output clock"}, + [990] = {296, 12, "DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK", "Output clock"}, + [991] = {152, 0, "DEV_DSS0_DSS_FUNC_CLK", "Input clock"}, + [992] = {152, 1, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK", "Input muxed clock"}, + [993] = {152, 2, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"}, + [994] = {152, 3, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"}, + [995] = {152, 4, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK", "Input muxed clock"}, + [996] = {152, 5, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, + [997] = {152, 6, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, + [998] = {152, 7, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, + [999] = {152, 8, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, + [1000] = {152, 9, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK", "Input muxed clock"}, + [1001] = {152, 10, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"}, + [1002] = {152, 11, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"}, + [1003] = {152, 12, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"}, + [1004] = {152, 13, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK", "Input muxed clock"}, + [1005] = {152, 14, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, + [1006] = {152, 15, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, + [1007] = {152, 16, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, + [1008] = {152, 17, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, + [1009] = {152, 18, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, + [1010] = {152, 23, "DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK", "Output clock"}, + [1011] = {152, 24, "DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK", "Output clock"}, + [1012] = {152, 25, "DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK", "Output clock"}, + [1013] = {152, 27, "DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK", "Output clock"}, + [1014] = {152, 29, "DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK", "Output clock"}, + [1015] = {152, 31, "DEV_DSS0_DPI0_EXT_CLKSEL", "Input muxed clock"}, + [1016] = {152, 32, "DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL"}, + [1017] = {152, 33, "DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_BOARD_0_VOUT1_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL"}, + [1018] = {152, 34, "DEV_DSS0_DPI1_EXT_CLKSEL", "Input muxed clock"}, + [1019] = {152, 35, "DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL"}, + [1020] = {152, 36, "DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_BOARD_0_VOUT2_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL"}, + [1021] = {150, 0, "DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK", "Input clock"}, + [1022] = {150, 1, "DEV_DSS_DSI0_DPI_0_CLK", "Input clock"}, + [1023] = {150, 2, "DEV_DSS_DSI0_PLL_CTRL_CLK", "Input clock"}, + [1024] = {150, 3, "DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK", "Input clock"}, + [1025] = {150, 4, "DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK", "Input clock"}, + [1026] = {150, 5, "DEV_DSS_DSI0_SYS_CLK", "Input clock"}, + [1027] = {151, 0, "DEV_DSS_EDP0_PHY_LN1_TXFCLK", "Input clock"}, + [1028] = {151, 1, "DEV_DSS_EDP0_DPI_2_CLK", "Input clock"}, + [1029] = {151, 2, "DEV_DSS_EDP0_PHY_LN2_TXFCLK", "Input clock"}, + [1030] = {151, 3, "DEV_DSS_EDP0_PHY_LN0_RXCLK", "Input clock"}, + [1031] = {151, 4, "DEV_DSS_EDP0_PHY_LN2_TXMCLK", "Input clock"}, + [1032] = {151, 5, "DEV_DSS_EDP0_PHY_LN0_RXFCLK", "Input clock"}, + [1033] = {151, 6, "DEV_DSS_EDP0_PHY_LN0_REFCLK", "Input clock"}, + [1034] = {151, 7, "DEV_DSS_EDP0_PHY_LN1_RXCLK", "Input clock"}, + [1035] = {151, 8, "DEV_DSS_EDP0_PHY_LN2_RXFCLK", "Input clock"}, + [1036] = {151, 9, "DEV_DSS_EDP0_DPI_4_CLK", "Input clock"}, + [1037] = {151, 10, "DEV_DSS_EDP0_DPI_2_2X_CLK", "Input clock"}, + [1038] = {151, 11, "DEV_DSS_EDP0_PHY_LN0_TXFCLK", "Input clock"}, + [1039] = {151, 12, "DEV_DSS_EDP0_PHY_LN2_RXCLK", "Input clock"}, + [1040] = {151, 13, "DEV_DSS_EDP0_PHY_LN2_REFCLK", "Input clock"}, + [1041] = {151, 14, "DEV_DSS_EDP0_PHY_LN3_REFCLK", "Input clock"}, + [1042] = {151, 15, "DEV_DSS_EDP0_DPI_5_CLK", "Input clock"}, + [1043] = {151, 16, "DEV_DSS_EDP0_PHY_LN3_RXCLK", "Input clock"}, + [1044] = {151, 17, "DEV_DSS_EDP0_PHY_LN1_REFCLK", "Input clock"}, + [1045] = {151, 18, "DEV_DSS_EDP0_AIF_I2S_CLK", "Input clock"}, + [1046] = {151, 19, "DEV_DSS_EDP0_PHY_LN3_TXFCLK", "Input clock"}, + [1047] = {151, 20, "DEV_DSS_EDP0_DPI_3_CLK", "Input clock"}, + [1048] = {151, 21, "DEV_DSS_EDP0_PHY_LN1_RXFCLK", "Input clock"}, + [1049] = {151, 22, "DEV_DSS_EDP0_PHY_LN1_TXMCLK", "Input clock"}, + [1050] = {151, 23, "DEV_DSS_EDP0_PLL_CTRL_CLK", "Input clock"}, + [1051] = {151, 24, "DEV_DSS_EDP0_PHY_LN3_TXMCLK", "Input clock"}, + [1052] = {151, 25, "DEV_DSS_EDP0_PHY_LN3_RXFCLK", "Input clock"}, + [1053] = {151, 26, "DEV_DSS_EDP0_PHY_LN0_TXMCLK", "Input clock"}, + [1054] = {151, 27, "DEV_DSS_EDP0_PHY_LN2_TXCLK", "Output clock"}, + [1055] = {151, 28, "DEV_DSS_EDP0_PHY_LN3_TXCLK", "Output clock"}, + [1056] = {151, 29, "DEV_DSS_EDP0_PHY_LN0_TXCLK", "Output clock"}, + [1057] = {151, 30, "DEV_DSS_EDP0_PHY_LN1_TXCLK", "Output clock"}, + [1058] = {151, 36, "DEV_DSS_EDP0_DPTX_MOD_CLK", "Input clock"}, + [1059] = {80, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"}, + [1060] = {81, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"}, + [1061] = {82, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"}, + [1062] = {83, 0, "DEV_EHRPWM0_VBUSP_CLK", "Input clock"}, + [1063] = {84, 0, "DEV_EHRPWM1_VBUSP_CLK", "Input clock"}, + [1064] = {85, 0, "DEV_EHRPWM2_VBUSP_CLK", "Input clock"}, + [1065] = {86, 0, "DEV_EHRPWM3_VBUSP_CLK", "Input clock"}, + [1066] = {87, 0, "DEV_EHRPWM4_VBUSP_CLK", "Input clock"}, + [1067] = {88, 0, "DEV_EHRPWM5_VBUSP_CLK", "Input clock"}, + [1068] = {89, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"}, + [1069] = {153, 0, "DEV_ENCODER0_SYS_CLK", "Input clock"}, + [1070] = {94, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"}, + [1071] = {95, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"}, + [1072] = {96, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"}, + [1073] = {97, 0, "DEV_ESM0_CLK", "Input clock"}, + [1074] = {105, 0, "DEV_GPIO0_MMR_CLK", "Input clock"}, + [1075] = {106, 0, "DEV_GPIO1_MMR_CLK", "Input clock"}, + [1076] = {107, 0, "DEV_GPIO2_MMR_CLK", "Input clock"}, + [1077] = {108, 0, "DEV_GPIO3_MMR_CLK", "Input clock"}, + [1078] = {109, 0, "DEV_GPIO4_MMR_CLK", "Input clock"}, + [1079] = {110, 0, "DEV_GPIO5_MMR_CLK", "Input clock"}, + [1080] = {111, 0, "DEV_GPIO6_MMR_CLK", "Input clock"}, + [1081] = {112, 0, "DEV_GPIO7_MMR_CLK", "Input clock"}, + [1082] = {131, 0, "DEV_GPIOMUX_INTRTR0_INTR_CLK", "Input clock"}, + [1083] = {115, 0, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"}, + [1084] = {115, 1, "DEV_GPMC0_VBUSP_CLK", "Input clock"}, + [1085] = {115, 2, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"}, + [1086] = {115, 3, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, + [1087] = {115, 4, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, + [1088] = {115, 5, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, + [1089] = {115, 6, "DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, + [1090] = {115, 7, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"}, + [1091] = {125, 0, "DEV_GPU0_GPU_0_GPU_PLL_CLK", "Input clock"}, + [1092] = {61, 0, "DEV_GTC0_VBUSP_CLK", "Input clock"}, + [1093] = {61, 1, "DEV_GTC0_GTC_CLK", "Input muxed clock"}, + [1094] = {61, 2, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [1095] = {61, 3, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [1096] = {61, 4, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [1097] = {61, 5, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [1098] = {61, 6, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [1099] = {61, 7, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [1100] = {61, 8, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [1101] = {61, 9, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [1102] = {61, 10, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [1103] = {61, 11, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [1104] = {61, 12, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [1105] = {61, 13, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [1106] = {61, 14, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [1107] = {61, 15, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [1108] = {61, 16, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [1109] = {61, 17, "DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, + [1110] = {187, 0, "DEV_I2C0_PISYS_CLK", "Input clock"}, + [1111] = {187, 1, "DEV_I2C0_PISCL", "Input clock"}, + [1112] = {187, 2, "DEV_I2C0_CLK", "Input clock"}, + [1113] = {188, 0, "DEV_I2C1_PISYS_CLK", "Input clock"}, + [1114] = {188, 1, "DEV_I2C1_PISCL", "Input clock"}, + [1115] = {188, 2, "DEV_I2C1_CLK", "Input clock"}, + [1116] = {189, 0, "DEV_I2C2_PISYS_CLK", "Input clock"}, + [1117] = {189, 1, "DEV_I2C2_PISCL", "Input clock"}, + [1118] = {189, 2, "DEV_I2C2_CLK", "Input clock"}, + [1119] = {190, 0, "DEV_I2C3_PISYS_CLK", "Input clock"}, + [1120] = {190, 1, "DEV_I2C3_PISCL", "Input clock"}, + [1121] = {190, 2, "DEV_I2C3_CLK", "Input clock"}, + [1122] = {191, 0, "DEV_I2C4_PISYS_CLK", "Input clock"}, + [1123] = {191, 1, "DEV_I2C4_PISCL", "Input clock"}, + [1124] = {191, 2, "DEV_I2C4_CLK", "Input clock"}, + [1125] = {192, 0, "DEV_I2C5_PISYS_CLK", "Input clock"}, + [1126] = {192, 1, "DEV_I2C5_PISCL", "Input clock"}, + [1127] = {192, 2, "DEV_I2C5_CLK", "Input clock"}, + [1128] = {193, 0, "DEV_I2C6_PISYS_CLK", "Input clock"}, + [1129] = {193, 1, "DEV_I2C6_PISCL", "Input clock"}, + [1130] = {193, 2, "DEV_I2C6_CLK", "Input clock"}, + [1131] = {116, 0, "DEV_I3C0_I3C_PCLK_CLK", "Input clock"}, + [1132] = {116, 1, "DEV_I3C0_I3C_SCL_DI", "Input clock"}, + [1133] = {116, 2, "DEV_I3C0_I3C_SCLK_CLK", "Input clock"}, + [1134] = {116, 3, "DEV_I3C0_I3C_SCL_DO", "Output clock"}, + [1135] = {127, 0, "DEV_LED0_LED_CLK", "Input clock"}, + [1136] = {127, 1, "DEV_LED0_VBUS_CLK", "Input clock"}, + [1137] = {128, 0, "DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK", "Input clock"}, + [1138] = {130, 0, "DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK", "Input clock"}, + [1139] = {156, 0, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, + [1140] = {156, 1, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, + [1141] = {156, 2, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, + [1142] = {156, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, + [1143] = {156, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, + [1144] = {156, 5, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, + [1145] = {158, 0, "DEV_MCAN1_MCANSS_HCLK_CLK", "Input clock"}, + [1146] = {158, 1, "DEV_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"}, + [1147] = {158, 2, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, + [1148] = {158, 3, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, + [1149] = {158, 4, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, + [1150] = {158, 5, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, + [1151] = {168, 0, "DEV_MCAN10_MCANSS_HCLK_CLK", "Input clock"}, + [1152] = {168, 1, "DEV_MCAN10_MCANSS_CCLK_CLK", "Input muxed clock"}, + [1153] = {168, 2, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, + [1154] = {168, 3, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, + [1155] = {168, 4, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, + [1156] = {168, 5, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, + [1157] = {169, 0, "DEV_MCAN11_MCANSS_HCLK_CLK", "Input clock"}, + [1158] = {169, 1, "DEV_MCAN11_MCANSS_CCLK_CLK", "Input muxed clock"}, + [1159] = {169, 2, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, + [1160] = {169, 3, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, + [1161] = {169, 4, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, + [1162] = {169, 5, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, + [1163] = {170, 0, "DEV_MCAN12_MCANSS_HCLK_CLK", "Input clock"}, + [1164] = {170, 1, "DEV_MCAN12_MCANSS_CCLK_CLK", "Input muxed clock"}, + [1165] = {170, 2, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, + [1166] = {170, 3, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, + [1167] = {170, 4, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, + [1168] = {170, 5, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, + [1169] = {171, 0, "DEV_MCAN13_MCANSS_HCLK_CLK", "Input clock"}, + [1170] = {171, 1, "DEV_MCAN13_MCANSS_CCLK_CLK", "Input muxed clock"}, + [1171] = {171, 2, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, + [1172] = {171, 3, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, + [1173] = {171, 4, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, + [1174] = {171, 5, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, + [1175] = {160, 0, "DEV_MCAN2_MCANSS_HCLK_CLK", "Input clock"}, + [1176] = {160, 1, "DEV_MCAN2_MCANSS_CCLK_CLK", "Input muxed clock"}, + [1177] = {160, 2, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, + [1178] = {160, 3, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, + [1179] = {160, 4, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, + [1180] = {160, 5, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, + [1181] = {161, 0, "DEV_MCAN3_MCANSS_HCLK_CLK", "Input clock"}, + [1182] = {161, 1, "DEV_MCAN3_MCANSS_CCLK_CLK", "Input muxed clock"}, + [1183] = {161, 2, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, + [1184] = {161, 3, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, + [1185] = {161, 4, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, + [1186] = {161, 5, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, + [1187] = {162, 0, "DEV_MCAN4_MCANSS_HCLK_CLK", "Input clock"}, + [1188] = {162, 1, "DEV_MCAN4_MCANSS_CCLK_CLK", "Input muxed clock"}, + [1189] = {162, 2, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, + [1190] = {162, 3, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, + [1191] = {162, 4, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, + [1192] = {162, 5, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, + [1193] = {163, 0, "DEV_MCAN5_MCANSS_HCLK_CLK", "Input clock"}, + [1194] = {163, 1, "DEV_MCAN5_MCANSS_CCLK_CLK", "Input muxed clock"}, + [1195] = {163, 2, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, + [1196] = {163, 3, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, + [1197] = {163, 4, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, + [1198] = {163, 5, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, + [1199] = {164, 0, "DEV_MCAN6_MCANSS_HCLK_CLK", "Input clock"}, + [1200] = {164, 1, "DEV_MCAN6_MCANSS_CCLK_CLK", "Input muxed clock"}, + [1201] = {164, 2, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, + [1202] = {164, 3, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, + [1203] = {164, 4, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, + [1204] = {164, 5, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, + [1205] = {165, 0, "DEV_MCAN7_MCANSS_HCLK_CLK", "Input clock"}, + [1206] = {165, 1, "DEV_MCAN7_MCANSS_CCLK_CLK", "Input muxed clock"}, + [1207] = {165, 2, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, + [1208] = {165, 3, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, + [1209] = {165, 4, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, + [1210] = {165, 5, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, + [1211] = {166, 0, "DEV_MCAN8_MCANSS_HCLK_CLK", "Input clock"}, + [1212] = {166, 1, "DEV_MCAN8_MCANSS_CCLK_CLK", "Input muxed clock"}, + [1213] = {166, 2, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, + [1214] = {166, 3, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, + [1215] = {166, 4, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, + [1216] = {166, 5, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, + [1217] = {167, 0, "DEV_MCAN9_MCANSS_HCLK_CLK", "Input clock"}, + [1218] = {167, 1, "DEV_MCAN9_MCANSS_CCLK_CLK", "Input muxed clock"}, + [1219] = {167, 2, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, + [1220] = {167, 3, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, + [1221] = {167, 4, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, + [1222] = {167, 5, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, + [1223] = {174, 0, "DEV_MCASP0_VBUSP_CLK", "Input clock"}, + [1224] = {174, 1, "DEV_MCASP0_AUX_CLK", "Input muxed clock"}, + [1225] = {174, 2, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, + [1226] = {174, 3, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, + [1227] = {174, 4, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, + [1228] = {174, 6, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, + [1229] = {174, 7, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, + [1230] = {174, 8, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, + [1231] = {174, 9, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, + [1232] = {174, 10, "DEV_MCASP0_MCASP_ACLKX_POUT", "Output clock"}, + [1233] = {174, 11, "DEV_MCASP0_MCASP_ACLKX_PIN", "Input clock"}, + [1234] = {174, 12, "DEV_MCASP0_MCASP_ACLKR_POUT", "Output clock"}, + [1235] = {174, 13, "DEV_MCASP0_MCASP_ACLKR_PIN", "Input clock"}, + [1236] = {174, 14, "DEV_MCASP0_MCASP_AHCLKX_POUT", "Output clock"}, + [1237] = {174, 15, "DEV_MCASP0_MCASP_AHCLKX_PIN", "Input muxed clock"}, + [1238] = {174, 16, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, + [1239] = {174, 17, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, + [1240] = {174, 18, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, + [1241] = {174, 19, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, + [1242] = {174, 20, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, + [1243] = {174, 21, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, + [1244] = {174, 22, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, + [1245] = {174, 23, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, + [1246] = {174, 24, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, + [1247] = {174, 25, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, + [1248] = {174, 26, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, + [1249] = {174, 27, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, + [1250] = {174, 28, "DEV_MCASP0_MCASP_AHCLKR_POUT", "Output clock"}, + [1251] = {174, 29, "DEV_MCASP0_MCASP_AHCLKR_PIN", "Input muxed clock"}, + [1252] = {174, 30, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, + [1253] = {174, 31, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, + [1254] = {174, 32, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, + [1255] = {174, 33, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, + [1256] = {174, 34, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, + [1257] = {174, 35, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, + [1258] = {174, 36, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, + [1259] = {174, 37, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, + [1260] = {174, 38, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, + [1261] = {174, 39, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, + [1262] = {174, 40, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, + [1263] = {174, 41, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, + [1264] = {175, 0, "DEV_MCASP1_VBUSP_CLK", "Input clock"}, + [1265] = {175, 1, "DEV_MCASP1_AUX_CLK", "Input muxed clock"}, + [1266] = {175, 2, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, + [1267] = {175, 3, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, + [1268] = {175, 4, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, + [1269] = {175, 6, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, + [1270] = {175, 7, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, + [1271] = {175, 8, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, + [1272] = {175, 9, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, + [1273] = {175, 10, "DEV_MCASP1_MCASP_ACLKX_POUT", "Output clock"}, + [1274] = {175, 11, "DEV_MCASP1_MCASP_ACLKX_PIN", "Input clock"}, + [1275] = {175, 12, "DEV_MCASP1_MCASP_ACLKR_POUT", "Output clock"}, + [1276] = {175, 13, "DEV_MCASP1_MCASP_ACLKR_PIN", "Input clock"}, + [1277] = {175, 14, "DEV_MCASP1_MCASP_AHCLKX_POUT", "Output clock"}, + [1278] = {175, 15, "DEV_MCASP1_MCASP_AHCLKX_PIN", "Input muxed clock"}, + [1279] = {175, 16, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, + [1280] = {175, 17, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, + [1281] = {175, 18, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, + [1282] = {175, 19, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, + [1283] = {175, 20, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, + [1284] = {175, 21, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, + [1285] = {175, 22, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, + [1286] = {175, 23, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, + [1287] = {175, 24, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, + [1288] = {175, 25, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, + [1289] = {175, 26, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, + [1290] = {175, 27, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, + [1291] = {175, 28, "DEV_MCASP1_MCASP_AHCLKR_POUT", "Output clock"}, + [1292] = {175, 29, "DEV_MCASP1_MCASP_AHCLKR_PIN", "Input muxed clock"}, + [1293] = {175, 30, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, + [1294] = {175, 31, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, + [1295] = {175, 32, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, + [1296] = {175, 33, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, + [1297] = {175, 34, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, + [1298] = {175, 35, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, + [1299] = {175, 36, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, + [1300] = {175, 37, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, + [1301] = {175, 38, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, + [1302] = {175, 39, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, + [1303] = {175, 40, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, + [1304] = {175, 41, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, + [1305] = {184, 0, "DEV_MCASP10_VBUSP_CLK", "Input clock"}, + [1306] = {184, 1, "DEV_MCASP10_AUX_CLK", "Input muxed clock"}, + [1307] = {184, 2, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, + [1308] = {184, 3, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, + [1309] = {184, 4, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, + [1310] = {184, 6, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, + [1311] = {184, 7, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, + [1312] = {184, 8, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, + [1313] = {184, 9, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, + [1314] = {184, 10, "DEV_MCASP10_MCASP_ACLKX_POUT", "Output clock"}, + [1315] = {184, 11, "DEV_MCASP10_MCASP_ACLKX_PIN", "Input clock"}, + [1316] = {184, 12, "DEV_MCASP10_MCASP_ACLKR_POUT", "Output clock"}, + [1317] = {184, 13, "DEV_MCASP10_MCASP_ACLKR_PIN", "Input clock"}, + [1318] = {184, 14, "DEV_MCASP10_MCASP_AHCLKX_POUT", "Output clock"}, + [1319] = {184, 15, "DEV_MCASP10_MCASP_AHCLKX_PIN", "Input muxed clock"}, + [1320] = {184, 16, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, + [1321] = {184, 17, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, + [1322] = {184, 18, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, + [1323] = {184, 19, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, + [1324] = {184, 20, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, + [1325] = {184, 21, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, + [1326] = {184, 22, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, + [1327] = {184, 23, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, + [1328] = {184, 24, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, + [1329] = {184, 25, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, + [1330] = {184, 26, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, + [1331] = {184, 27, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, + [1332] = {184, 28, "DEV_MCASP10_MCASP_AHCLKR_POUT", "Output clock"}, + [1333] = {184, 29, "DEV_MCASP10_MCASP_AHCLKR_PIN", "Input muxed clock"}, + [1334] = {184, 30, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, + [1335] = {184, 31, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, + [1336] = {184, 32, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, + [1337] = {184, 33, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, + [1338] = {184, 34, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, + [1339] = {184, 35, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, + [1340] = {184, 36, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, + [1341] = {184, 37, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, + [1342] = {184, 38, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, + [1343] = {184, 39, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, + [1344] = {184, 40, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, + [1345] = {184, 41, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, + [1346] = {185, 0, "DEV_MCASP11_VBUSP_CLK", "Input clock"}, + [1347] = {185, 1, "DEV_MCASP11_AUX_CLK", "Input muxed clock"}, + [1348] = {185, 2, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, + [1349] = {185, 3, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, + [1350] = {185, 4, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, + [1351] = {185, 6, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, + [1352] = {185, 7, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, + [1353] = {185, 8, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, + [1354] = {185, 9, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, + [1355] = {185, 10, "DEV_MCASP11_MCASP_ACLKX_POUT", "Output clock"}, + [1356] = {185, 11, "DEV_MCASP11_MCASP_ACLKX_PIN", "Input clock"}, + [1357] = {185, 12, "DEV_MCASP11_MCASP_ACLKR_POUT", "Output clock"}, + [1358] = {185, 13, "DEV_MCASP11_MCASP_ACLKR_PIN", "Input clock"}, + [1359] = {185, 14, "DEV_MCASP11_MCASP_AHCLKX_POUT", "Output clock"}, + [1360] = {185, 15, "DEV_MCASP11_MCASP_AHCLKX_PIN", "Input muxed clock"}, + [1361] = {185, 16, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, + [1362] = {185, 17, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, + [1363] = {185, 18, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, + [1364] = {185, 19, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, + [1365] = {185, 20, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, + [1366] = {185, 21, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, + [1367] = {185, 22, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, + [1368] = {185, 23, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, + [1369] = {185, 24, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, + [1370] = {185, 25, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, + [1371] = {185, 26, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, + [1372] = {185, 27, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, + [1373] = {185, 28, "DEV_MCASP11_MCASP_AHCLKR_POUT", "Output clock"}, + [1374] = {185, 29, "DEV_MCASP11_MCASP_AHCLKR_PIN", "Input muxed clock"}, + [1375] = {185, 30, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, + [1376] = {185, 31, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, + [1377] = {185, 32, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, + [1378] = {185, 33, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, + [1379] = {185, 34, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, + [1380] = {185, 35, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, + [1381] = {185, 36, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, + [1382] = {185, 37, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, + [1383] = {185, 38, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, + [1384] = {185, 39, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, + [1385] = {185, 40, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, + [1386] = {185, 41, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, + [1387] = {176, 0, "DEV_MCASP2_VBUSP_CLK", "Input clock"}, + [1388] = {176, 1, "DEV_MCASP2_AUX_CLK", "Input muxed clock"}, + [1389] = {176, 2, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, + [1390] = {176, 3, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, + [1391] = {176, 4, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, + [1392] = {176, 6, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, + [1393] = {176, 7, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, + [1394] = {176, 8, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, + [1395] = {176, 9, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, + [1396] = {176, 10, "DEV_MCASP2_MCASP_ACLKX_POUT", "Output clock"}, + [1397] = {176, 11, "DEV_MCASP2_MCASP_ACLKX_PIN", "Input clock"}, + [1398] = {176, 12, "DEV_MCASP2_MCASP_ACLKR_POUT", "Output clock"}, + [1399] = {176, 13, "DEV_MCASP2_MCASP_ACLKR_PIN", "Input clock"}, + [1400] = {176, 14, "DEV_MCASP2_MCASP_AHCLKX_POUT", "Output clock"}, + [1401] = {176, 15, "DEV_MCASP2_MCASP_AHCLKX_PIN", "Input muxed clock"}, + [1402] = {176, 16, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, + [1403] = {176, 17, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, + [1404] = {176, 18, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, + [1405] = {176, 19, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, + [1406] = {176, 20, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, + [1407] = {176, 21, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, + [1408] = {176, 22, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, + [1409] = {176, 23, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, + [1410] = {176, 24, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, + [1411] = {176, 25, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, + [1412] = {176, 26, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, + [1413] = {176, 27, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, + [1414] = {176, 28, "DEV_MCASP2_MCASP_AHCLKR_POUT", "Output clock"}, + [1415] = {176, 29, "DEV_MCASP2_MCASP_AHCLKR_PIN", "Input muxed clock"}, + [1416] = {176, 30, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, + [1417] = {176, 31, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, + [1418] = {176, 32, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, + [1419] = {176, 33, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, + [1420] = {176, 34, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, + [1421] = {176, 35, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, + [1422] = {176, 36, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, + [1423] = {176, 37, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, + [1424] = {176, 38, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, + [1425] = {176, 39, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, + [1426] = {176, 40, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, + [1427] = {176, 41, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, + [1428] = {177, 0, "DEV_MCASP3_VBUSP_CLK", "Input clock"}, + [1429] = {177, 1, "DEV_MCASP3_AUX_CLK", "Input muxed clock"}, + [1430] = {177, 2, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, + [1431] = {177, 3, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, + [1432] = {177, 4, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, + [1433] = {177, 6, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, + [1434] = {177, 7, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, + [1435] = {177, 8, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, + [1436] = {177, 9, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, + [1437] = {177, 10, "DEV_MCASP3_MCASP_ACLKX_POUT", "Output clock"}, + [1438] = {177, 11, "DEV_MCASP3_MCASP_ACLKX_PIN", "Input clock"}, + [1439] = {177, 12, "DEV_MCASP3_MCASP_ACLKR_POUT", "Output clock"}, + [1440] = {177, 13, "DEV_MCASP3_MCASP_ACLKR_PIN", "Input clock"}, + [1441] = {177, 14, "DEV_MCASP3_MCASP_AHCLKX_POUT", "Output clock"}, + [1442] = {177, 15, "DEV_MCASP3_MCASP_AHCLKX_PIN", "Input muxed clock"}, + [1443] = {177, 16, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, + [1444] = {177, 17, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, + [1445] = {177, 18, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, + [1446] = {177, 19, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, + [1447] = {177, 20, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, + [1448] = {177, 21, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, + [1449] = {177, 22, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, + [1450] = {177, 23, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, + [1451] = {177, 24, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, + [1452] = {177, 25, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, + [1453] = {177, 26, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, + [1454] = {177, 27, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, + [1455] = {177, 28, "DEV_MCASP3_MCASP_AHCLKR_POUT", "Output clock"}, + [1456] = {177, 29, "DEV_MCASP3_MCASP_AHCLKR_PIN", "Input muxed clock"}, + [1457] = {177, 30, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, + [1458] = {177, 31, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, + [1459] = {177, 32, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, + [1460] = {177, 33, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, + [1461] = {177, 34, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, + [1462] = {177, 35, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, + [1463] = {177, 36, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, + [1464] = {177, 37, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, + [1465] = {177, 38, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, + [1466] = {177, 39, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, + [1467] = {177, 40, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, + [1468] = {177, 41, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, + [1469] = {178, 0, "DEV_MCASP4_VBUSP_CLK", "Input clock"}, + [1470] = {178, 1, "DEV_MCASP4_AUX_CLK", "Input muxed clock"}, + [1471] = {178, 2, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, + [1472] = {178, 3, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, + [1473] = {178, 4, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, + [1474] = {178, 6, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, + [1475] = {178, 7, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, + [1476] = {178, 8, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, + [1477] = {178, 9, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, + [1478] = {178, 10, "DEV_MCASP4_MCASP_ACLKX_POUT", "Output clock"}, + [1479] = {178, 11, "DEV_MCASP4_MCASP_ACLKX_PIN", "Input clock"}, + [1480] = {178, 12, "DEV_MCASP4_MCASP_ACLKR_POUT", "Output clock"}, + [1481] = {178, 13, "DEV_MCASP4_MCASP_ACLKR_PIN", "Input clock"}, + [1482] = {178, 14, "DEV_MCASP4_MCASP_AHCLKX_POUT", "Output clock"}, + [1483] = {178, 15, "DEV_MCASP4_MCASP_AHCLKX_PIN", "Input muxed clock"}, + [1484] = {178, 16, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, + [1485] = {178, 17, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, + [1486] = {178, 18, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, + [1487] = {178, 19, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, + [1488] = {178, 20, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, + [1489] = {178, 21, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, + [1490] = {178, 22, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, + [1491] = {178, 23, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, + [1492] = {178, 24, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, + [1493] = {178, 25, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, + [1494] = {178, 26, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, + [1495] = {178, 27, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, + [1496] = {178, 28, "DEV_MCASP4_MCASP_AHCLKR_POUT", "Output clock"}, + [1497] = {178, 29, "DEV_MCASP4_MCASP_AHCLKR_PIN", "Input muxed clock"}, + [1498] = {178, 30, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, + [1499] = {178, 31, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, + [1500] = {178, 32, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, + [1501] = {178, 33, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, + [1502] = {178, 34, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, + [1503] = {178, 35, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, + [1504] = {178, 36, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, + [1505] = {178, 37, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, + [1506] = {178, 38, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, + [1507] = {178, 39, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, + [1508] = {178, 40, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, + [1509] = {178, 41, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, + [1510] = {179, 0, "DEV_MCASP5_VBUSP_CLK", "Input clock"}, + [1511] = {179, 1, "DEV_MCASP5_AUX_CLK", "Input muxed clock"}, + [1512] = {179, 2, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, + [1513] = {179, 3, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, + [1514] = {179, 4, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, + [1515] = {179, 6, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, + [1516] = {179, 7, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, + [1517] = {179, 8, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, + [1518] = {179, 9, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, + [1519] = {179, 10, "DEV_MCASP5_MCASP_ACLKX_POUT", "Output clock"}, + [1520] = {179, 11, "DEV_MCASP5_MCASP_ACLKX_PIN", "Input clock"}, + [1521] = {179, 12, "DEV_MCASP5_MCASP_ACLKR_POUT", "Output clock"}, + [1522] = {179, 13, "DEV_MCASP5_MCASP_ACLKR_PIN", "Input clock"}, + [1523] = {179, 14, "DEV_MCASP5_MCASP_AHCLKX_POUT", "Output clock"}, + [1524] = {179, 15, "DEV_MCASP5_MCASP_AHCLKX_PIN", "Input muxed clock"}, + [1525] = {179, 16, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, + [1526] = {179, 17, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, + [1527] = {179, 18, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, + [1528] = {179, 19, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, + [1529] = {179, 20, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, + [1530] = {179, 21, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, + [1531] = {179, 22, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, + [1532] = {179, 23, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, + [1533] = {179, 24, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, + [1534] = {179, 25, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, + [1535] = {179, 26, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, + [1536] = {179, 27, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, + [1537] = {179, 28, "DEV_MCASP5_MCASP_AHCLKR_POUT", "Output clock"}, + [1538] = {179, 29, "DEV_MCASP5_MCASP_AHCLKR_PIN", "Input muxed clock"}, + [1539] = {179, 30, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, + [1540] = {179, 31, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, + [1541] = {179, 32, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, + [1542] = {179, 33, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, + [1543] = {179, 34, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, + [1544] = {179, 35, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, + [1545] = {179, 36, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, + [1546] = {179, 37, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, + [1547] = {179, 38, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, + [1548] = {179, 39, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, + [1549] = {179, 40, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, + [1550] = {179, 41, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, + [1551] = {180, 0, "DEV_MCASP6_VBUSP_CLK", "Input clock"}, + [1552] = {180, 1, "DEV_MCASP6_AUX_CLK", "Input muxed clock"}, + [1553] = {180, 2, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, + [1554] = {180, 3, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, + [1555] = {180, 4, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, + [1556] = {180, 6, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, + [1557] = {180, 7, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, + [1558] = {180, 8, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, + [1559] = {180, 9, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, + [1560] = {180, 10, "DEV_MCASP6_MCASP_ACLKX_POUT", "Output clock"}, + [1561] = {180, 11, "DEV_MCASP6_MCASP_ACLKX_PIN", "Input clock"}, + [1562] = {180, 12, "DEV_MCASP6_MCASP_ACLKR_POUT", "Output clock"}, + [1563] = {180, 13, "DEV_MCASP6_MCASP_ACLKR_PIN", "Input clock"}, + [1564] = {180, 14, "DEV_MCASP6_MCASP_AHCLKX_POUT", "Output clock"}, + [1565] = {180, 15, "DEV_MCASP6_MCASP_AHCLKX_PIN", "Input muxed clock"}, + [1566] = {180, 16, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, + [1567] = {180, 17, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, + [1568] = {180, 18, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, + [1569] = {180, 19, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, + [1570] = {180, 20, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, + [1571] = {180, 21, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, + [1572] = {180, 22, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, + [1573] = {180, 23, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, + [1574] = {180, 24, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, + [1575] = {180, 25, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, + [1576] = {180, 26, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, + [1577] = {180, 27, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, + [1578] = {180, 28, "DEV_MCASP6_MCASP_AHCLKR_POUT", "Output clock"}, + [1579] = {180, 29, "DEV_MCASP6_MCASP_AHCLKR_PIN", "Input muxed clock"}, + [1580] = {180, 30, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, + [1581] = {180, 31, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, + [1582] = {180, 32, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, + [1583] = {180, 33, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, + [1584] = {180, 34, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, + [1585] = {180, 35, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, + [1586] = {180, 36, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, + [1587] = {180, 37, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, + [1588] = {180, 38, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, + [1589] = {180, 39, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, + [1590] = {180, 40, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, + [1591] = {180, 41, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, + [1592] = {181, 0, "DEV_MCASP7_VBUSP_CLK", "Input clock"}, + [1593] = {181, 1, "DEV_MCASP7_AUX_CLK", "Input muxed clock"}, + [1594] = {181, 2, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, + [1595] = {181, 3, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, + [1596] = {181, 4, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, + [1597] = {181, 6, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, + [1598] = {181, 7, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, + [1599] = {181, 8, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, + [1600] = {181, 9, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, + [1601] = {181, 10, "DEV_MCASP7_MCASP_ACLKX_POUT", "Output clock"}, + [1602] = {181, 11, "DEV_MCASP7_MCASP_ACLKX_PIN", "Input clock"}, + [1603] = {181, 12, "DEV_MCASP7_MCASP_ACLKR_POUT", "Output clock"}, + [1604] = {181, 13, "DEV_MCASP7_MCASP_ACLKR_PIN", "Input clock"}, + [1605] = {181, 14, "DEV_MCASP7_MCASP_AHCLKX_POUT", "Output clock"}, + [1606] = {181, 15, "DEV_MCASP7_MCASP_AHCLKX_PIN", "Input muxed clock"}, + [1607] = {181, 16, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, + [1608] = {181, 17, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, + [1609] = {181, 18, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, + [1610] = {181, 19, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, + [1611] = {181, 20, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, + [1612] = {181, 21, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, + [1613] = {181, 22, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, + [1614] = {181, 23, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, + [1615] = {181, 24, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, + [1616] = {181, 25, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, + [1617] = {181, 26, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, + [1618] = {181, 27, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, + [1619] = {181, 28, "DEV_MCASP7_MCASP_AHCLKR_POUT", "Output clock"}, + [1620] = {181, 29, "DEV_MCASP7_MCASP_AHCLKR_PIN", "Input muxed clock"}, + [1621] = {181, 30, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, + [1622] = {181, 31, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, + [1623] = {181, 32, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, + [1624] = {181, 33, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, + [1625] = {181, 34, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, + [1626] = {181, 35, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, + [1627] = {181, 36, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, + [1628] = {181, 37, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, + [1629] = {181, 38, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, + [1630] = {181, 39, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, + [1631] = {181, 40, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, + [1632] = {181, 41, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, + [1633] = {182, 0, "DEV_MCASP8_VBUSP_CLK", "Input clock"}, + [1634] = {182, 1, "DEV_MCASP8_AUX_CLK", "Input muxed clock"}, + [1635] = {182, 2, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, + [1636] = {182, 3, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, + [1637] = {182, 4, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, + [1638] = {182, 6, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, + [1639] = {182, 7, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, + [1640] = {182, 8, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, + [1641] = {182, 9, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, + [1642] = {182, 10, "DEV_MCASP8_MCASP_ACLKX_POUT", "Output clock"}, + [1643] = {182, 11, "DEV_MCASP8_MCASP_ACLKX_PIN", "Input clock"}, + [1644] = {182, 12, "DEV_MCASP8_MCASP_ACLKR_POUT", "Output clock"}, + [1645] = {182, 13, "DEV_MCASP8_MCASP_ACLKR_PIN", "Input clock"}, + [1646] = {182, 14, "DEV_MCASP8_MCASP_AHCLKX_POUT", "Output clock"}, + [1647] = {182, 15, "DEV_MCASP8_MCASP_AHCLKX_PIN", "Input muxed clock"}, + [1648] = {182, 16, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, + [1649] = {182, 17, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, + [1650] = {182, 18, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, + [1651] = {182, 19, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, + [1652] = {182, 20, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, + [1653] = {182, 21, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, + [1654] = {182, 22, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, + [1655] = {182, 23, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, + [1656] = {182, 24, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, + [1657] = {182, 25, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, + [1658] = {182, 26, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, + [1659] = {182, 27, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, + [1660] = {182, 28, "DEV_MCASP8_MCASP_AHCLKR_POUT", "Output clock"}, + [1661] = {182, 29, "DEV_MCASP8_MCASP_AHCLKR_PIN", "Input muxed clock"}, + [1662] = {182, 30, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, + [1663] = {182, 31, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, + [1664] = {182, 32, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, + [1665] = {182, 33, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, + [1666] = {182, 34, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, + [1667] = {182, 35, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, + [1668] = {182, 36, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, + [1669] = {182, 37, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, + [1670] = {182, 38, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, + [1671] = {182, 39, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, + [1672] = {182, 40, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, + [1673] = {182, 41, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, + [1674] = {183, 0, "DEV_MCASP9_VBUSP_CLK", "Input clock"}, + [1675] = {183, 1, "DEV_MCASP9_AUX_CLK", "Input muxed clock"}, + [1676] = {183, 2, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, + [1677] = {183, 3, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, + [1678] = {183, 4, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, + [1679] = {183, 6, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, + [1680] = {183, 7, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, + [1681] = {183, 8, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, + [1682] = {183, 9, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, + [1683] = {183, 10, "DEV_MCASP9_MCASP_ACLKX_POUT", "Output clock"}, + [1684] = {183, 11, "DEV_MCASP9_MCASP_ACLKX_PIN", "Input clock"}, + [1685] = {183, 12, "DEV_MCASP9_MCASP_ACLKR_POUT", "Output clock"}, + [1686] = {183, 13, "DEV_MCASP9_MCASP_ACLKR_PIN", "Input clock"}, + [1687] = {183, 14, "DEV_MCASP9_MCASP_AHCLKX_POUT", "Output clock"}, + [1688] = {183, 15, "DEV_MCASP9_MCASP_AHCLKX_PIN", "Input muxed clock"}, + [1689] = {183, 16, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, + [1690] = {183, 17, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, + [1691] = {183, 18, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, + [1692] = {183, 19, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, + [1693] = {183, 20, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, + [1694] = {183, 21, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, + [1695] = {183, 22, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, + [1696] = {183, 23, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, + [1697] = {183, 24, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, + [1698] = {183, 25, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, + [1699] = {183, 26, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, + [1700] = {183, 27, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, + [1701] = {183, 28, "DEV_MCASP9_MCASP_AHCLKR_POUT", "Output clock"}, + [1702] = {183, 29, "DEV_MCASP9_MCASP_AHCLKR_PIN", "Input muxed clock"}, + [1703] = {183, 30, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, + [1704] = {183, 31, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, + [1705] = {183, 32, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, + [1706] = {183, 33, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, + [1707] = {183, 34, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, + [1708] = {183, 35, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, + [1709] = {183, 36, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, + [1710] = {183, 37, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, + [1711] = {183, 38, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, + [1712] = {183, 39, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, + [1713] = {183, 40, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, + [1714] = {183, 41, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, + [1715] = {266, 0, "DEV_MCSPI0_VBUSP_CLK", "Input clock"}, + [1716] = {266, 1, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"}, + [1717] = {266, 2, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, + [1718] = {267, 0, "DEV_MCSPI1_VBUSP_CLK", "Input clock"}, + [1719] = {267, 1, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"}, + [1720] = {267, 2, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, + [1721] = {268, 0, "DEV_MCSPI2_VBUSP_CLK", "Input clock"}, + [1722] = {268, 1, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"}, + [1723] = {268, 2, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"}, + [1724] = {269, 0, "DEV_MCSPI3_VBUSP_CLK", "Input clock"}, + [1725] = {269, 1, "DEV_MCSPI3_CLKSPIREF_CLK", "Input clock"}, + [1726] = {269, 2, "DEV_MCSPI3_IO_CLKSPII_CLK", "Input muxed clock"}, + [1727] = {269, 3, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"}, + [1728] = {269, 4, "DEV_MCSPI3_IO_CLKSPIO_CLK", "Output clock"}, + [1729] = {270, 0, "DEV_MCSPI4_VBUSP_CLK", "Input clock"}, + [1730] = {270, 1, "DEV_MCSPI4_CLKSPIREF_CLK", "Input clock"}, + [1731] = {270, 2, "DEV_MCSPI4_IO_CLKSPII_CLK", "Input clock"}, + [1732] = {270, 3, "DEV_MCSPI4_IO_CLKSPIO_CLK", "Output clock"}, + [1733] = {271, 0, "DEV_MCSPI5_VBUSP_CLK", "Input clock"}, + [1734] = {271, 1, "DEV_MCSPI5_CLKSPIREF_CLK", "Input clock"}, + [1735] = {271, 2, "DEV_MCSPI5_IO_CLKSPIO_CLK", "Output clock"}, + [1736] = {272, 0, "DEV_MCSPI6_VBUSP_CLK", "Input clock"}, + [1737] = {272, 1, "DEV_MCSPI6_CLKSPIREF_CLK", "Input clock"}, + [1738] = {272, 2, "DEV_MCSPI6_IO_CLKSPIO_CLK", "Output clock"}, + [1739] = {273, 0, "DEV_MCSPI7_VBUSP_CLK", "Input clock"}, + [1740] = {273, 1, "DEV_MCSPI7_CLKSPIREF_CLK", "Input clock"}, + [1741] = {273, 2, "DEV_MCSPI7_IO_CLKSPIO_CLK", "Output clock"}, + [1742] = {0, 0, "DEV_MCU_ADC12_16FFC0_SYS_CLK", "Input clock"}, + [1743] = {0, 1, "DEV_MCU_ADC12_16FFC0_ADC_CLK", "Input muxed clock"}, + [1744] = {0, 2, "DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK"}, + [1745] = {0, 3, "DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK"}, + [1746] = {0, 4, "DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK"}, + [1747] = {0, 5, "DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK"}, + [1748] = {0, 6, "DEV_MCU_ADC12_16FFC0_VBUS_CLK", "Input clock"}, + [1749] = {1, 0, "DEV_MCU_ADC12_16FFC1_SYS_CLK", "Input clock"}, + [1750] = {1, 1, "DEV_MCU_ADC12_16FFC1_ADC_CLK", "Input muxed clock"}, + [1751] = {1, 2, "DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK"}, + [1752] = {1, 3, "DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK"}, + [1753] = {1, 4, "DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK"}, + [1754] = {1, 5, "DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK"}, + [1755] = {1, 6, "DEV_MCU_ADC12_16FFC1_VBUS_CLK", "Input clock"}, + [1756] = {18, 0, "DEV_MCU_CPSW0_RGMII1_RXC_I", "Input clock"}, + [1757] = {18, 1, "DEV_MCU_CPSW0_RGMII_MHZ_250_CLK", "Input clock"}, + [1758] = {18, 2, "DEV_MCU_CPSW0_CPTS_RFT_CLK", "Input muxed clock"}, + [1759] = {18, 3, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, + [1760] = {18, 4, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, + [1761] = {18, 5, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, + [1762] = {18, 6, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, + [1763] = {18, 7, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, + [1764] = {18, 8, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, + [1765] = {18, 9, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, + [1766] = {18, 10, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, + [1767] = {18, 11, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, + [1768] = {18, 12, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, + [1769] = {18, 13, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, + [1770] = {18, 14, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, + [1771] = {18, 15, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, + [1772] = {18, 16, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, + [1773] = {18, 17, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, + [1774] = {18, 18, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, + [1775] = {18, 19, "DEV_MCU_CPSW0_GMII_RFT_CLK", "Input clock"}, + [1776] = {18, 20, "DEV_MCU_CPSW0_RMII_MHZ_50_CLK", "Input clock"}, + [1777] = {18, 21, "DEV_MCU_CPSW0_RGMII_MHZ_50_CLK", "Input clock"}, + [1778] = {18, 22, "DEV_MCU_CPSW0_CPPI_CLK_CLK", "Input clock"}, + [1779] = {18, 23, "DEV_MCU_CPSW0_RGMII_MHZ_5_CLK", "Input clock"}, + [1780] = {18, 24, "DEV_MCU_CPSW0_GMII1_MR_CLK", "Input clock"}, + [1781] = {18, 25, "DEV_MCU_CPSW0_GMII1_MT_CLK", "Input clock"}, + [1782] = {18, 26, "DEV_MCU_CPSW0_RGMII1_TXC_I", "Input clock"}, + [1783] = {18, 27, "DEV_MCU_CPSW0_RGMII1_TXC_O", "Output clock"}, + [1784] = {18, 28, "DEV_MCU_CPSW0_CPTS_GENF0", "Output clock"}, + [1785] = {18, 29, "DEV_MCU_CPSW0_MDIO_MDCLK_O", "Output clock"}, + [1786] = {24, 0, "DEV_MCU_CPT2_AGGR0_VCLK_CLK", "Input clock"}, + [1787] = {44, 0, "DEV_MCU_DCC0_DCC_INPUT10_CLK", "Input clock"}, + [1788] = {44, 1, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"}, + [1789] = {44, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, + [1790] = {44, 3, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, + [1791] = {44, 4, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, + [1792] = {44, 5, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"}, + [1793] = {44, 6, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, + [1794] = {44, 7, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, + [1795] = {44, 8, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, + [1796] = {44, 9, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"}, + [1797] = {44, 10, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, + [1798] = {44, 11, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, + [1799] = {44, 12, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"}, + [1800] = {45, 0, "DEV_MCU_DCC1_DCC_INPUT10_CLK", "Input clock"}, + [1801] = {45, 1, "DEV_MCU_DCC1_DCC_INPUT01_CLK", "Input clock"}, + [1802] = {45, 2, "DEV_MCU_DCC1_DCC_CLKSRC2_CLK", "Input clock"}, + [1803] = {45, 3, "DEV_MCU_DCC1_DCC_CLKSRC7_CLK", "Input clock"}, + [1804] = {45, 4, "DEV_MCU_DCC1_DCC_CLKSRC0_CLK", "Input clock"}, + [1805] = {45, 5, "DEV_MCU_DCC1_VBUS_CLK", "Input clock"}, + [1806] = {45, 6, "DEV_MCU_DCC1_DCC_CLKSRC4_CLK", "Input clock"}, + [1807] = {45, 7, "DEV_MCU_DCC1_DCC_CLKSRC1_CLK", "Input clock"}, + [1808] = {45, 8, "DEV_MCU_DCC1_DCC_CLKSRC3_CLK", "Input clock"}, + [1809] = {45, 9, "DEV_MCU_DCC1_DCC_INPUT00_CLK", "Input clock"}, + [1810] = {45, 10, "DEV_MCU_DCC1_DCC_CLKSRC5_CLK", "Input clock"}, + [1811] = {45, 11, "DEV_MCU_DCC1_DCC_CLKSRC6_CLK", "Input clock"}, + [1812] = {45, 12, "DEV_MCU_DCC1_DCC_INPUT02_CLK", "Input clock"}, + [1813] = {46, 0, "DEV_MCU_DCC2_DCC_INPUT10_CLK", "Input clock"}, + [1814] = {46, 1, "DEV_MCU_DCC2_DCC_INPUT01_CLK", "Input clock"}, + [1815] = {46, 2, "DEV_MCU_DCC2_DCC_CLKSRC7_CLK", "Input clock"}, + [1816] = {46, 3, "DEV_MCU_DCC2_DCC_CLKSRC0_CLK", "Input clock"}, + [1817] = {46, 4, "DEV_MCU_DCC2_VBUS_CLK", "Input clock"}, + [1818] = {46, 5, "DEV_MCU_DCC2_DCC_CLKSRC4_CLK", "Input clock"}, + [1819] = {46, 6, "DEV_MCU_DCC2_DCC_CLKSRC1_CLK", "Input clock"}, + [1820] = {46, 7, "DEV_MCU_DCC2_DCC_CLKSRC3_CLK", "Input clock"}, + [1821] = {46, 8, "DEV_MCU_DCC2_DCC_INPUT00_CLK", "Input clock"}, + [1822] = {46, 9, "DEV_MCU_DCC2_DCC_CLKSRC6_CLK", "Input clock"}, + [1823] = {46, 10, "DEV_MCU_DCC2_DCC_INPUT02_CLK", "Input clock"}, + [1824] = {98, 0, "DEV_MCU_ESM0_CLK", "Input clock"}, + [1825] = {101, 0, "DEV_MCU_FSS0_FSAS_0_GCLK", "Input clock"}, + [1826] = {102, 0, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK", "Input clock"}, + [1827] = {102, 1, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK", "Input clock"}, + [1828] = {102, 2, "DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK", "Input clock"}, + [1829] = {102, 3, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK", "Input clock"}, + [1830] = {102, 4, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK", "Input clock"}, + [1831] = {102, 5, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N", "Output clock"}, + [1832] = {102, 6, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P", "Output clock"}, + [1833] = {103, 0, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK", "Input muxed clock"}, + [1834] = {103, 1, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"}, + [1835] = {103, 2, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"}, + [1836] = {103, 3, "DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"}, + [1837] = {103, 4, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"}, + [1838] = {103, 5, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"}, + [1839] = {103, 6, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"}, + [1840] = {103, 7, "DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"}, + [1841] = {103, 8, "DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"}, + [1842] = {103, 9, "DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"}, + [1843] = {104, 0, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK", "Input muxed clock"}, + [1844] = {104, 1, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"}, + [1845] = {104, 2, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"}, + [1846] = {104, 3, "DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK", "Input clock"}, + [1847] = {104, 4, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK", "Input muxed clock"}, + [1848] = {104, 5, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"}, + [1849] = {104, 6, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"}, + [1850] = {104, 7, "DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK", "Input clock"}, + [1851] = {104, 8, "DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK", "Input clock"}, + [1852] = {104, 9, "DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK", "Output clock"}, + [1853] = {194, 0, "DEV_MCU_I2C0_PISYS_CLK", "Input clock"}, + [1854] = {194, 1, "DEV_MCU_I2C0_PISCL", "Input clock"}, + [1855] = {194, 2, "DEV_MCU_I2C0_CLK", "Input clock"}, + [1856] = {194, 3, "DEV_MCU_I2C0_PORSCL", "Output clock"}, + [1857] = {195, 0, "DEV_MCU_I2C1_PISYS_CLK", "Input clock"}, + [1858] = {195, 1, "DEV_MCU_I2C1_PISCL", "Input clock"}, + [1859] = {195, 2, "DEV_MCU_I2C1_CLK", "Input clock"}, + [1860] = {117, 0, "DEV_MCU_I3C0_I3C_PCLK_CLK", "Input clock"}, + [1861] = {117, 1, "DEV_MCU_I3C0_I3C_SCL_DI", "Input clock"}, + [1862] = {117, 2, "DEV_MCU_I3C0_I3C_SCLK_CLK", "Input clock"}, + [1863] = {117, 3, "DEV_MCU_I3C0_I3C_SCL_DO", "Output clock"}, + [1864] = {118, 0, "DEV_MCU_I3C1_I3C_PCLK_CLK", "Input clock"}, + [1865] = {118, 1, "DEV_MCU_I3C1_I3C_SCL_DI", "Input clock"}, + [1866] = {118, 2, "DEV_MCU_I3C1_I3C_SCLK_CLK", "Input clock"}, + [1867] = {118, 3, "DEV_MCU_I3C1_I3C_SCL_DO", "Output clock"}, + [1868] = {172, 0, "DEV_MCU_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, + [1869] = {172, 1, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, + [1870] = {172, 2, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, + [1871] = {172, 3, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, + [1872] = {172, 4, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, + [1873] = {172, 5, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, + [1874] = {173, 0, "DEV_MCU_MCAN1_MCANSS_HCLK_CLK", "Input clock"}, + [1875] = {173, 1, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"}, + [1876] = {173, 2, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, + [1877] = {173, 3, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, + [1878] = {173, 4, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, + [1879] = {173, 5, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, + [1880] = {274, 0, "DEV_MCU_MCSPI0_VBUSP_CLK", "Input clock"}, + [1881] = {274, 1, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"}, + [1882] = {274, 2, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, + [1883] = {275, 0, "DEV_MCU_MCSPI1_VBUSP_CLK", "Input clock"}, + [1884] = {275, 1, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"}, + [1885] = {275, 2, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"}, + [1886] = {275, 3, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"}, + [1887] = {275, 4, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, + [1888] = {276, 0, "DEV_MCU_MCSPI2_VBUSP_CLK", "Input clock"}, + [1889] = {276, 1, "DEV_MCU_MCSPI2_CLKSPIREF_CLK", "Input clock"}, + [1890] = {276, 2, "DEV_MCU_MCSPI2_IO_CLKSPII_CLK", "Input clock"}, + [1891] = {276, 3, "DEV_MCU_MCSPI2_IO_CLKSPIO_CLK", "Output clock"}, + [1892] = {237, 0, "DEV_MCU_NAVSS0_INTR_0_INTR_CLK", "Input clock"}, + [1893] = {238, 0, "DEV_MCU_NAVSS0_MCRC_0_CLK", "Input clock"}, + [1894] = {302, 0, "DEV_MCU_NAVSS0_MODSS_VD2CLK", "Input clock"}, + [1895] = {234, 0, "DEV_MCU_NAVSS0_PROXY0_CLK_CLK", "Input clock"}, + [1896] = {235, 0, "DEV_MCU_NAVSS0_RINGACC0_SYS_CLK", "Input clock"}, + [1897] = {236, 0, "DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"}, + [1898] = {303, 0, "DEV_MCU_NAVSS0_UDMASS_VD2CLK", "Input clock"}, + [1899] = {233, 0, "DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK", "Input clock"}, + [1900] = {250, 0, "DEV_MCU_R5FSS0_CORE0_CPU_CLK", "Input muxed clock"}, + [1901] = {250, 1, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"}, + [1902] = {250, 2, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"}, + [1903] = {250, 3, "DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"}, + [1904] = {250, 4, "DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE", "Input clock"}, + [1905] = {251, 0, "DEV_MCU_R5FSS0_CORE1_CPU_CLK", "Input muxed clock"}, + [1906] = {251, 1, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"}, + [1907] = {251, 2, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"}, + [1908] = {251, 3, "DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"}, + [1909] = {251, 4, "DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE", "Input clock"}, + [1910] = {262, 0, "DEV_MCU_RTI0_VBUSP_CLK", "Input clock"}, + [1911] = {262, 1, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"}, + [1912] = {262, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, + [1913] = {262, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, + [1914] = {262, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, + [1915] = {262, 5, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, + [1916] = {263, 0, "DEV_MCU_RTI1_VBUSP_CLK", "Input clock"}, + [1917] = {263, 1, "DEV_MCU_RTI1_RTI_CLK", "Input muxed clock"}, + [1918] = {263, 2, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, + [1919] = {263, 3, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, + [1920] = {263, 4, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, + [1921] = {263, 5, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, + [1922] = {265, 0, "DEV_MCU_SA2_UL0_X2_CLK", "Input clock"}, + [1923] = {265, 1, "DEV_MCU_SA2_UL0_PKA_IN_CLK", "Input clock"}, + [1924] = {265, 2, "DEV_MCU_SA2_UL0_X1_CLK", "Input clock"}, + [1925] = {35, 0, "DEV_MCU_TIMER0_TIMER_HCLK_CLK", "Input clock"}, + [1926] = {35, 1, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, + [1927] = {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, + [1928] = {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, + [1929] = {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, + [1930] = {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, + [1931] = {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, + [1932] = {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, + [1933] = {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, + [1934] = {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, + [1935] = {35, 10, "DEV_MCU_TIMER0_TIMER_PWM", "Output clock"}, + [1936] = {71, 0, "DEV_MCU_TIMER1_TIMER_HCLK_CLK", "Input clock"}, + [1937] = {71, 1, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, + [1938] = {71, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, + [1939] = {71, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, + [1940] = {72, 0, "DEV_MCU_TIMER2_TIMER_HCLK_CLK", "Input clock"}, + [1941] = {72, 1, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, + [1942] = {72, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, + [1943] = {72, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, + [1944] = {72, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, + [1945] = {72, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, + [1946] = {72, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, + [1947] = {72, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, + [1948] = {72, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, + [1949] = {72, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, + [1950] = {72, 10, "DEV_MCU_TIMER2_TIMER_PWM", "Output clock"}, + [1951] = {73, 0, "DEV_MCU_TIMER3_TIMER_HCLK_CLK", "Input clock"}, + [1952] = {73, 1, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, + [1953] = {73, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, + [1954] = {73, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, + [1955] = {74, 0, "DEV_MCU_TIMER4_TIMER_HCLK_CLK", "Input clock"}, + [1956] = {74, 1, "DEV_MCU_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"}, + [1957] = {74, 2, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, + [1958] = {74, 3, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, + [1959] = {74, 4, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, + [1960] = {74, 5, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, + [1961] = {74, 6, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, + [1962] = {74, 7, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, + [1963] = {74, 8, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, + [1964] = {74, 9, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, + [1965] = {74, 10, "DEV_MCU_TIMER4_TIMER_PWM", "Output clock"}, + [1966] = {75, 0, "DEV_MCU_TIMER5_TIMER_HCLK_CLK", "Input clock"}, + [1967] = {75, 1, "DEV_MCU_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"}, + [1968] = {75, 2, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"}, + [1969] = {75, 3, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"}, + [1970] = {76, 0, "DEV_MCU_TIMER6_TIMER_HCLK_CLK", "Input clock"}, + [1971] = {76, 1, "DEV_MCU_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"}, + [1972] = {76, 2, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, + [1973] = {76, 3, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, + [1974] = {76, 4, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, + [1975] = {76, 5, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, + [1976] = {76, 6, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, + [1977] = {76, 7, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, + [1978] = {76, 8, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, + [1979] = {76, 9, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, + [1980] = {76, 10, "DEV_MCU_TIMER6_TIMER_PWM", "Output clock"}, + [1981] = {77, 0, "DEV_MCU_TIMER7_TIMER_HCLK_CLK", "Input clock"}, + [1982] = {77, 1, "DEV_MCU_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"}, + [1983] = {77, 2, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"}, + [1984] = {77, 3, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"}, + [1985] = {78, 0, "DEV_MCU_TIMER8_TIMER_HCLK_CLK", "Input clock"}, + [1986] = {78, 1, "DEV_MCU_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"}, + [1987] = {78, 2, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, + [1988] = {78, 3, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, + [1989] = {78, 4, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, + [1990] = {78, 5, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, + [1991] = {78, 6, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, + [1992] = {78, 7, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, + [1993] = {78, 8, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, + [1994] = {78, 9, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, + [1995] = {78, 10, "DEV_MCU_TIMER8_TIMER_PWM", "Output clock"}, + [1996] = {79, 0, "DEV_MCU_TIMER9_TIMER_HCLK_CLK", "Input clock"}, + [1997] = {79, 1, "DEV_MCU_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"}, + [1998] = {79, 2, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"}, + [1999] = {79, 3, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"}, + [2000] = {149, 0, "DEV_MCU_UART0_FCLK_CLK", "Input muxed clock"}, + [2001] = {149, 1, "DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"}, + [2002] = {149, 2, "DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"}, + [2003] = {149, 3, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"}, + [2004] = {186, 0, "DEV_MLB0_MLBSS_MLB_CLK", "Input clock"}, + [2005] = {186, 1, "DEV_MLB0_MLBSS_SCLK_CLK", "Input clock"}, + [2006] = {186, 2, "DEV_MLB0_MLBSS_HCLK_CLK", "Input clock"}, + [2007] = {186, 3, "DEV_MLB0_MLBSS_PCLK_CLK", "Input clock"}, + [2008] = {186, 4, "DEV_MLB0_MLBSS_AMLB_CLK", "Input clock"}, + [2009] = {91, 0, "DEV_MMCSD0_EMMCSS_VBUS_CLK", "Input clock"}, + [2010] = {91, 1, "DEV_MMCSD0_EMMCSS_XIN_CLK", "Input muxed clock"}, + [2011] = {91, 2, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, + [2012] = {91, 3, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, + [2013] = {91, 4, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, + [2014] = {91, 5, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, + [2015] = {91, 6, "DEV_MMCSD0_EMMCSS_IO_CLK", "Output clock"}, + [2016] = {92, 0, "DEV_MMCSD1_EMMCSDSS_XIN_CLK", "Input muxed clock"}, + [2017] = {92, 1, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, + [2018] = {92, 2, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, + [2019] = {92, 3, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, + [2020] = {92, 4, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, + [2021] = {92, 5, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"}, + [2022] = {92, 6, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I", "Input clock"}, + [2023] = {92, 7, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O", "Output clock"}, + [2024] = {93, 0, "DEV_MMCSD2_EMMCSDSS_XIN_CLK", "Input muxed clock"}, + [2025] = {93, 1, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"}, + [2026] = {93, 2, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"}, + [2027] = {93, 3, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"}, + [2028] = {93, 4, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"}, + [2029] = {93, 5, "DEV_MMCSD2_EMMCSDSS_VBUS_CLK", "Input clock"}, + [2030] = {93, 6, "DEV_MMCSD2_EMMCSDSS_IO_CLK_I", "Input clock"}, + [2031] = {93, 7, "DEV_MMCSD2_EMMCSDSS_IO_CLK_O", "Output clock"}, + [2032] = {199, 0, "DEV_NAVSS0_CPTS0_GENF3", "Output clock"}, + [2033] = {199, 1, "DEV_NAVSS0_CPTS0_GENF2", "Output clock"}, + [2034] = {201, 0, "DEV_NAVSS0_CPTS_0_VBUSP_GCLK", "Input clock"}, + [2035] = {201, 1, "DEV_NAVSS0_CPTS_0_RCLK", "Input muxed clock"}, + [2036] = {201, 2, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, + [2037] = {201, 3, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, + [2038] = {201, 4, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, + [2039] = {201, 5, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, + [2040] = {201, 6, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, + [2041] = {201, 7, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, + [2042] = {201, 8, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, + [2043] = {201, 9, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, + [2044] = {201, 10, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, + [2045] = {201, 11, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, + [2046] = {201, 12, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, + [2047] = {201, 13, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, + [2048] = {201, 14, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, + [2049] = {201, 15, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, + [2050] = {201, 16, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, + [2051] = {201, 17, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, + [2052] = {201, 18, "DEV_NAVSS0_CPTS_0_TS_GENF0", "Output clock"}, + [2053] = {201, 19, "DEV_NAVSS0_CPTS_0_TS_GENF1", "Output clock"}, + [2054] = {206, 0, "DEV_NAVSS0_DTI_0_CLK_CLK", "Input clock"}, + [2055] = {206, 1, "DEV_NAVSS0_DTI_0_EXT0_DTI_CLK_CLK", "Input clock"}, + [2056] = {206, 2, "DEV_NAVSS0_DTI_0_EXT3_DTI_CLK_CLK", "Input clock"}, + [2057] = {206, 3, "DEV_NAVSS0_DTI_0_EXT1_DTI_CLK_CLK", "Input clock"}, + [2058] = {206, 4, "DEV_NAVSS0_DTI_0_EXT2_DTI_CLK_CLK", "Input clock"}, + [2059] = {213, 0, "DEV_NAVSS0_INTR_ROUTER_0_INTR_CLK", "Input clock"}, + [2060] = {214, 0, "DEV_NAVSS0_MAILBOX_0_VCLK_CLK", "Input clock"}, + [2061] = {215, 0, "DEV_NAVSS0_MAILBOX_1_VCLK_CLK", "Input clock"}, + [2062] = {224, 0, "DEV_NAVSS0_MAILBOX_10_VCLK_CLK", "Input clock"}, + [2063] = {225, 0, "DEV_NAVSS0_MAILBOX_11_VCLK_CLK", "Input clock"}, + [2064] = {216, 0, "DEV_NAVSS0_MAILBOX_2_VCLK_CLK", "Input clock"}, + [2065] = {217, 0, "DEV_NAVSS0_MAILBOX_3_VCLK_CLK", "Input clock"}, + [2066] = {218, 0, "DEV_NAVSS0_MAILBOX_4_VCLK_CLK", "Input clock"}, + [2067] = {219, 0, "DEV_NAVSS0_MAILBOX_5_VCLK_CLK", "Input clock"}, + [2068] = {220, 0, "DEV_NAVSS0_MAILBOX_6_VCLK_CLK", "Input clock"}, + [2069] = {221, 0, "DEV_NAVSS0_MAILBOX_7_VCLK_CLK", "Input clock"}, + [2070] = {222, 0, "DEV_NAVSS0_MAILBOX_8_VCLK_CLK", "Input clock"}, + [2071] = {223, 0, "DEV_NAVSS0_MAILBOX_9_VCLK_CLK", "Input clock"}, + [2072] = {227, 0, "DEV_NAVSS0_MCRC_0_CLK", "Input clock"}, + [2073] = {299, 0, "DEV_NAVSS0_MODSS_VD2CLK", "Input clock"}, + [2074] = {207, 0, "DEV_NAVSS0_MODSS_INTAGGR_0_SYS_CLK", "Input clock"}, + [2075] = {208, 0, "DEV_NAVSS0_MODSS_INTAGGR_1_SYS_CLK", "Input clock"}, + [2076] = {210, 0, "DEV_NAVSS0_PROXY_0_CLK_CLK", "Input clock"}, + [2077] = {211, 0, "DEV_NAVSS0_RINGACC_0_SYS_CLK", "Input clock"}, + [2078] = {226, 0, "DEV_NAVSS0_SPINLOCK_0_CLK", "Input clock"}, + [2079] = {228, 0, "DEV_NAVSS0_TBU_0_CLK_CLK", "Input clock"}, + [2080] = {229, 0, "DEV_NAVSS0_TCU_0_CLK_CLK", "Input clock"}, + [2081] = {230, 0, "DEV_NAVSS0_TIMERMGR_0_VCLK_CLK", "Input clock"}, + [2082] = {230, 1, "DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT", "Input clock"}, + [2083] = {231, 0, "DEV_NAVSS0_TIMERMGR_1_VCLK_CLK", "Input clock"}, + [2084] = {231, 1, "DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT", "Input clock"}, + [2085] = {212, 0, "DEV_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"}, + [2086] = {300, 0, "DEV_NAVSS0_UDMASS_VD2CLK", "Input clock"}, + [2087] = {209, 0, "DEV_NAVSS0_UDMASS_INTAGGR_0_SYS_CLK", "Input clock"}, + [2088] = {301, 0, "DEV_NAVSS0_VIRTSS_VD2CLK", "Input clock"}, + [2089] = {239, 0, "DEV_PCIE0_PCIE_LANE1_TXMCLK", "Input clock"}, + [2090] = {239, 1, "DEV_PCIE0_PCIE_CBA_CLK", "Input clock"}, + [2091] = {239, 2, "DEV_PCIE0_PCIE_LANE1_RXCLK", "Input clock"}, + [2092] = {239, 3, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, + [2093] = {239, 4, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [2094] = {239, 5, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [2095] = {239, 6, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [2096] = {239, 7, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [2097] = {239, 8, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [2098] = {239, 9, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [2099] = {239, 10, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [2100] = {239, 11, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [2101] = {239, 12, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [2102] = {239, 13, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [2103] = {239, 14, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [2104] = {239, 15, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [2105] = {239, 16, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [2106] = {239, 17, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [2107] = {239, 18, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [2108] = {239, 19, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, + [2109] = {239, 20, "DEV_PCIE0_PCIE_LANE1_TXFCLK", "Input clock"}, + [2110] = {239, 21, "DEV_PCIE0_PCIE_LANE1_REFCLK", "Input clock"}, + [2111] = {239, 22, "DEV_PCIE0_PCIE_LANE0_REFCLK", "Input clock"}, + [2112] = {239, 23, "DEV_PCIE0_PCIE_LANE0_TXMCLK", "Input clock"}, + [2113] = {239, 24, "DEV_PCIE0_PCIE_LANE0_TXFCLK", "Input clock"}, + [2114] = {239, 25, "DEV_PCIE0_PCIE_PM_CLK", "Input clock"}, + [2115] = {239, 26, "DEV_PCIE0_PCIE_LANE0_RXFCLK", "Input clock"}, + [2116] = {239, 27, "DEV_PCIE0_PCIE_LANE1_RXFCLK", "Input clock"}, + [2117] = {239, 28, "DEV_PCIE0_PCIE_LANE0_RXCLK", "Input clock"}, + [2118] = {239, 29, "DEV_PCIE0_PCIE_LANE1_TXCLK", "Output clock"}, + [2119] = {239, 30, "DEV_PCIE0_PCIE_LANE0_TXCLK", "Output clock"}, + [2120] = {240, 0, "DEV_PCIE1_PCIE_LANE1_TXMCLK", "Input clock"}, + [2121] = {240, 1, "DEV_PCIE1_PCIE_CBA_CLK", "Input clock"}, + [2122] = {240, 2, "DEV_PCIE1_PCIE_LANE1_RXCLK", "Input clock"}, + [2123] = {240, 3, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, + [2124] = {240, 4, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, + [2125] = {240, 5, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, + [2126] = {240, 6, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, + [2127] = {240, 7, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, + [2128] = {240, 8, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, + [2129] = {240, 9, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, + [2130] = {240, 10, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, + [2131] = {240, 11, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, + [2132] = {240, 12, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, + [2133] = {240, 13, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, + [2134] = {240, 14, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, + [2135] = {240, 15, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, + [2136] = {240, 16, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, + [2137] = {240, 17, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, + [2138] = {240, 18, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, + [2139] = {240, 19, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, + [2140] = {240, 20, "DEV_PCIE1_PCIE_LANE1_TXFCLK", "Input clock"}, + [2141] = {240, 21, "DEV_PCIE1_PCIE_LANE1_REFCLK", "Input clock"}, + [2142] = {240, 22, "DEV_PCIE1_PCIE_LANE0_REFCLK", "Input clock"}, + [2143] = {240, 23, "DEV_PCIE1_PCIE_LANE0_TXMCLK", "Input clock"}, + [2144] = {240, 24, "DEV_PCIE1_PCIE_LANE0_TXFCLK", "Input clock"}, + [2145] = {240, 25, "DEV_PCIE1_PCIE_PM_CLK", "Input clock"}, + [2146] = {240, 26, "DEV_PCIE1_PCIE_LANE0_RXFCLK", "Input clock"}, + [2147] = {240, 27, "DEV_PCIE1_PCIE_LANE1_RXFCLK", "Input clock"}, + [2148] = {240, 28, "DEV_PCIE1_PCIE_LANE0_RXCLK", "Input clock"}, + [2149] = {240, 29, "DEV_PCIE1_PCIE_LANE1_TXCLK", "Output clock"}, + [2150] = {240, 30, "DEV_PCIE1_PCIE_LANE0_TXCLK", "Output clock"}, + [2151] = {241, 0, "DEV_PCIE2_PCIE_LANE1_TXMCLK", "Input clock"}, + [2152] = {241, 1, "DEV_PCIE2_PCIE_CBA_CLK", "Input clock"}, + [2153] = {241, 2, "DEV_PCIE2_PCIE_LANE1_RXCLK", "Input clock"}, + [2154] = {241, 3, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, + [2155] = {241, 4, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, + [2156] = {241, 5, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, + [2157] = {241, 6, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, + [2158] = {241, 7, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, + [2159] = {241, 8, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, + [2160] = {241, 9, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, + [2161] = {241, 10, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, + [2162] = {241, 11, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, + [2163] = {241, 12, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, + [2164] = {241, 13, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, + [2165] = {241, 14, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, + [2166] = {241, 15, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, + [2167] = {241, 16, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, + [2168] = {241, 17, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, + [2169] = {241, 18, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, + [2170] = {241, 19, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, + [2171] = {241, 20, "DEV_PCIE2_PCIE_LANE1_TXFCLK", "Input clock"}, + [2172] = {241, 21, "DEV_PCIE2_PCIE_LANE1_REFCLK", "Input clock"}, + [2173] = {241, 22, "DEV_PCIE2_PCIE_LANE0_REFCLK", "Input clock"}, + [2174] = {241, 23, "DEV_PCIE2_PCIE_LANE0_TXMCLK", "Input clock"}, + [2175] = {241, 24, "DEV_PCIE2_PCIE_LANE0_TXFCLK", "Input clock"}, + [2176] = {241, 25, "DEV_PCIE2_PCIE_PM_CLK", "Input clock"}, + [2177] = {241, 26, "DEV_PCIE2_PCIE_LANE0_RXFCLK", "Input clock"}, + [2178] = {241, 27, "DEV_PCIE2_PCIE_LANE1_RXFCLK", "Input clock"}, + [2179] = {241, 28, "DEV_PCIE2_PCIE_LANE0_RXCLK", "Input clock"}, + [2180] = {241, 29, "DEV_PCIE2_PCIE_LANE1_TXCLK", "Output clock"}, + [2181] = {241, 30, "DEV_PCIE2_PCIE_LANE0_TXCLK", "Output clock"}, + [2182] = {242, 0, "DEV_PCIE3_PCIE_LANE1_TXMCLK", "Input clock"}, + [2183] = {242, 1, "DEV_PCIE3_PCIE_CBA_CLK", "Input clock"}, + [2184] = {242, 2, "DEV_PCIE3_PCIE_LANE1_RXCLK", "Input clock"}, + [2185] = {242, 3, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, + [2186] = {242, 4, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, + [2187] = {242, 5, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, + [2188] = {242, 6, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, + [2189] = {242, 7, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, + [2190] = {242, 8, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, + [2191] = {242, 9, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, + [2192] = {242, 10, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, + [2193] = {242, 11, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, + [2194] = {242, 12, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, + [2195] = {242, 13, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, + [2196] = {242, 14, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, + [2197] = {242, 15, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, + [2198] = {242, 16, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, + [2199] = {242, 17, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, + [2200] = {242, 18, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, + [2201] = {242, 19, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, + [2202] = {242, 20, "DEV_PCIE3_PCIE_LANE1_TXFCLK", "Input clock"}, + [2203] = {242, 21, "DEV_PCIE3_PCIE_LANE1_REFCLK", "Input clock"}, + [2204] = {242, 22, "DEV_PCIE3_PCIE_LANE0_REFCLK", "Input clock"}, + [2205] = {242, 23, "DEV_PCIE3_PCIE_LANE0_TXMCLK", "Input clock"}, + [2206] = {242, 24, "DEV_PCIE3_PCIE_LANE0_TXFCLK", "Input clock"}, + [2207] = {242, 25, "DEV_PCIE3_PCIE_PM_CLK", "Input clock"}, + [2208] = {242, 26, "DEV_PCIE3_PCIE_LANE0_RXFCLK", "Input clock"}, + [2209] = {242, 27, "DEV_PCIE3_PCIE_LANE1_RXFCLK", "Input clock"}, + [2210] = {242, 28, "DEV_PCIE3_PCIE_LANE0_RXCLK", "Input clock"}, + [2211] = {242, 29, "DEV_PCIE3_PCIE_LANE1_TXCLK", "Output clock"}, + [2212] = {242, 30, "DEV_PCIE3_PCIE_LANE0_TXCLK", "Output clock"}, + [2213] = {119, 0, "DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I", "Input clock"}, + [2214] = {119, 1, "DEV_PRU_ICSSG0_VCLK_CLK", "Input clock"}, + [2215] = {119, 2, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I", "Input clock"}, + [2216] = {119, 3, "DEV_PRU_ICSSG0_IEP_CLK", "Input muxed clock"}, + [2217] = {119, 4, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [2218] = {119, 5, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [2219] = {119, 6, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [2220] = {119, 7, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [2221] = {119, 8, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [2222] = {119, 9, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [2223] = {119, 10, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [2224] = {119, 11, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [2225] = {119, 12, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [2226] = {119, 13, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [2227] = {119, 14, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [2228] = {119, 15, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [2229] = {119, 16, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [2230] = {119, 17, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [2231] = {119, 18, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [2232] = {119, 19, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, + [2233] = {119, 20, "DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK", "Input clock"}, + [2234] = {119, 21, "DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I", "Input clock"}, + [2235] = {119, 22, "DEV_PRU_ICSSG0_UCLK_CLK", "Input clock"}, + [2236] = {119, 23, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I", "Input clock"}, + [2237] = {119, 24, "DEV_PRU_ICSSG0_CORE_CLK", "Input muxed clock"}, + [2238] = {119, 25, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"}, + [2239] = {119, 26, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"}, + [2240] = {119, 27, "DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK", "Input clock"}, + [2241] = {119, 28, "DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK", "Input clock"}, + [2242] = {119, 29, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O", "Output clock"}, + [2243] = {119, 30, "DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O", "Output clock"}, + [2244] = {119, 31, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O", "Output clock"}, + [2245] = {120, 0, "DEV_PRU_ICSSG1_SERDES0_RXCLK", "Input muxed clock"}, + [2246] = {120, 1, "DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK"}, + [2247] = {120, 2, "DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK"}, + [2248] = {120, 3, "DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I", "Input clock"}, + [2249] = {120, 4, "DEV_PRU_ICSSG1_VCLK_CLK", "Input clock"}, + [2250] = {120, 5, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I", "Input clock"}, + [2251] = {120, 6, "DEV_PRU_ICSSG1_SERDES0_RXFCLK", "Input muxed clock"}, + [2252] = {120, 7, "DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK"}, + [2253] = {120, 8, "DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK"}, + [2254] = {120, 9, "DEV_PRU_ICSSG1_IEP_CLK", "Input muxed clock"}, + [2255] = {120, 10, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [2256] = {120, 11, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [2257] = {120, 12, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [2258] = {120, 13, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [2259] = {120, 14, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [2260] = {120, 15, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [2261] = {120, 16, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [2262] = {120, 17, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [2263] = {120, 18, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [2264] = {120, 19, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [2265] = {120, 20, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [2266] = {120, 21, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [2267] = {120, 22, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [2268] = {120, 23, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [2269] = {120, 24, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [2270] = {120, 25, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, + [2271] = {120, 26, "DEV_PRU_ICSSG1_RGMII_MHZ_5_CLK", "Input clock"}, + [2272] = {120, 27, "DEV_PRU_ICSSG1_SERDES0_TXMCLK", "Input muxed clock"}, + [2273] = {120, 28, "DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK"}, + [2274] = {120, 29, "DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK"}, + [2275] = {120, 30, "DEV_PRU_ICSSG1_SERDES0_REFCLK", "Input muxed clock"}, + [2276] = {120, 31, "DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK"}, + [2277] = {120, 32, "DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK"}, + [2278] = {120, 33, "DEV_PRU_ICSSG1_SERDES1_RXFCLK", "Input muxed clock"}, + [2279] = {120, 34, "DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK"}, + [2280] = {120, 35, "DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK"}, + [2281] = {120, 36, "DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I", "Input clock"}, + [2282] = {120, 37, "DEV_PRU_ICSSG1_SERDES1_RXCLK", "Input muxed clock"}, + [2283] = {120, 38, "DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK"}, + [2284] = {120, 39, "DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK"}, + [2285] = {120, 40, "DEV_PRU_ICSSG1_SERDES1_TXFCLK", "Input muxed clock"}, + [2286] = {120, 41, "DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK"}, + [2287] = {120, 42, "DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK"}, + [2288] = {120, 43, "DEV_PRU_ICSSG1_SERDES1_TXMCLK", "Input muxed clock"}, + [2289] = {120, 44, "DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK"}, + [2290] = {120, 45, "DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK"}, + [2291] = {120, 46, "DEV_PRU_ICSSG1_SERDES0_TXFCLK", "Input muxed clock"}, + [2292] = {120, 47, "DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK"}, + [2293] = {120, 48, "DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK"}, + [2294] = {120, 49, "DEV_PRU_ICSSG1_UCLK_CLK", "Input clock"}, + [2295] = {120, 50, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I", "Input clock"}, + [2296] = {120, 51, "DEV_PRU_ICSSG1_SERDES1_REFCLK", "Input muxed clock"}, + [2297] = {120, 52, "DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK"}, + [2298] = {120, 53, "DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK"}, + [2299] = {120, 54, "DEV_PRU_ICSSG1_CORE_CLK", "Input muxed clock"}, + [2300] = {120, 55, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"}, + [2301] = {120, 56, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"}, + [2302] = {120, 57, "DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK", "Input clock"}, + [2303] = {120, 58, "DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK", "Input clock"}, + [2304] = {120, 59, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O", "Output clock"}, + [2305] = {120, 60, "DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O", "Output clock"}, + [2306] = {120, 61, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O", "Output clock"}, + [2307] = {120, 62, "DEV_PRU_ICSSG1_SERDES0_TXCLK", "Output clock"}, + [2308] = {120, 63, "DEV_PRU_ICSSG1_SERDES1_TXCLK", "Output clock"}, + [2309] = {133, 0, "DEV_PSC0_SLOW_CLK", "Input clock"}, + [2310] = {133, 1, "DEV_PSC0_CLK", "Input clock"}, + [2311] = {245, 0, "DEV_R5FSS0_CORE0_CPU_CLK", "Input clock"}, + [2312] = {245, 1, "DEV_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"}, + [2313] = {245, 2, "DEV_R5FSS0_CORE0_INTERFACE_PHASE", "Input clock"}, + [2314] = {246, 0, "DEV_R5FSS0_CORE1_CPU_CLK", "Input clock"}, + [2315] = {246, 1, "DEV_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"}, + [2316] = {246, 2, "DEV_R5FSS0_CORE1_INTERFACE_PHASE", "Input clock"}, + [2317] = {134, 0, "DEV_R5FSS0_INTROUTER0_INTR_CLK", "Input clock"}, + [2318] = {247, 0, "DEV_R5FSS1_CORE0_CPU_CLK", "Input clock"}, + [2319] = {247, 1, "DEV_R5FSS1_CORE0_INTERFACE_CLK", "Input clock"}, + [2320] = {247, 2, "DEV_R5FSS1_CORE0_INTERFACE_PHASE", "Input clock"}, + [2321] = {248, 0, "DEV_R5FSS1_CORE1_CPU_CLK", "Input clock"}, + [2322] = {248, 1, "DEV_R5FSS1_CORE1_INTERFACE_CLK", "Input clock"}, + [2323] = {248, 2, "DEV_R5FSS1_CORE1_INTERFACE_PHASE", "Input clock"}, [2324] = {135, 0, "DEV_R5FSS1_INTROUTER0_INTR_CLK", "Input clock"}, [2325] = {252, 0, "DEV_RTI0_VBUSP_CLK", "Input clock"}, [2326] = {252, 1, "DEV_RTI0_RTI_CLK", "Input muxed clock"}, @@ -2562,8 +2562,8 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [2523] = {292, 41, "DEV_SERDES_16G0_IP1_LN1_TXFCLK", "Output clock"}, [2524] = {292, 42, "DEV_SERDES_16G0_IP2_LN0_RXCLK", "Output clock"}, [2525] = {292, 43, "DEV_SERDES_16G0_IP1_LN1_RXCLK", "Output clock"}, - [2526] = {292, 49, "DEV_SERDES_16G0_CMN_REFCLK1_M_0", "Input clock"}, - [2527] = {292, 57, "DEV_SERDES_16G0_CMN_REFCLK1_P_0", "Input clock"}, + [2526] = {292, 49, "DEV_SERDES_16G0_CMN_REFCLK1_M", "Input clock"}, + [2527] = {292, 57, "DEV_SERDES_16G0_CMN_REFCLK1_P", "Input clock"}, [2528] = {293, 0, "DEV_SERDES_16G1_CORE_REF1_CLK", "Input muxed clock"}, [2529] = {293, 1, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"}, [2530] = {293, 2, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"}, @@ -2619,8 +2619,8 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [2580] = {293, 53, "DEV_SERDES_16G1_IP4_LN0_TXMCLK", "Output clock"}, [2581] = {293, 54, "DEV_SERDES_16G1_IP1_LN1_RXCLK", "Output clock"}, [2582] = {293, 55, "DEV_SERDES_16G1_IP4_LN1_TXFCLK", "Output clock"}, - [2583] = {293, 60, "DEV_SERDES_16G1_CMN_REFCLK1_M_0", "Input clock"}, - [2584] = {293, 67, "DEV_SERDES_16G1_CMN_REFCLK1_P_0", "Input clock"}, + [2583] = {293, 60, "DEV_SERDES_16G1_CMN_REFCLK1_M", "Input clock"}, + [2584] = {293, 67, "DEV_SERDES_16G1_CMN_REFCLK1_P", "Input clock"}, [2585] = {294, 0, "DEV_SERDES_16G2_CORE_REF1_CLK", "Input muxed clock"}, [2586] = {294, 1, "DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK"}, [2587] = {294, 2, "DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK"}, @@ -2664,8 +2664,8 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [2625] = {294, 41, "DEV_SERDES_16G2_IP2_LN0_RXCLK", "Output clock"}, [2626] = {294, 42, "DEV_SERDES_16G2_IP4_LN0_TXMCLK", "Output clock"}, [2627] = {294, 43, "DEV_SERDES_16G2_IP4_LN1_TXFCLK", "Output clock"}, - [2628] = {294, 51, "DEV_SERDES_16G2_CMN_REFCLK1_M_0", "Input clock"}, - [2629] = {294, 61, "DEV_SERDES_16G2_CMN_REFCLK1_P_0", "Input clock"}, + [2628] = {294, 51, "DEV_SERDES_16G2_CMN_REFCLK1_M", "Input clock"}, + [2629] = {294, 61, "DEV_SERDES_16G2_CMN_REFCLK1_P", "Input clock"}, [2630] = {295, 0, "DEV_SERDES_16G3_CORE_REF1_CLK", "Input muxed clock"}, [2631] = {295, 1, "DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK"}, [2632] = {295, 2, "DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK"}, @@ -2697,8 +2697,8 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [2658] = {295, 29, "DEV_SERDES_16G3_IP2_LN0_REFCLK", "Output clock"}, [2659] = {295, 30, "DEV_SERDES_16G3_IP2_LN0_TXMCLK", "Output clock"}, [2660] = {295, 31, "DEV_SERDES_16G3_IP2_LN0_RXCLK", "Output clock"}, - [2661] = {295, 40, "DEV_SERDES_16G3_CMN_REFCLK1_M_0", "Input clock"}, - [2662] = {295, 51, "DEV_SERDES_16G3_CMN_REFCLK1_P_0", "Input clock"}, + [2661] = {295, 40, "DEV_SERDES_16G3_CMN_REFCLK1_M", "Input clock"}, + [2662] = {295, 51, "DEV_SERDES_16G3_CMN_REFCLK1_P", "Input clock"}, [2663] = {29, 0, "DEV_STM0_VBUSP_CLK", "Input clock"}, [2664] = {29, 1, "DEV_STM0_CORE_CLK", "Input clock"}, [2665] = {29, 2, "DEV_STM0_ATB_CLK", "Input clock"}, @@ -2716,15 +2716,15 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [2677] = {49, 11, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, [2678] = {49, 12, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, [2679] = {49, 13, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, - [2680] = {49, 14, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, - [2681] = {49, 15, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, - [2682] = {49, 16, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, + [2680] = {49, 14, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, + [2681] = {49, 15, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, + [2682] = {49, 16, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, [2683] = {49, 17, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, - [2684] = {49, 18, "DEV_TIMER0_TIMER_PWM_0", "Output clock"}, + [2684] = {49, 18, "DEV_TIMER0_TIMER_PWM", "Output clock"}, [2685] = {50, 0, "DEV_TIMER1_TIMER_HCLK_CLK", "Input clock"}, [2686] = {50, 1, "DEV_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, [2687] = {50, 2, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, - [2688] = {50, 3, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM_0", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, + [2688] = {50, 3, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, [2689] = {60, 0, "DEV_TIMER10_TIMER_HCLK_CLK", "Input clock"}, [2690] = {60, 1, "DEV_TIMER10_TIMER_TCLK_CLK", "Input muxed clock"}, [2691] = {60, 2, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, @@ -2739,15 +2739,15 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [2700] = {60, 11, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, [2701] = {60, 12, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, [2702] = {60, 13, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, - [2703] = {60, 14, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, - [2704] = {60, 15, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, - [2705] = {60, 16, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, + [2703] = {60, 14, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, + [2704] = {60, 15, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, + [2705] = {60, 16, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, [2706] = {60, 17, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, - [2707] = {60, 18, "DEV_TIMER10_TIMER_PWM_0", "Output clock"}, + [2707] = {60, 18, "DEV_TIMER10_TIMER_PWM", "Output clock"}, [2708] = {62, 0, "DEV_TIMER11_TIMER_HCLK_CLK", "Input clock"}, [2709] = {62, 1, "DEV_TIMER11_TIMER_TCLK_CLK", "Input muxed clock"}, [2710] = {62, 2, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, - [2711] = {62, 3, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM_0", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, + [2711] = {62, 3, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, [2712] = {63, 0, "DEV_TIMER12_TIMER_HCLK_CLK", "Input clock"}, [2713] = {63, 1, "DEV_TIMER12_TIMER_TCLK_CLK", "Input muxed clock"}, [2714] = {63, 2, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, @@ -2762,15 +2762,15 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [2723] = {63, 11, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, [2724] = {63, 12, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, [2725] = {63, 13, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, - [2726] = {63, 14, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, - [2727] = {63, 15, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, - [2728] = {63, 16, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, + [2726] = {63, 14, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, + [2727] = {63, 15, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, + [2728] = {63, 16, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, [2729] = {63, 17, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, - [2730] = {63, 18, "DEV_TIMER12_TIMER_PWM_0", "Output clock"}, + [2730] = {63, 18, "DEV_TIMER12_TIMER_PWM", "Output clock"}, [2731] = {64, 0, "DEV_TIMER13_TIMER_HCLK_CLK", "Input clock"}, [2732] = {64, 1, "DEV_TIMER13_TIMER_TCLK_CLK", "Input muxed clock"}, [2733] = {64, 2, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"}, - [2734] = {64, 3, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM_0", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"}, + [2734] = {64, 3, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"}, [2735] = {65, 0, "DEV_TIMER14_TIMER_HCLK_CLK", "Input clock"}, [2736] = {65, 1, "DEV_TIMER14_TIMER_TCLK_CLK", "Input muxed clock"}, [2737] = {65, 2, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, @@ -2785,15 +2785,15 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [2746] = {65, 11, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, [2747] = {65, 12, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, [2748] = {65, 13, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, - [2749] = {65, 14, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, - [2750] = {65, 15, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, - [2751] = {65, 16, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, + [2749] = {65, 14, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, + [2750] = {65, 15, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, + [2751] = {65, 16, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, [2752] = {65, 17, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, - [2753] = {65, 18, "DEV_TIMER14_TIMER_PWM_0", "Output clock"}, + [2753] = {65, 18, "DEV_TIMER14_TIMER_PWM", "Output clock"}, [2754] = {66, 0, "DEV_TIMER15_TIMER_HCLK_CLK", "Input clock"}, [2755] = {66, 1, "DEV_TIMER15_TIMER_TCLK_CLK", "Input muxed clock"}, [2756] = {66, 2, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"}, - [2757] = {66, 3, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM_0", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"}, + [2757] = {66, 3, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"}, [2758] = {67, 0, "DEV_TIMER16_TIMER_HCLK_CLK", "Input clock"}, [2759] = {67, 1, "DEV_TIMER16_TIMER_TCLK_CLK", "Input muxed clock"}, [2760] = {67, 2, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, @@ -2808,15 +2808,15 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [2769] = {67, 11, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, [2770] = {67, 12, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, [2771] = {67, 13, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, - [2772] = {67, 14, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, - [2773] = {67, 15, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, - [2774] = {67, 16, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, + [2772] = {67, 14, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, + [2773] = {67, 15, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, + [2774] = {67, 16, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, [2775] = {67, 17, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, - [2776] = {67, 18, "DEV_TIMER16_TIMER_PWM_0", "Output clock"}, + [2776] = {67, 18, "DEV_TIMER16_TIMER_PWM", "Output clock"}, [2777] = {68, 0, "DEV_TIMER17_TIMER_HCLK_CLK", "Input clock"}, [2778] = {68, 1, "DEV_TIMER17_TIMER_TCLK_CLK", "Input muxed clock"}, [2779] = {68, 2, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT17", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"}, - [2780] = {68, 3, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM_0", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"}, + [2780] = {68, 3, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"}, [2781] = {69, 0, "DEV_TIMER18_TIMER_HCLK_CLK", "Input clock"}, [2782] = {69, 1, "DEV_TIMER18_TIMER_TCLK_CLK", "Input muxed clock"}, [2783] = {69, 2, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, @@ -2831,15 +2831,15 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [2792] = {69, 11, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, [2793] = {69, 12, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, [2794] = {69, 13, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, - [2795] = {69, 14, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, - [2796] = {69, 15, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, - [2797] = {69, 16, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, + [2795] = {69, 14, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, + [2796] = {69, 15, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, + [2797] = {69, 16, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, [2798] = {69, 17, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, - [2799] = {69, 18, "DEV_TIMER18_TIMER_PWM_0", "Output clock"}, + [2799] = {69, 18, "DEV_TIMER18_TIMER_PWM", "Output clock"}, [2800] = {70, 0, "DEV_TIMER19_TIMER_HCLK_CLK", "Input clock"}, [2801] = {70, 1, "DEV_TIMER19_TIMER_TCLK_CLK", "Input muxed clock"}, [2802] = {70, 2, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT19", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"}, - [2803] = {70, 3, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM_0", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"}, + [2803] = {70, 3, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"}, [2804] = {51, 0, "DEV_TIMER2_TIMER_HCLK_CLK", "Input clock"}, [2805] = {51, 1, "DEV_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, [2806] = {51, 2, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, @@ -2854,15 +2854,15 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [2815] = {51, 11, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, [2816] = {51, 12, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, [2817] = {51, 13, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, - [2818] = {51, 14, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, - [2819] = {51, 15, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, - [2820] = {51, 16, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, + [2818] = {51, 14, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, + [2819] = {51, 15, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, + [2820] = {51, 16, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, [2821] = {51, 17, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, - [2822] = {51, 18, "DEV_TIMER2_TIMER_PWM_0", "Output clock"}, + [2822] = {51, 18, "DEV_TIMER2_TIMER_PWM", "Output clock"}, [2823] = {52, 0, "DEV_TIMER3_TIMER_HCLK_CLK", "Input clock"}, [2824] = {52, 1, "DEV_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, [2825] = {52, 2, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, - [2826] = {52, 3, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM_0", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, + [2826] = {52, 3, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, [2827] = {53, 0, "DEV_TIMER4_TIMER_HCLK_CLK", "Input clock"}, [2828] = {53, 1, "DEV_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"}, [2829] = {53, 2, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, @@ -2877,15 +2877,15 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [2838] = {53, 11, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, [2839] = {53, 12, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, [2840] = {53, 13, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, - [2841] = {53, 14, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, - [2842] = {53, 15, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, - [2843] = {53, 16, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, + [2841] = {53, 14, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, + [2842] = {53, 15, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, + [2843] = {53, 16, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, [2844] = {53, 17, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, - [2845] = {53, 18, "DEV_TIMER4_TIMER_PWM_0", "Output clock"}, + [2845] = {53, 18, "DEV_TIMER4_TIMER_PWM", "Output clock"}, [2846] = {54, 0, "DEV_TIMER5_TIMER_HCLK_CLK", "Input clock"}, [2847] = {54, 1, "DEV_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"}, [2848] = {54, 2, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, - [2849] = {54, 3, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM_0", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, + [2849] = {54, 3, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, [2850] = {55, 0, "DEV_TIMER6_TIMER_HCLK_CLK", "Input clock"}, [2851] = {55, 1, "DEV_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"}, [2852] = {55, 2, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, @@ -2900,15 +2900,15 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [2861] = {55, 11, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, [2862] = {55, 12, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, [2863] = {55, 13, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, - [2864] = {55, 14, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, - [2865] = {55, 15, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, - [2866] = {55, 16, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, + [2864] = {55, 14, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, + [2865] = {55, 15, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, + [2866] = {55, 16, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, [2867] = {55, 17, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, - [2868] = {55, 18, "DEV_TIMER6_TIMER_PWM_0", "Output clock"}, + [2868] = {55, 18, "DEV_TIMER6_TIMER_PWM", "Output clock"}, [2869] = {57, 0, "DEV_TIMER7_TIMER_HCLK_CLK", "Input clock"}, [2870] = {57, 1, "DEV_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"}, [2871] = {57, 2, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, - [2872] = {57, 3, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM_0", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, + [2872] = {57, 3, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, [2873] = {58, 0, "DEV_TIMER8_TIMER_HCLK_CLK", "Input clock"}, [2874] = {58, 1, "DEV_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"}, [2875] = {58, 2, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, @@ -2923,15 +2923,15 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [2884] = {58, 11, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, [2885] = {58, 12, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, [2886] = {58, 13, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, - [2887] = {58, 14, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, - [2888] = {58, 15, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, - [2889] = {58, 16, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, + [2887] = {58, 14, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, + [2888] = {58, 15, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, + [2889] = {58, 16, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, [2890] = {58, 17, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, - [2891] = {58, 18, "DEV_TIMER8_TIMER_PWM_0", "Output clock"}, + [2891] = {58, 18, "DEV_TIMER8_TIMER_PWM", "Output clock"}, [2892] = {59, 0, "DEV_TIMER9_TIMER_HCLK_CLK", "Input clock"}, [2893] = {59, 1, "DEV_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"}, [2894] = {59, 2, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, - [2895] = {59, 3, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM_0", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, + [2895] = {59, 3, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, [2896] = {136, 0, "DEV_TIMESYNC_INTRTR0_INTR_CLK", "Input clock"}, [2897] = {146, 0, "DEV_UART0_FCLK_CLK", "Input clock"}, [2898] = {146, 1, "DEV_UART0_VBUSP_CLK", "Input clock"}, @@ -2959,7 +2959,7 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [2920] = {277, 3, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"}, [2921] = {277, 4, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"}, [2922] = {277, 5, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"}, - [2923] = {277, 6, "DEV_UFS0_UFSHCI_MPHY_REFCLK_0", "Output clock"}, + [2923] = {277, 6, "DEV_UFS0_UFSHCI_MPHY_REFCLK", "Output clock"}, [2924] = {288, 0, "DEV_USB0_PIPE_REFCLK", "Input muxed clock"}, [2925] = {288, 1, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"}, [2926] = {288, 2, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"}, @@ -3008,8 +3008,8 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [2969] = {289, 21, "DEV_USB1_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB1_PIPE_TXFCLK"}, [2970] = {289, 22, "DEV_USB1_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB1_PIPE_TXFCLK"}, [2971] = {289, 23, "DEV_USB1_PIPE_TXCLK", "Output clock"}, - [2972] = {290, 0, "DEV_VPAC_TOP_MAIN_0_CLK", "Input clock"}, - [2973] = {290, 1, "DEV_VPAC_TOP_MAIN_0_PLL_DCO_CLK", "Input clock"}, + [2972] = {290, 0, "DEV_VPAC0_CLK", "Input clock"}, + [2973] = {290, 1, "DEV_VPAC0_PLL_DCO_CLK", "Input clock"}, [2974] = {291, 0, "DEV_VPFE0_CCD_PCLK_CLK", "Input clock"}, [2975] = {291, 1, "DEV_VPFE0_VPFE_CLK", "Input clock"}, [2976] = {145, 0, "DEV_WKUP_DDPA0_DDPA_CLK", "Input clock"}, @@ -3020,9 +3020,9 @@ struct ti_sci_clocks_info j721e_clocks_info[] = { [2981] = {197, 0, "DEV_WKUP_I2C0_PISYS_CLK", "Input muxed clock"}, [2982] = {197, 1, "DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK"}, [2983] = {197, 2, "DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK"}, - [2984] = {197, 3, "DEV_WKUP_I2C0_PISCL_0", "Input clock"}, + [2984] = {197, 3, "DEV_WKUP_I2C0_PISCL", "Input clock"}, [2985] = {197, 4, "DEV_WKUP_I2C0_CLK", "Input clock"}, - [2986] = {197, 5, "DEV_WKUP_I2C0_PORSCL_0", "Output clock"}, + [2986] = {197, 5, "DEV_WKUP_I2C0_PORSCL", "Output clock"}, [2987] = {132, 0, "DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK", "Input clock"}, [2988] = {138, 0, "DEV_WKUP_PSC0_SLOW_CLK", "Input clock"}, [2989] = {138, 1, "DEV_WKUP_PSC0_CLK", "Input clock"}, diff --git a/soc/j721e/j721e_devices_info.c b/soc/j721e/j721e_devices_info.c index 4859725..eef28a9 100644 --- a/soc/j721e/j721e_devices_info.c +++ b/soc/j721e/j721e_devices_info.c @@ -36,10 +36,10 @@ #include struct ti_sci_devices_info j721e_devices_info[] = { - [0] = {0, "J721E_DEV_MCU_ADC0"}, - [1] = {1, "J721E_DEV_MCU_ADC1"}, + [0] = {0, "J721E_DEV_MCU_ADC12_16FFC0"}, + [1] = {1, "J721E_DEV_MCU_ADC12_16FFC1"}, [2] = {2, "J721E_DEV_ATL0"}, - [3] = {3, "J721E_DEV_COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0"}, + [3] = {3, "J721E_DEV_COMPUTE_CLUSTER0"}, [4] = {4, "J721E_DEV_A72SS0"}, [5] = {5, "J721E_DEV_COMPUTE_CLUSTER0_CFG_WRAP"}, [6] = {6, "J721E_DEV_COMPUTE_CLUSTER0_CLEC"}, @@ -58,7 +58,7 @@ struct ti_sci_devices_info j721e_devices_info[] = { [19] = {19, "J721E_DEV_CPSW0"}, [20] = {20, "J721E_DEV_CPT2_AGGR0"}, [21] = {21, "J721E_DEV_CPT2_AGGR1"}, - [22] = {22, "J721E_DEV_DMSC_WKUP_0"}, + [22] = {22, "J721E_DEV_WKUP_DMSC0"}, [23] = {23, "J721E_DEV_CPT2_AGGR2"}, [24] = {24, "J721E_DEV_MCU_CPT2_AGGR0"}, [25] = {25, "J721E_DEV_CSI_PSILSS0"}, @@ -84,7 +84,7 @@ struct ti_sci_devices_info j721e_devices_info[] = { [45] = {45, "J721E_DEV_MCU_DCC1"}, [46] = {46, "J721E_DEV_MCU_DCC2"}, [47] = {47, "J721E_DEV_DDR0"}, - [48] = {48, "J721E_DEV_DMPAC_TOP_MAIN_0"}, + [48] = {48, "J721E_DEV_DMPAC0"}, [49] = {49, "J721E_DEV_TIMER0"}, [50] = {50, "J721E_DEV_TIMER1"}, [51] = {51, "J721E_DEV_TIMER2"}, @@ -135,7 +135,7 @@ struct ti_sci_devices_info j721e_devices_info[] = { [96] = {97, "J721E_DEV_ESM0"}, [97] = {98, "J721E_DEV_MCU_ESM0"}, [98] = {99, "J721E_DEV_WKUP_ESM0"}, - [99] = {100, "J721E_DEV_FSS_MCU_0"}, + [99] = {100, "J721E_DEV_MCU_FSS0"}, [100] = {101, "J721E_DEV_MCU_FSS0_FSAS_0"}, [101] = {102, "J721E_DEV_MCU_FSS0_HYPERBUS1P0_0"}, [102] = {103, "J721E_DEV_MCU_FSS0_OSPI_0"}, @@ -159,7 +159,7 @@ struct ti_sci_devices_info j721e_devices_info[] = { [120] = {121, "J721E_DEV_C66SS0_INTROUTER0"}, [121] = {122, "J721E_DEV_C66SS1_INTROUTER0"}, [122] = {123, "J721E_DEV_CMPEVENT_INTRTR0"}, - [123] = {124, "J721E_DEV_J7_LASCAR_GPU_WRAP_MAIN_0"}, + [123] = {124, "J721E_DEV_GPU0"}, [124] = {125, "J721E_DEV_GPU0_GPU_0"}, [125] = {126, "J721E_DEV_GPU0_GPUCORE_0"}, [126] = {127, "J721E_DEV_LED0"}, @@ -174,8 +174,8 @@ struct ti_sci_devices_info j721e_devices_info[] = { [135] = {137, "J721E_DEV_WKUP_GPIOMUX_INTRTR0"}, [136] = {138, "J721E_DEV_WKUP_PSC0"}, [137] = {139, "J721E_DEV_AASRC0"}, - [138] = {140, "J721E_DEV_K3_C66_COREPAC_MAIN_0"}, - [139] = {141, "J721E_DEV_K3_C66_COREPAC_MAIN_1"}, + [138] = {140, "J721E_DEV_C66SS0"}, + [139] = {141, "J721E_DEV_C66SS1"}, [140] = {142, "J721E_DEV_C66SS0_CORE0"}, [141] = {143, "J721E_DEV_C66SS1_CORE0"}, [142] = {144, "J721E_DEV_DECODER0"}, @@ -230,7 +230,7 @@ struct ti_sci_devices_info j721e_devices_info[] = { [191] = {194, "J721E_DEV_MCU_I2C0"}, [192] = {195, "J721E_DEV_MCU_I2C1"}, [193] = {197, "J721E_DEV_WKUP_I2C0"}, - [194] = {199, "J721E_DEV_NAVSS512L_MAIN_0"}, + [194] = {199, "J721E_DEV_NAVSS0"}, [195] = {201, "J721E_DEV_NAVSS0_CPTS_0"}, [196] = {202, "J721E_DEV_A72SS0_CORE0"}, [197] = {203, "J721E_DEV_A72SS0_CORE1"}, @@ -260,24 +260,24 @@ struct ti_sci_devices_info j721e_devices_info[] = { [221] = {229, "J721E_DEV_NAVSS0_TCU_0"}, [222] = {230, "J721E_DEV_NAVSS0_TIMERMGR_0"}, [223] = {231, "J721E_DEV_NAVSS0_TIMERMGR_1"}, - [224] = {232, "J721E_DEV_NAVSS_MCU_J7_MCU_0"}, - [225] = {233, "J721E_DEV_MCU_NAVSS0_INTAGGR_0"}, - [226] = {234, "J721E_DEV_MCU_NAVSS0_PROXY_0"}, - [227] = {235, "J721E_DEV_MCU_NAVSS0_RINGACC_0"}, + [224] = {232, "J721E_DEV_MCU_NAVSS0"}, + [225] = {233, "J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0"}, + [226] = {234, "J721E_DEV_MCU_NAVSS0_PROXY0"}, + [227] = {235, "J721E_DEV_MCU_NAVSS0_RINGACC0"}, [228] = {236, "J721E_DEV_MCU_NAVSS0_UDMAP_0"}, - [229] = {237, "J721E_DEV_MCU_NAVSS0_INTR_ROUTER_0"}, + [229] = {237, "J721E_DEV_MCU_NAVSS0_INTR_0"}, [230] = {238, "J721E_DEV_MCU_NAVSS0_MCRC_0"}, [231] = {239, "J721E_DEV_PCIE0"}, [232] = {240, "J721E_DEV_PCIE1"}, [233] = {241, "J721E_DEV_PCIE2"}, [234] = {242, "J721E_DEV_PCIE3"}, - [235] = {243, "J721E_DEV_PULSAR_SL_MAIN_0"}, - [236] = {244, "J721E_DEV_PULSAR_SL_MAIN_1"}, + [235] = {243, "J721E_DEV_R5FSS0"}, + [236] = {244, "J721E_DEV_R5FSS1"}, [237] = {245, "J721E_DEV_R5FSS0_CORE0"}, [238] = {246, "J721E_DEV_R5FSS0_CORE1"}, [239] = {247, "J721E_DEV_R5FSS1_CORE0"}, [240] = {248, "J721E_DEV_R5FSS1_CORE1"}, - [241] = {249, "J721E_DEV_PULSAR_SL_MCU_0"}, + [241] = {249, "J721E_DEV_MCU_R5FSS0"}, [242] = {250, "J721E_DEV_MCU_R5FSS0_CORE0"}, [243] = {251, "J721E_DEV_MCU_R5FSS0_CORE1"}, [244] = {252, "J721E_DEV_RTI0"}, @@ -318,7 +318,7 @@ struct ti_sci_devices_info j721e_devices_info[] = { [279] = {287, "J721E_DEV_WKUP_UART0"}, [280] = {288, "J721E_DEV_USB0"}, [281] = {289, "J721E_DEV_USB1"}, - [282] = {290, "J721E_DEV_VPAC_TOP_MAIN_0"}, + [282] = {290, "J721E_DEV_VPAC0"}, [283] = {291, "J721E_DEV_VPFE0"}, [284] = {292, "J721E_DEV_SERDES_16G0"}, [285] = {293, "J721E_DEV_SERDES_16G1"}, diff --git a/soc/j721e/j721e_host_info.c b/soc/j721e/j721e_host_info.c index d257c23..e4b3d2b 100644 --- a/soc/j721e/j721e_host_info.c +++ b/soc/j721e/j721e_host_info.c @@ -36,30 +36,33 @@ #include struct ti_sci_host_info j721e_host_info[] = { - [0] = {0, "DMSC", "Secure", "Device Management and Security Control"}, - [1] = {3, "MCU_0_R5_0", "Non Secure", "Cortex R5 context 0 on MCU island"}, - [2] = {4, "MCU_0_R5_1", "Secure", "Cortex R5 context 1 on MCU island(Boot)"}, - [3] = {5, "MCU_0_R5_2", "Non Secure", "Cortex R5 context 2 on MCU island"}, - [4] = {6, "MCU_0_R5_3", "Secure", "Cortex R5 context 3 on MCU island"}, - [5] = {10, "A72_0", "Secure", "Cortex A72 context 0 on Main island"}, - [6] = {11, "A72_1", "Secure", "Cortex A72 context 1 on Main island"}, - [7] = {12, "A72_2", "Non Secure", "Cortex A72 context 2 on Main island"}, - [8] = {13, "A72_3", "Non Secure", "Cortex A72 context 3 on Main island"}, - [9] = {14, "A72_4", "Non Secure", "Cortex A72 context 4 on Main island"}, - [10] = {20, "C7X_0", "Secure", "C7x Context 0 on Main island"}, - [11] = {21, "C7X_1", "Non Secure", "C7x context 1 on Main island"}, - [12] = {25, "C6X_0_0", "Secure", "C6x_0 Context 0 on Main island"}, - [13] = {26, "C6X_0_1", "Non Secure", "C6x_0 context 1 on Main island"}, - [14] = {27, "C6X_1_0", "Secure", "C6x_1 Context 0 on Main island"}, - [15] = {28, "C6X_1_1", "Non Secure", "C6x_1 context 1 on Main island"}, - [16] = {30, "GPU_0", "Non Secure", "RGX context 0 on Main island"}, - [17] = {35, "MAIN_0_R5_0", "Non Secure", "Cortex R5_0 context 0 on Main island"}, - [18] = {36, "MAIN_0_R5_1", "Secure", "Cortex R5_0 context 1 on Main island"}, - [19] = {37, "MAIN_0_R5_2", "Non Secure", "Cortex R5_0 context 2 on Main island"}, - [20] = {38, "MAIN_0_R5_3", "Secure", "Cortex R5_0 context 3 on MCU island"}, - [21] = {40, "MAIN_1_R5_0", "Non Secure", "Cortex R5_1 context 0 on Main island"}, - [22] = {41, "MAIN_1_R5_1", "Secure", "Cortex R5_1 context 1 on Main island"}, - [23] = {42, "MAIN_1_R5_2", "Non Secure", "Cortex R5_1 context 2 on Main island"}, - [24] = {43, "MAIN_1_R5_3", "Secure", "Cortex R5_1 context 3 on MCU island"}, - [25] = {50, "ICSSG_0", "Non Secure", "ICSSG context 0 on Main island"}, + [0] = {0, "DMSC", "Secure", "Security Controller"}, + [1] = {254, "DM", "Non Secure", "Device Management"}, + [2] = {3, "MCU_0_R5_0", "Non Secure", "Cortex R5 context 0 on MCU island"}, + [3] = {4, "MCU_0_R5_1", "Secure", "Cortex R5 context 1 on MCU island(Boot)"}, + [4] = {5, "MCU_0_R5_2", "Non Secure", "Cortex R5 context 2 on MCU island"}, + [5] = {6, "MCU_0_R5_3", "Secure", "Cortex R5 context 3 on MCU island"}, + [6] = {10, "A72_0", "Secure", "Cortex A72 context 0 on Main island"}, + [7] = {11, "A72_1", "Secure", "Cortex A72 context 1 on Main island"}, + [8] = {12, "A72_2", "Non Secure", "Cortex A72 context 2 on Main island"}, + [9] = {13, "A72_3", "Non Secure", "Cortex A72 context 3 on Main island"}, + [10] = {14, "A72_4", "Non Secure", "Cortex A72 context 4 on Main island"}, + [11] = {20, "C7X_0", "Secure", "C7x Context 0 on Main island"}, + [12] = {21, "C7X_1", "Non Secure", "C7x context 1 on Main island"}, + [13] = {25, "C6X_0_0", "Secure", "C6x_0 Context 0 on Main island"}, + [14] = {26, "C6X_0_1", "Non Secure", "C6x_0 context 1 on Main island"}, + [15] = {27, "C6X_1_0", "Secure", "C6x_1 Context 0 on Main island"}, + [16] = {28, "C6X_1_1", "Non Secure", "C6x_1 context 1 on Main island"}, + [17] = {30, "GPU_0", "Non Secure", "RGX context 0 on Main island"}, + [18] = {35, "MAIN_0_R5_0", "Non Secure", "Cortex R5_0 context 0 on Main island"}, + [19] = {36, "MAIN_0_R5_1", "Secure", "Cortex R5_0 context 1 on Main island"}, + [20] = {37, "MAIN_0_R5_2", "Non Secure", "Cortex R5_0 context 2 on Main island"}, + [21] = {38, "MAIN_0_R5_3", "Secure", "Cortex R5_0 context 3 on MCU island"}, + [22] = {40, "MAIN_1_R5_0", "Non Secure", "Cortex R5_1 context 0 on Main island"}, + [23] = {41, "MAIN_1_R5_1", "Secure", "Cortex R5_1 context 1 on Main island"}, + [24] = {42, "MAIN_1_R5_2", "Non Secure", "Cortex R5_1 context 2 on Main island"}, + [25] = {43, "MAIN_1_R5_3", "Secure", "Cortex R5_1 context 3 on MCU island"}, + [26] = {50, "ICSSG_0", "Non Secure", "ICSSG context 0 on Main island"}, + [27] = {250, "DM2DMSC", "Secure", "DM to DMSC communication"}, + [28] = {251, "DMSC2DM", "Non Secure", "DMSC to DM communication"}, }; diff --git a/soc/j721e/j721e_host_info.h b/soc/j721e/j721e_host_info.h index 781648f..6e162eb 100644 --- a/soc/j721e/j721e_host_info.h +++ b/soc/j721e/j721e_host_info.h @@ -36,6 +36,7 @@ #define __J721E_HOST_INFO_H #define J721E_HOST_ID_DMSC 0 +#define J721E_HOST_ID_DM 254 #define J721E_HOST_ID_MCU_0_R5_0 3 #define J721E_HOST_ID_MCU_0_R5_1 4 #define J721E_HOST_ID_MCU_0_R5_2 5 @@ -61,8 +62,10 @@ #define J721E_HOST_ID_MAIN_1_R5_2 42 #define J721E_HOST_ID_MAIN_1_R5_3 43 #define J721E_HOST_ID_ICSSG_0 50 +#define J721E_HOST_ID_DM2DMSC 250 +#define J721E_HOST_ID_DMSC2DM 251 -#define J721E_MAX_HOST_IDS 26 +#define J721E_MAX_HOST_IDS 29 extern struct ti_sci_host_info j721e_host_info[]; diff --git a/soc/j721e/j721e_processors_info.c b/soc/j721e/j721e_processors_info.c index 4e07310..193865c 100644 --- a/soc/j721e/j721e_processors_info.c +++ b/soc/j721e/j721e_processors_info.c @@ -1,5 +1,5 @@ /* - * SoC Processors Info + * J721E Processor Info * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * diff --git a/soc/j721e/j721e_sec_proxy_info.c b/soc/j721e/j721e_sec_proxy_info.c index 5280157..d74fa25 100644 --- a/soc/j721e/j721e_sec_proxy_info.c +++ b/soc/j721e/j721e_sec_proxy_info.c @@ -36,132 +36,178 @@ #include struct ti_sci_sec_proxy_info j721e_main_sp_info[] = { - [0] = {0, "read", 2, "A72_0", "notify"}, - [1] = {1, "read", 30, "A72_0", "response"}, - [2] = {2, "write", 10, "A72_0", "high_priority"}, - [3] = {3, "write", 20, "A72_0", "low_priority"}, - [4] = {4, "write", 2, "A72_0", "notify_resp"}, - [5] = {5, "read", 2, "A72_1", "notify"}, - [6] = {6, "read", 30, "A72_1", "response"}, - [7] = {7, "write", 10, "A72_1", "high_priority"}, - [8] = {8, "write", 20, "A72_1", "low_priority"}, - [9] = {9, "write", 2, "A72_1", "notify_resp"}, - [10] = {10, "read", 2, "A72_2", "notify"}, - [11] = {11, "read", 22, "A72_2", "response"}, - [12] = {12, "write", 2, "A72_2", "high_priority"}, - [13] = {13, "write", 20, "A72_2", "low_priority"}, - [14] = {14, "write", 2, "A72_2", "notify_resp"}, - [15] = {15, "read", 2, "A72_3", "notify"}, - [16] = {16, "read", 7, "A72_3", "response"}, - [17] = {17, "write", 2, "A72_3", "high_priority"}, - [18] = {18, "write", 5, "A72_3", "low_priority"}, - [19] = {19, "write", 2, "A72_3", "notify_resp"}, - [20] = {20, "read", 2, "A72_4", "notify"}, - [21] = {21, "read", 7, "A72_4", "response"}, - [22] = {22, "write", 2, "A72_4", "high_priority"}, - [23] = {23, "write", 5, "A72_4", "low_priority"}, - [24] = {24, "write", 2, "A72_4", "notify_resp"}, - [25] = {25, "read", 2, "C7X_0", "notify"}, - [26] = {26, "read", 7, "C7X_0", "response"}, - [27] = {27, "write", 2, "C7X_0", "high_priority"}, - [28] = {28, "write", 5, "C7X_0", "low_priority"}, - [29] = {29, "write", 2, "C7X_0", "notify_resp"}, - [30] = {30, "read", 2, "C7X_1", "notify"}, - [31] = {31, "read", 7, "C7X_1", "response"}, - [32] = {32, "write", 2, "C7X_1", "high_priority"}, - [33] = {33, "write", 5, "C7X_1", "low_priority"}, - [34] = {34, "write", 2, "C7X_1", "notify_resp"}, - [35] = {35, "read", 2, "C6X_0_0", "notify"}, - [36] = {36, "read", 7, "C6X_0_0", "response"}, - [37] = {37, "write", 2, "C6X_0_0", "high_priority"}, - [38] = {38, "write", 5, "C6X_0_0", "low_priority"}, - [39] = {39, "write", 2, "C6X_0_0", "notify_resp"}, - [40] = {40, "read", 2, "C6X_0_1", "notify"}, - [41] = {41, "read", 7, "C6X_0_1", "response"}, - [42] = {42, "write", 2, "C6X_0_1", "high_priority"}, - [43] = {43, "write", 5, "C6X_0_1", "low_priority"}, - [44] = {44, "write", 2, "C6X_0_1", "notify_resp"}, - [45] = {45, "read", 2, "C6X_1_0", "notify"}, - [46] = {46, "read", 7, "C6X_1_0", "response"}, - [47] = {47, "write", 2, "C6X_1_0", "high_priority"}, - [48] = {48, "write", 5, "C6X_1_0", "low_priority"}, - [49] = {49, "write", 2, "C6X_1_0", "notify_resp"}, - [50] = {50, "read", 2, "C6X_1_1", "notify"}, - [51] = {51, "read", 7, "C6X_1_1", "response"}, - [52] = {52, "write", 2, "C6X_1_1", "high_priority"}, - [53] = {53, "write", 5, "C6X_1_1", "low_priority"}, - [54] = {54, "write", 2, "C6X_1_1", "notify_resp"}, - [55] = {55, "read", 2, "GPU_0", "notify"}, - [56] = {56, "read", 7, "GPU_0", "response"}, - [57] = {57, "write", 2, "GPU_0", "high_priority"}, - [58] = {58, "write", 5, "GPU_0", "low_priority"}, - [59] = {59, "write", 2, "GPU_0", "notify_resp"}, - [60] = {60, "read", 2, "MAIN_0_R5_0", "notify"}, - [61] = {61, "read", 7, "MAIN_0_R5_0", "response"}, - [62] = {62, "write", 2, "MAIN_0_R5_0", "high_priority"}, - [63] = {63, "write", 5, "MAIN_0_R5_0", "low_priority"}, - [64] = {64, "write", 2, "MAIN_0_R5_0", "notify_resp"}, - [65] = {65, "read", 2, "MAIN_0_R5_1", "notify"}, - [66] = {66, "read", 7, "MAIN_0_R5_1", "response"}, - [67] = {67, "write", 2, "MAIN_0_R5_1", "high_priority"}, - [68] = {68, "write", 5, "MAIN_0_R5_1", "low_priority"}, - [69] = {69, "write", 2, "MAIN_0_R5_1", "notify_resp"}, - [70] = {70, "read", 1, "MAIN_0_R5_2", "notify"}, - [71] = {71, "read", 2, "MAIN_0_R5_2", "response"}, - [72] = {72, "write", 1, "MAIN_0_R5_2", "high_priority"}, - [73] = {73, "write", 1, "MAIN_0_R5_2", "low_priority"}, - [74] = {74, "write", 1, "MAIN_0_R5_2", "notify_resp"}, - [75] = {75, "read", 1, "MAIN_0_R5_3", "notify"}, - [76] = {76, "read", 2, "MAIN_0_R5_3", "response"}, - [77] = {77, "write", 1, "MAIN_0_R5_3", "high_priority"}, - [78] = {78, "write", 1, "MAIN_0_R5_3", "low_priority"}, - [79] = {79, "write", 1, "MAIN_0_R5_3", "notify_resp"}, - [80] = {80, "read", 2, "MAIN_1_R5_0", "notify"}, - [81] = {81, "read", 7, "MAIN_1_R5_0", "response"}, - [82] = {82, "write", 2, "MAIN_1_R5_0", "high_priority"}, - [83] = {83, "write", 5, "MAIN_1_R5_0", "low_priority"}, - [84] = {84, "write", 2, "MAIN_1_R5_0", "notify_resp"}, - [85] = {85, "read", 2, "MAIN_1_R5_1", "notify"}, - [86] = {86, "read", 7, "MAIN_1_R5_1", "response"}, - [87] = {87, "write", 2, "MAIN_1_R5_1", "high_priority"}, - [88] = {88, "write", 5, "MAIN_1_R5_1", "low_priority"}, - [89] = {89, "write", 2, "MAIN_1_R5_1", "notify_resp"}, - [90] = {90, "read", 1, "MAIN_1_R5_2", "notify"}, - [91] = {91, "read", 2, "MAIN_1_R5_2", "response"}, - [92] = {92, "write", 1, "MAIN_1_R5_2", "high_priority"}, - [93] = {93, "write", 1, "MAIN_1_R5_2", "low_priority"}, - [94] = {94, "write", 1, "MAIN_1_R5_2", "notify_resp"}, - [95] = {95, "read", 1, "MAIN_1_R5_3", "notify"}, - [96] = {96, "read", 2, "MAIN_1_R5_3", "response"}, - [97] = {97, "write", 1, "MAIN_1_R5_3", "high_priority"}, - [98] = {98, "write", 1, "MAIN_1_R5_3", "low_priority"}, - [99] = {99, "write", 1, "MAIN_1_R5_3", "notify_resp"}, - [100] = {100, "read", 2, "ICSSG_0", "notify"}, - [101] = {101, "read", 7, "ICSSG_0", "response"}, - [102] = {102, "write", 2, "ICSSG_0", "high_priority"}, - [103] = {103, "write", 5, "ICSSG_0", "low_priority"}, - [104] = {104, "write", 2, "ICSSG_0", "notify_resp"}, + [0] = {138, "read", 22, "DM", "nonsec_high_priority_rx"}, + [1] = {137, "read", 67, "DM", "nonsec_low_priority_rx"}, + [2] = {136, "read", 22, "DM", "nonsec_notify_resp_rx"}, + [3] = {135, "write", 2, "DM", "nonsec_A72_2_notify_tx"}, + [4] = {134, "write", 22, "DM", "nonsec_A72_2_response_tx"}, + [5] = {133, "write", 2, "DM", "nonsec_A72_3_notify_tx"}, + [6] = {132, "write", 7, "DM", "nonsec_A72_3_response_tx"}, + [7] = {131, "write", 2, "DM", "nonsec_A72_4_notify_tx"}, + [8] = {130, "write", 7, "DM", "nonsec_A72_4_response_tx"}, + [9] = {129, "write", 2, "DM", "nonsec_C7X_1_notify_tx"}, + [10] = {128, "write", 7, "DM", "nonsec_C7X_1_response_tx"}, + [11] = {127, "write", 2, "DM", "nonsec_C6X_0_1_notify_tx"}, + [12] = {126, "write", 7, "DM", "nonsec_C6X_0_1_response_tx"}, + [13] = {125, "write", 2, "DM", "nonsec_C6X_1_1_notify_tx"}, + [14] = {124, "write", 7, "DM", "nonsec_C6X_1_1_response_tx"}, + [15] = {123, "write", 2, "DM", "nonsec_GPU_0_notify_tx"}, + [16] = {122, "write", 7, "DM", "nonsec_GPU_0_response_tx"}, + [17] = {121, "write", 2, "DM", "nonsec_MAIN_0_R5_0_notify_tx"}, + [18] = {120, "write", 7, "DM", "nonsec_MAIN_0_R5_0_response_tx"}, + [19] = {119, "write", 1, "DM", "nonsec_MAIN_0_R5_2_notify_tx"}, + [20] = {118, "write", 2, "DM", "nonsec_MAIN_0_R5_2_response_tx"}, + [21] = {117, "write", 2, "DM", "nonsec_MAIN_1_R5_0_notify_tx"}, + [22] = {116, "write", 7, "DM", "nonsec_MAIN_1_R5_0_response_tx"}, + [23] = {115, "write", 1, "DM", "nonsec_MAIN_1_R5_2_notify_tx"}, + [24] = {114, "write", 2, "DM", "nonsec_MAIN_1_R5_2_response_tx"}, + [25] = {113, "write", 2, "DM", "nonsec_ICSSG_0_notify_tx"}, + [26] = {112, "write", 7, "DM", "nonsec_ICSSG_0_response_tx"}, + [27] = {0, "read", 2, "A72_0", "notify"}, + [28] = {1, "read", 30, "A72_0", "response"}, + [29] = {2, "write", 10, "A72_0", "high_priority"}, + [30] = {3, "write", 20, "A72_0", "low_priority"}, + [31] = {4, "write", 2, "A72_0", "notify_resp"}, + [32] = {5, "read", 2, "A72_1", "notify"}, + [33] = {6, "read", 30, "A72_1", "response"}, + [34] = {7, "write", 10, "A72_1", "high_priority"}, + [35] = {8, "write", 20, "A72_1", "low_priority"}, + [36] = {9, "write", 2, "A72_1", "notify_resp"}, + [37] = {10, "read", 2, "A72_2", "notify"}, + [38] = {11, "read", 22, "A72_2", "response"}, + [39] = {12, "write", 2, "A72_2", "high_priority"}, + [40] = {13, "write", 20, "A72_2", "low_priority"}, + [41] = {14, "write", 2, "A72_2", "notify_resp"}, + [42] = {15, "read", 2, "A72_3", "notify"}, + [43] = {16, "read", 7, "A72_3", "response"}, + [44] = {17, "write", 2, "A72_3", "high_priority"}, + [45] = {18, "write", 5, "A72_3", "low_priority"}, + [46] = {19, "write", 2, "A72_3", "notify_resp"}, + [47] = {20, "read", 2, "A72_4", "notify"}, + [48] = {21, "read", 7, "A72_4", "response"}, + [49] = {22, "write", 2, "A72_4", "high_priority"}, + [50] = {23, "write", 5, "A72_4", "low_priority"}, + [51] = {24, "write", 2, "A72_4", "notify_resp"}, + [52] = {25, "read", 2, "C7X_0", "notify"}, + [53] = {26, "read", 7, "C7X_0", "response"}, + [54] = {27, "write", 2, "C7X_0", "high_priority"}, + [55] = {28, "write", 5, "C7X_0", "low_priority"}, + [56] = {29, "write", 2, "C7X_0", "notify_resp"}, + [57] = {30, "read", 2, "C7X_1", "notify"}, + [58] = {31, "read", 7, "C7X_1", "response"}, + [59] = {32, "write", 2, "C7X_1", "high_priority"}, + [60] = {33, "write", 5, "C7X_1", "low_priority"}, + [61] = {34, "write", 2, "C7X_1", "notify_resp"}, + [62] = {35, "read", 2, "C6X_0_0", "notify"}, + [63] = {36, "read", 7, "C6X_0_0", "response"}, + [64] = {37, "write", 2, "C6X_0_0", "high_priority"}, + [65] = {38, "write", 5, "C6X_0_0", "low_priority"}, + [66] = {39, "write", 2, "C6X_0_0", "notify_resp"}, + [67] = {40, "read", 2, "C6X_0_1", "notify"}, + [68] = {41, "read", 7, "C6X_0_1", "response"}, + [69] = {42, "write", 2, "C6X_0_1", "high_priority"}, + [70] = {43, "write", 5, "C6X_0_1", "low_priority"}, + [71] = {44, "write", 2, "C6X_0_1", "notify_resp"}, + [72] = {45, "read", 2, "C6X_1_0", "notify"}, + [73] = {46, "read", 7, "C6X_1_0", "response"}, + [74] = {47, "write", 2, "C6X_1_0", "high_priority"}, + [75] = {48, "write", 5, "C6X_1_0", "low_priority"}, + [76] = {49, "write", 2, "C6X_1_0", "notify_resp"}, + [77] = {50, "read", 2, "C6X_1_1", "notify"}, + [78] = {51, "read", 7, "C6X_1_1", "response"}, + [79] = {52, "write", 2, "C6X_1_1", "high_priority"}, + [80] = {53, "write", 5, "C6X_1_1", "low_priority"}, + [81] = {54, "write", 2, "C6X_1_1", "notify_resp"}, + [82] = {55, "read", 2, "GPU_0", "notify"}, + [83] = {56, "read", 7, "GPU_0", "response"}, + [84] = {57, "write", 2, "GPU_0", "high_priority"}, + [85] = {58, "write", 5, "GPU_0", "low_priority"}, + [86] = {59, "write", 2, "GPU_0", "notify_resp"}, + [87] = {60, "read", 2, "MAIN_0_R5_0", "notify"}, + [88] = {61, "read", 7, "MAIN_0_R5_0", "response"}, + [89] = {62, "write", 2, "MAIN_0_R5_0", "high_priority"}, + [90] = {63, "write", 5, "MAIN_0_R5_0", "low_priority"}, + [91] = {64, "write", 2, "MAIN_0_R5_0", "notify_resp"}, + [92] = {65, "read", 2, "MAIN_0_R5_1", "notify"}, + [93] = {66, "read", 7, "MAIN_0_R5_1", "response"}, + [94] = {67, "write", 2, "MAIN_0_R5_1", "high_priority"}, + [95] = {68, "write", 5, "MAIN_0_R5_1", "low_priority"}, + [96] = {69, "write", 2, "MAIN_0_R5_1", "notify_resp"}, + [97] = {70, "read", 1, "MAIN_0_R5_2", "notify"}, + [98] = {71, "read", 2, "MAIN_0_R5_2", "response"}, + [99] = {72, "write", 1, "MAIN_0_R5_2", "high_priority"}, + [100] = {73, "write", 1, "MAIN_0_R5_2", "low_priority"}, + [101] = {74, "write", 1, "MAIN_0_R5_2", "notify_resp"}, + [102] = {75, "read", 1, "MAIN_0_R5_3", "notify"}, + [103] = {76, "read", 2, "MAIN_0_R5_3", "response"}, + [104] = {77, "write", 1, "MAIN_0_R5_3", "high_priority"}, + [105] = {78, "write", 1, "MAIN_0_R5_3", "low_priority"}, + [106] = {79, "write", 1, "MAIN_0_R5_3", "notify_resp"}, + [107] = {80, "read", 2, "MAIN_1_R5_0", "notify"}, + [108] = {81, "read", 7, "MAIN_1_R5_0", "response"}, + [109] = {82, "write", 2, "MAIN_1_R5_0", "high_priority"}, + [110] = {83, "write", 5, "MAIN_1_R5_0", "low_priority"}, + [111] = {84, "write", 2, "MAIN_1_R5_0", "notify_resp"}, + [112] = {85, "read", 2, "MAIN_1_R5_1", "notify"}, + [113] = {86, "read", 7, "MAIN_1_R5_1", "response"}, + [114] = {87, "write", 2, "MAIN_1_R5_1", "high_priority"}, + [115] = {88, "write", 5, "MAIN_1_R5_1", "low_priority"}, + [116] = {89, "write", 2, "MAIN_1_R5_1", "notify_resp"}, + [117] = {90, "read", 1, "MAIN_1_R5_2", "notify"}, + [118] = {91, "read", 2, "MAIN_1_R5_2", "response"}, + [119] = {92, "write", 1, "MAIN_1_R5_2", "high_priority"}, + [120] = {93, "write", 1, "MAIN_1_R5_2", "low_priority"}, + [121] = {94, "write", 1, "MAIN_1_R5_2", "notify_resp"}, + [122] = {95, "read", 1, "MAIN_1_R5_3", "notify"}, + [123] = {96, "read", 2, "MAIN_1_R5_3", "response"}, + [124] = {97, "write", 1, "MAIN_1_R5_3", "high_priority"}, + [125] = {98, "write", 1, "MAIN_1_R5_3", "low_priority"}, + [126] = {99, "write", 1, "MAIN_1_R5_3", "notify_resp"}, + [127] = {100, "read", 2, "ICSSG_0", "notify"}, + [128] = {101, "read", 7, "ICSSG_0", "response"}, + [129] = {102, "write", 2, "ICSSG_0", "high_priority"}, + [130] = {103, "write", 5, "ICSSG_0", "low_priority"}, + [131] = {104, "write", 2, "ICSSG_0", "notify_resp"}, }; struct ti_sci_sec_proxy_info j721e_mcu_sp_info[] = { - [0] = {0, "read", 2, "MCU_0_R5_0", "notify"}, - [1] = {1, "read", 7, "MCU_0_R5_0", "response"}, - [2] = {2, "write", 2, "MCU_0_R5_0", "high_priority"}, - [3] = {3, "write", 5, "MCU_0_R5_0", "low_priority"}, - [4] = {4, "write", 2, "MCU_0_R5_0", "notify_resp"}, - [5] = {5, "read", 2, "MCU_0_R5_1", "notify"}, - [6] = {6, "read", 7, "MCU_0_R5_1", "response"}, - [7] = {7, "write", 2, "MCU_0_R5_1", "high_priority"}, - [8] = {8, "write", 5, "MCU_0_R5_1", "low_priority"}, - [9] = {9, "write", 2, "MCU_0_R5_1", "notify_resp"}, - [10] = {10, "read", 1, "MCU_0_R5_2", "notify"}, - [11] = {11, "read", 2, "MCU_0_R5_2", "response"}, - [12] = {12, "write", 1, "MCU_0_R5_2", "high_priority"}, - [13] = {13, "write", 1, "MCU_0_R5_2", "low_priority"}, - [14] = {14, "write", 1, "MCU_0_R5_2", "notify_resp"}, - [15] = {15, "read", 1, "MCU_0_R5_3", "notify"}, - [16] = {16, "read", 2, "MCU_0_R5_3", "response"}, - [17] = {17, "write", 1, "MCU_0_R5_3", "high_priority"}, - [18] = {18, "write", 1, "MCU_0_R5_3", "low_priority"}, - [19] = {19, "write", 1, "MCU_0_R5_3", "notify_resp"}, + [0] = {80, "read", 13, "DM", "nonsec_high_priority_rx"}, + [1] = {79, "read", 13, "DM", "nonsec_low_priority_rx"}, + [2] = {78, "read", 5, "DM", "nonsec_notify_resp_rx"}, + [3] = {77, "write", 2, "DM", "nonsec_MCU_0_R5_0_notify_tx"}, + [4] = {76, "write", 20, "DM", "nonsec_MCU_0_R5_0_response_tx"}, + [5] = {75, "write", 1, "DM", "nonsec_MCU_0_R5_2_notify_tx"}, + [6] = {74, "write", 2, "DM", "nonsec_MCU_0_R5_2_response_tx"}, + [7] = {73, "write", 2, "DM", "nonsec_DMSC2DM_notify_tx"}, + [8] = {72, "write", 4, "DM", "nonsec_DMSC2DM_response_tx"}, + [9] = {0, "read", 2, "MCU_0_R5_0", "notify"}, + [10] = {1, "read", 20, "MCU_0_R5_0", "response"}, + [11] = {2, "write", 10, "MCU_0_R5_0", "high_priority"}, + [12] = {3, "write", 10, "MCU_0_R5_0", "low_priority"}, + [13] = {4, "write", 2, "MCU_0_R5_0", "notify_resp"}, + [14] = {5, "read", 2, "MCU_0_R5_1", "notify"}, + [15] = {6, "read", 20, "MCU_0_R5_1", "response"}, + [16] = {7, "write", 10, "MCU_0_R5_1", "high_priority"}, + [17] = {8, "write", 10, "MCU_0_R5_1", "low_priority"}, + [18] = {9, "write", 2, "MCU_0_R5_1", "notify_resp"}, + [19] = {10, "read", 1, "MCU_0_R5_2", "notify"}, + [20] = {11, "read", 2, "MCU_0_R5_2", "response"}, + [21] = {12, "write", 1, "MCU_0_R5_2", "high_priority"}, + [22] = {13, "write", 1, "MCU_0_R5_2", "low_priority"}, + [23] = {14, "write", 1, "MCU_0_R5_2", "notify_resp"}, + [24] = {15, "read", 1, "MCU_0_R5_3", "notify"}, + [25] = {16, "read", 2, "MCU_0_R5_3", "response"}, + [26] = {17, "write", 1, "MCU_0_R5_3", "high_priority"}, + [27] = {18, "write", 1, "MCU_0_R5_3", "low_priority"}, + [28] = {19, "write", 1, "MCU_0_R5_3", "notify_resp"}, + [29] = {20, "read", 2, "DM2DMSC", "notify"}, + [30] = {21, "read", 4, "DM2DMSC", "response"}, + [31] = {22, "write", 2, "DM2DMSC", "high_priority"}, + [32] = {23, "write", 2, "DM2DMSC", "low_priority"}, + [33] = {24, "write", 2, "DM2DMSC", "notify_resp"}, + [34] = {25, "read", 2, "DMSC2DM", "notify"}, + [35] = {26, "read", 4, "DMSC2DM", "response"}, + [36] = {27, "write", 2, "DMSC2DM", "high_priority"}, + [37] = {28, "write", 2, "DMSC2DM", "low_priority"}, + [38] = {29, "write", 2, "DMSC2DM", "notify_resp"}, }; diff --git a/soc/j721e/j721e_sec_proxy_info.h b/soc/j721e/j721e_sec_proxy_info.h index bae26dd..6f36fac 100644 --- a/soc/j721e/j721e_sec_proxy_info.h +++ b/soc/j721e/j721e_sec_proxy_info.h @@ -35,8 +35,8 @@ #ifndef __J721E_SEC_PROXY_INFO_H #define __J721E_SEC_PROXY_INFO_H -#define J721E_MAIN_SEC_PROXY_THREADS 105 -#define J721E_MCU_SEC_PROXY_THREADS 20 +#define J721E_MAIN_SEC_PROXY_THREADS 132 +#define J721E_MCU_SEC_PROXY_THREADS 39 extern struct ti_sci_sec_proxy_info j721e_main_sp_info[]; extern struct ti_sci_sec_proxy_info j721e_mcu_sp_info[]; -- 2.26.2