tci6638: fix number of netcp packet dma rx channels
tci6638 netcp packet dma has 26 rx channels. The last two channels are
dedicated for netcp slave port 2 end port 3 correspondingly.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638 netcp packet dma has 26 rx channels. The last two channels are
dedicated for netcp slave port 2 end port 3 correspondingly.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone2: correct number of gmac slave ports
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone2: fix number of ports
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone2: add tail to the emac_regs struct
This patch adds a reserve filed to the end of the emac_regs structure.
That corrects offset to the next MAC when using pointer arithmetic or
array of MACs.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
This patch adds a reserve filed to the end of the emac_regs structure.
That corrects offset to the next MAC when using pointer arithmetic or
array of MACs.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone2: add eht2 and eth3 interfaces
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
usb: remove unnecessary print in reset port
Since only USB 3.0 hub supports port warm resets and usb core
layer resets hub ports by default during a hub init. So if
port reset fails, it does not necessarily mean it is an error
and prints out an error message. This patch changes such
printf to a bedug print to avoid unnecessary alerts.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Since only USB 3.0 hub supports port warm resets and usb core
layer resets hub ports by default during a hub init. So if
port reset fails, it does not necessarily mean it is an error
and prints out an error message. This patch changes such
printf to a bedug print to avoid unnecessary alerts.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
usb: add support of usb3 device connected to usb3 hub
Support of USB 3.0 device connected to a USB 3.0 hub
is missing in USB 3.0 XHCI patch submitted by 3rd party
to mainline U-boot. This patch adds support of such use
case on top of the XHCI patch.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Support of USB 3.0 device connected to a USB 3.0 hub
is missing in USB 3.0 XHCI patch submitted by 3rd party
to mainline U-boot. This patch adds support of such use
case on top of the XHCI patch.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
tci6638: [tmp] add delays after usb port power is set
This patch adds a delay after enabling usb port power.
After updating the UCD on Keystone2 Rev2.0 and Rev3.0 EVM as a
workaround to the "5V rail turned off due to overshoot/undershoot
protection" issue, a time delay is needed after the usb port power
is enabled before the portsc register shows any connection status
change.
The amount of delay needed depends on the USB flash drives tested.
For USB2.0 flash drives, no delay is needed. For the USB3.0 flash
drives tested, the delay ranges from 0 to about 3 sec. Also, the
USB2.0 port power delay affects the amount of USB3.0 port power
delay needed.
Furthermore, even though capacitor C387 is removed on Rev3.0
Keystone2 EVMs as an alternative workaround to the original 5V rail
issue, UCD update is still needed on these EVMs in order for the
USB to work consistently with the aforementioned time delay added.
Further HW diagnosis is needed to root cause the problem.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
This patch adds a delay after enabling usb port power.
After updating the UCD on Keystone2 Rev2.0 and Rev3.0 EVM as a
workaround to the "5V rail turned off due to overshoot/undershoot
protection" issue, a time delay is needed after the usb port power
is enabled before the portsc register shows any connection status
change.
The amount of delay needed depends on the USB flash drives tested.
For USB2.0 flash drives, no delay is needed. For the USB3.0 flash
drives tested, the delay ranges from 0 to about 3 sec. Also, the
USB2.0 port power delay affects the amount of USB3.0 port power
delay needed.
Furthermore, even though capacitor C387 is removed on Rev3.0
Keystone2 EVMs as an alternative workaround to the original 5V rail
issue, UCD update is still needed on these EVMs in order for the
USB to work consistently with the aforementioned time delay added.
Further HW diagnosis is needed to root cause the problem.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
keystone: enable UART1
Currently PWREMU_MGMT is not configured in the Linux generic UART
driver as this register seems to be specific TI UART IP. So this
needs to be enabled in u-boot to use UART1 from kernel space.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Currently PWREMU_MGMT is not configured in the Linux generic UART
driver as this register seems to be specific TI UART IP. So this
needs to be enabled in u-boot to use UART1 from kernel space.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
tci6638: fix reset type check in ddr3 workaround
This patch fixes reset type check and removes some unnecessary
lines of code.
Signed-off-by: Cesar Iovescu <icesar@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
This patch fixes reset type check and removes some unnecessary
lines of code.
Signed-off-by: Cesar Iovescu <icesar@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
tci6638: correct i2c address length to read DIMM SPD data
The get_dimm_params() reads the data with wrong address length.
This patch fixes the bug.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
The get_dimm_params() reads the data with wrong address length.
This patch fixes the bug.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone2: net: close all opened resources in case of error
The tci6614_eth_open may not finish its job and exit with an error.
In that case it should close all already opened by that time resources.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
The tci6614_eth_open may not finish its job and exit with an error.
In that case it should close all already opened by that time resources.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: display DDR3 capacity for 8GiB SO-DIMM
Currently for 8GiB SO-DIMM, u-boot doesn't display DDR3 memory size.
As U-Boot currently can't detect beyond 2GiB, user needs some way to
know the DDR3 avaialble capacity. This patch adds this info in the
below format in u-boot boot up log.
DRAM: Capacity 8 GiB (includes reported below)
DRAM: 2 GiB
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Currently for 8GiB SO-DIMM, u-boot doesn't display DDR3 memory size.
As U-Boot currently can't detect beyond 2GiB, user needs some way to
know the DDR3 avaialble capacity. This patch adds this info in the
below format in u-boot boot up log.
DRAM: Capacity 8 GiB (includes reported below)
DRAM: 2 GiB
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
keystone: remove main PLL clock change option
This is currently not supported and is removed
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
This is currently not supported and is removed
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
tci6638: workaround for ddr3a/3b memory issue
This patch implements a workaround to fix DDR3 memory issue.
the code for workaround detects PGSR0 errors and then preps for
and executes a software-controlled hard reset. In board_early_init,
where logic has been added to identify whether or not the previous
reset was a PORz. PLL initialization is skipped in the case of a
software-controlled hard reset. The workaround is in sync with
v1.5 of the Gel file
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Keegan Garcia <kgarcia@ti.com>
This patch implements a workaround to fix DDR3 memory issue.
the code for workaround detects PGSR0 errors and then preps for
and executes a software-controlled hard reset. In board_early_init,
where logic has been added to identify whether or not the previous
reset was a PORz. PLL initialization is skipped in the case of a
software-controlled hard reset. The workaround is in sync with
v1.5 of the Gel file
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Keegan Garcia <kgarcia@ti.com>
keystone: net: update sgmii serdes configuration
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
tci6638: set TETRIS PLL to 1.2GHz and CORE to 1.2288GHz
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: fix DDR3A configuration for 8GB DIMM
This patch fixes a bug in the ddr3phy_1600_64A configuration.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
This patch fixes a bug in the ddr3phy_1600_64A configuration.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: restore i2c bus number after getting dimm parameters
The get_dimm_parameters changed the i2c bus number, which affects
the common eeprom read/write command, which assume EEPROM on the default
i2c bus.
This patch restores i2c bus after reading SPD data.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
The get_dimm_parameters changed the i2c bus number, which affects
the common eeprom read/write command, which assume EEPROM on the default
i2c bus.
This patch restores i2c bus after reading SPD data.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: add mtdparts for 512M NAND
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Add trailing zeroes in TI nand gph image
TI Keystone2 ROM bootloader expects 8 bytes of trailing zeroes in the
nand u-boot image. This commit implements that requirement.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
TI Keystone2 ROM bootloader expects 8 bytes of trailing zeroes in the
nand u-boot image. This commit implements that requirement.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
keystone: usb: modifications to align xhci updates with current u-boot
xhci updates are based on a later version of u-boot. This commit
modifies the xhci updates to align with current version of u-boot.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
xhci updates are based on a later version of u-boot. This commit
modifies the xhci updates to align with current version of u-boot.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
USB: XHCI: Add xHCI host controller stack driver
This commit is a cherry-pick of the patch
[PATCH v2 1/7] USB: xHCI: Add stack support for xHCI
(http://lists.denx.de/pipermail/u-boot/2013-August/161236.html)
submitted to mainstream u-boot by Vivek Gautam <gautam.vivek at samsung.com>
et al.
Comments from original patch:
This adds stack layer for eXtensible Host Controller Interface
which facilitates use of USB 3.0 in host mode.
Adapting xHCI host controller driver in linux-kernel
by Sarah Sharp to needs in u-boot.
This adds the basic xHCI host controller driver with bare minimum
features:
- Control/Bulk transfer support has been added with required
infrastructure for necessary xHC data structures.
- Stream protocol hasn't been supported yet.
- No support for quirky devices has been added.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
This commit is a cherry-pick of the patch
[PATCH v2 1/7] USB: xHCI: Add stack support for xHCI
(http://lists.denx.de/pipermail/u-boot/2013-August/161236.html)
submitted to mainstream u-boot by Vivek Gautam <gautam.vivek at samsung.com>
et al.
Comments from original patch:
This adds stack layer for eXtensible Host Controller Interface
which facilitates use of USB 3.0 in host mode.
Adapting xHCI host controller driver in linux-kernel
by Sarah Sharp to needs in u-boot.
This adds the basic xHCI host controller driver with bare minimum
features:
- Control/Bulk transfer support has been added with required
infrastructure for necessary xHC data structures.
- Stream protocol hasn't been supported yet.
- No support for quirky devices has been added.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
usb: ss: Some fixes and cleanup for USB super-speed support
This is a squashed commit of the following mainstream u-boot
commits. The purpose of cherry-picking these mainstream
u-boot commits is to facilitate some usb xhci fixes.
ceb4972a8f4082019f2b36bd24a27b5dedaa4801
usb: common: Weed out USB_**_PRINTFs from usb framework
605bd75af565011aa46e6d80a32e2aa03aff8159
USB: Some cleanup prior to USB 3.0 interface addition
020bbcb76b5be0d5406d2ae7c26dbdb013ead812
usb: hub: Power-cycle on root-hub ports
99c3491b78cc2a5e58f77da32c913f11fd16103f
usb: Update device class in usb device's descriptor
289f3cb28a3916b6c4c770db9a88463884be5b6c
usb: hub: Fix enumration timeout
6497c66704d03956e7ea49b54fcaa38740736416
USB: SS: Add support for Super Speed USB interface
0bf796f7ae22086f0504f3297e9fb4e96aa04161
usb: hub: Parallelize power-cycling of root-hub ports
55f4b57542de9f4bee8dc0b7ca70686bd20e2aa4
usb: fix: Fixing Port status and feature number constants
4f4eab4d14b181c3a9447c75fd2b41b9d0d761e4
usb: common: Use a global definition for 'min3'
This commit should not be picked alone without picking the next two
usb related commits in this series.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
This is a squashed commit of the following mainstream u-boot
commits. The purpose of cherry-picking these mainstream
u-boot commits is to facilitate some usb xhci fixes.
ceb4972a8f4082019f2b36bd24a27b5dedaa4801
usb: common: Weed out USB_**_PRINTFs from usb framework
605bd75af565011aa46e6d80a32e2aa03aff8159
USB: Some cleanup prior to USB 3.0 interface addition
020bbcb76b5be0d5406d2ae7c26dbdb013ead812
usb: hub: Power-cycle on root-hub ports
99c3491b78cc2a5e58f77da32c913f11fd16103f
usb: Update device class in usb device's descriptor
289f3cb28a3916b6c4c770db9a88463884be5b6c
usb: hub: Fix enumration timeout
6497c66704d03956e7ea49b54fcaa38740736416
USB: SS: Add support for Super Speed USB interface
0bf796f7ae22086f0504f3297e9fb4e96aa04161
usb: hub: Parallelize power-cycling of root-hub ports
55f4b57542de9f4bee8dc0b7ca70686bd20e2aa4
usb: fix: Fixing Port status and feature number constants
4f4eab4d14b181c3a9447c75fd2b41b9d0d761e4
usb: common: Use a global definition for 'min3'
This commit should not be picked alone without picking the next two
usb related commits in this series.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
keystone: usb: preparation of xhci fix.
This commit is a cherry-pick of the two mainstream u-boot commits
for the file include/part.h It is part of the preparation for the
xhci support update.
ae1768a72cf70c00eec6824a5cc9079b0a247640
disk/gpt: Fix GPT partition handling for blocksize != 512
0472fbfd3250d1a33d3de78afdcbf24f78ac026b
part/dev_desc: Add log2 of blocksize to block_dev_desc data struct
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
This commit is a cherry-pick of the two mainstream u-boot commits
for the file include/part.h It is part of the preparation for the
xhci support update.
ae1768a72cf70c00eec6824a5cc9079b0a247640
disk/gpt: Fix GPT partition handling for blocksize != 512
0472fbfd3250d1a33d3de78afdcbf24f78ac026b
part/dev_desc: Add log2 of blocksize to block_dev_desc data struct
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
tci6638: [tmp] use 2GB SO-DIMM as default
The 2GB SO-DIMM installed on EVM might have incorrect SPD data and
therefore cannot be recognized automatically. This patch, if doesn't detect
8GB SO-DIMM, assumes the 2GB SO-DIMM is installed.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
The 2GB SO-DIMM installed on EVM might have incorrect SPD data and
therefore cannot be recognized automatically. This patch, if doesn't detect
8GB SO-DIMM, assumes the 2GB SO-DIMM is installed.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: reorganize ddr3 initialization code
This patch reorganizes the ddr3 controller initialization code:
1. moves the ddr3 initialization code from board.c to the new ddr3.c file
2. leaves only init_plls at the board_early_init_f() and calls ddr3
initialization later from dram_init().
3. The init_plls doesn't initializes DDR3 plls. That is done later
together with ddr3 intialization.
4. pll macros moved to the clock-tci6638.h file.
5. adds code to read SO-DIMM SPD data.
6. As we don't know yet how to convert SPD data to DDR3 EMIF and PHY
register values the code uses read SO-DIMM module name to select
predefined DDR3 EMIF and PHY register values.
Currently the code supports only two types of SO-DIMM:
8GB 18KSF1G72HZ-1G6E2 and 2GB SQR-SD3T-2G1333SED for ddr3a.
ddr3b uses only one configuration.
7. DDR3A pll is initialized depending on SO-DIMM type.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
This patch reorganizes the ddr3 controller initialization code:
1. moves the ddr3 initialization code from board.c to the new ddr3.c file
2. leaves only init_plls at the board_early_init_f() and calls ddr3
initialization later from dram_init().
3. The init_plls doesn't initializes DDR3 plls. That is done later
together with ddr3 intialization.
4. pll macros moved to the clock-tci6638.h file.
5. adds code to read SO-DIMM SPD data.
6. As we don't know yet how to convert SPD data to DDR3 EMIF and PHY
register values the code uses read SO-DIMM module name to select
predefined DDR3 EMIF and PHY register values.
Currently the code supports only two types of SO-DIMM:
8GB 18KSF1G72HZ-1G6E2 and 2GB SQR-SD3T-2G1333SED for ddr3a.
ddr3b uses only one configuration.
7. DDR3A pll is initialized depending on SO-DIMM type.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: fix a typo
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
keystone: fix clobber list for asm call
Currently the asm instruction for mon_install and mon_power_*
doesn't include clobbered list of registers that are used inside
the call. This patch fixes this bug.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Currently the asm instruction for mon_install and mon_power_*
doesn't include clobbered list of registers that are used inside
the call. This patch fixes this bug.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
tci6638: enable cache coherence with QM PDSP
This patch enables cache coherence between ARM and QM PSPs. This is needed
for the keystone hwqueue driver in kernel to operate in cache coherent
mode
Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
This patch enables cache coherence between ARM and QM PSPs. This is needed
for the keystone hwqueue driver in kernel to operate in cache coherent
mode
Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
tci6638: fix the compilation error
The asm instruction to disable dcache is causing compilation issue.
This is not required to get the ARM core pac (Power domain and clock
domain) to off state. Verified that after issuing killme command
data at offset 0x235027c goes from 0x301 to 0x200 and at offset 0x23508d0
from 0x1f03 to 0xA00 indicating both power domain and clock domain are
transitioned to OFF state.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
The asm instruction to disable dcache is causing compilation issue.
This is not required to get the ARM core pac (Power domain and clock
domain) to off state. Verified that after issuing killme command
data at offset 0x235027c goes from 0x301 to 0x200 and at offset 0x23508d0
from 0x1f03 to 0xA00 indicating both power domain and clock domain are
transitioned to OFF state.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
tci6638: tuning off the last ARM
This commit adds function and shell command to show of
how ARM0 can turn off itself.
This assumes that all other ARM cores are already turned off.
It also turns off the tetris power domain
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
This commit adds function and shell command to show of
how ARM0 can turn off itself.
This assumes that all other ARM cores are already turned off.
It also turns off the tetris power domain
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone2: fix mon_power debug commands
If compiled in thumb mode smc instruction was encoded incorrectly.
This patch replaced the encoding by actual smc instruction.
The patch enables the security extension to allow compiling the "smc"
instruction.
The both mon_power_on and mon_power_off functions used wrong registers
to pass parameters. This patch fixes that as well.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
If compiled in thumb mode smc instruction was encoded incorrectly.
This patch replaced the encoding by actual smc instruction.
The patch enables the security extension to allow compiling the "smc"
instruction.
The both mon_power_on and mon_power_off functions used wrong registers
to pass parameters. This patch fixes that as well.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone: usb: update xhci host controller reset
The previous reset procedure works only when VBUS is low, which is the
case on VDB. The updated procedure works regardless of the VBUS state.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
The previous reset procedure works only when VBUS is low, which is the
case on VDB. The updated procedure works regardless of the VBUS state.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
tci6638: add debug_options environment variable
This patch adds the "debug_options" environment variable. This
variable may be used conditionally to include/exclude some code
to simplify debugging.
As the first option this patch controls of calling the
turn_off_all_dsps().
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
This patch adds the "debug_options" environment variable. This
variable may be used conditionally to include/exclude some code
to simplify debugging.
As the first option this patch controls of calling the
turn_off_all_dsps().
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: turn off all dsps
This patch adds a function to turn off all dsps. It also adds code
to call the function in the board_init().
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
This patch adds a function to turn off all dsps. It also adds code
to call the function in the board_init().
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone2: add calling psc_disable_domain to do_psc_cmd
The "psc" u-boot shell command could only enable or disable lpsc clocks.
This commit extends this command with the psc_dosable_domain() call.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
The "psc" u-boot shell command could only enable or disable lpsc clocks.
This commit extends this command with the psc_dosable_domain() call.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone2: fix psc_delay() return value
The psc_wait() uses the psc_delay() return value to calculate timeout.
Because the psc_delay() always returned zero the psc_wait() was
infinitely blocked on unsuccessful psc operations. Returning delayed
value allows the psc_wait() to handle timeout correctly.
This commit also fixes the return value of the psc_disable_domain()
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
The psc_wait() uses the psc_delay() return value to calculate timeout.
Because the psc_delay() always returned zero the psc_wait() was
infinitely blocked on unsuccessful psc operations. Returning delayed
value allows the psc_wait() to handle timeout correctly.
This commit also fixes the return value of the psc_disable_domain()
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone2: automate boot up using uinitrd fs
This patch adds env variables to automate boot using unitrd.
Also fixed some warnings in board.c. Also added a new boot
option value 'uinitrd' to enable boot using this method.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
This patch adds env variables to automate boot using unitrd.
Also fixed some warnings in board.c. Also added a new boot
option value 'uinitrd' to enable boot using this method.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
tci6638: make ddr3 1333_32 configuration for MT18KSF1G72HZ SODIMM
This patch changes the 1333_32 DDR configuration to support dual rank
SODIMM.
Uncomment the DUAL_RANK definition to enable the "dual rank"
This patch also removes duplicated ZCKSEL masks
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
This patch changes the 1333_32 DDR configuration to support dual rank
SODIMM.
Uncomment the DUAL_RANK definition to enable the "dual rank"
This patch also removes duplicated ZCKSEL masks
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: passing more than 2GB ddr3a memory size to kernel
U-boot works without MMU enabled and therefore cannot detect and use
more than 2GB of DDR3A. But u-boot has to pass the correct memory
configuration to kernel. It does that by fixing the memory node in
the device tree.
Even if the DDR3A physically is one solid bank, u-boot uses two logical
banks. The first bank is configured in the same way as before.
Thus it maximum size is 2GB and it may be reduced by the size of
reserved memory. We reserve memory at the end of the first 2GB of
DDR3A as that is only memory accessible from DSPs.
If the "mem_lpae" environment variable is set and the "ddr3a_size" is set
to 4 or 8 (GB) u-boot creates the second memory bank with the size equal
to (ddr3a_size - 2).
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
U-boot works without MMU enabled and therefore cannot detect and use
more than 2GB of DDR3A. But u-boot has to pass the correct memory
configuration to kernel. It does that by fixing the memory node in
the device tree.
Even if the DDR3A physically is one solid bank, u-boot uses two logical
banks. The first bank is configured in the same way as before.
Thus it maximum size is 2GB and it may be reduced by the size of
reserved memory. We reserve memory at the end of the first 2GB of
DDR3A as that is only memory accessible from DSPs.
If the "mem_lpae" environment variable is set and the "ddr3a_size" is set
to 4 or 8 (GB) u-boot creates the second memory bank with the size equal
to (ddr3a_size - 2).
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: fix BYTEMASK of the DDR3 configuration
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: [tmp] add setmpax shell command
This patch adds a command to configure SES MPAX segments for ARM PrivId.
It may be used to debug access to the entire DDR3A memory range.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
This patch adds a command to configure SES MPAX segments for ARM PrivId.
It may be used to debug access to the entire DDR3A memory range.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: add high memory test - initial code
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: adds EMAC POST test
This patch adds the EMAC POST test to the Keystone platform.
It also makes the post.c compliant to the Linux coding standard.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
This patch adds the EMAC POST test to the Keystone platform.
It also makes the post.c compliant to the Linux coding standard.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone: adds netcp_release_rxhd() prototype
This patch adds the netcp_release_rxhd() prototype to the keystone_nav.h
to eliminate compiler warnings.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
This patch adds the netcp_release_rxhd() prototype to the keystone_nav.h
to eliminate compiler warnings.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: adds get_num_ports() and get_eth_priv_ptr() functions
Keystone EMAC POST test requires number of port and pointers to
The private Ethernet structures defined in the board.c. This patch
adds the functions to get that information.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Keystone EMAC POST test requires number of port and pointers to
The private Ethernet structures defined in the board.c. This patch
adds the functions to get that information.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone: net: add helpers for POST
POST EMAC PHY loop-back test requires having the mdio to set
the phy in loop-back. But the driver doesn't need to checl the phy
during that test.
This patch add the loopback_test variable. If the variable is set,
driver doesn't access the phy.
The patch adds helper functions to set the loopback_test variable and
get the value of the sys_has_mdio variables.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
POST EMAC PHY loop-back test requires having the mdio to set
the phy in loop-back. But the driver doesn't need to checl the phy
during that test.
This patch add the loopback_test variable. If the variable is set,
driver doesn't access the phy.
The patch adds helper functions to set the loopback_test variable and
get the value of the sys_has_mdio variables.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tic6638: add sgmii base addresses for all ports
TCI6638 has 4 SGMII ports. This patch adds base addresses definitions
for them.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
TCI6638 has 4 SGMII ports. This patch adds base addresses definitions
for them.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone: dt fix up for uinitrd
When uinitrd image (uImage formatted initrd cpio or cpio.gz) is used
as the ramfs and the address of the same is passed as 2nd parameter
of bootm command, kernel doesn't boot up. There are a couple of dt
fix up required to get this working for lpae.
- fix up the initrd_start and initrd_end properties to have 64 bit
addresses
- fix up the reserved memory address for initrd embedded in the
dtb to have 64 bit address as well.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
When uinitrd image (uImage formatted initrd cpio or cpio.gz) is used
as the ramfs and the address of the same is passed as 2nd parameter
of bootm command, kernel doesn't boot up. There are a couple of dt
fix up required to get this working for lpae.
- fix up the initrd_start and initrd_end properties to have 64 bit
addresses
- fix up the reserved memory address for initrd embedded in the
dtb to have 64 bit address as well.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
keystone2: implement aemif errata performance degradation fix
Following errata for keystone2 devices exist for emif16 and this patch
implements the work around suggested in the errata. The errata is
described with title "Performance degradation for asynchronous accesses
caused by an unused feature enabled in EMIF16".
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Following errata for keystone2 devices exist for emif16 and this patch
implements the work around suggested in the errata. The errata is
described with title "Performance degradation for asynchronous accesses
caused by an unused feature enabled in EMIF16".
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
tci6638: [tmp] set TETRIS and CORE freq
This patch sets CORE PLL to 1167 MHz and TETRIS PLL to 1188 MHz
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
This patch sets CORE PLL to 1167 MHz and TETRIS PLL to 1188 MHz
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone2: add ubi image burn commands
Add get_ubi and burn_ubi commands for ease of programming UBI images
onto flash.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Add get_ubi and burn_ubi commands for ease of programming UBI images
onto flash.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
tci6638: add DDR3A 64bit configuration
TCI6638 PG1.1 has fixed the DDR3A controller bug and may access DDR3A in
64 bit mode. This patch adds the DDR3A 1600 64bit configuration.
The board_early_init_f() reads the chip revision and selects 1333_32bit
DDR3A configuration for PG1.0 and 1600_64bit for PG1.1.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
TCI6638 PG1.1 has fixed the DDR3A controller bug and may access DDR3A in
64 bit mode. This patch adds the DDR3A 1600 64bit configuration.
The board_early_init_f() reads the chip revision and selects 1333_32bit
DDR3A configuration for PG1.0 and 1600_64bit for PG1.1.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone: add functions to read chip ID and revision
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: set ENSAT bit for tetris pll
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone2: fix init_pll for Tetris PLL clock
Currently CHIPMISCCTL1 register offset used for reg_clrbits() is wrong
and should be changed to 0x2620c7c. The output clk setting seems to be
not impacted as we had tested the clock frequency is correct by probing
the signal.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Currently CHIPMISCCTL1 register offset used for reg_clrbits() is wrong
and should be changed to 0x2620c7c. The output clk setting seems to be
not impacted as we had tested the clock frequency is correct by probing
the signal.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
tci6638: share PCIE privId
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone: fix initramfs default image name
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
tci6638: [tmp] open and close tci6638 ethernet
Kernel expects u-boot to initialize serdes. If u-boot boots kernel from
ubifs the serdes remain uninitialized.
This patch explicitly opens immediately closes the eth0 to power on
network related IPs and initialize the serdes.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Kernel expects u-boot to initialize serdes. If u-boot boots kernel from
ubifs the serdes remain uninitialized.
This patch explicitly opens immediately closes the eth0 to power on
network related IPs and initialize the serdes.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: post: initial version
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone: net: register phy only once
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone: add board specific enable_caches function
Even if keystone u-boot doesn't enable D-cache it has to implement the
enable_caches(). That eliminates warning from __enable_caches() in
the lib/cache.c.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Even if keystone u-boot doesn't enable D-cache it has to implement the
enable_caches(). That eliminates warning from __enable_caches() in
the lib/cache.c.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone: i2c: add multiple i2c buses support
This patch adds multiple I2C buses support to keystone devices.
The keystone_i2c.c driver copied from davinci_i2c.c. In the driver
all reads/writes to hard-coded register addresses where replaced to
reads/writes to corresponding fields of the i2c_regs struct.
Base address of the struct is set from i2c_set_bus_num(). This function
is part of generic uboot i2c framework, which already has shell commands
to switch active i2c bus.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
This patch adds multiple I2C buses support to keystone devices.
The keystone_i2c.c driver copied from davinci_i2c.c. In the driver
all reads/writes to hard-coded register addresses where replaced to
reads/writes to corresponding fields of the i2c_regs struct.
Base address of the struct is set from i2c_set_bus_num(). This function
is part of generic uboot i2c framework, which already has shell commands
to switch active i2c bus.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone: net: use port number for the MACCONTROL CPSW register
Function tci6614_eth_gigabit_enable() always wrote to the MACCONTROL
register of the salve port 0 independently on actual active port.
This patch fixes the bug. The function uses the correct MAC slave module.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Function tci6614_eth_gigabit_enable() always wrote to the MACCONTROL
register of the salve port 0 independently on actual active port.
This patch fixes the bug. The function uses the correct MAC slave module.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone: nav: change queue numbers for netcp
This patch sets queue numbers, which are used by NETCP to match to the
queues used by kernel (defined in DTS)
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
This patch sets queue numbers, which are used by NETCP to match to the
queues used by kernel (defined in DTS)
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone: nav: change tear-down timeout count
There is a issue related to tear-down. The RX/TX channels don't set
the completion bit. That caused a significant delay to close them.
This patch temporally decreases number of attempts.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
There is a issue related to tear-down. The RX/TX channels don't set
the completion bit. That caused a significant delay to close them.
This patch temporally decreases number of attempts.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone: disable sgmii_serdes_shutdown()
This patch is addition to the
"[tmp] net: keystone2: don't disable clocks and domain"
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
This patch is addition to the
"[tmp] net: keystone2: don't disable clocks and domain"
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone: multiple Ethernet interfaces support
This patch reworks keystone_net driver to support multiple Ethernet
interfaces.
Configuration for all interfaces moved from board configuration file
to the eth_priv_cfg[] array in the board.c.
Actual HW initialization is moved from tci6614_emac_initialize() to
the tci6614_eth_open();
The new environment variables configures whether ethernet driver
uses on doesn't use MDIO and set interface sgmii types.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
This patch reworks keystone_net driver to support multiple Ethernet
interfaces.
Configuration for all interfaces moved from board configuration file
to the eth_priv_cfg[] array in the board.c.
Actual HW initialization is moved from tci6614_emac_initialize() to
the tci6614_eth_open();
The new environment variables configures whether ethernet driver
uses on doesn't use MDIO and set interface sgmii types.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone: call the tci6614_eth_set_mac_addr() from initialize function
The function sets the dev->enetaddr with the value from MACID register.
This value has to be set before the eth_initialize() calls the
eth_write_hwAddr().
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
The function sets the dev->enetaddr with the value from MACID register.
This value has to be set before the eth_initialize() calls the
eth_write_hwAddr().
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6614: post: [tmp] remove emac loopback from post
Rework of queue manager and cppi driver significantly changed the API
and requires a rework of the post_test_emac_loopback().
This patch temporally removes removes the function until the rework.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Rework of queue manager and cppi driver significantly changed the API
and requires a rework of the post_test_emac_loopback().
This patch temporally removes removes the function until the rework.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone: MC navigator rework
This patch deletes cppi_dma driver and adds keystone_nav.
The keystone_nav implements:
- queue manager API
- netcp cppi API
Also the patch removes all CPPI related code form keystone_net.c
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
This patch deletes cppi_dma driver and adds keystone_nav.
The keystone_nav implements:
- queue manager API
- netcp cppi API
Also the patch removes all CPPI related code form keystone_net.c
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: update to sync up the default DTB name to that in Linux kernel
The default DTB name is changed to uImage-k2hk-evm.dtb to be in sync with
that in kernel. yocto build adds a uImage prefix to the actual dtb name
of k2hk-evm.dtb.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
The default DTB name is changed to uImage-k2hk-evm.dtb to be in sync with
that in kernel. yocto build adds a uImage prefix to the actual dtb name
of k2hk-evm.dtb.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
tci6638: update to reflect the changed default dtb name
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
tci6638: set PA PLL to operate at 983.04 Mhz
This commit makes the PA subsystem to be clocked at 327.68 Mhz.
Using this frequency enables the PA counter ticks to be converted to nanoseconds without losing precision. Keystone PA driver in kernel calculates mult/shift factors for scaled math operation on PA clocksource using this frequency.
Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
This commit makes the PA subsystem to be clocked at 327.68 Mhz.
Using this frequency enables the PA counter ticks to be converted to nanoseconds without losing precision. Keystone PA driver in kernel calculates mult/shift factors for scaled math operation on PA clocksource using this frequency.
Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
tci6638: disable MDIO by default for ethernet driver
Rev 1.0 EVMs have a hardware issue with the MDIO bus due to which the
MDIO bus is unstable. The software work around is to disable MDIO in
Etherner driver in u-boot and Linux so that users of this EVM are not
affected by this issue.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Rev 1.0 EVMs have a hardware issue with the MDIO bus due to which the
MDIO bus is unstable. The software work around is to disable MDIO in
Etherner driver in u-boot and Linux so that users of this EVM are not
affected by this issue.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
[tmp] net: keystone2: don't disable clocks and domain.
This is a temporary patch for the crc errors
seen in the kernel. The clocks and the domain
are not disabled.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This is a temporary patch for the crc errors
seen in the kernel. The clocks and the domain
are not disabled.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
keystone: setting PLL BWADJ accordingly to the datasheet
Accordingly to the spec the bwadj value should be programmed to a
value equal to half of the pllm value round down if pllm has an odd
value. This patch calculates the bwadj following the spec.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Accordingly to the spec the bwadj value should be programmed to a
value equal to half of the pllm value round down if pllm has an odd
value. This patch calculates the bwadj following the spec.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone: Fix bug in PASS/DDR3 PLL setup
This patch fixes the following issues:
- PA timestamp was not correct and is 20% off from the expected value. This is root caused
to PA SS being clocked from SYSCLK0 instead of PA PLL output. Fixed by doing the following
changes
- PLL select (bit 13) in PAPLLCTL1 should always be set to 1.
- Fixed the mask for reset bit for PASS/DDR3 PLLs
Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
This patch fixes the following issues:
- PA timestamp was not correct and is 20% off from the expected value. This is root caused
to PA SS being clocked from SYSCLK0 instead of PA PLL output. Fixed by doing the following
changes
- PLL select (bit 13) in PAPLLCTL1 should always be set to 1.
- Fixed the mask for reset bit for PASS/DDR3 PLLs
Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
keystone: fix bug in init_ddrphy()
The PGCR1 was not written, since "base" was not added to the offset.
This patch fixes that bug.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
The PGCR1 was not written, since "base" was not added to the offset.
This patch fixes that bug.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
clean up spl/*gph images for distclean
currently make distclean doesn't clean up gph images under spl
directory. This patch fixes this.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
currently make distclean doesn't clean up gph images under spl
directory. This patch fixes this.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
tci6638: set PA PLL to operate at 1050 Mhz
this commit enables the PA PLL to operate
at 1050 Mhz.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
this commit enables the PA PLL to operate
at 1050 Mhz.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
tci6638: add MSMC cache coherency support
This patch adds the share_all_segments(priv_id). This function makes all
segments for the priv_id shared.
The arch_cpu_init() calls the function for ARM and NETCP priv_ids.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
This patch adds the share_all_segments(priv_id). This function makes all
segments for the priv_id shared.
The arch_cpu_init() calls the function for ARM and NETCP priv_ids.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: set lower CORE and TETRIS PLL frequencies
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: set initrdfs as default of the env default
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: change CORE and PA PLLs settings
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: set default frequencies for core and tetris plls
Set 1228MHz for CORE PLL
Set 1375MHz for Tetris PLL
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Set 1228MHz for CORE PLL
Set 1375MHz for Tetris PLL
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: fix pll_freq_get() calculation
This patch fixes possible overflow when pll frequency is being calculated
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
This patch fixes possible overflow when pll frequency is being calculated
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: fix sgmii serdes configuration
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone: set default DDR3_1333 configuration
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
[tmp]: keystone: increase the NET_RETRY_COUNT to work around tftp timeout
This is a temporary fix to allow tftp to succeed for large files.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
This is a temporary fix to allow tftp to succeed for large files.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
keystone: move reset_cpu() to C file
The assembly version of the reset_cpu() function is written
for arm instruction set and doesn't work correctly when ARM is in thumb
mode. This patch implements the reset_cpu() in C, which fixes the issue.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
The assembly version of the reset_cpu() function is written
for arm instruction set and doesn't work correctly when ARM is in thumb
mode. This patch implements the reset_cpu() in C, which fixes the issue.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
tci6638: add support for memory reservation and lpae mapping
tci6638: cleanup configuration
This also adds a default set of environment variables to make life easier for
most developers
This also adds a default set of environment variables to make life easier for
most developers
keystone: cleanup monitor commands
tci6638: use dynamic memory sizing
keystone: net: setup ale in bypass
This patch sets the CPSW ALE to bypass mode and configures
host packet descriptor to send packed directly to the slave port.
Setting the ALE to bypass mode eliminates necessity of sending a
dummy packet at the tci6614_eth_open().
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Conflicts:
arch/arm/include/asm/arch-keystone/emac_defs.h
drivers/net/keystone_net.c
This patch sets the CPSW ALE to bypass mode and configures
host packet descriptor to send packed directly to the slave port.
Setting the ALE to bypass mode eliminates necessity of sending a
dummy packet at the tci6614_eth_open().
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Conflicts:
arch/arm/include/asm/arch-keystone/emac_defs.h
drivers/net/keystone_net.c
tci6638: use actual clock for arch timer instead of hard-coded value
Instead of assuming that the core pll runs at 1GHz we use the
clk_get_rate() to read the actual arch timer frequency
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Instead of assuming that the core pll runs at 1GHz we use the
clk_get_rate() to read the actual arch timer frequency
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
keystone: tci6638: enable support of nand ecclayout command
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
keystone: nand: add support of changing nand ecc layout during runtime
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>