Incorporated new osal functions for QMSS accumulator queues for IR

SDOCM00107127: Separate protection OSALs for QMSS LLD. A new semaphore
was added for QMSS Accumulator queue access in the OSAL, and the BCP
semaphore number was changed in test/src/test_main.c to accommodate the
new semaphore usage.

diff --git a/bcpver.h b/bcpver.h
index 414afa358a5ae2fa8420bb883bb73bbcfc4c6110..acd92effd23dbcc5cb2c87896700db45d731c932 100644 (file)
--- a/bcpver.h
+++ b/bcpver.h
@@ -14,7 +14,7 @@ extern "C" {
  *   @brief  BCP Driver Version Definitions
  *
  *  ============================================================
- *  Copyright (c) Texas Instruments Incorporated 2009-2014
+ *  Copyright (c) Texas Instruments Incorporated 2009, 2014
  * 
  *  Redistribution and use in source and binary forms, with or without 
  *  modification, are permitted provided that the following conditions 
@@ -51,13 +51,13 @@ extern "C" {
  * format:
  *  0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD)
  */
-#define BCP_VERSION_ID                      (0x02010000)
+#define BCP_VERSION_ID                      (0x02010001)
 
 /**
  * @brief   This is the version string which describes the BCP Driver along with the
  * date and build information.
  */
-#define BCP_VERSION_STR                     "BCP Driver Revision: 02.01.00.00"
+#define BCP_VERSION_STR                     "BCP Driver Revision: 02.01.00.01"
 
 
 #ifdef __cplusplus

diff --git a/docs/ReleaseNotes_BCPDriver.doc b/docs/ReleaseNotes_BCPDriver.doc
index 3749efb6a592e1aaa4a1bd407366d3fcec9e3e8f..bdf0bd4655e9883d16546965b2455f98afce68fa 100755 (executable)
Binary files a/docs/ReleaseNotes_BCPDriver.doc and b/docs/ReleaseNotes_BCPDriver.doc differ

diff --git a/docs/ReleaseNotes_BCPDriver.pdf b/docs/ReleaseNotes_BCPDriver.pdf
index 76b41e93050b06a600f7ff0d85b8cb907f6eff4a..a4190b6d50b95d5e8db4f3832092b149c142b183 100755 (executable)
Binary files a/docs/ReleaseNotes_BCPDriver.pdf and b/docs/ReleaseNotes_BCPDriver.pdf differ

diff --git a/example/k2h/c66/bios/bcp_osal.c b/example/k2h/c66/bios/bcp_osal.c
index 92315b241e6d1120e768c292c350762b1c507581..66f7866a9e2c065239122c1b4eb3e5ca004a10f9 100755 (executable)
--- a/example/k2h/c66/bios/bcp_osal.c
+++ b/example/k2h/c66/bios/bcp_osal.c
@@ -93,7 +93,7 @@
  * multiple BCP applications across different cores to\r
  * the BCP driver.\r
  */\r
-#define     BCP_HW_SEM         2 \r
+#define     BCP_HW_SEM          2 \r
 \r
 /* Hardware Semaphore to synchronize access from\r
  * multiple applications (BCP applications and non-BCP applications)\r
@@ -107,24 +107,29 @@
  */\r
 #define     CPPI_HW_SEM         4 \r
 \r
-\r
 /* Hardware Semaphore to synchronize access from\r
  * multiple applications (BCP applications and non-BCP applications)\r
  * across different cores to the SRIO library.\r
  */\r
-#define SRIO_HW_SEM             5\r
+#define     SRIO_HW_SEM         5\r
 \r
+/* Hardware Semaphore to synchronize access from\r
+ * multiple applications (BCP applications and non-BCP applications)\r
+ * for accumulator queues across different cores to the QMSS library.\r
+ */\r
+#define     QMSS_ACC_HW_SEM     6\r
+ \r
 /**********************************************************************\r
  ************************** Global Variables **************************\r
  **********************************************************************/\r
-UInt32      bcpMallocCounter        =   0;\r
-UInt32      bcpFreeCounter          =   0;\r
-UInt32      bcpCppiMallocCounter    =   0;\r
-UInt32      bcpCppiFreeCounter      =   0;\r
-UInt32      bcpQmssMallocCounter    =   0;\r
-UInt32      bcpQmssFreeCounter      =   0;\r
-UInt32      bcpSrioMallocCounter    =   0;\r
-UInt32      bcpSrioFreeCounter      =   0;\r
+UInt32      bcpMallocCounter       =   0;\r
+UInt32      bcpFreeCounter         =   0;\r
+UInt32      bcpCppiMallocCounter   =   0;\r
+UInt32      bcpCppiFreeCounter     =   0;\r
+UInt32      bcpQmssMallocCounter   =   0;\r
+UInt32      bcpQmssFreeCounter     =   0;\r
+UInt32      bcpSrioMallocCounter   =   0;\r
+UInt32      bcpSrioFreeCounter     =   0;\r
 \r
 UInt32      coreKey [NUM_CORES];\r
 \r
@@ -823,6 +828,76 @@ Void Osal_qmssCsExit (Void* CsHandle)
     return;\r
 }\r
 \r
+/**\r
+ * ============================================================================\r
+ *  @n@b Osal_qmssAccCsEnter\r
+ *\r
+ *  @b  brief\r
+ *  @n  This API ensures multi-core and multi-threaded\r
+ *      synchronization to the caller.\r
+ *\r
+ *      This is a BLOCKING API.\r
+ *\r
+ *      This API ensures multi-core synchronization between\r
+ *      multiple processes trying to access QMSS shared\r
+ *      library at the same time.\r
+ *\r
+ *  @param[in]  None\r
+ *\r
+ *  @return     \r
+ *      Handle used to lock critical section\r
+ * =============================================================================\r
+ */\r
+Void* Osal_qmssAccCsEnter (Void)\r
+{\r
+    /* Get the hardware semaphore. \r
+     *\r
+     * Acquire Multi core QMSS synchronization lock \r
+     */\r
+    while ((CSL_semAcquireDirect (QMSS_ACC_HW_SEM)) == 0);\r
+\r
+    /* Disable all interrupts and OS scheduler. \r
+     *\r
+     * Acquire Multi threaded / process synchronization lock.\r
+     */\r
+    coreKey [CSL_chipReadDNUM ()] = Hwi_disable();\r
+\r
+    return NULL;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ *  @n@b Osal_qmssAccCsExit\r
+ *\r
+ *  @b  brief\r
+ *  @n  This API needs to be called to exit a previously\r
+ *      acquired critical section lock using @a Osal_qmssAccCsEnter ()\r
+ *      API. It resets the multi-core and multi-threaded lock,\r
+ *      enabling another process/core to grab QMSS access.\r
+ *\r
+ *  @param[in]  CsHandle\r
+ *      Handle for unlocking critical section.\r
+ *\r
+ *  @return     None\r
+ * =============================================================================\r
+ */\r
+Void Osal_qmssAccCsExit (Void *CsHandle)\r
+{\r
+    /* Enable all interrupts and enables the OS scheduler back on.\r
+     *\r
+     * Release multi-threaded / multi-process lock on this core.\r
+     */\r
+    Hwi_restore(coreKey [CSL_chipReadDNUM ()]);\r
+\r
+    /* Release the hardware semaphore \r
+     *\r
+     * Release multi-core lock.\r
+     */ \r
+    CSL_semReleaseSemaphore (QMSS_ACC_HW_SEM);\r
+\r
+    return;\r
+}\r
+\r
 /**\r
  * ============================================================================\r
  *  @n@b Osal_qmssMtCsEnter\r

diff --git a/example/k2k/c66/bios/bcp_osal.c b/example/k2k/c66/bios/bcp_osal.c
index 92315b241e6d1120e768c292c350762b1c507581..66f7866a9e2c065239122c1b4eb3e5ca004a10f9 100755 (executable)
--- a/example/k2k/c66/bios/bcp_osal.c
+++ b/example/k2k/c66/bios/bcp_osal.c
@@ -93,7 +93,7 @@
  * multiple BCP applications across different cores to\r
  * the BCP driver.\r
  */\r
-#define     BCP_HW_SEM         2 \r
+#define     BCP_HW_SEM          2 \r
 \r
 /* Hardware Semaphore to synchronize access from\r
  * multiple applications (BCP applications and non-BCP applications)\r
@@ -107,24 +107,29 @@
  */\r
 #define     CPPI_HW_SEM         4 \r
 \r
-\r
 /* Hardware Semaphore to synchronize access from\r
  * multiple applications (BCP applications and non-BCP applications)\r
  * across different cores to the SRIO library.\r
  */\r
-#define SRIO_HW_SEM             5\r
+#define     SRIO_HW_SEM         5\r
 \r
+/* Hardware Semaphore to synchronize access from\r
+ * multiple applications (BCP applications and non-BCP applications)\r
+ * for accumulator queues across different cores to the QMSS library.\r
+ */\r
+#define     QMSS_ACC_HW_SEM     6\r
+ \r
 /**********************************************************************\r
  ************************** Global Variables **************************\r
  **********************************************************************/\r
-UInt32      bcpMallocCounter        =   0;\r
-UInt32      bcpFreeCounter          =   0;\r
-UInt32      bcpCppiMallocCounter    =   0;\r
-UInt32      bcpCppiFreeCounter      =   0;\r
-UInt32      bcpQmssMallocCounter    =   0;\r
-UInt32      bcpQmssFreeCounter      =   0;\r
-UInt32      bcpSrioMallocCounter    =   0;\r
-UInt32      bcpSrioFreeCounter      =   0;\r
+UInt32      bcpMallocCounter       =   0;\r
+UInt32      bcpFreeCounter         =   0;\r
+UInt32      bcpCppiMallocCounter   =   0;\r
+UInt32      bcpCppiFreeCounter     =   0;\r
+UInt32      bcpQmssMallocCounter   =   0;\r
+UInt32      bcpQmssFreeCounter     =   0;\r
+UInt32      bcpSrioMallocCounter   =   0;\r
+UInt32      bcpSrioFreeCounter     =   0;\r
 \r
 UInt32      coreKey [NUM_CORES];\r
 \r
@@ -823,6 +828,76 @@ Void Osal_qmssCsExit (Void* CsHandle)
     return;\r
 }\r
 \r
+/**\r
+ * ============================================================================\r
+ *  @n@b Osal_qmssAccCsEnter\r
+ *\r
+ *  @b  brief\r
+ *  @n  This API ensures multi-core and multi-threaded\r
+ *      synchronization to the caller.\r
+ *\r
+ *      This is a BLOCKING API.\r
+ *\r
+ *      This API ensures multi-core synchronization between\r
+ *      multiple processes trying to access QMSS shared\r
+ *      library at the same time.\r
+ *\r
+ *  @param[in]  None\r
+ *\r
+ *  @return     \r
+ *      Handle used to lock critical section\r
+ * =============================================================================\r
+ */\r
+Void* Osal_qmssAccCsEnter (Void)\r
+{\r
+    /* Get the hardware semaphore. \r
+     *\r
+     * Acquire Multi core QMSS synchronization lock \r
+     */\r
+    while ((CSL_semAcquireDirect (QMSS_ACC_HW_SEM)) == 0);\r
+\r
+    /* Disable all interrupts and OS scheduler. \r
+     *\r
+     * Acquire Multi threaded / process synchronization lock.\r
+     */\r
+    coreKey [CSL_chipReadDNUM ()] = Hwi_disable();\r
+\r
+    return NULL;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ *  @n@b Osal_qmssAccCsExit\r
+ *\r
+ *  @b  brief\r
+ *  @n  This API needs to be called to exit a previously\r
+ *      acquired critical section lock using @a Osal_qmssAccCsEnter ()\r
+ *      API. It resets the multi-core and multi-threaded lock,\r
+ *      enabling another process/core to grab QMSS access.\r
+ *\r
+ *  @param[in]  CsHandle\r
+ *      Handle for unlocking critical section.\r
+ *\r
+ *  @return     None\r
+ * =============================================================================\r
+ */\r
+Void Osal_qmssAccCsExit (Void *CsHandle)\r
+{\r
+    /* Enable all interrupts and enables the OS scheduler back on.\r
+     *\r
+     * Release multi-threaded / multi-process lock on this core.\r
+     */\r
+    Hwi_restore(coreKey [CSL_chipReadDNUM ()]);\r
+\r
+    /* Release the hardware semaphore \r
+     *\r
+     * Release multi-core lock.\r
+     */ \r
+    CSL_semReleaseSemaphore (QMSS_ACC_HW_SEM);\r
+\r
+    return;\r
+}\r
+\r
 /**\r
  * ============================================================================\r
  *  @n@b Osal_qmssMtCsEnter\r

diff --git a/example/k2l/c66/bios/bcp_osal.c b/example/k2l/c66/bios/bcp_osal.c
index b3136752a6b6abd0eae5e47df655212e7c1daec1..ff1426c9a40d30bea18b4944969cf1f3aa592337 100644 (file)
--- a/example/k2l/c66/bios/bcp_osal.c
+++ b/example/k2l/c66/bios/bcp_osal.c
@@ -93,7 +93,7 @@
  * multiple BCP applications across different cores to\r
  * the BCP driver.\r
  */\r
-#define     BCP_HW_SEM         2 \r
+#define     BCP_HW_SEM          2 \r
 \r
 /* Hardware Semaphore to synchronize access from\r
  * multiple applications (BCP applications and non-BCP applications)\r
@@ -107,24 +107,29 @@
  */\r
 #define     CPPI_HW_SEM         4 \r
 \r
-\r
 /* Hardware Semaphore to synchronize access from\r
  * multiple applications (BCP applications and non-BCP applications)\r
  * across different cores to the SRIO library.\r
  */\r
-#define SRIO_HW_SEM             5\r
+#define     SRIO_HW_SEM         5\r
 \r
+/* Hardware Semaphore to synchronize access from\r
+ * multiple applications (BCP applications and non-BCP applications)\r
+ * for accumulator queues across different cores to the QMSS library.\r
+ */\r
+#define     QMSS_ACC_HW_SEM     6\r
+ \r
 /**********************************************************************\r
  ************************** Global Variables **************************\r
  **********************************************************************/\r
-UInt32      bcpMallocCounter        =   0;\r
-UInt32      bcpFreeCounter          =   0;\r
-UInt32      bcpCppiMallocCounter    =   0;\r
-UInt32      bcpCppiFreeCounter      =   0;\r
-UInt32      bcpQmssMallocCounter    =   0;\r
-UInt32      bcpQmssFreeCounter      =   0;\r
-UInt32      bcpSrioMallocCounter    =   0;\r
-UInt32      bcpSrioFreeCounter      =   0;\r
+UInt32      bcpMallocCounter       =   0;\r
+UInt32      bcpFreeCounter         =   0;\r
+UInt32      bcpCppiMallocCounter   =   0;\r
+UInt32      bcpCppiFreeCounter     =   0;\r
+UInt32      bcpQmssMallocCounter   =   0;\r
+UInt32      bcpQmssFreeCounter     =   0;\r
+UInt32      bcpSrioMallocCounter   =   0;\r
+UInt32      bcpSrioFreeCounter     =   0;\r
 \r
 UInt32      coreKey [NUM_CORES];\r
 \r
@@ -823,6 +828,76 @@ Void Osal_qmssCsExit (Void* CsHandle)
     return;\r
 }\r
 \r
+/**\r
+ * ============================================================================\r
+ *  @n@b Osal_qmssAccCsEnter\r
+ *\r
+ *  @b  brief\r
+ *  @n  This API ensures multi-core and multi-threaded\r
+ *      synchronization to the caller.\r
+ *\r
+ *      This is a BLOCKING API.\r
+ *\r
+ *      This API ensures multi-core synchronization between\r
+ *      multiple processes trying to access QMSS shared\r
+ *      library at the same time.\r
+ *\r
+ *  @param[in]  None\r
+ *\r
+ *  @return     \r
+ *      Handle used to lock critical section\r
+ * =============================================================================\r
+ */\r
+Void* Osal_qmssAccCsEnter (Void)\r
+{\r
+    /* Get the hardware semaphore. \r
+     *\r
+     * Acquire Multi core QMSS synchronization lock \r
+     */\r
+    while ((CSL_semAcquireDirect (QMSS_ACC_HW_SEM)) == 0);\r
+\r
+    /* Disable all interrupts and OS scheduler. \r
+     *\r
+     * Acquire Multi threaded / process synchronization lock.\r
+     */\r
+    coreKey [CSL_chipReadDNUM ()] = Hwi_disable();\r
+\r
+    return NULL;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ *  @n@b Osal_qmssAccCsExit\r
+ *\r
+ *  @b  brief\r
+ *  @n  This API needs to be called to exit a previously\r
+ *      acquired critical section lock using @a Osal_qmssAccCsEnter ()\r
+ *      API. It resets the multi-core and multi-threaded lock,\r
+ *      enabling another process/core to grab QMSS access.\r
+ *\r
+ *  @param[in]  CsHandle\r
+ *      Handle for unlocking critical section.\r
+ *\r
+ *  @return     None\r
+ * =============================================================================\r
+ */\r
+Void Osal_qmssAccCsExit (Void *CsHandle)\r
+{\r
+    /* Enable all interrupts and enables the OS scheduler back on.\r
+     *\r
+     * Release multi-threaded / multi-process lock on this core.\r
+     */\r
+    Hwi_restore(coreKey [CSL_chipReadDNUM ()]);\r
+\r
+    /* Release the hardware semaphore \r
+     *\r
+     * Release multi-core lock.\r
+     */ \r
+    CSL_semReleaseSemaphore (QMSS_ACC_HW_SEM);\r
+\r
+    return;\r
+}\r
+\r
 /**\r
  * ============================================================================\r
  *  @n@b Osal_qmssMtCsEnter\r

diff --git a/package.xdc b/package.xdc
index 9321b1710c96040d2da3332f975c75b1ccabd8b6..7369e5bf841279ada3710ba53d86ef1b045c9a1f 100755 (executable)
--- a/package.xdc
+++ b/package.xdc
@@ -9,7 +9,7 @@
  * Copyright (C) 2012, Texas Instruments, Inc.\r
  *****************************************************************************/\r
 \r
-package ti.drv.bcp[2, 01, 00, 00] {\r
+package ti.drv.bcp[2, 01, 00, 01] {\r
     module Settings;\r
 }\r
 \r

diff --git a/test/k2h/c66/bios/test_osal.c b/test/k2h/c66/bios/test_osal.c
index 892c5cfa84602f80789d480a85050777f9ffc767..7567a29c29865b85751597a96544972b7026091e 100755 (executable)
--- a/test/k2h/c66/bios/test_osal.c
+++ b/test/k2h/c66/bios/test_osal.c
@@ -97,7 +97,7 @@
  * multiple BCP applications across different cores to\r
  * the BCP driver.\r
  */\r
-#define     BCP_HW_SEM         2 \r
+#define     BCP_HW_SEM          2 \r
 \r
 /* Hardware Semaphore to synchronize access from\r
  * multiple applications (BCP applications and non-BCP applications)\r
@@ -116,12 +116,18 @@
  * across different cores to the SRIO library.\r
  */\r
 #define     SRIO_HW_SEM         5\r
+\r
+/* Hardware Semaphore to synchronize access from\r
+ * multiple applications (BCP applications and non-BCP applications)\r
+ * for accumulator queues across different cores to the QMSS library.\r
+ */\r
+#define     QMSS_ACC_HW_SEM     6\r
  \r
 /**********************************************************************\r
  ************************** Global Variables **************************\r
  **********************************************************************/\r
-UInt32      bcpMallocCounter   =   0;\r
-UInt32      bcpFreeCounter     =   0;\r
+UInt32      bcpMallocCounter       =   0;\r
+UInt32      bcpFreeCounter         =   0;\r
 UInt32      bcpCppiMallocCounter   =   0;\r
 UInt32      bcpCppiFreeCounter     =   0;\r
 UInt32      bcpQmssMallocCounter   =   0;\r
@@ -830,6 +836,76 @@ Void Osal_qmssCsExit (Void* CsHandle)
     return;\r
 }\r
 \r
+/**\r
+ * ============================================================================\r
+ *  @n@b Osal_qmssAccCsEnter\r
+ *\r
+ *  @b  brief\r
+ *  @n  This API ensures multi-core and multi-threaded\r
+ *      synchronization to the caller.\r
+ *\r
+ *      This is a BLOCKING API.\r
+ *\r
+ *      This API ensures multi-core synchronization between\r
+ *      multiple processes trying to access QMSS shared\r
+ *      library at the same time.\r
+ *\r
+ *  @param[in]  None\r
+ *\r
+ *  @return     \r
+ *      Handle used to lock critical section\r
+ * =============================================================================\r
+ */\r
+Void* Osal_qmssAccCsEnter (Void)\r
+{\r
+    /* Get the hardware semaphore. \r
+     *\r
+     * Acquire Multi core QMSS synchronization lock \r
+     */\r
+    while ((CSL_semAcquireDirect (QMSS_ACC_HW_SEM)) == 0);\r
+\r
+    /* Disable all interrupts and OS scheduler. \r
+     *\r
+     * Acquire Multi threaded / process synchronization lock.\r
+     */\r
+    coreKey [CSL_chipReadDNUM ()] = Hwi_disable();\r
+\r
+    return NULL;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ *  @n@b Osal_qmssAccCsExit\r
+ *\r
+ *  @b  brief\r
+ *  @n  This API needs to be called to exit a previously\r
+ *      acquired critical section lock using @a Osal_qmssAccCsEnter ()\r
+ *      API. It resets the multi-core and multi-threaded lock,\r
+ *      enabling another process/core to grab QMSS access.\r
+ *\r
+ *  @param[in]  CsHandle\r
+ *      Handle for unlocking critical section.\r
+ *\r
+ *  @return     None\r
+ * =============================================================================\r
+ */\r
+Void Osal_qmssAccCsExit (Void *CsHandle)\r
+{\r
+    /* Enable all interrupts and enables the OS scheduler back on.\r
+     *\r
+     * Release multi-threaded / multi-process lock on this core.\r
+     */\r
+    Hwi_restore(coreKey [CSL_chipReadDNUM ()]);\r
+\r
+    /* Release the hardware semaphore \r
+     *\r
+     * Release multi-core lock.\r
+     */ \r
+    CSL_semReleaseSemaphore (QMSS_ACC_HW_SEM);\r
+\r
+    return;\r
+}\r
+\r
 /**\r
  * ============================================================================\r
  *  @n@b Osal_qmssMtCsEnter\r

diff --git a/test/k2k/c66/bios/test_osal.c b/test/k2k/c66/bios/test_osal.c
index 892c5cfa84602f80789d480a85050777f9ffc767..7567a29c29865b85751597a96544972b7026091e 100755 (executable)
--- a/test/k2k/c66/bios/test_osal.c
+++ b/test/k2k/c66/bios/test_osal.c
@@ -97,7 +97,7 @@
  * multiple BCP applications across different cores to\r
  * the BCP driver.\r
  */\r
-#define     BCP_HW_SEM         2 \r
+#define     BCP_HW_SEM          2 \r
 \r
 /* Hardware Semaphore to synchronize access from\r
  * multiple applications (BCP applications and non-BCP applications)\r
@@ -116,12 +116,18 @@
  * across different cores to the SRIO library.\r
  */\r
 #define     SRIO_HW_SEM         5\r
+\r
+/* Hardware Semaphore to synchronize access from\r
+ * multiple applications (BCP applications and non-BCP applications)\r
+ * for accumulator queues across different cores to the QMSS library.\r
+ */\r
+#define     QMSS_ACC_HW_SEM     6\r
  \r
 /**********************************************************************\r
  ************************** Global Variables **************************\r
  **********************************************************************/\r
-UInt32      bcpMallocCounter   =   0;\r
-UInt32      bcpFreeCounter     =   0;\r
+UInt32      bcpMallocCounter       =   0;\r
+UInt32      bcpFreeCounter         =   0;\r
 UInt32      bcpCppiMallocCounter   =   0;\r
 UInt32      bcpCppiFreeCounter     =   0;\r
 UInt32      bcpQmssMallocCounter   =   0;\r
@@ -830,6 +836,76 @@ Void Osal_qmssCsExit (Void* CsHandle)
     return;\r
 }\r
 \r
+/**\r
+ * ============================================================================\r
+ *  @n@b Osal_qmssAccCsEnter\r
+ *\r
+ *  @b  brief\r
+ *  @n  This API ensures multi-core and multi-threaded\r
+ *      synchronization to the caller.\r
+ *\r
+ *      This is a BLOCKING API.\r
+ *\r
+ *      This API ensures multi-core synchronization between\r
+ *      multiple processes trying to access QMSS shared\r
+ *      library at the same time.\r
+ *\r
+ *  @param[in]  None\r
+ *\r
+ *  @return     \r
+ *      Handle used to lock critical section\r
+ * =============================================================================\r
+ */\r
+Void* Osal_qmssAccCsEnter (Void)\r
+{\r
+    /* Get the hardware semaphore. \r
+     *\r
+     * Acquire Multi core QMSS synchronization lock \r
+     */\r
+    while ((CSL_semAcquireDirect (QMSS_ACC_HW_SEM)) == 0);\r
+\r
+    /* Disable all interrupts and OS scheduler. \r
+     *\r
+     * Acquire Multi threaded / process synchronization lock.\r
+     */\r
+    coreKey [CSL_chipReadDNUM ()] = Hwi_disable();\r
+\r
+    return NULL;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ *  @n@b Osal_qmssAccCsExit\r
+ *\r
+ *  @b  brief\r
+ *  @n  This API needs to be called to exit a previously\r
+ *      acquired critical section lock using @a Osal_qmssAccCsEnter ()\r
+ *      API. It resets the multi-core and multi-threaded lock,\r
+ *      enabling another process/core to grab QMSS access.\r
+ *\r
+ *  @param[in]  CsHandle\r
+ *      Handle for unlocking critical section.\r
+ *\r
+ *  @return     None\r
+ * =============================================================================\r
+ */\r
+Void Osal_qmssAccCsExit (Void *CsHandle)\r
+{\r
+    /* Enable all interrupts and enables the OS scheduler back on.\r
+     *\r
+     * Release multi-threaded / multi-process lock on this core.\r
+     */\r
+    Hwi_restore(coreKey [CSL_chipReadDNUM ()]);\r
+\r
+    /* Release the hardware semaphore \r
+     *\r
+     * Release multi-core lock.\r
+     */ \r
+    CSL_semReleaseSemaphore (QMSS_ACC_HW_SEM);\r
+\r
+    return;\r
+}\r
+\r
 /**\r
  * ============================================================================\r
  *  @n@b Osal_qmssMtCsEnter\r

diff --git a/test/k2l/c66/bios/test_osal.c b/test/k2l/c66/bios/test_osal.c
index 6bee3c3b5f7c7537764d435d6c14e42d05641859..ff68179957edbfe1a20a2ecbe749e96b21110850 100644 (file)
--- a/test/k2l/c66/bios/test_osal.c
+++ b/test/k2l/c66/bios/test_osal.c
@@ -95,7 +95,7 @@
  * multiple BCP applications across different cores to\r
  * the BCP driver.\r
  */\r
-#define     BCP_HW_SEM         2 \r
+#define     BCP_HW_SEM          2 \r
 \r
 /* Hardware Semaphore to synchronize access from\r
  * multiple applications (BCP applications and non-BCP applications)\r
@@ -114,12 +114,18 @@
  * across different cores to the SRIO library.\r
  */\r
 #define     SRIO_HW_SEM         5\r
+\r
+/* Hardware Semaphore to synchronize access from\r
+ * multiple applications (BCP applications and non-BCP applications)\r
+ * for accumulator queues across different cores to the QMSS library.\r
+ */\r
+#define     QMSS_ACC_HW_SEM     6\r
  \r
 /**********************************************************************\r
  ************************** Global Variables **************************\r
  **********************************************************************/\r
-UInt32      bcpMallocCounter   =   0;\r
-UInt32      bcpFreeCounter     =   0;\r
+UInt32      bcpMallocCounter       =   0;\r
+UInt32      bcpFreeCounter         =   0;\r
 UInt32      bcpCppiMallocCounter   =   0;\r
 UInt32      bcpCppiFreeCounter     =   0;\r
 UInt32      bcpQmssMallocCounter   =   0;\r
@@ -828,6 +834,76 @@ Void Osal_qmssCsExit (Void* CsHandle)
     return;\r
 }\r
 \r
+/**\r
+ * ============================================================================\r
+ *  @n@b Osal_qmssAccCsEnter\r
+ *\r
+ *  @b  brief\r
+ *  @n  This API ensures multi-core and multi-threaded\r
+ *      synchronization to the caller.\r
+ *\r
+ *      This is a BLOCKING API.\r
+ *\r
+ *      This API ensures multi-core synchronization between\r
+ *      multiple processes trying to access QMSS shared\r
+ *      library at the same time.\r
+ *\r
+ *  @param[in]  None\r
+ *\r
+ *  @return     \r
+ *      Handle used to lock critical section\r
+ * =============================================================================\r
+ */\r
+Void* Osal_qmssAccCsEnter (Void)\r
+{\r
+    /* Get the hardware semaphore. \r
+     *\r
+     * Acquire Multi core QMSS synchronization lock \r
+     */\r
+    while ((CSL_semAcquireDirect (QMSS_ACC_HW_SEM)) == 0);\r
+\r
+    /* Disable all interrupts and OS scheduler. \r
+     *\r
+     * Acquire Multi threaded / process synchronization lock.\r
+     */\r
+    coreKey [CSL_chipReadDNUM ()] = Hwi_disable();\r
+\r
+    return NULL;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ *  @n@b Osal_qmssAccCsExit\r
+ *\r
+ *  @b  brief\r
+ *  @n  This API needs to be called to exit a previously\r
+ *      acquired critical section lock using @a Osal_qmssAccCsEnter ()\r
+ *      API. It resets the multi-core and multi-threaded lock,\r
+ *      enabling another process/core to grab QMSS access.\r
+ *\r
+ *  @param[in]  CsHandle\r
+ *      Handle for unlocking critical section.\r
+ *\r
+ *  @return     None\r
+ * =============================================================================\r
+ */\r
+Void Osal_qmssAccCsExit (Void *CsHandle)\r
+{\r
+    /* Enable all interrupts and enables the OS scheduler back on.\r
+     *\r
+     * Release multi-threaded / multi-process lock on this core.\r
+     */\r
+    Hwi_restore(coreKey [CSL_chipReadDNUM ()]);\r
+\r
+    /* Release the hardware semaphore \r
+     *\r
+     * Release multi-core lock.\r
+     */ \r
+    CSL_semReleaseSemaphore (QMSS_ACC_HW_SEM);\r
+\r
+    return;\r
+}\r
+\r
 /**\r
  * ============================================================================\r
  *  @n@b Osal_qmssMtCsEnter\r

diff --git a/test/src/test_main.c b/test/src/test_main.c
index f7f1bbf7ca512a037473417b4d36beb42d8d4d9a..07e91687965b8898b518f1acd5a2af99b8d6217e 100755 (executable)
--- a/test/src/test_main.c
+++ b/test/src/test_main.c
@@ -151,7 +151,7 @@ static volatile UInt32                           bIsSysInitDone         = 0;
 #pragma DATA_SECTION (bIsCoreTestDone, ".bcp");\r
 static volatile UInt32                           bIsCoreTestDone       = 0;\r
 \r
-#define BCP_APP_SEM 6\r
+#define BCP_APP_SEM 7\r
 \r
 /**************************************************************\r
 ************************* TEST FUNCTIONS **********************\r