| author | Prasad Jondhale <prasad.jondhale@ti.com> | |
| Sat, 3 Aug 2019 13:35:40 +0000 (19:05 +0530) | ||
| committer | Sivaraj R <sivaraj@ti.com> | |
| Sat, 14 Sep 2019 02:52:30 +0000 (21:52 -0500) | ||
| commit | 2eee4b1a09e07ee9b4a05d0addab5750da70a63f | |
| tree | e2e1972d28f702f3d241860353ddbd923671edf9 | tree | snapshot (tar.xz tar.gz zip) |
| parent | 7c0f9c50d5a18ed2f106e8485fc4b91ab2907008 | commit | diff |
j7 clock config - Remove CPSW9G from default
- The CPSW9G is needed in exclusive mode by EthFw, adding
it in list of default clocks makes mcu1_0 running SBL owner
of core causing mcu2_0 not to get exclusive access.
Signed-off-by: Prasad Jondhale <prasad.jondhale@ti.com>
- The CPSW9G is needed in exclusive mode by EthFw, adding
it in list of default clocks makes mcu1_0 running SBL owner
of core causing mcu2_0 not to get exclusive access.
Signed-off-by: Prasad Jondhale <prasad.jondhale@ti.com>
| src/j721e_evm/board_clock.c | diff | blob | history |