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raw | patch | inline | side by side (parent: 7077be5)
raw | patch | inline | side by side (parent: 7077be5)
author | M V Pratap Reddy <x0257344> | |
Thu, 12 Sep 2019 08:24:57 +0000 (13:54 +0530) | ||
committer | Ankur <a0132173@ti.com> | |
Thu, 26 Sep 2019 05:45:22 +0000 (00:45 -0500) |
src/j721e_evm/AM7xxx_pinmux_data_gesi_cpsw9g.c | patch | blob | history |
diff --git a/src/j721e_evm/AM7xxx_pinmux_data_gesi_cpsw9g.c b/src/j721e_evm/AM7xxx_pinmux_data_gesi_cpsw9g.c
index d19d44941270cec207ef1b887d9bf10a2eb18bfe..8751c78461818615abf167ef4690d9eb33878ce8 100755 (executable)
};\r
\r
\r
+static pinmuxPerCfg_t gGpio0PinCfg[] =\r
+{\r
+ /* MyGPIO0 -> GPIO0_104 -> W26 */\r
+ {\r
+ PIN_RGMII6_RXC, PIN_MODE(7) | \\r
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+ },\r
+ {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gGpioPinCfg[] =\r
+{\r
+ {0, TRUE, gGpio0PinCfg},\r
+ {PINMUX_END}\r
+};\r
+\r
+\r
static pinmuxPerCfg_t gMdio0PinCfg[] =\r
{\r
/* MyMDIO1 -> MDIO0_MDC -> V24 */\r
};\r
\r
\r
+static pinmuxPerCfg_t gRmii8PinCfg[] =\r
+{\r
+ /* MyRMII8 -> RMII8_CRS_DV -> Y28 */\r
+ {\r
+ PIN_RGMII6_TX_CTL, PIN_MODE(1) | \\r
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+ },\r
+ /* MyRMII8 -> RMII8_RXD0 -> W25 */\r
+ {\r
+ PIN_RGMII6_RD0, PIN_MODE(1) | \\r
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+ },\r
+ /* MyRMII8 -> RMII8_RXD1 -> W24 */\r
+ {\r
+ PIN_RGMII6_RD1, PIN_MODE(1) | \\r
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+ },\r
+ /* MyRMII8 -> RMII8_RX_ER -> V23 */\r
+ {\r
+ PIN_RGMII6_RX_CTL, PIN_MODE(1) | \\r
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+ },\r
+ /* MyRMII8 -> RMII8_TXD0 -> W27 */\r
+ {\r
+ PIN_RGMII6_TD0, PIN_MODE(1) | \\r
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+ },\r
+ /* MyRMII8 -> RMII8_TXD1 -> V25 */\r
+ {\r
+ PIN_RGMII6_TD1, PIN_MODE(1) | \\r
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+ },\r
+ /* MyRMII8 -> RMII8_TX_EN -> W29 */\r
+ {\r
+ PIN_RGMII6_TXC, PIN_MODE(1) | \\r
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+ },\r
+ {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gRmii0PinCfg[] =\r
+{\r
+ /* MyRMII0 -> RMII_REF_CLK -> AD18 */\r
+ {\r
+ PIN_PRG1_MDIO0_MDC, PIN_MODE(5) | \\r
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+ },\r
+ {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gRmiiPinCfg[] =\r
+{\r
+ {8, TRUE, gRmii8PinCfg},\r
+ {0, TRUE, gRmii0PinCfg},\r
+ {PINMUX_END}\r
+};\r
+\r
+\r
pinmuxBoardCfg_t gAM7xMainPinmuxDataGesiCpsw9g[] =\r
{\r
{0, gCpsw9gPinCfg},\r
- {1, gMdioPinCfg},\r
- {2, gRgmiiPinCfg},\r
+ {1, gGpioPinCfg},\r
+ {2, gMdioPinCfg},\r
+ {3, gRgmiiPinCfg},\r
+ {4, gRmiiPinCfg},\r
{PINMUX_END}\r
};\r
\r