board: nor ospi: PRSDK-7095: fix OSPI SDR mode issue

1. In the SDR mode, the OSPI flash driver should send a volatile config
command to the flash device to set the SPI mode to Extended SPI mode
2. In the DDR mode, the OSPI flash driver should send a volatile config
command to the flash device to set the SPI mode to DDR mode
3. The address bytes should be set to 4 for DDR mode and 3 for SDR mode
4. Use Sciclient API to get the actual R5 CPU clock frequency and set
the frequency to the timer input PMU counter clock

Signed-off-by: Hao Zhang <hzhang@ti.com>

diff --git a/src/am65xx_evm/am65xx_evm.c b/src/am65xx_evm/am65xx_evm.c
index 2102fae64bd7b5cf8911c22fb8f2d4936e7a6fd5..447e00fd3050fdd0468add0d8c559effdff44dd1 100644 (file)
--- a/src/am65xx_evm/am65xx_evm.c
+++ b/src/am65xx_evm/am65xx_evm.c
@@ -76,6 +76,36 @@ static Board_STATUS Board_sysInit(void)
     {
         Sciclient_configPrmsInit(&config);
         ret = Sciclient_init(&config);
+
+#if defined(__TI_ARM_V7R4__)
+        uint64_t mcuClkFreq;
+
+        if(ret == 0)
+        {
+            ret = Sciclient_pmGetModuleClkFreq(TISCI_DEV_MCU_ARMSS0_CPU0,
+                                               TISCI_DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK,
+                                               &mcuClkFreq,
+                                               SCICLIENT_SERVICE_WAIT_FOREVER);
+        }
+        if(ret == 0)
+        {
+            Osal_HwAttrs  hwAttrs;
+            uint32_t      ctrlBitmap;
+
+            ret = Osal_getHwAttrs(&hwAttrs);
+            if(ret == 0)
+            {
+                /*
+                 * Change the timer input clock frequency configuration
+                   based on R5 CPU clock configured
+                 */
+                hwAttrs.cpuFreqKHz = (int32_t)(mcuClkFreq/1000U);
+                ctrlBitmap         = OSAL_HWATTR_SET_CPU_FREQ;
+                ret = Osal_setHwAttrs(ctrlBitmap, &hwAttrs);
+            }
+        }
+#endif
+
         if(ret != 0)
         {
             status = BOARD_FAIL;

diff --git a/src/am65xx_idk/am65xx_idk.c b/src/am65xx_idk/am65xx_idk.c
index ecbc59a2d7937ee53279025016eb44d3c6077643..fefa0e3937cfeeb40757ac1219c2ee063a827cfb 100644 (file)
--- a/src/am65xx_idk/am65xx_idk.c
+++ b/src/am65xx_idk/am65xx_idk.c
@@ -76,6 +76,36 @@ static Board_STATUS Board_sysInit(void)
     {
         Sciclient_configPrmsInit(&config);
         ret = Sciclient_init(&config);
+
+#if defined(__TI_ARM_V7R4__)
+        uint64_t mcuClkFreq;
+
+        if(ret == 0)
+        {
+            ret = Sciclient_pmGetModuleClkFreq(TISCI_DEV_MCU_ARMSS0_CPU0,
+                                               TISCI_DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK,
+                                               &mcuClkFreq,
+                                               SCICLIENT_SERVICE_WAIT_FOREVER);
+        }
+        if(ret == 0)
+        {
+            Osal_HwAttrs  hwAttrs;
+            uint32_t      ctrlBitmap;
+
+            ret = Osal_getHwAttrs(&hwAttrs);
+            if(ret == 0)
+            {
+                /*
+                 * Change the timer input clock frequency configuration
+                   based on R5 CPU clock configured
+                 */
+                hwAttrs.cpuFreqKHz = (int32_t)(mcuClkFreq/1000U);
+                ctrlBitmap         = OSAL_HWATTR_SET_CPU_FREQ;
+                ret = Osal_setHwAttrs(ctrlBitmap, &hwAttrs);
+            }
+        }
+#endif
+
         if(ret != 0)
         {
             status = BOARD_FAIL;

diff --git a/src/flash/nor/device/m35xu512.h b/src/flash/nor/device/m35xu512.h
index 7fe30b26d7ea89a587e12567ec3132b5b1fa3f6b..4cc3a9da6c365e7cd3f6fb2af7ed826193296315 100644 (file)
--- a/src/flash/nor/device/m35xu512.h
+++ b/src/flash/nor/device/m35xu512.h
@@ -97,8 +97,8 @@
 #define NOR_CMD_OCTAL_FAST_PROG      (0x82U)
 #define NOR_CMD_EXT_OCTAL_FAST_PROG  (0xC2U)
 #define NOR_CMD_OCTAL_PROG           (NOR_CMD_OCTAL_FAST_PROG)
-#define NOR_CMD_WRITE_NVCR           (0x81U)
-#define NOR_CMD_READ_NVCR            (0x85U)
+#define NOR_CMD_WRITE_VCR            (0x81U)
+#define NOR_CMD_READ_VCR             (0x85U)
 #endif
 
 /* \brief Read ID command definitions */

diff --git a/src/flash/nor/ospi/nor_ospi.c b/src/flash/nor/ospi/nor_ospi.c
index 4f1e96a76c8def3411f863f1a36a1211b9f6e28b..3d7a4cb4107a5dd7ade62e496f29b9d666f6380d 100644 (file)
--- a/src/flash/nor/ospi/nor_ospi.c
+++ b/src/flash/nor/ospi/nor_ospi.c
@@ -126,11 +126,12 @@ static NOR_STATUS Nor_ospiReadId(SPI_Handle handle)
 \r
 static NOR_STATUS Nor_ospiEnableDDR(SPI_Handle handle)\r
 {\r
-    NOR_STATUS       retVal;\r
-    uint8_t          cmdWren = NOR_CMD_WREN;\r
-    uint32_t         data[3];\r
-    uint32_t         dummyCycles;\r
-    uint32_t         rx_lines;\r
+    NOR_STATUS             retVal;\r
+    uint8_t                cmdWren = NOR_CMD_WREN;\r
+    uint32_t               data[3];\r
+    uint32_t               dummyCycles;\r
+    uint32_t               rx_lines;\r
+    OSPI_v0_HwAttrs const *hwAttrs= (OSPI_v0_HwAttrs const *)handle->hwAttrs;\r
 \r
     /* Send Write Enable command */\r
     retVal = Nor_ospiCmdWrite(handle, &cmdWren, 1, 0);\r
@@ -139,7 +140,7 @@ static NOR_STATUS Nor_ospiEnableDDR(SPI_Handle handle)
     if (retVal == NOR_PASS)\r
     {\r
         /* send write VCR command to reg addr 0x0 to set to DDR mode */\r
-        data[0] = (NOR_CMD_WRITE_NVCR << 24)        | /* write non-volatile config reg cmd */\r
+        data[0] = (NOR_CMD_WRITE_VCR << 24)         | /* write volatile config reg cmd */\r
                   (0 << 23)                         | /* read data disable */\r
                   (7 << 20)                         | /* read 8 data bytes */\r
                   (1 << 19)                         | /* enable cmd adddr */\r
@@ -151,7 +152,7 @@ static NOR_STATUS Nor_ospiEnableDDR(SPI_Handle handle)
 \r
         /* Set opcodes */\r
         dummyCycles = NOR_OCTAL_READ_DUMMY_CYCLE;\r
-        rx_lines    = OSPI_XFER_LINES_OCTAL;\r
+        rx_lines    = hwAttrs->xferLines;\r
         data[0]     = NOR_CMD_OCTAL_DDR_O_FAST_RD;\r
         data[1]     = NOR_CMD_OCTAL_FAST_PROG;\r
         data[2]     = NOR_CMD_RDSR;\r
@@ -167,20 +168,42 @@ static NOR_STATUS Nor_ospiEnableDDR(SPI_Handle handle)
 \r
 static NOR_STATUS Nor_ospiEnableSDR(SPI_Handle handle)\r
 {\r
-    uint32_t         opCode[3];\r
-    uint32_t         dummyCycles;\r
-    uint32_t         rx_lines;\r
+    NOR_STATUS             retVal;\r
+    uint8_t                cmdWren = NOR_CMD_WREN;\r
+    uint32_t               data[3];\r
+    uint32_t               dummyCycles;\r
+    uint32_t               rx_lines;\r
+    OSPI_v0_HwAttrs const *hwAttrs= (OSPI_v0_HwAttrs const *)handle->hwAttrs;\r
+\r
+    /* Send Write Enable command */\r
+    retVal = Nor_ospiCmdWrite(handle, &cmdWren, 1, 0);\r
+\r
+    /* Enable double transfer rate mode */\r
+    if (retVal == NOR_PASS)\r
+    {\r
+        /* send write VCR command to reg addr 0x0 to set to DDR mode */\r
+        data[0] = (NOR_CMD_WRITE_VCR << 24)         | /* write volatile config reg cmd */\r
+                  (0 << 23)                         | /* read data disable */\r
+                  (7 << 20)                         | /* read 8 data bytes */\r
+                  (1 << 19)                         | /* enable cmd adddr */\r
+                  (2 << 16)                         | /* 3 address bytes */\r
+                  (1 << 15);                          /* write data enable */\r
+        data[1] = 0;     /* Non-volatile config register address */\r
+        data[2] = 0xFFU; /* set to Extended SPI mode in Nonvolatile Config Reg 0x0 */\r
+        SPI_control(handle, SPI_V0_CMD_ENABLE_SDR, (void *)data);\r
 \r
-    dummyCycles = NOR_OCTAL_READ_DUMMY_CYCLE;\r
-    rx_lines    = OSPI_XFER_LINES_OCTAL;\r
-    opCode[0]   = NOR_CMD_OCTAL_IO_FAST_RD;\r
-    opCode[1]   = NOR_CMD_EXT_OCTAL_FAST_PROG;\r
-    opCode[2]   = NOR_CMD_RDSR;\r
+        /* Set opcodes */\r
+        dummyCycles = NOR_OCTAL_READ_DUMMY_CYCLE;\r
+        rx_lines    = hwAttrs->xferLines;\r
+        data[0]     = NOR_CMD_OCTAL_IO_FAST_RD;\r
+        data[1]     = NOR_CMD_EXT_OCTAL_FAST_PROG;\r
+        data[2]     = NOR_CMD_RDSR;\r
 \r
-    /* Update the read opCode, rx lines and read dummy cycles */\r
-    SPI_control(handle, SPI_V0_CMD_RD_DUMMY_CLKS, (void *)&dummyCycles);\r
-    SPI_control(handle, SPI_V0_CMD_SET_XFER_LINES, (void *)&rx_lines);\r
-    SPI_control(handle, SPI_V0_CMD_XFER_OPCODE, (void *)opCode);\r
+        /* Update the read opCode, rx lines and read dummy cycles */\r
+        SPI_control(handle, SPI_V0_CMD_RD_DUMMY_CLKS, (void *)&dummyCycles);\r
+        SPI_control(handle, SPI_V0_CMD_SET_XFER_LINES, (void *)&rx_lines);\r
+        SPI_control(handle, SPI_V0_CMD_XFER_OPCODE, (void *)data);\r
+    }\r
 \r
     return NOR_PASS;\r
 }\r
@@ -198,7 +221,7 @@ static NOR_STATUS Nor_ospiXipEnable(SPI_Handle handle)
 \r
     if (retVal == NOR_PASS)\r
     {\r
-        stigCmd[0] = NOR_CMD_WRITE_NVCR; /* opcode */\r
+        stigCmd[0] = NOR_CMD_WRITE_VCR; /* opcode */\r
         stigCmd[1] = 0x0; /* disable read operation */\r
         stigCmd[2] = 0x7; /* read 0x7=8 data bytes (ignored) */\r
         stigCmd[3] = 0x1; /* enable cmd address */\r
@@ -558,6 +581,7 @@ NOR_STATUS Nor_ospiErase(NOR_HANDLE handle, int32_t erLoc, bool blkErase)
     uint8_t         cmdWren  = NOR_CMD_WREN;\r
     NOR_Info       *norOspiInfo;\r
     SPI_Handle      spiHandle;\r
+    OSPI_v0_HwAttrs const *hwAttrs;\r
 \r
     if (!handle)\r
     {\r
@@ -570,6 +594,7 @@ NOR_STATUS Nor_ospiErase(NOR_HANDLE handle, int32_t erLoc, bool blkErase)
         return NOR_FAIL;\r
     }\r
     spiHandle = (SPI_Handle)norOspiInfo->hwHandle;\r
+    hwAttrs = (OSPI_v0_HwAttrs const *)spiHandle->hwAttrs;\r
 \r
     if (erLoc == NOR_BE_SECTOR_NUM)\r
     {\r
@@ -596,12 +621,23 @@ NOR_STATUS Nor_ospiErase(NOR_HANDLE handle, int32_t erLoc, bool blkErase)
             address   = erLoc * NOR_SECTOR_SIZE;\r
             cmd[0] = NOR_CMD_SECTOR_ERASE;\r
         }\r
-        cmd[1] = (address >> 24) & 0xff; /* 64MB flash device */\r
-        cmd[2] = (address >> 16) & 0xff;\r
-        cmd[3] = (address >>  8) & 0xff;\r
-        cmd[4] = (address >>  0) & 0xff;\r
 \r
-        cmdLen = 5;\r
+        if (hwAttrs->dtrEnable == (bool)true)\r
+        {\r
+            cmd[1] = (address >> 24) & 0xff; /* 4 address bytes */\r
+            cmd[2] = (address >> 16) & 0xff;\r
+            cmd[3] = (address >>  8) & 0xff;\r
+            cmd[4] = (address >>  0) & 0xff;\r
+            cmdLen = 5;\r
+        }\r
+        else\r
+        {\r
+            cmd[1] = (address >> 16) & 0xff; /* 3 address bytes */\r
+            cmd[2] = (address >>  8) & 0xff;\r
+            cmd[3] = (address >>  0) & 0xff;\r
+            cmdLen = 4;\r
+        }\r
+\r
     }\r
 \r
     if (Nor_ospiCmdWrite(spiHandle, &cmdWren, 1, 0))\r

diff --git a/src/j721e_evm/board_init.c b/src/j721e_evm/board_init.c
index 2bdcda336cc7a3e3750ba5d030151bd879ad6094..25dab8e151f3a8b94a8f1719d4e0a71d632f9e4b 100755 (executable)
--- a/src/j721e_evm/board_init.c
+++ b/src/j721e_evm/board_init.c
@@ -88,6 +88,36 @@ static Board_STATUS Board_sysInit(void)
     {
         Sciclient_configPrmsInit(&config);
         ret = Sciclient_init(&config);
+
+#if defined(BUILD_MCU)
+        uint64_t mcuClkFreq;
+
+        if(ret == 0)
+        {
+            ret = Sciclient_pmGetModuleClkFreq(TISCI_DEV_MCU_R5FSS0_CORE0,
+                                               TISCI_DEV_MCU_R5FSS0_CORE0_CPU_CLK,
+                                               &mcuClkFreq,
+                                               SCICLIENT_SERVICE_WAIT_FOREVER);
+        }
+        if(ret == 0)
+        {
+            Osal_HwAttrs  hwAttrs;
+            uint32_t      ctrlBitmap;
+
+            ret = Osal_getHwAttrs(&hwAttrs);
+            if(ret == 0)
+            {
+                /*
+                 * Change the timer input clock frequency configuration
+                   based on R5 CPU clock configured
+                 */
+                hwAttrs.cpuFreqKHz = (int32_t)(mcuClkFreq/1000U);
+                ctrlBitmap         = OSAL_HWATTR_SET_CPU_FREQ;
+                ret = Osal_setHwAttrs(ctrlBitmap, &hwAttrs);
+            }
+        }
+#endif
+
         if(ret != 0)
         {
             status = BOARD_FAIL;