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raw | patch | inline | side by side (parent: 8d2968c)
raw | patch | inline | side by side (parent: 8d2968c)
author | Dasnavis Sabiya <x0265826@ti.com> | |
Mon, 29 Jul 2019 09:39:25 +0000 (15:09 +0530) | ||
committer | Dasnavis Sabiya <x0265826@ti.com> | |
Mon, 16 Sep 2019 08:41:46 +0000 (14:11 +0530) |
Updated DSS module clock initialization to fix for VPS test failure over
MMCSD and UARtApploader on am571x-idk, am572x-evm and am572x-idk platforms
MMCSD and UARtApploader on am571x-idk, am572x-evm and am572x-idk platforms
src/evmAM572x/evmAM572x_clock.c | patch | blob | history | |
src/idkAM571x/idkAM571x_clock.c | patch | blob | history | |
src/idkAM572x/idkAM572x_clock.c | patch | blob | history |
index 1bd4e9038e6a7bdac1750ebe4782d351f749edc3..d0159e935981f54b34a428f490e6933371c35b5f 100644 (file)
\r
CSL_FINST(dssCmReg->CM_DSS_CLKSTCTRL_REG,\r
DSS_CM_CORE_CM_DSS_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);\r
-/*\r
+\r
while(CSL_DSS_CM_CORE_CM_DSS_CLKSTCTRL_REG_CLKACTIVITY_DSS_L3_GICLK_ACT !=\r
CSL_FEXT(dssCmReg->CM_DSS_CLKSTCTRL_REG,\r
DSS_CM_CORE_CM_DSS_CLKSTCTRL_REG_CLKACTIVITY_DSS_L3_GICLK));\r
-*/\r
+\r
\r
CSL_FINST(ipuCmReg->CM_IPU1_CLKSTCTRL_REG,\r
IPU_CM_CORE_AON_CM_IPU1_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);\r
CSL_FEXT(coreCmReg->CM_IPU2_IPU2_CLKCTRL_REG,\r
CORE_CM_CORE_CM_IPU2_IPU2_CLKCTRL_REG_IDLEST));\r
\r
+ CSL_FINS (((CSL_control_coreRegs *) CSL_MPU_CTRL_MODULE_CORE_CORE_REGISTERS_REGS)->CONTROL_IO_2,\r
+ CONTROL_CORE_CONTROL_IO_2_DSS_DESHDCP_CLKEN, 1U);\r
+\r
CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_MODULEMODE, ENABLED);\r
-/*\r
+\r
+ CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
+ DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_OPTFCLKEN_DSSCLK, FCLK_EN);\r
+\r
+ CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
+ DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_OPTFCLKEN_48MHZ_CLK, FCLK_EN);\r
+\r
+ CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
+ DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_OPTFCLKEN_HDMI_CLK, FCLK_EN);\r
+\r
+ CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
+ DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_OPTFCLKEN_32KHZ_CLK, FCLK_EN);\r
+\r
+ CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
+ DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_OPTFCLKEN_VIDEO1_CLK, FCLK_EN);\r
+\r
+ CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
+ DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_OPTFCLKEN_VIDEO2_CLK, FCLK_EN);\r
+\r
while(CSL_DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_IDLEST_FUNC !=\r
CSL_FEXT(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_IDLEST));\r
-*/\r
\r
CSL_FINST(ipuCmReg->CM_IPU1_IPU1_CLKCTRL_REG,\r
IPU_CM_CORE_AON_CM_IPU1_IPU1_CLKCTRL_REG_MODULEMODE, AUTO);\r
index ce393de44fb4fdbcd2b9e5278068c867a7d45f86..6dfc1f3ef53a0d93055664afb87574c6ee780c60 100644 (file)
\r
CSL_FINST(dssCmReg->CM_DSS_CLKSTCTRL_REG,\r
DSS_CM_CORE_CM_DSS_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);\r
-/*\r
+\r
while(CSL_DSS_CM_CORE_CM_DSS_CLKSTCTRL_REG_CLKACTIVITY_DSS_L3_GICLK_ACT !=\r
CSL_FEXT(dssCmReg->CM_DSS_CLKSTCTRL_REG,\r
DSS_CM_CORE_CM_DSS_CLKSTCTRL_REG_CLKACTIVITY_DSS_L3_GICLK));\r
-*/\r
+\r
\r
CSL_FINST(ipuCmReg->CM_IPU1_CLKSTCTRL_REG,\r
IPU_CM_CORE_AON_CM_IPU1_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);\r
while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_IDLEST_FUNC !=\r
CSL_FEXT(l4PerCmReg->CM_L4PER_UART3_CLKCTRL_REG,\r
L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_IDLEST));\r
-
- CSL_FINST(l4PerCmReg->CM_L4PER2_UART9_CLKCTRL_REG,
- L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART9_CLKCTRL_REG_MODULEMODE, ENABLE);
-
- while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART9_CLKCTRL_REG_IDLEST_FUNC !=
- CSL_FEXT(l4PerCmReg->CM_L4PER2_UART9_CLKCTRL_REG,
- L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART9_CLKCTRL_REG_IDLEST));
+\r
+ CSL_FINST(l4PerCmReg->CM_L4PER2_UART9_CLKCTRL_REG,\r
+ L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART9_CLKCTRL_REG_MODULEMODE, ENABLE);\r
+\r
+ while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART9_CLKCTRL_REG_IDLEST_FUNC !=\r
+ CSL_FEXT(l4PerCmReg->CM_L4PER2_UART9_CLKCTRL_REG,\r
+ L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART9_CLKCTRL_REG_IDLEST));\r
\r
CSL_FINS(mpuCmReg->CM_MPU_MPU_CLKCTRL_REG,\r
MPU_CM_CORE_AON_CM_MPU_MPU_CLKCTRL_REG_MODULEMODE, 2U);\r
CSL_FEXT(coreCmReg->CM_IPU2_IPU2_CLKCTRL_REG,\r
CORE_CM_CORE_CM_IPU2_IPU2_CLKCTRL_REG_IDLEST));\r
\r
+ CSL_FINS (((CSL_control_coreRegs *) CSL_MPU_CTRL_MODULE_CORE_CORE_REGISTERS_REGS)->CONTROL_IO_2,\r
+ CONTROL_CORE_CONTROL_IO_2_DSS_DESHDCP_CLKEN, 1U);\r
+\r
CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_MODULEMODE, ENABLED);\r
-/*\r
+\r
+ CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
+ DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_OPTFCLKEN_DSSCLK, FCLK_EN);\r
+\r
+ CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
+ DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_OPTFCLKEN_48MHZ_CLK, FCLK_EN);\r
+\r
+ CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
+ DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_OPTFCLKEN_HDMI_CLK, FCLK_EN);\r
+\r
+ CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
+ DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_OPTFCLKEN_32KHZ_CLK, FCLK_EN);\r
+\r
+ CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
+ DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_OPTFCLKEN_VIDEO1_CLK, FCLK_EN);\r
+\r
+ CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
+ DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_OPTFCLKEN_VIDEO2_CLK, FCLK_EN);\r
+\r
while(CSL_DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_IDLEST_FUNC !=\r
CSL_FEXT(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_IDLEST));\r
-*/\r
\r
CSL_FINST(ipuCmReg->CM_IPU1_IPU1_CLKCTRL_REG,\r
IPU_CM_CORE_AON_CM_IPU1_IPU1_CLKCTRL_REG_MODULEMODE, AUTO);\r
index 8f849e73a4effeb39b697b3462671aa1921605bc..ab3453b18dcab8d09af52db860fa0933fbc94dfe 100644 (file)
\r
CSL_FINST(dssCmReg->CM_DSS_CLKSTCTRL_REG,\r
DSS_CM_CORE_CM_DSS_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);\r
-/*\r
+\r
while(CSL_DSS_CM_CORE_CM_DSS_CLKSTCTRL_REG_CLKACTIVITY_DSS_L3_GICLK_ACT !=\r
CSL_FEXT(dssCmReg->CM_DSS_CLKSTCTRL_REG,\r
DSS_CM_CORE_CM_DSS_CLKSTCTRL_REG_CLKACTIVITY_DSS_L3_GICLK));\r
-*/\r
+\r
\r
CSL_FINST(ipuCmReg->CM_IPU1_CLKSTCTRL_REG,\r
IPU_CM_CORE_AON_CM_IPU1_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);\r
while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_IDLEST_FUNC !=\r
CSL_FEXT(l4PerCmReg->CM_L4PER_UART3_CLKCTRL_REG,\r
L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_IDLEST));\r
-
- CSL_FINST(l4PerCmReg->CM_L4PER2_UART9_CLKCTRL_REG,
- L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART9_CLKCTRL_REG_MODULEMODE, ENABLE);
-
- while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART9_CLKCTRL_REG_IDLEST_FUNC !=
- CSL_FEXT(l4PerCmReg->CM_L4PER2_UART9_CLKCTRL_REG,
- L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART9_CLKCTRL_REG_IDLEST));
+\r
+ CSL_FINST(l4PerCmReg->CM_L4PER2_UART9_CLKCTRL_REG,\r
+ L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART9_CLKCTRL_REG_MODULEMODE, ENABLE);\r
+\r
+ while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART9_CLKCTRL_REG_IDLEST_FUNC !=\r
+ CSL_FEXT(l4PerCmReg->CM_L4PER2_UART9_CLKCTRL_REG,\r
+ L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART9_CLKCTRL_REG_IDLEST));\r
\r
CSL_FINS(mpuCmReg->CM_MPU_MPU_CLKCTRL_REG,\r
MPU_CM_CORE_AON_CM_MPU_MPU_CLKCTRL_REG_MODULEMODE, 2U);\r
CSL_FEXT(coreCmReg->CM_IPU2_IPU2_CLKCTRL_REG,\r
CORE_CM_CORE_CM_IPU2_IPU2_CLKCTRL_REG_IDLEST));\r
\r
+ CSL_FINS (((CSL_control_coreRegs *) CSL_MPU_CTRL_MODULE_CORE_CORE_REGISTERS_REGS)->CONTROL_IO_2,\r
+ CONTROL_CORE_CONTROL_IO_2_DSS_DESHDCP_CLKEN, 1U);\r
+\r
CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_MODULEMODE, ENABLED);\r
-/*\r
+\r
+ CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
+ DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_OPTFCLKEN_DSSCLK, FCLK_EN);\r
+\r
+ CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
+ DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_OPTFCLKEN_48MHZ_CLK, FCLK_EN);\r
+\r
+ CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
+ DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_OPTFCLKEN_HDMI_CLK, FCLK_EN);\r
+\r
+ CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
+ DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_OPTFCLKEN_32KHZ_CLK, FCLK_EN);\r
+\r
+ CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
+ DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_OPTFCLKEN_VIDEO1_CLK, FCLK_EN);\r
+\r
+ CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
+ DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_OPTFCLKEN_VIDEO2_CLK, FCLK_EN);\r
+\r
while(CSL_DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_IDLEST_FUNC !=\r
CSL_FEXT(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,\r
DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_IDLEST));\r
-*/\r
\r
CSL_FINST(ipuCmReg->CM_IPU1_IPU1_CLKCTRL_REG,\r
IPU_CM_CORE_AON_CM_IPU1_IPU1_CLKCTRL_REG_MODULEMODE, AUTO);\r