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raw | patch | inline | side by side (parent: 4e6a084)
author | prasad konnur <prasadkonnur@ti.com> | |
Wed, 30 May 2018 13:39:01 +0000 (19:09 +0530) | ||
committer | prasad konnur <prasadkonnur@ti.com> | |
Thu, 31 May 2018 13:11:31 +0000 (18:41 +0530) |
Signed-off-by: prasad konnur <prasadkonnur@ti.com>
22 files changed:
diff --git a/cal_component.mk b/cal_component.mk
index 88f7e2c9e62f7ba07bb7210e2c06db2e6e5ff63c..eb770da3b49841770fa479aa5e458cb828aecbcc 100755 (executable)
--- a/cal_component.mk
+++ b/cal_component.mk
#
ifeq ($(cal_component_make_include), )
-cal_default_SOCLIST = tda2ex am65xx
-cal_default_BOARDLIST = tda2ex-evm am65xx_evm
-cal_default_tda2ex_CORELIST = ipu1_0
+cal_default_SOCLIST = am65xx
+cal_default_BOARDLIST = am65xx_evm
cal_default_am65xx_CORELIST = mpu1_0 mpu1_1 mcu1_0 mcu1_1
############################
cal_capture_test_$(SOC)_CORELIST = $(cal_default_$(SOC)_CORELIST)
export cal_capture_test_$(SOC)_CORELIST
cal_EXAMPLE_LIST += cal_capture_test
-ifeq ($(SOC),$(filter $(SOC), tda2ex))
- cal_capture_test_SBL_APPIMAGEGEN = yes
- export cal_capture_test_SBL_APPIMAGEGEN
-endif
export cal_LIB_LIST
export cal_EXAMPLE_LIST
diff --git a/examples/cal_capture_test/BIOS_common_m4.cfg b/examples/cal_capture_test/BIOS_common_m4.cfg
+++ /dev/null
@@ -1,116 +0,0 @@
-/* =============================================================================
- * Copyright (c) Texas Instruments Incorporated 2012-2015
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/* Move BIOS to release build. This is to reduce link time */
-xdc.loadPackage ("ti.sysbios").profile="release";
-
-/* use modules */
-var Task = xdc.useModule('ti.sysbios.knl.Task');
-var Idle = xdc.useModule('ti.sysbios.knl.Idle');
-var BIOS = xdc.useModule('ti.sysbios.BIOS');
-var Startup = xdc.useModule('xdc.runtime.Startup');
-var SysStd = xdc.useModule('xdc.runtime.SysStd');
-var System = xdc.useModule('xdc.runtime.System');
-var Assert = xdc.useModule('xdc.runtime.Assert');
-var Main = xdc.useModule('xdc.runtime.Main');
-var Memory = xdc.useModule('xdc.runtime.Memory');
-var Program = xdc.useModule('xdc.cfg.Program');
-var Diags = xdc.useModule('xdc.runtime.Diags');
-var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
-//var SemaphoreP = xdc.useModule('ti.sysbios.knl.SemaphoreP');
-var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
-var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
-var GIO = xdc.useModule('ti.sysbios.io.GIO');
-var Clock = xdc.useModule('ti.sysbios.knl.Clock');
-var Timestamp = xdc.useModule('xdc.runtime.Timestamp');
-var Core = xdc.useModule('ti.sysbios.family.arm.ducati.Core');
-var HalCore = xdc.useModule('ti.sysbios.hal.Core');
-var Load = xdc.useModule('ti.sysbios.utils.Load');
-var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
-var SyncSem = xdc.useModule('ti.sysbios.syncs.SyncSem');
-var Cache = xdc.useModule('ti.sysbios.hal.unicache.Cache');
-var HalCache = xdc.useModule('ti.sysbios.hal.Cache');
-var GateDualCore = xdc.useModule('ti.sysbios.family.arm.ducati.GateDualCore');
-var InitXbar = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");
-
-/* Enable cache */
-Cache.enableCache = true;
-
-/* load calculation related settings */
-Load.swiEnabled = true;
-Load.hwiEnabled = true;
-Load.taskEnabled = true;
-Load.updateInIdle = true;
-Load.windowInMs = 500;
-//Load.postUpdate = '&BspUtils_prfLoadUpdate';
-
-/* Disable SMP BIOS */
-BIOS.smpEnabled = false;
-
-/* Bios lib instrumentation */
-BIOS.libType = BIOS.LibType_Custom;
-
-/* Fix for right clock of M4 */
-BIOS.cpuFreq.hi = 0;
-BIOS.cpuFreq.lo = 212500000; /* Actual CPU Clock Rate */
-
-/* uncomment below line to run examples on IPU2 */
-/* Core.ipuId = 2; */
-
-Core.id = 0;
-
-/* Clock tick in microseconds */
-Clock.tickPeriod = 1000;
-
-/* Stack size when NULL is passed as stack during TSK create */
-Task.defaultStackSize = 0x4000;
-Task.defaultAffinity = 0;
-
-Memory.defaultHeapSize = 0x15000;
-
-/* ISR/SWI stack */
-Program.stack = 0x4000;
-/* Heap used when creating semaphore's, TSK's or malloc() ... */
-Program.heap = 0x15000;
-
-Main.common$.diags_ASSERT = Diags.ALWAYS_ON;
-Main.common$.diags_INTERNAL = Diags.ALWAYS_ON;
-
-/* To suppress the file name in BIOS compilation*/
-var SourceDir = xdc.useModule('xdc.cfg.SourceDir');
-SourceDir.verbose = 1;
-
-/* Set the proxy for System module. This enables print statements at runtime in
- * the application */
-System.SupportProxy = SysStd;
-
-
diff --git a/examples/cal_capture_test/bspCommonBIOS.cfg b/examples/cal_capture_test/bspCommonBIOS.cfg
+++ /dev/null
@@ -1,115 +0,0 @@
-/* =============================================================================
- * Copyright (c) Texas Instruments Incorporated 2012-2015
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-var CurrentSoc = java.lang.System.getenv("SOC");
-var CurrentCore = java.lang.System.getenv("CORE");
-xdc.print("# !!! Current build BOARD is [" + CurrentPlatform + "] !!!" );
-xdc.print("# !!! Current build SOC is [" + CurrentSoc + "] !!!" );
-xdc.print("# !!! Current build CORE is [" + CurrentCore + "] !!!" );
-
-
-xdc.loadCapsule("BIOS_common_m4.cfg");
-
-if (CurrentCore == "ipu1_1")
-{
- Core.id = 1;
- GateDualCore.initGates = true;
-}
-
-/* section mapping over-ride with respect to default */
-if (CurrentPlatform == "tda3xx-zebu" || CurrentPlatform == "tda2xx-zebu")
-{
- Hwi.initStackFlag = false;
- Hwi.checkStackFlag = false;
- Task.initStackFlag = false;
- Task.checkStackFlag = false;
- Program.sectMap[".bss:extMemNonCache:vpdma"] = "APP_UNCACHED_DATA_BLK3_MEM";
- Program.sectMap[".bss:frameBuffer"] = new Program.SectionSpec();
- Program.sectMap[".bss:frameBuffer"].loadSegment = "APP_CACHED_DATA_BLK1_MEM";
- Program.sectMap[".bss:frameBuffer"].type = "NOLOAD";
- Program.sectMap[".bss:tilerBuffer"] = new Program.SectionSpec();
- Program.sectMap[".bss:tilerBuffer"].loadSegment = "APP_CACHED_DATA_BLK2_MEM";
- Program.sectMap[".bss:tilerBuffer"].type = "NOLOAD";
- if (CurrentCore == "ipu1_1")
- {
- Program.sectMap[".plt"] = "APP_CODE2_MEM";
- }
- else
- {
- Program.sectMap[".plt"] = "APP_CODE_MEM";
- }
- var M3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
- M3Hwi.resetVectorAddress = (Core.id + 1) * 0 + 0x20000400;
- M3Hwi.vectorTableAddress = M3Hwi.resetVectorAddress;
- Program.sectMap[".ducatiBoot"] = "L2_RAM";
- Program.sectMap[".bootVecs"] = "L2_RAM";
- Program.sectMap[".ducatiGates"] = "L2_RAM";
-}
-else
-{
- Program.sectMap[".bss:extMemNonCache:vpdma"] = "APP_UNCACHED_DATA_BLK3_MEM";
- Program.sectMap[".bss:frameBuffer"] = new Program.SectionSpec();
- Program.sectMap[".bss:frameBuffer"].loadSegment = "APP_CACHED_DATA_BLK1_MEM";
- Program.sectMap[".bss:frameBuffer"].type = "NOLOAD";
- if (CurrentSoc != "tda3xx" && CurrentSoc != "tda2ex")
- {
- Program.sectMap[".bss:tilerBuffer"] = new Program.SectionSpec();
- Program.sectMap[".bss:tilerBuffer"].loadSegment = "APP_CACHED_DATA_BLK2_MEM";
- Program.sectMap[".bss:tilerBuffer"].type = "NOLOAD";
- }
- if (CurrentCore == "ipu1_1")
- {
- Program.sectMap[".plt"] = "APP_CODE2_MEM";
- }
- else
- {
- Program.sectMap[".plt"] = "APP_CODE_MEM";
- }
-}
-
-if (CurrentPlatform != "tda3xx-zebu")
-{
- if (CurrentPlatform == "tda2xx-interposer" || CurrentSoc == "tda2ex" || CurrentSoc == "tda2xx" || CurrentSoc == "tda2px")
- {
- xdc.loadCapsule("bspCommon_AMMU_512MBDDR.cfg");
- }
- else if (CurrentSoc == "tda3xx")
- {
- xdc.loadCapsule("bspCommon_tda3xx_AMMU_512MBDDR.cfg");
- }
- else
- {
- xdc.loadCapsule("bspCommon_AMMU.cfg");
- }
-}
-
diff --git a/examples/cal_capture_test/bspCommon_AMMU_512MBDDR.cfg b/examples/cal_capture_test/bspCommon_AMMU_512MBDDR.cfg
+++ /dev/null
@@ -1,152 +0,0 @@
-/* =============================================================================
- * Copyright (c) Texas Instruments Incorporated 2009-2015
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*******************************************************************************
- * AMMU Config
- *
- ******************************************************************************/
-
-/* use modules */
-var AMMU = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
-
-/* Large PAGE */
-AMMU.largePages[0].pageEnabled = AMMU.Enable_YES;
-AMMU.largePages[0].logicalAddress = 0x40000000;
-AMMU.largePages[0].translatedAddress = 0x40000000;
-AMMU.largePages[0].translationEnabled = AMMU.Enable_YES;
-AMMU.largePages[0].size = AMMU.Large_512M;
-AMMU.largePages[0].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-AMMU.largePages[0].L1_posted = AMMU.PostedPolicy_NON_POSTED;
-AMMU.largePages[0].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-AMMU.largePages[0].L2_posted = AMMU.PostedPolicy_NON_POSTED;
-
-AMMU.largePages[1].pageEnabled = AMMU.Enable_YES;
-AMMU.largePages[1].logicalAddress = 0x80000000;
-AMMU.largePages[1].translatedAddress = 0x80000000;
-AMMU.largePages[1].translationEnabled = AMMU.Enable_YES;
-AMMU.largePages[1].size = AMMU.Large_512M;
-AMMU.largePages[1].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
-AMMU.largePages[1].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
-AMMU.largePages[1].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
-AMMU.largePages[1].L1_posted = AMMU.PostedPolicy_POSTED;
-AMMU.largePages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-AMMU.largePages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED;
-
-AMMU.largePages[2].pageEnabled = AMMU.Enable_YES;
-AMMU.largePages[2].logicalAddress = 0xA0000000;
-AMMU.largePages[2].translatedAddress = 0x80000000;
-AMMU.largePages[2].translationEnabled = AMMU.Enable_YES;
-AMMU.largePages[2].size = AMMU.Large_512M;
-AMMU.largePages[2].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-AMMU.largePages[2].L1_posted = AMMU.PostedPolicy_NON_POSTED;
-AMMU.largePages[2].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-AMMU.largePages[2].L2_posted = AMMU.PostedPolicy_NON_POSTED;
-
-AMMU.largePages[3].pageEnabled = AMMU.Enable_YES;
-AMMU.largePages[3].logicalAddress = 0x60000000;
-AMMU.largePages[3].translatedAddress = 0x40000000;
-AMMU.largePages[3].translationEnabled = AMMU.Enable_YES;
-AMMU.largePages[3].size = AMMU.Large_512M;
-AMMU.largePages[3].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-AMMU.largePages[3].L1_posted = AMMU.PostedPolicy_NON_POSTED;
-AMMU.largePages[3].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-AMMU.largePages[3].L2_posted = AMMU.PostedPolicy_NON_POSTED;
-
-/* Medium Page */
-AMMU.mediumPages[0].pageEnabled = AMMU.Enable_YES;
-AMMU.mediumPages[0].logicalAddress = 0x00300000;
-AMMU.mediumPages[0].translatedAddress = 0x40300000;
-AMMU.mediumPages[0].translationEnabled = AMMU.Enable_YES;
-AMMU.mediumPages[0].size = AMMU.Medium_256K;
-
-AMMU.mediumPages[1].pageEnabled = AMMU.Enable_YES;
-AMMU.mediumPages[1].logicalAddress = 0x00340000;
-AMMU.mediumPages[1].translatedAddress = 0x40340000;
-AMMU.mediumPages[1].translationEnabled = AMMU.Enable_YES;
-AMMU.mediumPages[1].size = AMMU.Medium_256K;
-AMMU.mediumPages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-AMMU.mediumPages[1].L1_posted = AMMU.PostedPolicy_POSTED;
-AMMU.mediumPages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-AMMU.mediumPages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED;
-
-/* Small Page */
-AMMU.smallPages[0].pageEnabled = AMMU.Enable_YES;
-AMMU.smallPages[0].logicalAddress = 0x00000000;
-AMMU.smallPages[0].translatedAddress = 0x55020000;
-AMMU.smallPages[0].translationEnabled = AMMU.Enable_YES;
-AMMU.smallPages[0].size = AMMU.Small_16K;
-AMMU.smallPages[0].volatileQualifier = AMMU.Volatile_FOLLOW;
-AMMU.smallPages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
-AMMU.smallPages[0].L1_posted = AMMU.PostedPolicy_NON_POSTED;
-AMMU.smallPages[0].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-AMMU.smallPages[0].L2_posted = AMMU.PostedPolicy_NON_POSTED;
-
-AMMU.smallPages[1].pageEnabled = AMMU.Enable_YES;
-AMMU.smallPages[1].logicalAddress = 0x40000000;
-AMMU.smallPages[1].translatedAddress = 0x55080000;
-AMMU.smallPages[1].translationEnabled = AMMU.Enable_YES;
-AMMU.smallPages[1].size = AMMU.Small_16K;
-AMMU.smallPages[1].volatileQualifier = AMMU.Volatile_FOLLOW;
-AMMU.smallPages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-AMMU.smallPages[1].L1_posted = AMMU.PostedPolicy_NON_POSTED;
-AMMU.smallPages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-AMMU.smallPages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED;
-
-AMMU.smallPages[2].pageEnabled = AMMU.Enable_YES;
-AMMU.smallPages[2].logicalAddress = 0x00004000;
-AMMU.smallPages[2].translatedAddress = 0x55024000;
-AMMU.smallPages[2].translationEnabled = AMMU.Enable_YES;
-AMMU.smallPages[2].size = AMMU.Small_16K;
-AMMU.smallPages[2].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
-AMMU.smallPages[2].L1_posted = AMMU.PostedPolicy_NON_POSTED;
-AMMU.smallPages[2].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-AMMU.smallPages[2].L2_posted = AMMU.PostedPolicy_NON_POSTED;
-
-AMMU.smallPages[3].pageEnabled = AMMU.Enable_YES;
-AMMU.smallPages[3].logicalAddress = 0x00008000;
-AMMU.smallPages[3].translatedAddress = 0x55028000;
-AMMU.smallPages[3].translationEnabled = AMMU.Enable_YES;
-AMMU.smallPages[3].size = AMMU.Small_16K;
-AMMU.smallPages[3].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-AMMU.smallPages[3].L1_posted = AMMU.PostedPolicy_NON_POSTED;
-AMMU.smallPages[3].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-AMMU.smallPages[3].L2_posted = AMMU.PostedPolicy_NON_POSTED;
-
-AMMU.smallPages[4].pageEnabled = AMMU.Enable_YES;
-AMMU.smallPages[4].logicalAddress = 0x20000000;
-AMMU.smallPages[4].translatedAddress = 0x55020000;
-AMMU.smallPages[4].translationEnabled = AMMU.Enable_YES;
-AMMU.smallPages[4].size = AMMU.Small_16K;
-AMMU.smallPages[4].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-AMMU.smallPages[4].L1_posted = AMMU.PostedPolicy_NON_POSTED;
-AMMU.smallPages[4].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-AMMU.smallPages[4].L2_posted = AMMU.PostedPolicy_NON_POSTED;
diff --git a/examples/cal_capture_test/cal_capture_tda2ex.cfg b/examples/cal_capture_test/cal_capture_tda2ex.cfg
+++ /dev/null
@@ -1 +0,0 @@
-xdc.loadCapsule("bspCommonBIOS.cfg");
index 093d7fe27978c6c17a5f39dacbc630325d2745c5..32665ee750db2c337d46954dc43583063cf57bd9 100755 (executable)
COMP_LIST_COMMON = csl fvid2 cal osal_tirtos
# Enable XDC build for application by providing XDC CFG File per core
-ifeq ($(SOC),$(filter $(SOC), tda2ex))
- XDC_CFG_FILE_ipu1_0 = cal_capture_tda2ex.cfg
-else
XDC_CFG_FILE_$(CORE) = $(PDK_INSTALL_PATH)/ti/build/$(SOC)/sysbios_$(ISA).cfg
-endif
CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) $(CAL_CFLAGS)
PACKAGE_SRCS_COMMON = .
# Common source files and CFLAGS across all platforms and cores
SRCS_COMMON = CaptureCal_main.c calutils_mem_default.c calutils_mem.c
-ifeq ($(SOC),$(filter $(SOC), tda2ex))
- SRCS_COMMON += calapp_sensor.c
- SRCS_COMMON += calutils_ub95x.c calutils_i2c.c
-else
- SRCS_COMMON += calapp_sensor.c
- SRCS_COMMON += calutils_ub95x.c
- #SRCS_COMMON += calutils_i2c.c
- COMP_LIST_COMMON += board uart
- COMP_LIST_COMMON += i2c
-endif
+SRCS_COMMON += calapp_sensor.c
+SRCS_COMMON += calutils_ub95x.c
+COMP_LIST_COMMON += board uart
+COMP_LIST_COMMON += i2c
# Core/SoC/platform specific source files and CFLAGS
# Example:
diff --git a/examples/cal_capture_test/src/CaptureCal_main.c b/examples/cal_capture_test/src/CaptureCal_main.c
index 216b1d89003a8118e1009f599ff5ab10b60a75af..7d64725acb343fccecc7c4a36cbe7d9940e420f6 100755 (executable)
* Most board / EVM specifics are handled in function
* appCaptcreateVidSensor () In addition to configuring the sensor
* for the given config and enable sensor to stream.
- * On TDA2EX only CSI2 based capture is supported.
+ * On AM65xx only CSI2 based capture is supported.
*/
/* ========================================================================== */
/* Include Files */
/**< CSI2 PHY Clock Custom sensor. */
#define APP_CAPT_CAL_SENSOR_BYPASS_PHY_CLK_MHz (400U)
-#if defined (SOC_TDA2EX)
-#define APP_CAPT_MAX_WIDTH (640U)
-#define APP_CAPT_MAX_HEIGHT (480U)
-#else
#define APP_CAPT_MAX_WIDTH (128U)
#define APP_CAPT_MAX_HEIGHT (256U)
-#endif
/* ========================================================================== */
/* Structure Declarations */
/**< Different capture options supported by this demo */
appCaptCfg_t gTestCfg[] = {
-#if defined (SOC_TDA2EX)
- {"Sensor Config Bypassed CSI2 4Lanes capture color bars from UB954", 0U,
- TRUE,
- FVID2_VIFM_SCH_CSI2,
- FVID2_VIFW_4LANES, 1U, 0U, CAL_CSI2_RGB888, FVID2_CCSF_BITS24_PACKED,
- CAPT_APP_RUN_COUNT, 640U, 480U, (640U * 3U),
- //FVID2_VID_SENSOR_BYPASS_CSI2_DRV,
- FVID2_STD_1080P_30, FVID2_DF_BAYER_BGGR, FVID2_CCSF_BITS24_PACKED
- },
-#else
{"Sensor Config Bypassed CSI2 4Lanes capture color bars from UB954", 0U,
TRUE,
FVID2_VIFM_SCH_CSI2,
FVID2_VIFW_4LANES, 1U, 0U, CAL_CSI2_RGB888, FVID2_CCSF_BITS24_PACKED,
CAPT_APP_RUN_COUNT, 128U, 256U, (128U * 3U),
- //FVID2_VID_SENSOR_BYPASS_CSI2_DRV,
FVID2_STD_1080P_30, FVID2_DF_BAYER_BGGR, FVID2_CCSF_BITS24_PACKED
},
-#endif
};
/**< Number of options supported */
diff --git a/examples/cal_capture_test/src/am65xx/calutils_ub95x.h b/examples/cal_capture_test/src/am65xx/calutils_ub95x.h
index 8ac7d9ca570471caa3196b307701c2c11dd490b1..5f28f20e4c8efc2a4e65334ece0c484ec417aed3 100755 (executable)
/* Macros & Typedefs */
/* ========================================================================== */
/**< I2C Instance to be used */
-#if defined (SOC_TDA2EX)
- #define CALUTILS_UB954_I2C_INST_BASEADDR (0x4807C000U)
- /**< I2C Inst Base addr */
-#else
- #define CALUTILS_UB954_I2C_INST_BASEADDR (0x02010000U)
- #define CALUTILS_UB954_I2C_INST (0x1U)
- /**< I2C Inst Base addr */
-#endif
+#define CALUTILS_UB954_I2C_INST (0x1U)
+
+/**< I2C Inst Base addr */
+#define CALUTILS_UB954_I2C_INST_BASEADDR (0x02010000U)
/** \brief Log enable for CAL modules. */
#define calUtilsTrace (GT_INFO | GT_TraceState_Enable)
diff --git a/examples/cal_capture_test/src/calutils_mem_default.c b/examples/cal_capture_test/src/calutils_mem_default.c
index 547d0be76c1845b93291f24dd9a0b4d8226e7dbc..74ed7510db4b58fab32e7316bd95cec3f69873d2 100755 (executable)
#include <calutils_mem.h>
/** \brief Maximum frame buffer memory pool size */
-#if defined (SOC_TDA2XX) || defined (SOC_DRA75x) || defined (SOC_TDA2PX)
-#define CALUTILS_MEM_FRAME_HEAP_SIZE (236U * MB)
-#endif
-
-#if defined (SOC_AM574x) || defined (SOC_AM572x) || defined (SOC_TDA2EX) || defined (SOC_AM571x)
-#define CALUTILS_MEM_FRAME_HEAP_SIZE (242U * MB)
-#endif
-
#if defined (SOC_AM65XX)
#define CALUTILS_MEM_FRAME_HEAP_SIZE (512U * KB)
#endif
-#if defined (SOC_TDA3XX)
- #ifdef PLATFORM_ZEBU
-#define CALUTILS_MEM_FRAME_HEAP_SIZE (64U * MB)
- #else
-#define CALUTILS_MEM_FRAME_HEAP_SIZE (240U * MB)
- #endif
-#define CALUTILS_MEM_FRAME_HEAP_SIZE_12x12 (48U * MB)
-#endif
-
-#if defined (OMAP5430_BUILD)
-#define CALUTILS_MEM_FRAME_HEAP_SIZE (246U * MB)
-#endif
-
-#if defined (TI814X_BUILD) || defined (TI8149_BUILD)
-#define CALUTILS_MEM_FRAME_HEAP_SIZE (123U * MB)
-#endif
-
-#if defined (TI811X_BUILD)
-#define CALUTILS_MEM_FRAME_HEAP_SIZE (57U * MB)
-#endif
-
#ifdef CUSTOM_MEM_FRAME_HEAP_SIZE
#undef CALUTILS_MEM_FRAME_HEAP_SIZE
#define CALUTILS_MEM_FRAME_HEAP_SIZE (CUSTOM_MEM_FRAME_HEAP_SIZE * MB)
diff --git a/examples/cal_capture_test/src/tda2ex/calapp_sensor.c b/examples/cal_capture_test/src/tda2ex/calapp_sensor.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright (c) Texas Instruments Incorporated 2018
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * \file calapp_sensor.c
- *
- * \brief Frame buffer memory allocator API.
- *
- */
-
-/* ========================================================================== */
-/* Include Files */
-/* ========================================================================== */
-
-#include "calutils_ub95x.h"
-
-
-/* ========================================================================== */
-/* Macros & Typedefs */
-/* ========================================================================== */
-
-/* None */
-
-/* ========================================================================== */
-/* Structure Declarations */
-/* ========================================================================== */
-
-/* None */
-
-/* ========================================================================== */
-/* Function Declarations */
-/* ========================================================================== */
-
-/* None */
-
-/* ========================================================================== */
-/* Global Variables */
-/* ========================================================================== */
-
-/* None */
-
-/* ========================================================================== */
-/* Function Definitions */
-/* ========================================================================== */
-int32_t appBoardInit(void)
-{
- return FVID2_SOK;
-}
-
-void appSensorConfigInit(void)
-{
- CalUtils_appInitUb954_Ub953();
-}
-
-void appSensorConfigDeInit(void)
-{
- CalUtils_appDeInitUb954_Ub953();
-}
-
-
diff --git a/examples/cal_capture_test/src/tda2ex/calutils_i2c.c b/examples/cal_capture_test/src/tda2ex/calutils_i2c.c
+++ /dev/null
@@ -1,749 +0,0 @@
-/*
- * Copyright (c) Texas Instruments Incorporated 2018
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * \file calutils_i2c.c
- *
- * \brief I2C driver file
- *
- */
-
-/* ========================================================================== */
-/* Include Files */
-/* ========================================================================== */
-
-#include <stdint.h>
-#include <stdio.h>
-#include <ti/drv/fvid2/fvid2.h>
-#include "calutils_i2c.h"
-
-/* ========================================================================== */
-/* Macros & Typedefs */
-/* ========================================================================== */
-
-/*
- * This below code always uses a single instance of I2C module indicated by
- * I2C_BASE. This baseAddr parameter in several functions is kept for future
- * functionality to use any of the I2C module specified. Currently this is
- * unused.
- */
-#define PRINT_ERROR printf("Error in I2C: %d\n", __LINE__);
-
-/* ========================================================================== */
-/* Structure Declarations */
-/* ========================================================================== */
-
-/* None */
-
-/* ========================================================================== */
-/* Function Declarations */
-/* ========================================================================== */
-
-/* None */
-
-/* ========================================================================== */
-/* Global Variables */
-/* ========================================================================== */
-
-/* None */
-
-/* ========================================================================== */
-/* Function Definitions */
-/* ========================================================================== */
-
-static void udelay(int32_t delay_usec)
-{
- int32_t delay_msec;
- uint32_t i;
- volatile int32_t dummyVar = 0;
-
- delay_msec = (delay_usec / 1000);
- if (delay_msec == 0)
- {
- delay_msec = 1;
- }
- for (i = 0; i < (delay_msec * 100); i++)
- {
- dummyVar += 1;
- }
-
- return;
-}
-
-/* No dependency on platform other than I2C_BASE which
- * is set compile-time.
- */
-int32_t I2C_init(uint32_t baseAddr)
-{
- uint32_t fclk_rate, internal_clk;
- uint32_t psc = 0, scll = 0, sclh = 0;
- uint32_t delay = 1000;
- uint32_t reg_val = 0;
- uint16_t selfAddress = 0xCC;
- CSL_I2cRegs *I2C_BASE = (CSL_I2cRegs *) baseAddr;
-
- /* Reset all registers */
- I2C_WRITE_REG_WORD(0, &(I2C_BASE->I2C_CON));
- I2C_WRITE_REG_WORD(0, &(I2C_BASE->I2C_PSC));
- I2C_WRITE_REG_WORD(0, &(I2C_BASE->I2C_SCLL));
- I2C_WRITE_REG_WORD(0, &(I2C_BASE->I2C_SCLH));
- I2C_WRITE_REG_WORD(0, &(I2C_BASE->I2C_BUF));
- I2C_WRITE_REG_WORD(0, &(I2C_BASE->I2C_SYSC));
- I2C_WRITE_REG_WORD(0, &(I2C_BASE->I2C_WE));
-
- /* Soft-reset */
- I2C_WRITE_REG_WORD(SYSC_SOFTRESET_MASK, &(I2C_BASE->I2C_SYSC));
- I2C_WRITE_REG_WORD(I2C_CON_EN, &(I2C_BASE->I2C_CON));
-
- /* Wait for the reset to get complete */
- while ((!(I2C_READ_REG_WORD(&(I2C_BASE->I2C_SYSS)) &
- SYSS_RESETDONE_MASK)) &&
- delay)
- {
- delay--;
- udelay(I2C_DELAY_SMALL);
- }
- if (!delay)
- {
- /* reset has failed, return!!! */
- PRINT_ERROR;
- return I2C_ERR_TIMEDOUT;
- }
-
- /* SYSC register is cleared by the reset, rewrite it */
- reg_val = SYSC_AUTOIDLE_MASK
- | SYSC_ENAWAKEUP_MASK
- | (SYSC_IDLEMODE_SMART << SYSC_IDLEMODE_SHIFT)
- | (SYSC_CLOCKACTIVITY_FCLK << SYSC_CLOCKACTIVITY_SHIFT);
- I2C_WRITE_REG_WORD(reg_val, &(I2C_BASE->I2C_SYSC));
-
- /* Disable it again */
- I2C_WRITE_REG_WORD(0, &(I2C_BASE->I2C_CON));
-
- internal_clk = I2C_CLK_FREQ;
-
- /* Compute prescaler divisor */
- fclk_rate = I2C_FUNC_CLOCK / 1000;
- psc = fclk_rate / internal_clk;
- psc = psc - 1;
-
- /* Standard and fast speed (upto 400Khz) */
- scll = sclh = internal_clk / (2 * I2C_BUS_FREQ);
-
- scll -= I2C_FASTSPEED_SCLL_TRIM;
- sclh -= I2C_FASTSPEED_SCLH_TRIM;
-
- I2C_WRITE_REG_WORD(psc, &(I2C_BASE->I2C_PSC));
- I2C_WRITE_REG_WORD(scll, &(I2C_BASE->I2C_SCLL));
- I2C_WRITE_REG_WORD(sclh, &(I2C_BASE->I2C_SCLH));
-
- /* Own address */
- I2C_WRITE_REG_WORD(selfAddress, &(I2C_BASE->I2C_OA));
-
- /* Take the I2C module out of reset: */
- I2C_WRITE_REG_WORD(I2C_CON_EN, &(I2C_BASE->I2C_CON));
-
- /* Enable interrupts, if required */
- if (0)
- {
- I2C_WRITE_REG_WORD(I2C_IE_XRDY | I2C_IE_RRDY | I2C_IE_ARDY |
- I2C_IE_NACK | I2C_IE_AL, &I2C_BASE->I2C_IE);
- }
-
- /* Clear STAT register */
- I2C_WRITE_REG_WORD(0xFFFFu, &(I2C_BASE->I2C_STAT));
- /* Read it again */
- reg_val = I2C_READ_REG_WORD(&(I2C_BASE->I2C_STAT));
-
- reg_val = I2C_READ_REG_WORD(&(I2C_BASE->I2C_SYSTEST));
- I2C_WRITE_REG_WORD((reg_val | 0x4000U), &(I2C_BASE->I2C_SYSTEST));
-
- //I2C_WRITE_REG_WORD(0x00u, &(I2C_BASE->I2C_CON));
- return (0);
-}
-
-static int32_t wait_for_bb(uint32_t baseAddr)
-{
- volatile int32_t timeout = 5000;
- uint16_t stat;
- int32_t res = FVID2_SOK;
- CSL_I2cRegs *I2C_BASE = (CSL_I2cRegs *) baseAddr;
-
- /* Clear current interrupts...*/
- I2C_WRITE_REG_WORD(0xFFFF, &I2C_BASE->I2C_STAT);
-
- while ((stat = I2C_READ_REG_WORD(&I2C_BASE->I2C_STAT) & I2C_STAT_BB)
- && timeout--)
- {
- I2C_WRITE_REG_WORD(stat, &I2C_BASE->I2C_STAT);
- udelay(I2C_DELAY_SMALL);
- }
-
- if (timeout <= 0)
- {
- PRINT_ERROR;
- res = I2C_ERR_TIMEDOUT;
- }
-
- /* clear delayed stuff*/
- I2C_WRITE_REG_WORD(0xFFFF, &I2C_BASE->I2C_STAT);
-
- return (res);
-}
-
-static uint16_t wait_for_pin(uint32_t baseAddr)
-{
- uint16_t status;
- CSL_I2cRegs *I2C_BASE = (CSL_I2cRegs *) baseAddr;
- volatile int32_t timeout = 5000;
-
- do
- {
- /*
- * TBD: I2C_DELAY_BIG required with cache ON,
- * otherwise I2C_DELAY_SMALL works.
- * Interrupt mode read/write will not have such problems.
- */
- udelay(I2C_DELAY_BIG);
- status = I2C_READ_REG_WORD(&I2C_BASE->I2C_STAT);
- } while (!(status &
- (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
- I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
- I2C_STAT_AL)) && timeout--);
-
- if (timeout <= 0)
- {
- printf("timed out in wait_for_pin: I2C_STAT=%x\n",
- I2C_READ_REG_WORD(&I2C_BASE->I2C_STAT));
- I2C_WRITE_REG_WORD(0xFFFF, &I2C_BASE->I2C_STAT);
- }
-
- return status;
-}
-
-static void flush_fifo(uint32_t baseAddr)
-{
- volatile uint8_t tempReg;
- uint16_t stat;
- CSL_I2cRegs *I2C_BASE = (CSL_I2cRegs *) baseAddr;
-
- /* note: if you try and read data when its not there or ready
- * you get a bus error
- */
- while (1)
- {
- stat = I2C_READ_REG_WORD(&I2C_BASE->I2C_STAT);
- if (stat == I2C_STAT_RRDY)
- {
- /* Require to drain the data and drop */
- tempReg = I2C_READ_REG_BYTE(&I2C_BASE->I2C_DATA);
- /* Remove the un-used variable warning */
- tempReg = tempReg;
-
- I2C_WRITE_REG_WORD(I2C_STAT_RRDY, &I2C_BASE->I2C_STAT);
- udelay(I2C_DELAY_SMALL);
- }
- else
- {
- break;
- }
- }
-
- return;
-}
-
-static int32_t I2Ci2cTransferMsgPoll(I2c_XferParams *i2cXferParams,
- uint32_t baseAddr)
-{
- uint16_t w = 0;
- uint16_t status = 0;
- CSL_I2cRegs *I2C_BASE = (CSL_I2cRegs *) baseAddr;
- int32_t i2c_error = 0;
- int32_t buflen;
- int32_t retVal = FVID2_SOK;
-
- if (!(i2cXferParams->flags & I2C_IGNORE_BUS_BUSY))
- retVal = wait_for_bb(baseAddr);
- if (FVID2_SOK != retVal)
- {
- PRINT_ERROR;
- return retVal;
- }
- I2C_WRITE_REG_WORD(i2cXferParams->slaveAddr & I2C_ADDR_MASK,
- &I2C_BASE->I2C_SA);
-
- I2C_WRITE_REG_WORD(i2cXferParams->bufLen, &I2C_BASE->I2C_CNT);
-
- /* Enable I2C controller */
- w = I2C_CON_EN;
-
- /* High speed configuration */
- if (I2C_BUS_FREQ > 400)
- w |= I2C_CON_OPMODE_HS;
-
- if (I2C_ADDR_MASK == 0x3FFu)
- w |= I2C_CON_XA;
-
- if (i2cXferParams->flags & I2C_MASTER)
- w |= I2C_CON_MST;
-
- if (i2cXferParams->flags & I2C_WRITE)
- w |= I2C_CON_TRX;
-
- if (i2cXferParams->flags & I2C_START)
- w |= I2C_CON_STT;
-
- if (i2cXferParams->flags & I2C_STOP)
- w |= I2C_CON_STP;
-
- I2C_WRITE_REG_WORD(w, &I2C_BASE->I2C_CON);
-
- status = wait_for_pin(baseAddr);
-
- if (i2cXferParams->flags & I2C_WRITE)
- {
- /* Transmit */
- for (buflen = 0; buflen < i2cXferParams->bufLen; buflen++)
- {
- udelay(0x500000);
- if (status & I2C_STAT_XRDY)
- {
- I2C_WRITE_REG_BYTE(i2cXferParams->buffer[buflen],
- &I2C_BASE->I2C_DATA);
-
- /* dont wait for the last byte */
- if (buflen < i2cXferParams->bufLen - 1)
- status = wait_for_pin(baseAddr);
- }
- else
- {
- PRINT_ERROR;
- i2c_error = 1;
- }
- }
-
- /* must have enough delay to allow BB bit to go low */
- udelay(I2C_DELAY_BIG);
- if (I2C_READ_REG_WORD(&I2C_BASE->I2C_STAT) & I2C_STAT_NACK)
- {
- PRINT_ERROR;
- i2c_error = 1;
- }
- if (!(I2C_READ_REG_WORD(&I2C_BASE->I2C_STAT) & I2C_STAT_ARDY))
- {
- PRINT_ERROR;
- }
- }
- else
- {
- /* Receive */
- for (buflen = 0; buflen < i2cXferParams->bufLen; buflen++)
- {
- if (status & I2C_STAT_RRDY)
- {
- i2cXferParams->buffer[buflen] =
- I2C_READ_REG_BYTE(&I2C_BASE->I2C_DATA);
- udelay(I2C_DELAY_MED);
-
- /* dont wait for the last byte */
- if (buflen < i2cXferParams->bufLen - 1)
- status = wait_for_pin(baseAddr);
- }
- else
- {
- PRINT_ERROR;
- i2c_error = 1;
- }
- }
-
- /* must have enough delay to allow BB bit to go low */
- udelay(I2C_DELAY_BIG);
- if (I2C_READ_REG_WORD(&I2C_BASE->I2C_STAT) & I2C_STAT_NACK)
- {
- PRINT_ERROR;
- i2c_error = 1;
- }
- }
-
- if (i2cXferParams->flags & I2C_STOP)
- {
- flush_fifo(baseAddr);
-
- I2C_WRITE_REG_WORD(0xFFFF, &I2C_BASE->I2C_STAT);
- I2C_WRITE_REG_WORD(0, &I2C_BASE->I2C_CNT);
- }
-
- /* Re-initialize I2C again in case of error */
- if (i2c_error)
- {
- I2C_init(baseAddr);
- }
-
- return i2c_error;
-}
-
-int32_t I2C_deviceWrite8(uint32_t baseAddr, uint32_t devAddr,
- const uint8_t *regAddr,
- const uint8_t *regValue, uint32_t numRegs)
-{
- int32_t status = 0;
- uint32_t regId;
- I2c_XferParams i2cParams;
- uint8_t buffer[2];
-
- if (regAddr == 0 || regValue == 0 || numRegs == 0)
- {
- PRINT_ERROR;
- return FVID2_EFAIL;
- }
-
- if (status == FVID2_SOK)
- {
- i2cParams.slaveAddr = devAddr;
- i2cParams.buffer = buffer;
- i2cParams.bufLen = 2;
- i2cParams.flags = I2C_DEFAULT_WRITE;
- i2cParams.timeout = I2C_TIMEOUT;
-
- for (regId = 0; regId < numRegs; regId++)
- {
- buffer[0] = regAddr[regId];
- buffer[1] = regValue[regId];
-
- status = I2Ci2cTransferMsgPoll(&i2cParams, baseAddr);
- if (status != FVID2_SOK)
- {
- PRINT_ERROR;
- break;
- }
- }
- }
-
- return status;
-}
-
-int32_t I2C_deviceWrite16(uint32_t baseAddr, uint32_t devAddr,
- uint16_t *regAddr,
- const uint8_t *regValue, uint32_t numRegs)
-{
- int32_t status = 0;
- uint32_t regId;
- I2c_XferParams i2cParams;
- uint8_t buffer[3];
-
- if (regAddr == 0 || regValue == 0 || numRegs == 0)
- {
- PRINT_ERROR;
- return FVID2_EFAIL;
- }
-
- if (status == FVID2_SOK)
- {
- i2cParams.slaveAddr = devAddr;
- i2cParams.buffer = buffer;
- i2cParams.bufLen = 3;
- i2cParams.flags = I2C_DEFAULT_WRITE;
- i2cParams.timeout = I2C_TIMEOUT;
-
- for (regId = 0; regId < numRegs; regId++)
- {
- buffer[0] = ((regAddr[regId] >> 8) & 0xFFU);
- buffer[1] = (regAddr[regId] & 0xFFU);
- buffer[2] = regValue[regId];
-
- status = I2Ci2cTransferMsgPoll(&i2cParams, baseAddr);
- if (status != FVID2_SOK)
- {
- PRINT_ERROR;
- break;
- }
- }
- }
-
- return status;
-}
-
-int32_t I2C_deviceWrite16_16(uint32_t baseAddr, uint32_t devAddr,
- uint16_t *regAddr,
- const uint16_t *regValue, uint32_t numRegs)
-{
- int32_t status = 0;
- uint32_t regId;
- I2c_XferParams i2cParams;
- uint8_t buffer[4];
-
- if (regAddr == 0 || regValue == 0 || numRegs == 0)
- {
- PRINT_ERROR;
- return FVID2_EFAIL;
- }
-
- if (status == FVID2_SOK)
- {
- i2cParams.slaveAddr = devAddr;
- i2cParams.buffer = buffer;
- i2cParams.bufLen = 4;
- i2cParams.flags = I2C_DEFAULT_WRITE;
- i2cParams.timeout = I2C_TIMEOUT;
-
- for (regId = 0; regId < numRegs; regId++)
- {
- buffer[0] = ((regAddr[regId] >> 8) & 0xFF);
- buffer[1] = (regAddr[regId] & 0xFF);
- buffer[2] = ((regValue[regId] >> 8) & 0xFF);
- buffer[3] = (regValue[regId] & 0xFF);
-
- status = I2Ci2cTransferMsgPoll(&i2cParams, baseAddr);
- if (status != FVID2_SOK)
- {
- PRINT_ERROR;
- break;
- }
- }
- }
-
- return status;
-}
-
-int32_t I2C_deviceRead8(uint32_t baseAddr, uint32_t devAddr,
- const uint8_t *regAddr,
- uint8_t *regValue, uint32_t numRegs)
-{
- int32_t status = 0;
- uint32_t regId;
- I2c_XferParams i2cParams;
-
- if (regAddr == 0 || regValue == 0 || numRegs == 0)
- {
- PRINT_ERROR;
- return FVID2_EFAIL;
- }
-
- if (status == FVID2_SOK)
- {
- i2cParams.slaveAddr = devAddr;
- i2cParams.bufLen = 1;
- i2cParams.timeout = I2C_TIMEOUT;
-
- for (regId = 0; regId < numRegs; regId++)
- {
- i2cParams.buffer = (uint8_t *) ®Addr[regId];
- i2cParams.flags
- = (I2C_WRITE | I2C_MASTER | I2C_START /* | I2C_STOP */);
-
- status = I2Ci2cTransferMsgPoll(&i2cParams, baseAddr);
- if (status != FVID2_SOK)
- {
- PRINT_ERROR;
- break;
- }
-
- i2cParams.buffer = ®Value[regId];
- i2cParams.flags
- = (I2C_READ | I2C_MASTER | I2C_START | I2C_STOP |
- I2C_IGNORE_BUS_BUSY);
-
- status = I2Ci2cTransferMsgPoll(&i2cParams, baseAddr);
- if (status != FVID2_SOK)
- {
- PRINT_ERROR;
- break;
- }
- }
- }
-
- return status;
-}
-
-int32_t I2C_deviceRead16(uint32_t baseAddr, uint32_t devAddr,
- uint16_t *regAddr,
- uint8_t *regValue, uint32_t numRegs)
-{
- int32_t status = 0;
- uint32_t regId;
- I2c_XferParams i2cParams;
- uint8_t buffer[2];
-
- if (regAddr == 0 || regValue == 0 || numRegs == 0)
- {
- PRINT_ERROR;
- return FVID2_EFAIL;
- }
-
- if (status == FVID2_SOK)
- {
- i2cParams.slaveAddr = devAddr;
- i2cParams.timeout = I2C_TIMEOUT;
-
- for (regId = 0; regId < numRegs; regId++)
- {
- buffer[0] = ((regAddr[regId] >> 8) & 0xFF);
- buffer[1] = (regAddr[regId] & 0xFF);
- i2cParams.buffer = buffer;
- i2cParams.bufLen = 2;
- i2cParams.flags
- = (I2C_WRITE | I2C_MASTER | I2C_START /* | I2C_STOP */);
-
- status = I2Ci2cTransferMsgPoll(&i2cParams, baseAddr);
- if (status != FVID2_SOK)
- {
- PRINT_ERROR;
- break;
- }
-
- i2cParams.bufLen = 1;
- i2cParams.buffer = ®Value[regId];
- i2cParams.flags
- = (I2C_READ | I2C_MASTER | I2C_START | I2C_STOP |
- I2C_IGNORE_BUS_BUSY);
-
- status = I2Ci2cTransferMsgPoll(&i2cParams, baseAddr);
- if (status != FVID2_SOK)
- {
- PRINT_ERROR;
- break;
- }
- }
- }
-
- return status;
-}
-
-int32_t I2C_probe(uint32_t baseAddr, uint8_t slaveAddr)
-{
- int32_t res = 1; /* default = fail */
- uint32_t reg_val;
- CSL_I2cRegs *I2C_BASE = (CSL_I2cRegs *) baseAddr;
- if (slaveAddr == I2C_READ_REG_WORD(&I2C_BASE->I2C_OA))
- {
- PRINT_ERROR;
- return res;
- }
-
- /* Disable interrupts first */
- reg_val = I2C_READ_REG_WORD(&I2C_BASE->I2C_IE);
- I2C_WRITE_REG_WORD(0x00u, &I2C_BASE->I2C_IE);
-
- /* wait until bus not busy */
- wait_for_bb(baseAddr);
-
- /* try to write one byte */
- I2C_WRITE_REG_WORD(1, &I2C_BASE->I2C_CNT);
-
- /* set slave address */
- I2C_WRITE_REG_WORD(slaveAddr, &I2C_BASE->I2C_SA);
-
- /* stop bit needed here */
- I2C_WRITE_REG_WORD(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
- &I2C_BASE->I2C_CON);
-
- /* enough delay for the NACK bit set */
- udelay(I2C_DELAY_BIG);
-
- if (!(I2C_READ_REG_WORD(&I2C_BASE->I2C_STAT) & I2C_STAT_NACK))
- {
- res = 0; /* success case */
- flush_fifo(baseAddr);
- I2C_WRITE_REG_WORD(0xFFFF, &I2C_BASE->I2C_STAT);
- }
- else
- {
- I2C_WRITE_REG_WORD(0xFFFF, &I2C_BASE->I2C_STAT); /* failue, clear
- *sources*/
- I2C_WRITE_REG_WORD(I2C_READ_REG_WORD(&I2C_BASE->I2C_CON) | I2C_CON_STP,
- &I2C_BASE->I2C_CON); /* finish up
- *xfer */
- udelay(I2C_DELAY_MED);
- wait_for_bb(baseAddr);
- }
-
- flush_fifo(baseAddr);
-
- I2C_WRITE_REG_WORD(0, &I2C_BASE->I2C_CNT);
- I2C_WRITE_REG_WORD(0xFFFF, &I2C_BASE->I2C_STAT);
-
- /* Enable interrupts now */
- I2C_WRITE_REG_WORD(reg_val, &I2C_BASE->I2C_IE);
-
- return res;
-}
-
-int32_t I2C_deviceRawRead8(uint32_t baseAddr,
- uint32_t devAddr,
- uint8_t *regValue,
- uint32_t numRegs)
-{
- int32_t status = 0;
- I2c_XferParams i2cParams;
-
- if (FVID2_SOK == status)
- {
- i2cParams.slaveAddr = devAddr;
- i2cParams.bufLen = numRegs;
- i2cParams.timeout = I2C_TIMEOUT;
- i2cParams.buffer = (uint8_t *) regValue;
- i2cParams.flags = (I2C_DEFAULT_READ);
- status = I2Ci2cTransferMsgPoll(&i2cParams, baseAddr);
- if (FVID2_SOK != status)
- {
- PRINT_ERROR;
- }
- }
-
- return status;
-}
-
-int32_t I2C_deviceRawWrite8(uint32_t baseAddr,
- uint32_t devAddr,
- uint8_t *regValue,
- uint32_t numRegs)
-{
- int32_t status = 0;
- I2c_XferParams i2cParams;
-
- if (FVID2_SOK == status)
- {
- i2cParams.slaveAddr = devAddr;
- i2cParams.buffer = regValue;
- i2cParams.bufLen = numRegs;
- i2cParams.flags = I2C_DEFAULT_WRITE;
- i2cParams.timeout = I2C_TIMEOUT;
- status = I2Ci2cTransferMsgPoll(&i2cParams, baseAddr);
- if (FVID2_SOK != status)
- {
- PRINT_ERROR;
- }
- }
-
- return status;
-}
-
diff --git a/examples/cal_capture_test/src/tda2ex/calutils_i2c.h b/examples/cal_capture_test/src/tda2ex/calutils_i2c.h
+++ /dev/null
@@ -1,393 +0,0 @@
-/*
- * Copyright (c) Texas Instruments Incorporated 2018
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * \file calutils_i2c.h
- *
- * \brief I2C driver header file
- *
- */
-
-#ifndef CAL_UTILS_I2C_H_
-#define CAL_UTILS_I2C_H_
-
-/* ========================================================================== */
-/* Include Files */
-/* ========================================================================== */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* ========================================================================== */
-/* Macros & Typedefs */
-/* ========================================================================== */
-
-/* None */
-
-/* ========================================================================== */
-/* Structures and Enums */
-/* ========================================================================== */
-
-/**************************************************************************\
- * Register Overlay Structure
- \**************************************************************************/
-typedef struct
-{
- volatile uint32_t I2C_REVNB_LO; /* 0x00 */
- volatile uint32_t I2C_REVNB_HI; /* 0x04 */
- volatile uint32_t RSVD0[2];
- volatile uint32_t I2C_SYSC; /* 0x10 */
- volatile uint32_t RSVD1[3];
- volatile uint32_t I2C_EOI; /* 0x20 */
- volatile uint32_t I2C_IRQSTATUS_RAW; /* 0x24 */
- volatile uint32_t I2C_IRQSTATUS; /* 0x28 */
- volatile uint32_t I2C_IRQENABLE_SET; /* 0x2C */
- volatile uint32_t I2C_IRQENABLE_CLR; /* 0x30 */
- volatile uint32_t I2C_WE; /* 0x34 */
- volatile uint32_t I2C_DMARXENABLE_SET; /* 0x38 */
- volatile uint32_t I2C_DMATXENABLE_SET; /* 0x3C */
- volatile uint32_t I2C_DMARXENABLE_CLR; /* 0x40 */
- volatile uint32_t I2C_DMATXENABLE_CLR; /* 0x44 */
- volatile uint32_t I2C_DMARXWAKE_EN; /* 0x48 */
- volatile uint32_t I2C_DMATXWAKE_EN; /* 0x4C */
- volatile uint32_t RSVD2[13];
- volatile uint32_t I2C_IE; /* 0x84 */
- volatile uint32_t I2C_STAT; /* 0x88 */
- volatile uint32_t RSVD3; /* 0x8C */
- volatile uint32_t I2C_SYSS; /* 0x90 */
- volatile uint32_t I2C_BUF; /* 0x94 */
- volatile uint32_t I2C_CNT; /* 0x98 */
- volatile uint32_t I2C_DATA; /* 0x9C */
- volatile uint32_t RSVD4; /* 0xA0 */
- volatile uint32_t I2C_CON; /* 0xA4 */
- volatile uint32_t I2C_OA; /* 0xA8 */
- volatile uint32_t I2C_SA; /* 0xAC */
- volatile uint32_t I2C_PSC; /* 0xB0 */
- volatile uint32_t I2C_SCLL; /* 0xB4 */
- volatile uint32_t I2C_SCLH; /* 0xB8 */
- volatile uint32_t I2C_SYSTEST; /* 0xBC */
- volatile uint32_t I2C_BUFSTAT; /* 0xC0 */
- volatile uint32_t I2C_OA1; /* 0xC4 */
- volatile uint32_t I2C_OA2; /* 0xC8 */
- volatile uint32_t I2C_OA3; /* 0xCC */
- volatile uint32_t I2C_ACTOA; /* 0xD0 */
- volatile uint32_t I2C_SBLOCK; /* 0xD4 */
-} CSL_I2cRegs;
-
-/**************************************************************************\
- * Overlay structure typedef definition
- \**************************************************************************/
-typedef volatile CSL_I2cRegs *CSL_I2cRegsOvly;
-
-/**************************************************************************\
- * Field Definition Macros
- \**************************************************************************/
-/* I2C Interrupt Enable Register (I2C_IE): */
-#define I2C_IE_XDR (1u << 14) /* TX Buffer drain int enable */
-#define I2C_IE_RDR (1u << 13) /* RX Buffer drain int enable */
-#define I2C_IE_XRDY (1u << 4) /* TX data ready int enable */
-#define I2C_IE_RRDY (1u << 3) /* RX data ready int enable */
-#define I2C_IE_ARDY (1u << 2) /* Access ready int enable */
-#define I2C_IE_NACK (1u << 1) /* No ack interrupt enable */
-#define I2C_IE_AL (1u << 0) /* Arbitration lost int ena */
-
-/* I2C Status Register (I2C_STAT): */
-#define I2C_STAT_XDR (1u << 14) /* TX Buffer draining */
-#define I2C_STAT_RDR (1u << 13) /* RX Buffer draining */
-#define I2C_STAT_BB (1u << 12) /* Bus busy */
-#define I2C_STAT_ROVR (1u << 11) /* Receive overrun */
-#define I2C_STAT_XUDF (1u << 10) /* Transmit underflow */
-#define I2C_STAT_AAS (1u << 9) /* Address as slave */
-#define I2C_STAT_AD0 (1u << 8) /* Address zero */
-#define I2C_STAT_XRDY (1u << 4) /* Transmit data ready */
-#define I2C_STAT_RRDY (1u << 3) /* Receive data ready */
-#define I2C_STAT_ARDY (1u << 2) /* Register access ready */
-#define I2C_STAT_NACK (1u << 1) /* No ack interrupt enable */
-#define I2C_STAT_AL (1u << 0) /* Arbitration lost int ena */
-
-/* I2C WE wakeup enable register */
-#define I2C_WE_XDR_WE (1u << 14) /* TX drain wakup */
-#define I2C_WE_RDR_WE (1u << 13) /* RX drain wakeup */
-#define I2C_WE_AAS_WE (1u << 9) /* Address as slave wakeup*/
-#define I2C_WE_BF_WE (1u << 8) /* Bus free wakeup */
-#define I2C_WE_STC_WE (1u << 6) /* Start condition wakeup */
-#define I2C_WE_GC_WE (1u << 5) /* General call wakeup */
-#define I2C_WE_DRDY_WE (1u << 3) /* TX/RX data ready wakeup */
-#define I2C_WE_ARDY_WE (1u << 2) /* Reg access ready wakeup */
-#define I2C_WE_NACK_WE (1u << 1) /* No acknowledgment wakeup */
-#define I2C_WE_AL_WE (1u << 0) /* Arbitration lost wakeup */
-
-#define I2C_WE_ALL (I2C_WE_XDR_WE | I2C_WE_RDR_WE | \
- I2C_WE_AAS_WE | I2C_WE_BF_WE | \
- I2C_WE_STC_WE | I2C_WE_GC_WE | \
- I2C_WE_DRDY_WE | I2C_WE_ARDY_WE | \
- I2C_WE_NACK_WE | I2C_WE_AL_WE)
-
-/* I2C Buffer Configuration Register (I2C_BUF): */
-#define I2C_BUF_RDMA_EN (1u << 15) /* RX DMA channel enable */
-#define I2C_BUF_RXFIF_CLR (1u << 14) /* RX FIFO Clear */
-#define I2C_BUF_XDMA_EN (1u << 7) /* TX DMA channel enable */
-#define I2C_BUF_TXFIF_CLR (1u << 6) /* TX FIFO Clear */
-
-/* I2C Configuration Register (I2C_CON): */
-#define I2C_CON_EN (1u << 15) /* I2C module enable */
-#define I2C_CON_BE (1u << 14) /* Big endian mode */
-#define I2C_CON_OPMODE_HS (1u << 12) /* High Speed support */
-#define I2C_CON_STB (1u << 11) /* Start byte mode (master) */
-#define I2C_CON_MST (1u << 10) /* Master/slave mode */
-#define I2C_CON_TRX (1u << 9) /* TX/RX mode (master only) */
-#define I2C_CON_XA (1u << 8) /* Expand address */
-#define I2C_CON_RM (1u << 2) /* Repeat mode (master only) */
-#define I2C_CON_STP (1u << 1) /* Stop cond (master only) */
-#define I2C_CON_STT (1u << 0) /* Start condition (master) */
-
-/* I2C SCL time value when Master */
-#define I2C_SCLL_HSSCLL (8u)
-#define I2C_SCLH_HSSCLH (8u)
-
-/* OCP_SYSSTATUS bit definitions */
-#define SYSS_RESETDONE_MASK (1u << 0)
-
-/* OCP_SYSCONFIG bit definitions */
-#define SYSC_CLOCKACTIVITY_MASK (0x3u << 8)
-#define SYSC_CLOCKACTIVITY_SHIFT (8u)
-#define SYSC_SIDLEMODE_MASK (0x3u << 3)
-#define SYSC_IDLEMODE_SHIFT (3u)
-#define SYSC_ENAWAKEUP_MASK (1u << 2)
-#define SYSC_SOFTRESET_MASK (1u << 1)
-#define SYSC_AUTOIDLE_MASK (1u << 0)
-
-#define SYSC_IDLEMODE_SMART (0x2u)
-#define SYSC_CLOCKACTIVITY_FCLK (0x2u)
-
-#define I2C_ADDR_MASK (0x7Fu)
-
-/**
- * Max I2C driver opens allowed.
- * Note: If required, this number can be increased
- */
-#define I2C_NUM_OPENS (4u)
-
-/** Min I2C bus frequency - 1 KHz */
-#define I2C_MIN_BUS_FREQ (1u)
-/** Max I2C bus frequency - 400 KHz */
-#define I2C_MAX_BUS_FREQ (400u)
-
-/** Bus Busy Timeout (counter, should depend upon CPU speed) */
-#define I2C_BUS_BUSY_TIMEOUT_CNT (10000000u)
-/** Bus Busy Timeout (mSecs) */
-#define I2C_BUS_BUSY_TIMEOUT_MSECS (10u)
-
-/* I2C data transfer timeout (in mSecs) */
-#define I2C_DATA_TRANSFER_TIMEOUT_SECS (1000u)
-
-/* I2C device busy timeout (in mSecs) */
-#define I2C_DEVICE_BUSY_TIMEOUT_SECS (5000u)
-
-/** Maximum buffer length which could be transferred */
-#define I2C_BUFFER_MAXLENGTH (65536u)
-
-#define I2C_DELAY_MULTIPLIER (100u)
-
-/**
- * \brief I2C driver state
- *
- * These enums are used to maintain the current state of the driver
- */
-typedef enum
-{
- I2C_DELETED = 0u, /**< Instance Deleted */
- I2C_CREATED, /**< Instance Created */
- I2C_OPENED, /**< Instance Open */
- I2C_CLOSED /**< Instance Closed */
-} I2cState;
-
-/* ========================================================================== */
-/* Macros & Typedefs */
-/* ========================================================================== */
-
-#define I2C_TIMEOUT ((uint32_t) - 1)
-
-#define I2C_READ_REG_BYTE(reg) (*(volatile unsigned char *) (reg))
-#define I2C_READ_REG_WORD(reg) (*(volatile unsigned int *) (reg))
-
-#define I2C_WRITE_REG_BYTE(val, reg) (*(volatile unsigned char *) (reg) = \
- (val))
-#define I2C_WRITE_REG_WORD(val, reg) (*(volatile unsigned int *) (reg) = \
- (val))
-
-#define I2C_STANDARD (100000)
-#define I2C_FAST_MODE (400000)
-#define I2C_HIGH_SPEED (3400000)
-
-/* I2C functional clock is 96MHz */
-#define I2C_FUNC_CLOCK (96000000)
-#define I2C_BUS_FREQ (400)
-#if (I2C_BUS_FREQ > 100)
- #define I2C_CLK_FREQ (12000)
-#else
- #define I2C_CLK_FREQ (4000)
-#endif
-
-#define I2C_FASTSPEED_SCLL_TRIM (7)
-#define I2C_FASTSPEED_SCLH_TRIM (5)
-
-#define I2C_DELAY_BIG (500000)
-#define I2C_DELAY_MED (50000)
-#define I2C_DELAY_SMALL (50000)
-
-#define I2C_ERR_TIMEDOUT (-100)
-#define I2C_ERR_INVALID_PARAMS (-101)
-#define I2C_ERR_IO (-102)
-
-/**
- * \brief I2C Transfer Params
- *
- * This structure holds the information needed to carry out a transaction on
- * I2C bus to a slave device.
- */
-typedef struct
-{
- uint8_t slaveAddr;
- /**< Address of the slave to talk to, not valid in Slave mode */
- uint8_t *buffer;
- /**< Data buffer */
- uint32_t bufLen;
- /**< Length of buffer */
- uint32_t flags;
- /**< Flags to indicate the various modes of operation */
- uint32_t timeout;
- /**< Timeout value */
- void *param;
- /**< Extra parameter for future use */
-} I2c_XferParams;
-
-/* ========================================================================== */
-/* Macros & Typedefs */
-/* ========================================================================== */
-
-/*
- * I2C Driver Error codes
- */
-
-/** \brief Returned when the I2C bus find that the bus is busy */
-#define I2C_BUS_BUSY_ERR ((int32_t) - 1)
-
-/** \brief Returned when the I2C driver lost the bus arbitration */
-#define I2C_ARBITRATION_LOSS_ERR ((int32_t) - 2)
-
-/** \brief Returned when the I2C slave did not acknowledgement */
-#define I2C_NACK_ERR ((int32_t) - 3)
-
-/** \brief Returned in case of an transmit underflow error */
-#define I2C_TRANSMIT_UNDERFLOW_ERR ((int32_t) - 4)
-
-/** \brief Returned in case of an receive overflow error */
-#define I2C_RECEIVE_OVERFLOW_ERR ((int32_t) - 5)
-
-/* Note: The following flags offer the user maximum flexibility in terms
- * of making the right I2C transaction. In case the user does not want
- * to set the flags on his own, the default read/write flag can be specified
- */
-
-/** \brief Read from I2C bus (device) */
-#define I2C_READ (0x0001u)
-
-/** \brief Write to I2C bus (device) */
-#define I2C_WRITE (0x0002u)
-
-/** \brief Configure I2C in Master mode */
-#define I2C_MASTER (0x0004u)
-
-/** \brief Configure I2C in Slave mode (currently not supported) */
-#define I2C_SLAVE (0x0008u)
-
-/** \brief Generate Start - valid in master mode only */
-#define I2C_START (0x0010u)
-
-/** \brief Generate Stop - valid in master mode only */
-#define I2C_STOP (0x0020u)
-
-/** \brief Re-Start is generated by Master */
-#define I2C_RESTART (0x0040u)
-
-/** \brief Repeat mode */
-#define I2C_REPEAT (0x0080u)
-
-/** \brief Ignore Bus Busy condition */
-#define I2C_IGNORE_BUS_BUSY (0x0100u)
-
-/** \brief Ignore NAK */
-#define I2C_M_IGNORE_NAK (0x0200u)
-
-/* Use these flags for simple MASTER read/write transactions on the I2C bus */
-/** \brief Default read flag */
-#define I2C_DEFAULT_READ \
- (I2C_READ | I2C_MASTER | I2C_START | I2C_STOP)
-/** \brief Default write flag */
-#define I2C_DEFAULT_WRITE \
- (I2C_WRITE | I2C_MASTER | I2C_START | I2C_STOP)
-
-/* ========================================================================== */
-/* Function Declarations */
-/* ========================================================================== */
-
-int32_t I2C_init(uint32_t baseAddr);
-int32_t I2C_probe(uint32_t baseAddr, uint8_t slaveAddr);
-
-int32_t I2C_deviceRead8(uint32_t baseAddr, uint32_t devAddr,
- const uint8_t *regAddr,
- uint8_t *regValue, uint32_t numRegs);
-int32_t I2C_deviceWrite8(uint32_t baseAddr, uint32_t devAddr,
- const uint8_t *regAddr,
- const uint8_t *regValue, uint32_t numRegs);
-int32_t I2C_deviceRawRead8(uint32_t baseAddr,
- uint32_t devAddr,
- uint8_t *regValue,
- uint32_t numRegs);
-int32_t I2C_deviceRawWrite8(uint32_t baseAddr,
- uint32_t devAddr,
- uint8_t *regValue,
- uint32_t numRegs);
-int32_t I2C_deviceWrite16(uint32_t baseAddr, uint32_t devAddr,
- uint16_t *regAddr,
- const uint8_t *regValue, uint32_t numRegs);
-int32_t I2C_deviceRead16(uint32_t baseAddr, uint32_t devAddr,
- uint16_t *regAddr,
- uint8_t *regValue, uint32_t numRegs);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* I2C_H_ */
diff --git a/examples/cal_capture_test/src/tda2ex/calutils_ub95x.c b/examples/cal_capture_test/src/tda2ex/calutils_ub95x.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Copyright (c) Texas Instruments Incorporated 2018
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * \file calutils_ub95x.c
- *
- * \brief Implements APIs to initialize, de-initialize UB954 * UB953 EVM,
- * address aliases & reset sensors.
- *
- */
-
-/* ========================================================================== */
-/* Include Files */
-/* ========================================================================== */
-
-#include <ti/csl/soc.h>
-#include <calutils_ub95x.h>
-#include <calutils_i2c.h>
-
-
-/* ========================================================================== */
-/* Macros & Typedefs */
-/* ========================================================================== */
-/**< UB954 I2C Address */
-#define UB954_I2C_ADDRESS (0x3D)
-
-/**< UB953 I2C Address */
-#define UB953_I2C_ADDRESS (0x18)
-/**< UB953 Alias I2C Address */
-#define UB953_I2C_ALIAS_ADDRESS (0x74)
-
-/**< OV7261 I2C Address */
-#define OV7261_I2C_ADDRESS (0x60)
-/**< OV7261 Alias I2C Address */
-#define OV7261_I2C_ALIAS_ADDRESS (0x38)
-
-/**< Temperature sensor I2C Address */
-#define TEMP_SENS_I2C_ADDRESS (0x48)
-/**< Temperature sensor Alias I2C Address */
-#define TEMP_SENS_I2C_ALIAS_ADDRESS (0x76)
-
-/**< LED Driver I2C Address */
-#define LED_DRV_I2C_ADDRESS (0x49)
-/**< LED Driver Alias I2C Address */
-#define LED_DRV_I2C_ALIAS_ADDRESS (0x78)
-
-/**
- * \brief Register address and value pair, with delay.
- */
-typedef struct
-{
- uint8_t nRegAddr;
- /**< Register Address */
- uint8_t nRegValue;
- /**< Slave Address */
- uint32_t nDelay;
- /**< Delay to be applied, after the register is programmed */
-} CalUtils_Ub95xI2cParams;
-
-/* ========================================================================== */
-/* Function Declarations */
-/* ========================================================================== */
-static void CalUtils_setI2cPinmux(void);
-
-/* ========================================================================== */
-/* Global Variables */
-/* ========================================================================== */
-
-static CalUtils_Ub95xI2cParams gUb954Cfg[]={
- {0x4c, 0x01, 0x1},
- {0x58, 0X5e, 0x2},
- {0x5b, (UB953_I2C_ADDRESS << 1U), 0x1},
- {0x5c, (UB953_I2C_ALIAS_ADDRESS << 1U), 0x1},
- {0x5D, (OV7261_I2C_ADDRESS << 1U), 0x1},
- {0x65, (OV7261_I2C_ALIAS_ADDRESS << 1U), 0x1},
- {0x5e, (TEMP_SENS_I2C_ADDRESS << 1U), 0x1},
- {0x66, (TEMP_SENS_I2C_ALIAS_ADDRESS << 1U), 0x1},
- {0x5f, (LED_DRV_I2C_ADDRESS << 1U), 0x1},
- {0x67, (LED_DRV_I2C_ALIAS_ADDRESS << 1U), 0x1},
- {0x1f, 0x02, 0x1},
- {0x12, 0x13, 0x1},
- {0x32, 0x01, 0x1},
- {0x33, 0x03, 0x1},
- {0xB0, 0x00, 0x1}, /* Indirect access to pattern genrator */
- {0xB1, 0x01, 0x1}, /* Select Reg PGEN_CTL */
- {0xB2, 0x01, 0x1}, /* Write 1 to it */
- {0x20, 0x00, 0x1}
- };
-
-/* NOTE : Expect to see color bar, where the color values should be default
- i.e. first bar = 0xAA, 2nd Bar = 0x33, 3rd bar = 0xF0, 4th bar = 0x7F
- 5th bar = 0x55, 6th bar = 0xCC, 7th bar = 0x0F and 8th bar = 0x80 */
-/* ========================================================================== */
-/* Function Implementation */
-/* ========================================================================== */
-void CalUtils_appInitUb954_Ub953(void)
-{
- int32_t retVal;
- uint32_t idx, numRegs;
- uint8_t ub954I2CAddr = UB954_I2C_ADDRESS;
- CalUtils_setI2cPinmux();
- I2C_init(CALUTILS_UB954_I2C_INST_BASEADDR);
- numRegs = sizeof(gUb954Cfg) / (sizeof(gUb954Cfg[0]));
- for (idx = 0U; idx < numRegs; idx++)
- {
- retVal = I2C_deviceWrite8(CALUTILS_UB954_I2C_INST_BASEADDR,
- ub954I2CAddr,
- &(gUb954Cfg[idx].nRegAddr),
- &(gUb954Cfg[idx].nRegValue),
- (uint32_t) 1U);
- if (retVal != FVID2_SOK)
- {
- GT_0trace(calUtilsTrace, GT_ERR,
- "Could not configure UB954 !!!\r\n");
- break;
- }
- if (0 != gUb954Cfg[idx].nDelay)
- {
- Osal_delay(gUb954Cfg[idx].nDelay * 100);
- }
- }
- GT_1trace(calUtilsTrace, GT_INFO,
- "Configured UB954 [%d]!!!\r\n", retVal);
-
- return;
-}
-
-void CalUtils_appDeInitUb954_Ub953(void)
-{
- uint8_t regAddr, regValue;
- int32_t retVal;
-
- /* Disable Forwarding */
- regAddr = 0x20;
- regValue = 0x48;
-
- retVal = I2C_deviceWrite8(CALUTILS_UB954_I2C_INST_BASEADDR,
- UB954_I2C_ADDRESS,
- ®Addr,
- ®Value,
- (uint32_t) 1U);
- if (retVal != FVID2_SOK)
- {
- GT_0trace(calUtilsTrace, GT_ERR, "Could not disable forwarding UB954 !!!\r\n");
- }
- else
- {
- /* Reset */
- regAddr = 0x01;
- regValue = 0x03;
-
- retVal = I2C_deviceWrite8(CALUTILS_UB954_I2C_INST_BASEADDR,
- UB954_I2C_ADDRESS,
- ®Addr,
- ®Value,
- (uint32_t) 1U);
- if (retVal != FVID2_SOK)
- {
- GT_0trace(calUtilsTrace, GT_ERR, "Could not reset UB954 !!!\r\n");
- }
- }
-
-}
-
-void CalUtils_setI2cPinmux(void)
-{
-#ifdef SOC_TDA2EX
- *((volatile uint32_t *)(0x4A0036B4)) = 0xC000A;
- *((volatile uint32_t *)(0x4A0036B8)) = 0xC000A;
-#endif
-}
-
diff --git a/examples/cal_capture_test/src/tda2ex/calutils_ub95x.h b/examples/cal_capture_test/src/tda2ex/calutils_ub95x.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Copyright (c) Texas Instruments Incorporated 2018
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * \addtogroup CALUTILS_UB960_API
- * @{
- */
-
-/**
- * \file calutils_ub960.h
- *
- * \brief Defines APIs to initialize, de-initialize UB960 EVM, address aliases
- * & reset sensors.
- *
- * TODO: Get serializer address function should be common for all modules.
- * Right now, its seperate for TIDA, SAT0088 & IMI modules
- */
-
-#ifndef CALUTILS_UB95X_H_
-#define CALUTILS_UB95X_H_
-
-/* ========================================================================== */
-/* Include Files */
-/* ========================================================================== */
-#include <ti/drv/fvid2/fvid2.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* ========================================================================== */
-/* Macros & Typedefs */
-/* ========================================================================== */
-/**< I2C Instance to be used */
-#if defined (SOC_TDA2EX)
- #define CALUTILS_UB954_I2C_INST_BASEADDR (0x4807C000U)
- /**< I2C Inst Base addr */
-#else
- #define CALUTILS_UB954_I2C_INST_BASEADDR (0x02000000U)
- /**< I2C Inst Base addr */
-#endif
-
-/** \brief Log enable for CAL modules. */
-#define calUtilsTrace (GT_INFO | GT_TraceState_Enable)
-/* ========================================================================== */
-/* Structure Declarations */
-/* ========================================================================== */
-/* None */
-
-/* ========================================================================== */
-/* Function Declarations */
-/* ========================================================================== */
-
-/**
- * \brief Initializes the UB954 & UB953.
- * Initializes UB954, UB953 and configures to access 2 other remote
- * I2C slaves
- */
-void CalUtils_appInitUb954_Ub953(void);
-
-/**
- * \brief De Initializes the UB954 & UB953
- * Turns off power to 1 slave, resets UB953 & UB954
- */
-void CalUtils_appDeInitUb954_Ub953(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #define CALUTILS_UB95X_H_ */
-
-/* @} */
diff --git a/include/cal_cfg.h b/include/cal_cfg.h
index ffb0bf8038e3d738079b23b592e5540f3180a3d3..11e0ed8f29a507db2cc6022fc9fc6d9e9e72e70c 100755 (executable)
--- a/include/cal_cfg.h
+++ b/include/cal_cfg.h
/** \brief Number of queue length per capture channel in capture driver */
#define CAL_CAPT_QUEUE_LEN_PER_CH (16U)
-/** \brief Defines the total number of complex IO available per CAL (2) */
-#if defined (SOC_TDA2EX)
-#define CAL_CAPT_MAX_CMPLXIO_INST (2U)
-#endif
-/** \brief Defines the total number of complex IO available per CAL (1) */
-#if defined (SOC_TDA3XX)
-#define CAL_CAPT_MAX_CMPLXIO_INST (1U)
-#endif
/** \brief Defines the total number of complex IO available per CAL (1) */
#if defined (SOC_AM65XX)
#define CAL_CAPT_MAX_CMPLXIO_INST (1U)
diff --git a/src/core/cal_evtmgr.c b/src/core/cal_evtmgr.c
index e37724bfc206913711ef6f5e8806e71ffff45b1c..c0065257a2646e9c099c2b1068989be0d43023e3 100755 (executable)
--- a/src/core/cal_evtmgr.c
+++ b/src/core/cal_evtmgr.c
{
CAL_EM_INST_ID_CAL0,
71,
- #if defined (SOC_TDA2EX)
- {ISS_CALA_BASE_REGISTER}
- #else
{CSL_CAL0_BASE}
- #endif
},
}
};
instObj->eoiAddr =
initPrms->baseAddress[instCnt] +
- CAL_HL_IRQ_EOI;
+ CSL_CAL_C2CTL_HL_IRQ_EOI;
/* ----------------- Register ISR --------------- */
HwiP_Params_init(&hwiParams);
/* Disable the interrupts at the CAL level */
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_HL_IRQENABLE_CLR(calIrqNum);
+ CSL_CAL_C2IRQ_HL_IRQENABLE_CLR(calIrqNum);
HW_WR_REG32(regAddr, ((uint32_t) 1 << calEvent));
/* Clear the status of the interrupt */
}
/* Disable the interrupts at the CAL level */
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_HL_IRQENABLE_CLR(0U);
+ CSL_CAL_C2IRQ_HL_IRQENABLE_CLR(0U);
HW_WR_REG32(regAddr, ((uint32_t) 1 << calEvent));
/* Clear the status of the interrupt */
/* Disable the interrupt and clear status */
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_CSI2_COMPLEXIO_IRQENABLE(0U);
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_IRQENABLE(0U);
regVal = HW_RD_REG32(regAddr);
regVal &= ~((uint32_t) 1 << event);
HW_WR_REG32(regAddr, regVal);
/* Disable the interrupts at the CAL level */
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_HL_IRQENABLE_CLR(0U);
+ CSL_CAL_C2IRQ_HL_IRQENABLE_CLR(0U);
HW_WR_REG32(regAddr, ((uint32_t) 1 << calEvent));
/* Clear the status of the interrupt */
calEvent = event - CAL_CSI2_PPI_VC_SOF1;
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_CSI2_VC_IRQENABLE(0U);
+ CSL_CAL_C2PPI_CSI2_VC_IRQENABLE(0U);
regVal = HW_RD_REG32(regAddr);
regVal &= ~((uint32_t) 1 << calEvent);
HW_WR_REG32(regAddr, regVal);
/* Disable the interrupts at the CAL level */
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_HL_IRQENABLE_CLR(calIrqNum);
+ CSL_CAL_C2IRQ_HL_IRQENABLE_CLR(calIrqNum);
HW_WR_REG32(regAddr, ((uint32_t) 1 << calEvent));
/* Clear the status of the interrupt */
}
/* Disable the interrupts at the CAL level */
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_HL_IRQENABLE_CLR(0U);
+ CSL_CAL_C2IRQ_HL_IRQENABLE_CLR(0U);
HW_WR_REG32(regAddr, ((uint32_t) 1 << calEvent));
/* Clear the status of the interrupt */
/* Disable the interrupt and clear status */
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_CSI2_COMPLEXIO_IRQENABLE(0U);
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_IRQENABLE(0U);
regVal = HW_RD_REG32(regAddr);
regVal &= ~((uint32_t) 1 << event);
HW_WR_REG32(regAddr, regVal);
}
/* Disable the interrupts at the CAL level */
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_HL_IRQENABLE_CLR(0U);
+ CSL_CAL_C2IRQ_HL_IRQENABLE_CLR(0U);
HW_WR_REG32(regAddr, ((uint32_t) 1 << calEvent));
/* Clear the status of the interrupt */
calEvent = event - CAL_CSI2_PPI_VC_SOF1;
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_CSI2_VC_IRQENABLE(0U);
+ CSL_CAL_C2PPI_CSI2_VC_IRQENABLE(0U);
regVal = HW_RD_REG32(regAddr);
regVal &= ~((uint32_t) 1 << calEvent);
HW_WR_REG32(regAddr, regVal);
}
/* Enable the interrupts at the CAL level */
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_HL_IRQENABLE_SET(calIrqNum);
+ CSL_CAL_C2IRQ_HL_IRQENABLE_SET(calIrqNum);
/* Clear the status of the interrupt */
HW_WR_REG32(clientInfo->statusClrReg[cnt][1U],
}
/* Disable the interrupts at the CAL level */
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_HL_IRQENABLE_SET(0U);
+ CSL_CAL_C2IRQ_HL_IRQENABLE_SET(0U);
HW_WR_REG32(regAddr, ((uint32_t) 1 << calEvent));
/* Clear the status of the interrupt */
/* Disable the interrupt and clear status */
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_CSI2_COMPLEXIO_IRQENABLE(0U);
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_IRQENABLE(0U);
regVal = HW_RD_REG32(regAddr);
regVal |= ((uint32_t) 1 << event);
HW_WR_REG32(regAddr, regVal);
}
/* Disable the interrupts at the CAL level */
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_HL_IRQENABLE_SET(0U);
+ CSL_CAL_C2IRQ_HL_IRQENABLE_SET(0U);
HW_WR_REG32(regAddr, ((uint32_t) 1 << calEvent));
/* Clear the status of the interrupt */
calEvent = event - CAL_CSI2_PPI_VC_SOF1;
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_CSI2_VC_IRQENABLE(0U);
+ CSL_CAL_C2PPI_CSI2_VC_IRQENABLE(0U);
regVal = HW_RD_REG32(regAddr);
regVal |= ((uint32_t) 1 << calEvent);
HW_WR_REG32(regAddr, regVal);
/* Enable the interrupts at the CAL level */
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_HL_IRQENABLE_SET(calIrqNum);
+ CSL_CAL_C2IRQ_HL_IRQENABLE_SET(calIrqNum);
regVal = HW_RD_REG32(regAddr);
regVal |= ((uint32_t) 1 << calEvent);
HW_WR_REG32(regAddr, regVal);
/* Store the register address in clientInfo instance */
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_HL_IRQSTATUS(calIrqNum);
+ CSL_CAL_C2IRQ_HL_IRQSTATUS(calIrqNum);
clientInfo->statusReg[cnt][1U] = regAddr;
clientInfo->statusClrReg[cnt][1U] = regAddr;
clientInfo->mask[cnt][1U] = ((uint32_t) 1U << calEvent);
clientInfo->subModuleEoiAddr[cnt] =
initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_HL_IRQ_EOI;
+ CSL_CAL_C2CTL_HL_IRQ_EOI;
clientInfo->subModuleEoiLine[cnt] = 0U;
}
#if defined(NOT_YET)
/* These events are to processed at 3 levels
0 : Top CAL level - Above for loop address this
1 : At CAL level either PPI, PPI_VC or BYS_OVR
- 2 : Instance specific errors CAL_CSI2_COMPLEXIO_IRQSTATUS &
- per virtual channel CAL_CSI2_VC_IRQENABLE */
+ 2 : Instance specific errors CSL_CAL_C2PPI_CSI2_COMPLEXIO_IRQSTATUS &
+ per virtual channel CSL_CAL_C2PPI_CSI2_VC_IRQENABLE */
if ((CAL_EM_EG_CAL_PPI0_CSI2 == eventGroup) ||
(CAL_EM_EG_CAL_PPI1_CSI2 == eventGroup))
{
if (FVID2_SOK == status)
{
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_HL_IRQENABLE_SET(0U);
+ CSL_CAL_C2IRQ_HL_IRQENABLE_SET(0U);
regVal = HW_RD_REG32(regAddr);
regVal |= ((uint32_t) 1 << calEvent);
HW_WR_REG32(regAddr, regVal);
/* Store the register address in clientInfo instance */
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_HL_IRQSTATUS(0U);
+ CSL_CAL_C2IRQ_HL_IRQSTATUS(0U);
clientInfo->statusReg[cnt][1U] = regAddr;
clientInfo->statusClrReg[cnt][1U] = regAddr;
clientInfo->mask[cnt][1U] = ((uint32_t) 1U << calEvent);
{
calEvent = event[cnt];
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_CSI2_COMPLEXIO_IRQENABLE(0U);
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_IRQENABLE(0U);
regVal = HW_RD_REG32(regAddr);
regVal |= ((uint32_t) 1 << calEvent);
HW_WR_REG32(regAddr, regVal);
/* Store the register address in clientInfo instance */
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_CSI2_COMPLEXIO_IRQSTATUS(0U);
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_IRQSTATUS(0U);
clientInfo->statusReg[cnt][2U] = regAddr;
clientInfo->statusClrReg[cnt][2U] = regAddr;
clientInfo->mask[cnt][2U] =
calEvent = event[cnt] - CAL_CSI2_PPI_VC_SOF1;
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_CSI2_VC_IRQENABLE(0U);
+ CSL_CAL_C2PPI_CSI2_VC_IRQENABLE(0U);
regVal = HW_RD_REG32(regAddr);
regVal |= ((uint32_t) 1 << calEvent);
HW_WR_REG32(regAddr, regVal);
/* Store the register address in clientInfo instance */
regAddr = initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_CSI2_VC_IRQSTATUS(0U);
+ CSL_CAL_C2PPI_CSI2_VC_IRQSTATUS(0U);
clientInfo->statusReg[cnt][2U] = regAddr;
clientInfo->statusClrReg[cnt][2U] = regAddr;
clientInfo->mask[cnt][2U] =
clientInfo->subModuleEoiAddr[cnt] =
initPrms->baseAddress[CAL_EM_MODULE_CAL] +
- CAL_HL_IRQ_EOI;
+ CSL_CAL_C2CTL_HL_IRQ_EOI;
clientInfo->subModuleEoiLine[cnt] = 0U;
}
}
diff --git a/src/drv/cal_drvInit.c b/src/drv/cal_drvInit.c
index 17a66483325f4f5edfbb26622102bf79b924e1d3..4a64ea78906f431318d81832a2a62fc44566ad69 100755 (executable)
--- a/src/drv/cal_drvInit.c
+++ b/src/drv/cal_drvInit.c
/* ========================================================================== */
/* Global Variables */
/* ========================================================================== */
-#if defined (SOC_TDA2EX) || defined (SOC_AM65XX)
-static CalDrv_PlatformData gCalDrvPlatDataTda2ex;
-#endif
-//static CalDrv_PlatformData gCalDrvPlatDataAm6xx;
+static CalDrv_PlatformData gCalDrvPlatDataAm6xx;
/* ========================================================================== */
/* Function Definitions */
uint32_t instCnt, CalInstCnt = 0;
CalDrv_CaptInitParams calDrvInitPrms[CAL_CAPT_INST_ID_MAX];
-#if defined (SOC_TDA2EX) || defined (SOC_AM65XX)
+#if defined (SOC_AM65XX)
CalDrv_initPlatData();
#endif
{
uint32_t idx = 0;
- gCalDrvPlatDataTda2ex.calDrvInitPrms[idx].drvInstId = CAL_CAPT_INST_ID_A_ID;
- gCalDrvPlatDataTda2ex.calDrvInitPrms[idx].coreInstObj = NULL;
- gCalDrvPlatDataTda2ex.calDrvInitPrms[idx].coreOps = NULL;
+ gCalDrvPlatDataAm6xx.calDrvInitPrms[idx].drvInstId = CAL_CAPT_INST_ID_A_ID;
+ gCalDrvPlatDataAm6xx.calDrvInitPrms[idx].coreInstObj = NULL;
+ gCalDrvPlatDataAm6xx.calDrvInitPrms[idx].coreOps = NULL;
idx++;
- gCalDrvPlatDataTda2ex.calDrvInitPrms[idx].drvInstId = CAL_CAPT_INST_ID_A_ID;
- gCalDrvPlatDataTda2ex.calDrvInitPrms[idx].coreInstObj = NULL;
- gCalDrvPlatDataTda2ex.calDrvInitPrms[idx].coreOps = NULL;
+ gCalDrvPlatDataAm6xx.calDrvInitPrms[idx].drvInstId = CAL_CAPT_INST_ID_A_ID;
+ gCalDrvPlatDataAm6xx.calDrvInitPrms[idx].coreInstObj = NULL;
+ gCalDrvPlatDataAm6xx.calDrvInitPrms[idx].coreOps = NULL;
idx++;
GT_assert(CalTrace, (CAL_CAPT_INST_ID_MAX >= idx));
}
const CalDrv_PlatformData *CalDrv_getPlatformData(void)
{
CalDrv_PlatformData *platData = NULL;
-#if defined (SOC_TDA2EX) || defined (SOC_AM65XX)
- platData = &gCalDrvPlatDataTda2ex;
+#if defined (SOC_AM65XX)
+ platData = &gCalDrvPlatDataAm6xx;
#else
GT_0trace(CalTrace, GT_ERR, "VPS: Unsupported SOC!!\r\n");
#endif
diff --git a/src/hal/cal_hal.c b/src/hal/cal_hal.c
index 0b74443cd21b9414bda82de652cc902a6580042d..c526e5ac08a07210df63a8bf04fbcdef3f8c6ca8 100755 (executable)
--- a/src/hal/cal_hal.c
+++ b/src/hal/cal_hal.c
/* Assuming CAL receives via a sensor */
gCalInstDefaults.rdDmaStall = (uint32_t)TRUE;
gCalInstDefaults.pwrScpClk = (uint32_t)FALSE;
- gCalInstDefaults.dmaBurstSize = CAL_CTRL_BURSTSIZE_BURST128;
+ gCalInstDefaults.dmaBurstSize = CSL_CAL_C2VID_CTRL_BURSTSIZE_BURST128;
gCalInstDefaults.tagCnt = 15U;
gCalInstDefaults.postedWrites = (uint32_t)FALSE;
{
/* Last instance of open, disable PPI */
reg = HW_RD_REG32(hndl->pInstObj->baseAddr +
- CAL_CSI2_PPI_CTRL(instance));
- reg &= ~CAL_CSI2_PPI_CTRL_IF_EN_MASK;
+ CSL_CAL_C2PPI_CSI2_PPI_CTRL(instance));
+ reg &= ~CSL_CAL_C2PPI_CSI2_PPI_CTRL_IF_EN_MASK;
HW_WR_REG32(hndl->pInstObj->baseAddr +
- CAL_CSI2_PPI_CTRL(instance), reg);
+ CSL_CAL_C2PPI_CSI2_PPI_CTRL(instance), reg);
rtnVal = FVID2_SOK;
}
#endif /* ENABLE_PPI_WHEN_STARTING */
if(1U == hndl->pInstObj->openCnt)
{
reg = HW_RD_REG32(hndl->pInstObj->baseAddr +
- CAL_CSI2_COMPLEXIO_CFG(i));
- reg &= ~(CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK);
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG(i));
+ reg &= ~(CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK);
HW_WR_REG32(hndl->pInstObj->baseAddr +
- CAL_CSI2_COMPLEXIO_CFG(i), reg);
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG(i), reg);
/* Wait for power down completion */
timeOut = 0xFFFFU;
while(timeOut)
{
reg = HW_RD_REG32(hndl->pInstObj->baseAddr +
- CAL_CSI2_COMPLEXIO_CFG(i));
- if(0U == (reg & CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK))
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG(i));
+ if(0U == (reg & CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK))
{
break;
}
{
/* For the very last clos ensure that there are no pending
DMA reads */
- reg = HW_RD_REG32(hndl->pInstObj->baseAddr + CAL_RD_DMA_CTRL);
- if(CAL_RD_DMA_CTRL_GO_MASK == (reg & CAL_RD_DMA_CTRL_GO_MASK))
+ reg = HW_RD_REG32(hndl->pInstObj->baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL);
+ if(CSL_CAL_C2VID_RD_DMA_CTRL_GO_MASK == (reg & CSL_CAL_C2VID_RD_DMA_CTRL_GO_MASK))
{
rtnVal = FVID2_EDEVICE_INUSE;
}
baseAddr = pInstObj->baseAddr;
offset = pInstObj->instCfg.ppiCfg[idx].instance;
reg =
- HW_RD_REG32(baseAddr + CAL_CSI2_PPI_CTRL(offset));
- reg |= CAL_CSI2_PPI_CTRL_IF_EN_MASK;
- HW_WR_REG32(baseAddr + CAL_CSI2_PPI_CTRL(offset),
+ HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_PPI_CTRL(offset));
+ reg |= CSL_CAL_C2PPI_CSI2_PPI_CTRL_IF_EN_MASK;
+ HW_WR_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_PPI_CTRL(offset),
reg);
}
}
baseAddr = pInstObj->baseAddr;
offset = pInstObj->instCfg.ppiCfg[idx].instance;
reg =
- HW_RD_REG32(baseAddr + CAL_CSI2_PPI_CTRL(offset));
- reg &= ~((uint32_t) CAL_CSI2_PPI_CTRL_IF_EN_MASK);
- HW_WR_REG32(baseAddr + CAL_CSI2_PPI_CTRL(offset),
+ HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_PPI_CTRL(offset));
+ reg &= ~((uint32_t) CSL_CAL_C2PPI_CSI2_PPI_CTRL_IF_EN_MASK);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_PPI_CTRL(offset),
reg);
}
}
if(((uint32_t)0x0 == (uint32_t)bufPtrs->cPortId[idx]) &&
(CAL_HAL_MODE_M2M == hndl->mode))
{
- reg = HW_RD_REG32(baseAddr + CAL_RD_DMA_PIX_ADDR);
- reg &= ~CAL_RD_DMA_PIX_ADDR_MASK;
- reg |= CAL_RD_DMA_PIX_ADDR_MASK &
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_PIX_ADDR);
+ reg &= ~CSL_CAL_C2VID_RD_DMA_PIX_ADDR_ADDR_MASK;
+ reg |= CSL_CAL_C2VID_RD_DMA_PIX_ADDR_ADDR_MASK &
bufPtrs->buffAddr[idx];
- HW_WR_REG32(baseAddr + CAL_RD_DMA_PIX_ADDR, reg);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_PIX_ADDR, reg);
- reg = HW_RD_REG32(baseAddr + CAL_RD_DMA_PIX_OFST);
- reg &= ~CAL_RD_DMA_PIX_OFST_MASK;
- reg |= CAL_RD_DMA_PIX_OFST_MASK &
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_PIX_OFST);
+ reg &= ~CSL_CAL_C2VID_RD_DMA_PIX_OFST_OFST_MASK;
+ reg |= CSL_CAL_C2VID_RD_DMA_PIX_OFST_OFST_MASK &
bufPtrs->pitch[idx];
- HW_WR_REG32(baseAddr + CAL_RD_DMA_PIX_OFST, reg);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_PIX_OFST, reg);
}
if((CAL_HAL_MODE_M2M == hndl->mode) ||
(CAL_HAL_MODE_CAPTURE == hndl->mode))
{
reg = HW_RD_REG32(baseAddr +
- CAL_WR_DMA_ADRR(bufPtrs->wrDmaCtx
+ CSL_CAL_WR_DMA_WR_DMA_ADDR(bufPtrs->wrDmaCtx
[idx]));
- reg &= ~CAL_WR_DMA_ADRR_ADDR_MASK;
- reg |= CAL_WR_DMA_ADRR_ADDR_MASK &
+ reg &= ~CSL_CAL_WR_DMA_WR_DMA_ADDR_ADDR_MASK;
+ reg |= CSL_CAL_WR_DMA_WR_DMA_ADDR_ADDR_MASK &
bufPtrs->buffAddr[idx];
HW_WR_REG32(baseAddr +
- CAL_WR_DMA_ADRR(
+ CSL_CAL_WR_DMA_WR_DMA_ADDR(
bufPtrs->wrDmaCtx[idx]), reg);
}
}
rtnVal = FVID2_EAGAIN;
- reg = HW_RD_REG32(pInstObj->baseAddr + CAL_RD_DMA_CTRL);
- if(CAL_RD_DMA_CTRL_GO_MASK != (reg & CAL_RD_DMA_CTRL_GO_MASK))
+ reg = HW_RD_REG32(pInstObj->baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL);
+ if(CSL_CAL_C2VID_RD_DMA_CTRL_GO_MASK != (reg & CSL_CAL_C2VID_RD_DMA_CTRL_GO_MASK))
{
- reg |= CAL_RD_DMA_CTRL_GO_MASK;
+ reg |= CSL_CAL_C2VID_RD_DMA_CTRL_GO_MASK;
rtnVal = FVID2_SOK;
- HW_WR_REG32(pInstObj->baseAddr + CAL_RD_DMA_CTRL, reg);
+ HW_WR_REG32(pInstObj->baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL, reg);
}
}
else
{
baseAddr = hndl->pInstObj->baseAddr;
- rtnVal = (HW_RD_REG32(baseAddr + CAL_HL_IRQSTATUS_RAW(0U)) &
- CAL_HL_IRQSTATUS_RAW_IRQ3_MASK) >> CAL_HL_IRQSTATUS_RAW_IRQ3_SHIFT;
+ rtnVal = (HW_RD_REG32(baseAddr + CSL_CAL_C2IRQ_HL_IRQSTATUS_RAW(0U)) &
+ CSL_CAL_C2IRQ_HL_IRQSTATUS_RAW_IRQ3_MASK) >> CSL_CAL_C2IRQ_HL_IRQSTATUS_RAW_IRQ3_SHIFT;
}
return (rtnVal);
else
{
baseAddr = hndl->pInstObj->baseAddr;
- regVal = HW_RD_REG32(baseAddr + CAL_HL_IRQSTATUS_RAW(0U));
- regVal |= CAL_HL_IRQSTATUS_RAW_IRQ2_MASK;
- HW_WR_REG32(baseAddr + CAL_HL_IRQSTATUS_RAW(0U), regVal);
+ regVal = HW_RD_REG32(baseAddr + CSL_CAL_C2IRQ_HL_IRQSTATUS_RAW(0U));
+ regVal |= CSL_CAL_C2IRQ_HL_IRQSTATUS_RAW_IRQ2_MASK;
+ HW_WR_REG32(baseAddr + CSL_CAL_C2IRQ_HL_IRQSTATUS_RAW(0U), regVal);
}
}
else
{
baseAddr = hndl->pInstObj->baseAddr;
- rtnVal = (HW_RD_REG32(baseAddr + CAL_HL_IRQSTATUS_RAW(0U)) &
- CAL_HL_IRQSTATUS_RAW_IRQ2_MASK) >> CAL_HL_IRQSTATUS_RAW_IRQ2_SHIFT;
+ rtnVal = (HW_RD_REG32(baseAddr + CSL_CAL_C2IRQ_HL_IRQSTATUS_RAW(0U)) &
+ CSL_CAL_C2IRQ_HL_IRQSTATUS_RAW_IRQ2_MASK) >> CSL_CAL_C2IRQ_HL_IRQSTATUS_RAW_IRQ2_SHIFT;
}
return (rtnVal);
GT_assert(CalTrace, (0U != baseAddr));
timeOut = 0xFFFFU;
- reg = HW_RD_REG32(baseAddr + CAL_HL_SYSCONFIG);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2CTL_HL_SYSCONFIG);
- reg &= ~((uint32_t) CAL_HL_SYSCONFIG_IDLEMODE_MASK);
- reg |= CAL_HL_SYSCONFIG_IDLEMODE_MASK & ((uint32_t) CAL_HL_SYSCONFIG_IDLEMODE_NO <<
- CAL_HL_SYSCONFIG_IDLEMODE_SHIFT);
+ reg &= ~((uint32_t) CSL_CAL_C2CTL_HL_SYSCONFIG_IDLEMODE_MASK);
+ reg |= CSL_CAL_C2CTL_HL_SYSCONFIG_IDLEMODE_MASK & ((uint32_t) CSL_CAL_C2CTL_HL_SYSCONFIG_IDLEMODE_NO <<
+ CSL_CAL_C2CTL_HL_SYSCONFIG_IDLEMODE_SHIFT);
- reg |= CAL_HL_SYSCONFIG_SOFTRESET_MASK;
- HW_WR_REG32(baseAddr + CAL_HL_SYSCONFIG, reg);
+ reg |= CSL_CAL_C2CTL_HL_SYSCONFIG_SOFTRESET_MASK;
+ HW_WR_REG32(baseAddr + CSL_CAL_C2CTL_HL_SYSCONFIG, reg);
while(timeOut)
{
- reg = HW_RD_REG32(baseAddr + CAL_HL_SYSCONFIG);
- if(CAL_HL_SYSCONFIG_SOFTRESET_MASK !=
- (reg & CAL_HL_SYSCONFIG_SOFTRESET_MASK))
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2CTL_HL_SYSCONFIG);
+ if(CSL_CAL_C2CTL_HL_SYSCONFIG_SOFTRESET_MASK !=
+ (reg & CSL_CAL_C2CTL_HL_SYSCONFIG_SOFTRESET_MASK))
{
break;
}
/* If reset is not done, timeOut will be zero, so only one
condition check required here
If reset is done, this condition is anyway false. */
- if((reg & CAL_HL_SYSCONFIG_SOFTRESET_MASK) ==
- CAL_HL_SYSCONFIG_SOFTRESET_MASK)
+ if((reg & CSL_CAL_C2CTL_HL_SYSCONFIG_SOFTRESET_MASK) ==
+ CSL_CAL_C2CTL_HL_SYSCONFIG_SOFTRESET_MASK)
{
/* Reset did not complete. We would require an PRCM reset now! */
rtnVal = FVID2_ETIMEOUT;
uint32_t baseAddr, const Cal_HalInstCfg_t *pCfg)
{
volatile uint32_t reg;
- reg = HW_RD_REG32(baseAddr + CAL_CTRL);
- reg &= ~(CAL_CTRL_POSTED_WRITES_MASK | CAL_CTRL_TAGCNT_MASK |
- CAL_CTRL_BURSTSIZE_MASK | CAL_CTRL_MFLAGL_MASK |
- CAL_CTRL_PWRSCPCLK_MASK | CAL_CTRL_RD_DMA_STALL_MASK |
- CAL_CTRL_MFLAGH_MASK);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_CTRL);
+ reg &= ~(CSL_CAL_C2VID_CTRL_POSTED_WRITES_MASK | CSL_CAL_C2VID_CTRL_TAGCNT_MASK |
+ CSL_CAL_C2VID_CTRL_BURSTSIZE_MASK | CSL_CAL_C2VID_CTRL_MFLAGL_MASK |
+ CSL_CAL_C2VID_CTRL_PWRSCPCLK_MASK | CSL_CAL_C2VID_CTRL_RD_DMA_STALL_MASK |
+ CSL_CAL_C2VID_CTRL_MFLAGH_MASK);
- reg |= CAL_CTRL_MFLAGH_MASK & (pCfg->mFlagH << CAL_CTRL_MFLAGH_SHIFT);
+ reg |= CSL_CAL_C2VID_CTRL_MFLAGH_MASK & (pCfg->mFlagH << CSL_CAL_C2VID_CTRL_MFLAGH_SHIFT);
if((uint32_t)TRUE == pCfg->rdDmaStall)
{
- reg |= CAL_CTRL_RD_DMA_STALL_MASK;
+ reg |= CSL_CAL_C2VID_CTRL_RD_DMA_STALL_MASK;
}
if((uint32_t)TRUE == pCfg->pwrScpClk)
{
- reg |= CAL_CTRL_PWRSCPCLK_MASK;
+ reg |= CSL_CAL_C2VID_CTRL_PWRSCPCLK_MASK;
}
- reg |= CAL_CTRL_MFLAGL_MASK & (pCfg->mFlagL << CAL_CTRL_MFLAGL_SHIFT);
+ reg |= CSL_CAL_C2VID_CTRL_MFLAGL_MASK & (pCfg->mFlagL << CSL_CAL_C2VID_CTRL_MFLAGL_SHIFT);
- reg |= CAL_CTRL_BURSTSIZE_MASK &
- (pCfg->dmaBurstSize << CAL_CTRL_BURSTSIZE_SHIFT);
+ reg |= CSL_CAL_C2VID_CTRL_BURSTSIZE_MASK &
+ (pCfg->dmaBurstSize << CSL_CAL_C2VID_CTRL_BURSTSIZE_SHIFT);
- reg |= CAL_CTRL_TAGCNT_MASK & (pCfg->tagCnt << CAL_CTRL_TAGCNT_SHIFT);
+ reg |= CSL_CAL_C2VID_CTRL_TAGCNT_MASK & (pCfg->tagCnt << CSL_CAL_C2VID_CTRL_TAGCNT_SHIFT);
if((uint32_t)TRUE == pCfg->postedWrites)
{
- reg |= CAL_CTRL_POSTED_WRITES_MASK;
+ reg |= CSL_CAL_C2VID_CTRL_POSTED_WRITES_MASK;
}
- HW_WR_REG32(baseAddr + CAL_CTRL, reg);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_CTRL, reg);
return FVID2_SOK;
}
@@ -1250,51 +1250,51 @@ static int32_t CalCfgInstLanePpiCfg(uint32_t baseAddr, Cal_HalInstCfg_t *pCfg)
/* Setup the polarity of lanes */
if((uint32_t)TRUE == pCmplxIoCfg->enable)
{
- reg = HW_RD_REG32(baseAddr + CAL_CSI2_COMPLEXIO_CFG(idx));
- reg &= ~(CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK |
- CAL_CSI2_COMPLEXIO_CFG_DATA1_POSITION_MASK |
- CAL_CSI2_COMPLEXIO_CFG_DATA2_POSITION_MASK |
- CAL_CSI2_COMPLEXIO_CFG_DATA3_POSITION_MASK |
- CAL_CSI2_COMPLEXIO_CFG_DATA4_POSITION_MASK);
- reg &= ~(CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK |
- CAL_CSI2_COMPLEXIO_CFG_DATA1_POL_MASK |
- CAL_CSI2_COMPLEXIO_CFG_DATA2_POL_MASK |
- CAL_CSI2_COMPLEXIO_CFG_DATA3_POL_MASK |
- CAL_CSI2_COMPLEXIO_CFG_DATA4_POL_MASK);
- reg |= CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK &
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG(idx));
+ reg &= ~(CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK |
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA1_POSITION_MASK |
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA2_POSITION_MASK |
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA3_POSITION_MASK |
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA4_POSITION_MASK);
+ reg &= ~(CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK |
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA1_POL_MASK |
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA2_POL_MASK |
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA3_POL_MASK |
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA4_POL_MASK);
+ reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK &
pCmplxIoCfg->clockLane.position;
- reg |= CAL_CSI2_COMPLEXIO_CFG_DATA1_POSITION_MASK &
+ reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA1_POSITION_MASK &
(pCmplxIoCfg->data1Lane.position <<
- CAL_CSI2_COMPLEXIO_CFG_DATA1_POSITION_SHIFT);
- reg |= CAL_CSI2_COMPLEXIO_CFG_DATA2_POSITION_MASK &
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA1_POSITION_SHIFT);
+ reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA2_POSITION_MASK &
(pCmplxIoCfg->data2Lane.position <<
- CAL_CSI2_COMPLEXIO_CFG_DATA2_POSITION_SHIFT);
- reg |= CAL_CSI2_COMPLEXIO_CFG_DATA3_POSITION_MASK &
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA2_POSITION_SHIFT);
+ reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA3_POSITION_MASK &
(pCmplxIoCfg->data3Lane.position <<
- CAL_CSI2_COMPLEXIO_CFG_DATA3_POSITION_SHIFT);
- reg |= CAL_CSI2_COMPLEXIO_CFG_DATA4_POSITION_MASK &
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA3_POSITION_SHIFT);
+ reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA4_POSITION_MASK &
(pCmplxIoCfg->data4Lane.position <<
- CAL_CSI2_COMPLEXIO_CFG_DATA4_POSITION_SHIFT);
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA4_POSITION_SHIFT);
- reg |= CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK &
+ reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK &
(pCmplxIoCfg->clockLane.pol <<
- CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_SHIFT);
- reg |= CAL_CSI2_COMPLEXIO_CFG_DATA1_POL_MASK &
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_CLOCK_POL_SHIFT);
+ reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA1_POL_MASK &
(pCmplxIoCfg->data1Lane.pol <<
- CAL_CSI2_COMPLEXIO_CFG_DATA1_POL_SHIFT);
- reg |= CAL_CSI2_COMPLEXIO_CFG_DATA2_POL_MASK &
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA1_POL_SHIFT);
+ reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA2_POL_MASK &
(pCmplxIoCfg->data2Lane.pol <<
- CAL_CSI2_COMPLEXIO_CFG_DATA2_POL_SHIFT);
- reg |= CAL_CSI2_COMPLEXIO_CFG_DATA3_POL_MASK &
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA2_POL_SHIFT);
+ reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA3_POL_MASK &
(pCmplxIoCfg->data3Lane.pol <<
- CAL_CSI2_COMPLEXIO_CFG_DATA3_POL_SHIFT);
- reg |= CAL_CSI2_COMPLEXIO_CFG_DATA4_POL_MASK &
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA3_POL_SHIFT);
+ reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA4_POL_MASK &
(pCmplxIoCfg->data4Lane.pol <<
- CAL_CSI2_COMPLEXIO_CFG_DATA4_POL_SHIFT);
- HW_WR_REG32(baseAddr + CAL_CSI2_COMPLEXIO_CFG(idx), reg);
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA4_POL_SHIFT);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG(idx), reg);
/* Dummy read to wait for SCP write to complete */
- reg = HW_RD_REG32(baseAddr + CAL_CSI2_COMPLEXIO_CFG(idx));
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG(idx));
}
}
/* PPI Config */
@@ -1310,25 +1310,25 @@ static int32_t CalCfgInstLanePpiCfg(uint32_t baseAddr, Cal_HalInstCfg_t *pCfg)
break;
}
- reg = HW_RD_REG32(baseAddr + CAL_CSI2_PPI_CTRL(offset));
- reg &= ~((uint32_t) (CAL_CSI2_PPI_CTRL_IF_EN_MASK |
- CAL_CSI2_PPI_CTRL_FRAME_MASK |
- CAL_CSI2_PPI_CTRL_ECC_EN_MASK));
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_PPI_CTRL(offset));
+ reg &= ~((uint32_t) (CSL_CAL_C2PPI_CSI2_PPI_CTRL_IF_EN_MASK |
+ CSL_CAL_C2PPI_CSI2_PPI_CTRL_FRAME_MASK |
+ CSL_CAL_C2PPI_CSI2_PPI_CTRL_ECC_EN_MASK));
if((uint32_t)TRUE == pCfg->ppiCfg[idx].ecc)
{
- reg |= CAL_CSI2_PPI_CTRL_ECC_EN_MASK;
+ reg |= CSL_CAL_C2PPI_CSI2_PPI_CTRL_ECC_EN_MASK;
}
if((uint32_t)TRUE == pCfg->ppiCfg[idx].frame)
{
- reg |= CAL_CSI2_PPI_CTRL_FRAME_MASK;
+ reg |= CSL_CAL_C2PPI_CSI2_PPI_CTRL_FRAME_MASK;
}
- HW_WR_REG32(baseAddr + CAL_CSI2_PPI_CTRL(offset), reg);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_PPI_CTRL(offset), reg);
#ifndef ENABLE_PPI_WHEN_STARTING
- reg = HW_RD_REG32(baseAddr + CAL_CSI2_PPI_CTRL(offset));
- reg |= CAL_CSI2_PPI_CTRL_IF_EN_MASK;
- HW_WR_REG32(baseAddr + CAL_CSI2_PPI_CTRL(offset), reg);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_PPI_CTRL(offset));
+ reg |= CSL_CAL_C2PPI_CSI2_PPI_CTRL_IF_EN_MASK;
+ HW_WR_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_PPI_CTRL(offset), reg);
#endif /* ENABLE_PPI_WHEN_STARTING */
}
}
/* . Apply M2M config */
if((FVID2_SOK == rtnVal) && (CAL_HAL_MODE_M2M == mode))
{
- reg = HW_RD_REG32(baseAddr + CAL_CTRL);
- reg &= ~(CAL_CTRL_RD_DMA_STALL_MASK | CAL_CTRL_PWRSCPCLK_MASK |
- CAL_CTRL_TAGCNT_MASK);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_CTRL);
+ reg &= ~(CSL_CAL_C2VID_CTRL_RD_DMA_STALL_MASK | CSL_CAL_C2VID_CTRL_PWRSCPCLK_MASK |
+ CSL_CAL_C2VID_CTRL_TAGCNT_MASK);
if((uint32_t)TRUE == pCfg->rdDmaStall)
{
- reg |= CAL_CTRL_RD_DMA_STALL_MASK;
+ reg |= CSL_CAL_C2VID_CTRL_RD_DMA_STALL_MASK;
}
if((uint32_t)TRUE == pCfg->pwrScpClk)
{
- reg |= CAL_CTRL_PWRSCPCLK_MASK;
+ reg |= CSL_CAL_C2VID_CTRL_PWRSCPCLK_MASK;
}
- reg |= CAL_CTRL_TAGCNT_MASK & (pCfg->tagCnt << CAL_CTRL_TAGCNT_SHIFT);
+ reg |= CSL_CAL_C2VID_CTRL_TAGCNT_MASK & (pCfg->tagCnt << CSL_CAL_C2VID_CTRL_TAGCNT_SHIFT);
- HW_WR_REG32(baseAddr + CAL_CTRL, reg);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_CTRL, reg);
}
else if(CAL_HAL_MODE_CAPTURE == mode)
{
baseAddr = pInst->baseAddr;
/* Ensure there are no pending reads */
- reg = HW_RD_REG32(baseAddr + CAL_RD_DMA_CTRL);
- if(((reg & CAL_RD_DMA_CTRL_GO_MASK) == CAL_RD_DMA_CTRL_GO_MASK) &&
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL);
+ if(((reg & CSL_CAL_C2VID_RD_DMA_CTRL_GO_MASK) == CSL_CAL_C2VID_RD_DMA_CTRL_GO_MASK) &&
(CAL_HAL_MODE_M2M == mode))
{
rtnVal = FVID2_EAGAIN;
/* CFG BYS In */
if((uint32_t)TRUE == cfg->bysInEnable[idx])
{
- reg = HW_RD_REG32(baseAddr + CAL_BYS_CTRL2);
- reg &= ~((uint32_t) CAL_BYS_CTRL2_CPORTIN_MASK);
- reg |= CAL_BYS_CTRL2_CPORTIN_MASK & cId;
- HW_WR_REG32(baseAddr + CAL_BYS_CTRL2, reg);
-
- reg = HW_RD_REG32(baseAddr + CAL_BYS_CTRL1);
- reg |= CAL_BYS_CTRL1_BYSINEN_MASK;
- HW_WR_REG32(baseAddr + CAL_BYS_CTRL1, reg);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL2);
+ reg &= ~((uint32_t) CSL_CAL_C2VID_BYS_CTRL2_BC2_CPORTIN_MASK);
+ reg |= CSL_CAL_C2VID_BYS_CTRL2_BC2_CPORTIN_MASK & cId;
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL2, reg);
+
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL1);
+ reg |= CSL_CAL_C2VID_BYS_CTRL1_BC1_BYSINEN_MASK;
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL1, reg);
}
else
{
- reg = HW_RD_REG32(baseAddr + CAL_BYS_CTRL1);
- reg &= ~CAL_BYS_CTRL1_BYSINEN_MASK;
- HW_WR_REG32(baseAddr + CAL_BYS_CTRL1, reg);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL1);
+ reg &= ~CSL_CAL_C2VID_BYS_CTRL1_BC1_BYSINEN_MASK;
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL1, reg);
}
}
if((uint32_t)TRUE == cfg->isVportCfgValid[idx])
GT_assert(CalTrace, (CAL_CAPT_MAX_STREAMS > context));
GT_assert(CalTrace, ((0x0U == instance) || (0x1U == instance)));
- reg = HW_RD_REG32(baseAddr + CAL_CSI2_CTX0(instance) + (context * 4U));
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_CTX0(instance) + (context * 4U));
- reg &= ~(CAL_CSI2_CTX0_DT_MASK | CAL_CSI2_CTX0_VC_MASK |
- CAL_CSI2_CTX0_CPORT_MASK | CAL_CSI2_CTX0_ATT_MASK |
- CAL_CSI2_CTX0_PACK_MODE_MASK | CAL_CSI2_CTX0_LINES_MASK);
+ reg &= ~(CSL_CAL_C2PPI_CSI2_CTX0_CTX0_DT_MASK | CSL_CAL_C2PPI_CSI2_CTX0_CTX0_VC_MASK |
+ CSL_CAL_C2PPI_CSI2_CTX0_CTX0_CPORT_MASK | CSL_CAL_C2PPI_CSI2_CTX0_CTX0_ATT_MASK |
+ CSL_CAL_C2PPI_CSI2_CTX0_CTX0_PACK_MODE_MASK | CSL_CAL_C2PPI_CSI2_CTX0_CTX0_LINES_MASK);
- reg |= CAL_CSI2_CTX0_LINES_MASK & (cfg->lines << CAL_CSI2_CTX0_LINES_SHIFT);
+ reg |= CSL_CAL_C2PPI_CSI2_CTX0_CTX0_LINES_MASK & (cfg->lines << CSL_CAL_C2PPI_CSI2_CTX0_CTX0_LINES_SHIFT);
/* TODO Remove the hard-coding, get appropriate macros */
if((cfg->dt < 0x17) && (cfg->dt != 0x1))
* Pixel typically line boundaries is specified. Data is packed between
* LS & LE.
*/
- reg |= CAL_CSI2_CTX0_PACK_MODE_MASK;
+ reg |= CSL_CAL_C2PPI_CSI2_CTX0_CTX0_PACK_MODE_MASK;
}
- reg |= CAL_CSI2_CTX0_ATT_MASK & (cfg->att << CAL_CSI2_CTX0_ATT_SHIFT);
- reg |= CAL_CSI2_CTX0_CPORT_MASK & (cportId << CAL_CSI2_CTX0_CPORT_SHIFT);
- reg |= CAL_CSI2_CTX0_VC_MASK & (cfg->virtualChanNum <<
- CAL_CSI2_CTX0_VC_SHIFT);
- reg |= CAL_CSI2_CTX0_DT_MASK & (cfg->dt << CAL_CSI2_CTX0_DT_SHIFT);
+ reg |= CSL_CAL_C2PPI_CSI2_CTX0_CTX0_ATT_MASK & (cfg->att << CSL_CAL_C2PPI_CSI2_CTX0_CTX0_ATT_SHIFT);
+ reg |= CSL_CAL_C2PPI_CSI2_CTX0_CTX0_CPORT_MASK & (cportId << CSL_CAL_C2PPI_CSI2_CTX0_CTX0_CPORT_SHIFT);
+ reg |= CSL_CAL_C2PPI_CSI2_CTX0_CTX0_VC_MASK & (cfg->virtualChanNum <<
+ CSL_CAL_C2PPI_CSI2_CTX0_CTX0_VC_SHIFT);
+ reg |= CSL_CAL_C2PPI_CSI2_CTX0_CTX0_DT_MASK & (cfg->dt << CSL_CAL_C2PPI_CSI2_CTX0_CTX0_DT_SHIFT);
- HW_WR_REG32(baseAddr + CAL_CSI2_CTX0(instance) + (context * 4U), reg);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_CTX0(instance) + (context * 4U), reg);
return (rtnVal);
}
}
else
{
- reg = HW_RD_REG32(baseAddr + CAL_PIX_PROC(context));
- reg &= ~((uint32_t) CAL_PIX_PROC_EN_MASK);
- HW_WR_REG32(baseAddr + CAL_PIX_PROC(context), reg);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PIX_PIX_PROC(context));
+ reg &= ~((uint32_t) CSL_CAL_C2PIX_PIX_PROC_EN_MASK);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2PIX_PIX_PROC(context), reg);
- reg = HW_RD_REG32(baseAddr + CAL_PIX_PROC(context));
- reg &= ~(CAL_PIX_PROC_EXTRACT_MASK | CAL_PIX_PROC_DPCMD_MASK |
- CAL_PIX_PROC_DPCME_MASK | CAL_PIX_PROC_PACK_MASK |
- CAL_PIX_PROC_CPORT_MASK);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PIX_PIX_PROC(context));
+ reg &= ~(CSL_CAL_C2PIX_PIX_PROC_EXTRACT_MASK | CSL_CAL_C2PIX_PIX_PROC_DPCMD_MASK |
+ CSL_CAL_C2PIX_PIX_PROC_DPCME_MASK | CSL_CAL_C2PIX_PIX_PROC_PACK_MASK |
+ CSL_CAL_C2PIX_PIX_PROC_CPORT_MASK);
GT_assert(CalTrace, (CAL_PIX_EXRCT_MIN != cfg->extract));
GT_assert(CalTrace, (CAL_PIX_EXRCT_MAX >= cfg->extract));
- reg |= CAL_PIX_PROC_EXTRACT_MASK &
- ((extract) << CAL_PIX_PROC_EXTRACT_SHIFT);
+ reg |= CSL_CAL_C2PIX_PIX_PROC_EXTRACT_MASK &
+ ((extract) << CSL_CAL_C2PIX_PIX_PROC_EXTRACT_SHIFT);
- reg |= CAL_PIX_PROC_DPCMD_MASK &
- (cfg->decCodec << CAL_PIX_PROC_DPCMD_SHIFT);
+ reg |= CSL_CAL_C2PIX_PIX_PROC_DPCMD_MASK &
+ (cfg->decCodec << CSL_CAL_C2PIX_PIX_PROC_DPCMD_SHIFT);
- reg |= CAL_PIX_PROC_DPCME_MASK &
- (cfg->encCodec << CAL_PIX_PROC_DPCME_SHIFT);
+ reg |= CSL_CAL_C2PIX_PIX_PROC_DPCME_MASK &
+ (cfg->encCodec << CSL_CAL_C2PIX_PIX_PROC_DPCME_SHIFT);
- reg |= CAL_PIX_PROC_PACK_MASK & (cfg->pack << CAL_PIX_PROC_PACK_SHIFT);
- reg |= CAL_PIX_PROC_CPORT_MASK & (cportId << CAL_PIX_PROC_CPORT_SHIFT);
+ reg |= CSL_CAL_C2PIX_PIX_PROC_PACK_MASK & (cfg->pack << CSL_CAL_C2PIX_PIX_PROC_PACK_SHIFT);
+ reg |= CSL_CAL_C2PIX_PIX_PROC_CPORT_MASK & (cportId << CSL_CAL_C2PIX_PIX_PROC_CPORT_SHIFT);
- HW_WR_REG32(baseAddr + CAL_PIX_PROC(context), reg);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2PIX_PIX_PROC(context), reg);
- reg = HW_RD_REG32(baseAddr + CAL_RD_DMA_CTRL);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL);
if((uint32_t)TRUE == cfg->enableDpcmInitContext)
{
- reg |= CAL_RD_DMA_CTRL_INIT_MASK;
+ reg |= CSL_CAL_C2VID_RD_DMA_CTRL_INIT_MASK;
GT_assert(CalTrace, (0U != cfg->addr));
}
else
{
- reg &= ~((uint32_t) CAL_RD_DMA_CTRL_INIT_MASK);
+ reg &= ~((uint32_t) CSL_CAL_C2VID_RD_DMA_CTRL_INIT_MASK);
}
- HW_WR_REG32(baseAddr + CAL_RD_DMA_CTRL, reg);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL, reg);
if((uint32_t)TRUE == cfg->enableDpcmInitContext)
{
- reg = HW_RD_REG32(baseAddr + CAL_RD_DMA_INIT_ADDR);
- reg &= ~CAL_RD_DMA_INIT_ADDR_MASK;
- reg |= CAL_RD_DMA_INIT_ADDR_MASK & cfg->addr;
- HW_WR_REG32(baseAddr + CAL_RD_DMA_INIT_ADDR, reg);
-
- reg = HW_RD_REG32(baseAddr + CAL_RD_DMA_INIT_OFST);
- reg &= ~CAL_RD_DMA_INIT_OFST_MASK;
- reg |= CAL_RD_DMA_INIT_OFST_MASK & cfg->offSet;
- HW_WR_REG32(baseAddr + CAL_RD_DMA_INIT_OFST, reg);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_INIT_ADDR);
+ reg &= ~CSL_CAL_C2VID_RD_DMA_INIT_ADDR_DIA_ADDR_MASK;
+ reg |= CSL_CAL_C2VID_RD_DMA_INIT_ADDR_DIA_ADDR_MASK & cfg->addr;
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_INIT_ADDR, reg);
+
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_INIT_OFST);
+ reg &= ~CSL_CAL_C2VID_RD_DMA_INIT_OFST_DIO_OFST_MASK;
+ reg |= CSL_CAL_C2VID_RD_DMA_INIT_OFST_DIO_OFST_MASK & cfg->offSet;
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_INIT_OFST, reg);
}
/* Enable Pixel Processing, as a last step */
- reg = HW_RD_REG32(baseAddr + CAL_PIX_PROC(context));
- reg |= CAL_PIX_PROC_EN_MASK;
- HW_WR_REG32(baseAddr + CAL_PIX_PROC(context), reg);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PIX_PIX_PROC(context));
+ reg |= CSL_CAL_C2PIX_PIX_PROC_EN_MASK;
+ HW_WR_REG32(baseAddr + CSL_CAL_C2PIX_PIX_PROC(context), reg);
}
return rtnVal;
baseAddr = pInst->baseAddr;
GT_assert(CalTrace, (0U != baseAddr));
- reg = HW_RD_REG32(baseAddr + CAL_BYS_CTRL1);
- reg &= ~CAL_BYS_CTRL1_PCLK_MASK;
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL1);
+ reg &= ~CSL_CAL_C2VID_BYS_CTRL1_BC1_PCLK_MASK;
if((uint32_t)TRUE == cfg->enable)
{
- reg &= ~(CAL_BYS_CTRL1_XBLK_MASK | CAL_BYS_CTRL1_YBLK_MASK);
+ reg &= ~(CSL_CAL_C2VID_BYS_CTRL1_BC1_XBLK_MASK | CSL_CAL_C2VID_VPORT_CTRL1_VC1_YBLK_MASK);
- reg |= CAL_BYS_CTRL1_PCLK_MASK &
- (cfg->pixClock << CAL_BYS_CTRL1_PCLK_SHIFT);
+ reg |= CSL_CAL_C2VID_BYS_CTRL1_BC1_PCLK_MASK &
+ (cfg->pixClock << CSL_CAL_C2VID_BYS_CTRL1_BC1_PCLK_SHIFT);
- reg |= CAL_BYS_CTRL1_XBLK_MASK &
- (cfg->xBlk << CAL_BYS_CTRL1_XBLK_SHIFT);
+ reg |= CSL_CAL_C2VID_BYS_CTRL1_BC1_XBLK_MASK &
+ (cfg->xBlk << CSL_CAL_C2VID_BYS_CTRL1_BC1_XBLK_SHIFT);
- reg |= CAL_BYS_CTRL1_YBLK_MASK &
- (cfg->yBlk << CAL_BYS_CTRL1_YBLK_SHIFT);
- HW_WR_REG32(baseAddr + CAL_BYS_CTRL1, reg);
+ reg |= CSL_CAL_C2VID_VPORT_CTRL1_VC1_YBLK_MASK &
+ (cfg->yBlk << CSL_CAL_C2VID_BYS_CTRL1_BC1_YBLK_SHIFT);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL1, reg);
- reg = HW_RD_REG32(baseAddr + CAL_BYS_CTRL2);
- reg &= ~((uint32_t) (CAL_BYS_CTRL2_CPORTOUT_MASK |
- CAL_BYS_CTRL2_DUPLICATEDDATA_MASK |
- CAL_BYS_CTRL2_FREERUNNING_MASK));
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL2);
+ reg &= ~((uint32_t) (CSL_CAL_C2VID_BYS_CTRL2_BC2_CPORTOUT_MASK |
+ CSL_CAL_C2VID_BYS_CTRL2_BC2_DUPLICATEDDATA_MASK |
+ CSL_CAL_C2VID_BYS_CTRL2_BC2_FREERUNNING_MASK));
if((uint32_t)TRUE == cfg->freeRun)
{
- reg |= CAL_BYS_CTRL2_FREERUNNING_MASK;
+ reg |= CSL_CAL_C2VID_BYS_CTRL2_BC2_FREERUNNING_MASK;
}
if((uint32_t)TRUE == cfg->copyStreamToEncode)
{
- reg |= CAL_BYS_CTRL2_DUPLICATEDDATA_MASK;
+ reg |= CSL_CAL_C2VID_BYS_CTRL2_BC2_DUPLICATEDDATA_MASK;
}
- reg |= CAL_BYS_CTRL2_CPORTOUT_MASK &
- (cportId << CAL_BYS_CTRL2_CPORTOUT_SHIFT);
+ reg |= CSL_CAL_C2VID_BYS_CTRL2_BC2_CPORTOUT_MASK &
+ (cportId << CSL_CAL_C2VID_BYS_CTRL2_BC2_CPORTOUT_SHIFT);
- HW_WR_REG32(baseAddr + CAL_BYS_CTRL2, reg);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL2, reg);
}
else
{
- HW_WR_REG32(baseAddr + CAL_BYS_CTRL1, reg);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL1, reg);
}
return FVID2_SOK;
baseAddr = pInst->baseAddr;
GT_assert(CalTrace, (0U != baseAddr));
- reg = HW_RD_REG32(baseAddr + CAL_VPORT_CTRL1);
- reg &= ~CAL_VPORT_CTRL1_PCLK_MASK;
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_VPORT_CTRL1);
+ reg &= ~CSL_CAL_C2VID_VPORT_CTRL1_VC1_PCLK_MASK;
if((uint32_t)TRUE == cfg->enable)
{
- reg &= ~(CAL_VPORT_CTRL1_XBLK_MASK | CAL_VPORT_CTRL1_YBLK_MASK |
- CAL_VPORT_CTRL1_WIDTH_MASK);
+ reg &= ~(CSL_CAL_C2VID_VPORT_CTRL1_VC1_XBLK_MASK | CSL_CAL_C2VID_VPORT_CTRL1_VC1_YBLK_MASK |
+ CSL_CAL_C2VID_VPORT_CTRL1_VC1_WIDTH_MASK);
- reg |= CAL_VPORT_CTRL1_PCLK_MASK & cfg->pixClock;
+ reg |= CSL_CAL_C2VID_VPORT_CTRL1_VC1_PCLK_MASK & cfg->pixClock;
- reg |= CAL_VPORT_CTRL1_XBLK_MASK &
- (cfg->xBlk << CAL_VPORT_CTRL1_XBLK_SHIFT);
+ reg |= CSL_CAL_C2VID_VPORT_CTRL1_VC1_XBLK_MASK &
+ (cfg->xBlk << CSL_CAL_C2VID_VPORT_CTRL1_VC1_XBLK_SHIFT);
- reg |= CAL_VPORT_CTRL1_YBLK_MASK &
- (cfg->yBlk << CAL_VPORT_CTRL1_YBLK_SHIFT);
+ reg |= CSL_CAL_C2VID_VPORT_CTRL1_VC1_YBLK_MASK &
+ (cfg->yBlk << CSL_CAL_C2VID_VPORT_CTRL1_VC1_YBLK_SHIFT);
if(0x0U != cfg->width)
{
- reg |= CAL_VPORT_CTRL1_WIDTH_MASK;
+ reg |= CSL_CAL_C2VID_VPORT_CTRL1_VC1_WIDTH_MASK;
}
- HW_WR_REG32(baseAddr + CAL_VPORT_CTRL1, reg);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_VPORT_CTRL1, reg);
- reg = HW_RD_REG32(baseAddr + CAL_VPORT_CTRL2);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_VPORT_CTRL2);
reg &=
- ~(CAL_VPORT_CTRL2_RDY_THR_MASK | CAL_VPORT_CTRL2_FSM_RESET_MASK |
- CAL_VPORT_CTRL2_FS_RESETS_MASK |
- CAL_VPORT_CTRL2_FREERUNNING_MASK |
- CAL_VPORT_CTRL2_CPORT_MASK);
+ ~(CSL_CAL_C2VID_VPORT_CTRL2_VC2_RDY_THR_MASK | CSL_CAL_C2VID_VPORT_CTRL2_VC2_FSM_RESET_MASK |
+ CSL_CAL_C2VID_VPORT_CTRL2_VC2_FS_RESETS_MASK |
+ CSL_CAL_C2VID_VPORT_CTRL2_VC2_FREERUNNING_MASK |
+ CSL_CAL_C2VID_VPORT_CTRL2_VC2_CPORT_MASK);
- reg |= CAL_VPORT_CTRL2_CPORT_MASK & cportId;
+ reg |= CSL_CAL_C2VID_VPORT_CTRL2_VC2_CPORT_MASK & cportId;
if((uint32_t)TRUE == cfg->freeRun)
{
- reg |= CAL_VPORT_CTRL2_FREERUNNING_MASK;
+ reg |= CSL_CAL_C2VID_VPORT_CTRL2_VC2_FREERUNNING_MASK;
}
if((uint32_t)TRUE == cfg->fsReset)
{
- reg |= CAL_VPORT_CTRL2_FS_RESETS_MASK;
+ reg |= CSL_CAL_C2VID_VPORT_CTRL2_VC2_FS_RESETS_MASK;
}
- reg |= CAL_VPORT_CTRL2_RDY_THR_MASK &
- (cfg->rdyThr << CAL_VPORT_CTRL2_RDY_THR_SHIFT);
+ reg |= CSL_CAL_C2VID_VPORT_CTRL2_VC2_RDY_THR_MASK &
+ (cfg->rdyThr << CSL_CAL_C2VID_VPORT_CTRL2_VC2_RDY_THR_SHIFT);
- HW_WR_REG32(baseAddr + CAL_VPORT_CTRL2, reg);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_VPORT_CTRL2, reg);
}
else
{
- HW_WR_REG32(baseAddr + CAL_VPORT_CTRL1, reg);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_VPORT_CTRL1, reg);
}
return FVID2_SOK;
baseAddr = pInst->baseAddr;
GT_assert(CalTrace, (0U != baseAddr));
- reg = HW_RD_REG32(baseAddr + CAL_RD_DMA_CTRL);
- reg &= ~CAL_RD_DMA_CTRL_PCLK_MASK;
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL);
+ reg &= ~CSL_CAL_C2VID_RD_DMA_CTRL_PCLK_MASK;
if((uint32_t)TRUE == cfg->enable)
{
- reg &= ~((uint32_t) (CAL_RD_DMA_CTRL_GO_MASK |
- CAL_RD_DMA_CTRL_BW_LIMITER_MASK |
- CAL_RD_DMA_CTRL_OCP_TAG_CNT_MASK));
+ reg &= ~((uint32_t) (CSL_CAL_C2VID_RD_DMA_CTRL_GO_MASK |
+ CSL_CAL_C2VID_RD_DMA_CTRL_BW_LIMITER_MASK |
+ CSL_CAL_C2VID_RD_DMA_CTRL_OCP_TAG_CNT_MASK));
- reg |= CAL_RD_DMA_CTRL_BW_LIMITER_MASK &
- (cfg->bwLimit << CAL_RD_DMA_CTRL_BW_LIMITER_SHIFT);
+ reg |= CSL_CAL_C2VID_RD_DMA_CTRL_BW_LIMITER_MASK &
+ (cfg->bwLimit << CSL_CAL_C2VID_RD_DMA_CTRL_BW_LIMITER_SHIFT);
- reg |= CAL_RD_DMA_CTRL_OCP_TAG_CNT_MASK &
- (cfg->ocpTagCnt << CAL_RD_DMA_CTRL_OCP_TAG_CNT_SHIFT);
+ reg |= CSL_CAL_C2VID_RD_DMA_CTRL_OCP_TAG_CNT_MASK &
+ (cfg->ocpTagCnt << CSL_CAL_C2VID_RD_DMA_CTRL_OCP_TAG_CNT_SHIFT);
- reg |= CAL_RD_DMA_CTRL_PCLK_MASK &
- (cfg->pixClock << CAL_RD_DMA_CTRL_PCLK_SHIFT);
+ reg |= CSL_CAL_C2VID_RD_DMA_CTRL_PCLK_MASK &
+ (cfg->pixClock << CSL_CAL_C2VID_RD_DMA_CTRL_PCLK_SHIFT);
- HW_WR_REG32(baseAddr + CAL_RD_DMA_CTRL, reg);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL, reg);
- reg = HW_RD_REG32(baseAddr + CAL_RD_DMA_CTRL2);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL2);
- reg &= ~(CAL_RD_DMA_CTRL2_CIRC_MODE_MASK |
- CAL_RD_DMA_CTRL2_CIRC_SIZE_MASK |
- CAL_RD_DMA_CTRL2_ICM_CSTART_MASK |
- CAL_RD_DMA_CTRL2_PATTERN_MASK |
- CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_MASK);
- reg |= CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_MASK &
- (cfg->bysOutLeWait << CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_SHIFT);
+ reg &= ~(CSL_CAL_C2VID_RD_DMA_CTRL2_CIRC_MODE_MASK |
+ CSL_CAL_C2VID_RD_DMA_CTRL2_CIRC_SIZE_MASK |
+ CSL_CAL_C2VID_RD_DMA_CTRL2_ICM_CSTART_MASK |
+ CSL_CAL_C2VID_RD_DMA_CTRL2_RD_PATTERN_MASK |
+ CSL_CAL_C2VID_RD_DMA_CTRL2_BYSOUT_LE_WAIT_MASK);
+ reg |= CSL_CAL_C2VID_RD_DMA_CTRL2_BYSOUT_LE_WAIT_MASK &
+ (cfg->bysOutLeWait << CSL_CAL_C2VID_RD_DMA_CTRL2_BYSOUT_LE_WAIT_SHIFT);
- reg |= CAL_RD_DMA_CTRL2_PATTERN_MASK &
- (cfg->ySkipMode << CAL_RD_DMA_CTRL2_PATTERN_SHIFT);
+ reg |= CSL_CAL_C2VID_RD_DMA_CTRL2_RD_PATTERN_MASK &
+ (cfg->ySkipMode << CSL_CAL_C2VID_RD_DMA_CTRL2_RD_PATTERN_SHIFT);
- HW_WR_REG32(baseAddr + CAL_RD_DMA_CTRL2, reg);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL2, reg);
CalSetRdDmaFrameCfg(pInst, &cfg->format);
}
else
{
- HW_WR_REG32(baseAddr + CAL_RD_DMA_CTRL, reg);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL, reg);
}
return FVID2_SOK;
}
hSize = (cfg->width / 8U);
}
- reg = HW_RD_REG32(baseAddr + CAL_RD_DMA_XSIZE);
- reg &= ~CAL_RD_DMA_XSIZE_MASK;
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_XSIZE);
+ reg &= ~CSL_CAL_WR_DMA_WR_DMA_XSIZE_XSIZE_MASK;
/* Require to specify the number of 64 bits read, essentially
* total bits / 64 or byte count / 8 */
- reg |= CAL_RD_DMA_XSIZE_MASK & ((hSize) << CAL_RD_DMA_XSIZE_SHIFT);
- HW_WR_REG32(baseAddr + CAL_RD_DMA_XSIZE, reg);
+ reg |= CSL_CAL_WR_DMA_WR_DMA_XSIZE_XSIZE_MASK & ((hSize) << CSL_CAL_C2VID_RD_DMA_XSIZE_XSIZE_SHIFT);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_XSIZE, reg);
- reg = HW_RD_REG32(baseAddr + CAL_RD_DMA_YSIZE);
- reg &= ~CAL_RD_DMA_YSIZE_MASK;
- reg |= CAL_RD_DMA_YSIZE_MASK & (cfg->height << CAL_RD_DMA_YSIZE_SHIFT);
- HW_WR_REG32(baseAddr + CAL_RD_DMA_YSIZE, reg);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_YSIZE);
+ reg &= ~CSL_CAL_C2VID_RD_DMA_YSIZE_YSIZE_MASK;
+ reg |= CSL_CAL_C2VID_RD_DMA_YSIZE_YSIZE_MASK & (cfg->height << CSL_CAL_C2VID_RD_DMA_YSIZE_YSIZE_SHIFT);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_YSIZE, reg);
- reg = HW_RD_REG32(baseAddr + CAL_RD_DMA_PIX_OFST);
- reg &= ~CAL_RD_DMA_PIX_OFST_MASK;
- reg |= (CAL_RD_DMA_PIX_OFST_MASK & cfg->pitch[0U]);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_PIX_OFST);
+ reg &= ~CSL_CAL_C2VID_RD_DMA_PIX_OFST_OFST_MASK;
+ reg |= (CSL_CAL_C2VID_RD_DMA_PIX_OFST_OFST_MASK & cfg->pitch[0U]);
- HW_WR_REG32(baseAddr + CAL_RD_DMA_PIX_OFST, reg);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_PIX_OFST, reg);
return FVID2_SOK;
}
GT_assert(CalTrace, (0U != baseAddr));
GT_assert(CalTrace, (CAL_CAPT_MAX_STREAMS > context));
- reg = HW_RD_REG32(baseAddr + CAL_WR_DMA_CTRL(context));
- reg &= ~(CAL_WR_DMA_CTRL_YSIZE_MASK | CAL_WR_DMA_CTRL_STALL_RD_DMA_MASK |
- CAL_WR_DMA_CTRL_CPORT_MASK | CAL_WR_DMA_CTRL_DTAG_MASK |
- CAL_WR_DMA_CTRL_WR_PATTERN_MASK | CAL_WR_DMA_CTRL_MODE_MASK);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_WR_DMA_WR_DMA_CTRL(context));
+ reg &= ~(CSL_CAL_WR_DMA_WR_DMA_CTRL_YSIZE_MASK | CSL_CAL_WR_DMA_WR_DMA_CTRL_STALL_RD_DMA_MASK |
+ CSL_CAL_WR_DMA_WR_DMA_CTRL_CPORT_MASK | CSL_CAL_WR_DMA_WR_DMA_CTRL_DTAG_MASK |
+ CSL_CAL_WR_DMA_WR_DMA_CTRL_WR_PATTERN_MASK | CSL_CAL_WR_DMA_WR_DMA_CTRL_MODE_MASK);
- reg |= CAL_WR_DMA_CTRL_MODE_MASK & cfg->mode;
+ reg |= CSL_CAL_WR_DMA_WR_DMA_CTRL_MODE_MASK & cfg->mode;
- reg |= CAL_WR_DMA_CTRL_WR_PATTERN_MASK &
- (cfg->ySkipMode << CAL_WR_DMA_CTRL_WR_PATTERN_SHIFT);
+ reg |= CSL_CAL_WR_DMA_WR_DMA_CTRL_WR_PATTERN_MASK &
+ (cfg->ySkipMode << CSL_CAL_WR_DMA_WR_DMA_CTRL_WR_PATTERN_SHIFT);
- reg |= CAL_WR_DMA_CTRL_DTAG_MASK &
- (cfg->stream << CAL_WR_DMA_CTRL_DTAG_SHIFT);
+ reg |= CSL_CAL_WR_DMA_WR_DMA_CTRL_DTAG_MASK &
+ (cfg->stream << CSL_CAL_WR_DMA_WR_DMA_CTRL_DTAG_SHIFT);
- reg |= CAL_WR_DMA_CTRL_CPORT_MASK &
- (cportId << CAL_WR_DMA_CTRL_CPORT_SHIFT);
+ reg |= CSL_CAL_WR_DMA_WR_DMA_CTRL_CPORT_MASK &
+ (cportId << CSL_CAL_WR_DMA_WR_DMA_CTRL_CPORT_SHIFT);
- reg |= CAL_WR_DMA_CTRL_STALL_RD_DMA_MASK &
- (cfg->stallM2MRd << CAL_WR_DMA_CTRL_STALL_RD_DMA_SHIFT);
+ reg |= CSL_CAL_WR_DMA_WR_DMA_CTRL_STALL_RD_DMA_MASK &
+ (cfg->stallM2MRd << CSL_CAL_WR_DMA_WR_DMA_CTRL_STALL_RD_DMA_SHIFT);
- reg |= CAL_WR_DMA_CTRL_YSIZE_MASK &
- (cfg->format.height << CAL_WR_DMA_CTRL_YSIZE_SHIFT);
- HW_WR_REG32(baseAddr + CAL_WR_DMA_CTRL(context), reg);
+ reg |= CSL_CAL_WR_DMA_WR_DMA_CTRL_YSIZE_MASK &
+ (cfg->format.height << CSL_CAL_WR_DMA_WR_DMA_CTRL_YSIZE_SHIFT);
+ HW_WR_REG32(baseAddr + CSL_CAL_WR_DMA_WR_DMA_CTRL(context), reg);
- reg = HW_RD_REG32(baseAddr + CAL_WR_DMA_OFST(context));
- reg &= ~CAL_WR_DMA_OFST_OFFST_MASK;
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_WR_DMA_WR_DMA_OFST(context));
+ reg &= ~CSL_CAL_WR_DMA_WR_DMA_OFST_OFST_MASK;
/* No support for circular mode as of now */
- reg &= ~(CAL_WR_DMA_OFST_CIRC_MODE_MASK | CAL_WR_DMA_OFST_CIRC_SIZE_MASK);
+ reg &= ~(CSL_CAL_WR_DMA_WR_DMA_OFST_CIRC_MODE_MASK | CSL_CAL_WR_DMA_WR_DMA_OFST_CIRC_SIZE_MASK);
/* Shifting is not required */
- reg |= CAL_WR_DMA_OFST_OFFST_MASK & cfg->format.pitch[0];
- HW_WR_REG32(baseAddr + CAL_WR_DMA_OFST(context), reg);
+ reg |= CSL_CAL_WR_DMA_WR_DMA_OFST_OFST_MASK & cfg->format.pitch[0];
+ HW_WR_REG32(baseAddr + CSL_CAL_WR_DMA_WR_DMA_OFST(context), reg);
- reg = HW_RD_REG32(baseAddr + CAL_WR_DMA_XSIZE(context));
- reg &= ~(CAL_WR_DMA_XSIZE_XSIZE_MASK | CAL_WR_DMA_XSIZE_XSKIP_MASK);
- reg |= CAL_WR_DMA_XSIZE_XSKIP_MASK &
- (cfg->xPixelSkip << CAL_WR_DMA_XSIZE_XSKIP_SHIFT);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_WR_DMA_WR_DMA_XSIZE(context));
+ reg &= ~(CSL_CAL_WR_DMA_WR_DMA_XSIZE_XSIZE_MASK | CSL_CAL_WR_DMA_WR_DMA_XSIZE_XSKIP_MASK);
+ reg |= CSL_CAL_WR_DMA_WR_DMA_XSIZE_XSKIP_MASK &
+ (cfg->xPixelSkip << CSL_CAL_WR_DMA_WR_DMA_XSIZE_XSKIP_SHIFT);
- reg |= CAL_WR_DMA_XSIZE_XSIZE_MASK &
- (cfg->format.width << CAL_WR_DMA_XSIZE_XSIZE_SHIFT);
- HW_WR_REG32(baseAddr + CAL_WR_DMA_XSIZE(context), reg);
+ reg |= CSL_CAL_WR_DMA_WR_DMA_XSIZE_XSIZE_MASK &
+ (cfg->format.width << CSL_CAL_WR_DMA_WR_DMA_XSIZE_XSIZE_SHIFT);
+ HW_WR_REG32(baseAddr + CSL_CAL_WR_DMA_WR_DMA_XSIZE(context), reg);
return FVID2_SOK;
}
if((uint32_t)TRUE == pDmaCfg->isWrDmaCfgValid[i])
{
instance = pDmaCfg->wrDmaCfg[i].contextToBeUsed;
- reg = HW_RD_REG32(baseAddr + CAL_WR_DMA_CTRL(instance));
- reg &= ~((uint32_t) CAL_WR_DMA_CTRL_MODE_MASK);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_WR_DMA_WR_DMA_CTRL(instance));
+ reg &= ~((uint32_t) CSL_CAL_WR_DMA_WR_DMA_CTRL_MODE_MASK);
- reg |= CAL_WR_DMA_CTRL_MODE_MASK &
+ reg |= CSL_CAL_WR_DMA_WR_DMA_CTRL_MODE_MASK &
pDmaCfg->wrDmaCfg[i].mode;
- HW_WR_REG32(baseAddr + CAL_WR_DMA_CTRL(instance), reg);
+ HW_WR_REG32(baseAddr + CSL_CAL_WR_DMA_WR_DMA_CTRL(instance), reg);
}
}
for(i = 0; i < plnEvtCfg->numCPortId; i++)
{
cportId = plnEvtCfg->cportId[i];
- reg = HW_RD_REG32(baseAddr + CAL_LINE_NUMBER_EVT);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_LINE_NUMBER_EVT);
- reg &= ~((uint32_t)CAL_LINE_NUMBER_EVT_CPORT_MASK);
- reg &= ~CAL_LINE_NUMBER_EVT_MASK;
+ reg &= ~((uint32_t)CSL_CAL_C2VID_LINE_NUMBER_EVT_CPORT_MASK);
+ reg &= ~CSL_CAL_C2VID_LINE_NUMBER_EVT_LINE_MASK;
- reg |= CAL_LINE_NUMBER_EVT_CPORT_MASK &
- (cportId << CAL_LINE_NUMBER_EVT_CPORT_SHIFT);
+ reg |= CSL_CAL_C2VID_LINE_NUMBER_EVT_CPORT_MASK &
+ (cportId << CSL_CAL_C2VID_LINE_NUMBER_EVT_CPORT_SHIFT);
- reg |= CAL_LINE_NUMBER_EVT_MASK &
- (plnEvtCfg->lineNumber[cportId] << CAL_LINE_NUMBER_EVT_SHIFT);
+ reg |= CSL_CAL_C2VID_LINE_NUMBER_EVT_LINE_MASK &
+ (plnEvtCfg->lineNumber[cportId] << CSL_CAL_C2VID_LINE_NUMBER_EVT_LINE_SHIFT);
- HW_WR_REG32(baseAddr + CAL_LINE_NUMBER_EVT, reg);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2VID_LINE_NUMBER_EVT, reg);
}
return (FVID2_SOK);
}
diff --git a/src/hal/cal_hal.h b/src/hal/cal_hal.h
index 2aa6926a78bae857075ca3ecf2943f4a43a5b871..6303135cc9828bfa8ded9e69871abbdd2a2eca6c 100755 (executable)
--- a/src/hal/cal_hal.h
+++ b/src/hal/cal_hal.h
/* Applicable only when CAL is used to interface to sensor (via the
* complex IO, which is normal expected connection.
* These config are to have a valid value when operated in capture mode.
- * Maps to following registers CAL_CSI2_COMPLEXIO_CFG_XX */
+ * Maps to following registers CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_XX */
uint32_t numCmplxIoInst;
/**< Number of complex IO used */
index db6f2240a9bec712b22e88bc26d751f0a505a9bb..e2a7896728ec0a513753783b14b6d3bbdc28abbc 100755 (executable)
if((FVID2_SOK == rtnVal) && (0U != rxCoreBaseAddr))
{
/* 2. Reset complex IO - Do not wait for reset completion */
- reg = HW_RD_REG32(baseAddr + CAL_CSI2_COMPLEXIO_CFG(idx));
- reg |= CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK;
- HW_WR_REG32(baseAddr + CAL_CSI2_COMPLEXIO_CFG(idx), reg);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG(idx));
+ reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK;
+ HW_WR_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG(idx), reg);
/* Dummy read to allow SCP to complete */
- reg = HW_RD_REG32(baseAddr + CAL_CSI2_COMPLEXIO_CFG(idx));
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG(idx));
timeOut = 0xFFFFFU;
/* Timeouts */
idx);
/* B. Enable stop state transition timeouts */
- reg = HW_RD_REG32(baseAddr + CAL_CSI2_TIMING(idx));
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_TIMING(idx));
- reg &= ~((uint32_t) (CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK |
- CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK |
- CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK |
- CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK));
- reg |= CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK &
+ reg &= ~((uint32_t) (CSL_CAL_C2PPI_CSI2_TIMING_STOP_STATE_X4_IO1_MASK |
+ CSL_CAL_C2PPI_CSI2_TIMING_STOP_STATE_X16_IO1_MASK |
+ CSL_CAL_C2PPI_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK |
+ CSL_CAL_C2PPI_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK));
+ reg |= CSL_CAL_C2PPI_CSI2_TIMING_STOP_STATE_X16_IO1_MASK &
(pCfg->ppiCfg[idx].csi2Cfg.stop_state_x16_I01 <<
- CAL_CSI2_TIMING_STOP_STATE_X16_IO1_SHIFT);
- reg |= CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK &
+ CSL_CAL_C2PPI_CSI2_TIMING_STOP_STATE_X16_IO1_SHIFT);
+ reg |= CSL_CAL_C2PPI_CSI2_TIMING_STOP_STATE_X4_IO1_MASK &
(pCfg->ppiCfg[idx].csi2Cfg.stop_state_x4_I01 <<
- CAL_CSI2_TIMING_STOP_STATE_X4_IO1_SHIFT);
- reg |= CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK &
+ CSL_CAL_C2PPI_CSI2_TIMING_STOP_STATE_X4_IO1_SHIFT);
+ reg |= CSL_CAL_C2PPI_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK &
(pCfg->ppiCfg[idx].csi2Cfg.stop_state_counter_I01 <<
- CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_SHIFT);
- HW_WR_REG32(baseAddr + CAL_CSI2_TIMING(idx), reg);
+ CSL_CAL_C2PPI_CSI2_TIMING_STOP_STATE_COUNTER_IO1_SHIFT);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_TIMING(idx), reg);
/* 4 Force FORCERXMODE */
- reg = HW_RD_REG32(baseAddr + CAL_CSI2_TIMING(idx));
- reg |= CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK;
- HW_WR_REG32(baseAddr + CAL_CSI2_TIMING(idx), reg);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_TIMING(idx));
+ reg |= CSL_CAL_C2PPI_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK;
+ HW_WR_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_TIMING(idx), reg);
/* E. Power up the PHY using the complex IO */
- reg = HW_RD_REG32(baseAddr + CAL_CSI2_COMPLEXIO_CFG(idx));
- reg |= CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK &
- ((uint32_t) CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON <<
- CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_SHIFT);
- HW_WR_REG32(baseAddr + CAL_CSI2_COMPLEXIO_CFG(idx), reg);
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG(idx));
+ reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK &
+ ((uint32_t) CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON <<
+ CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_PWR_CMD_SHIFT);
+ HW_WR_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG(idx), reg);
/* F. Wait for power up completion */
timeOut = 0xFFFFFFU;
while(timeOut)
{
- reg = HW_RD_REG32(baseAddr + CAL_CSI2_COMPLEXIO_CFG(idx));
- reg = (reg & CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK);
- reg = (reg >> CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_SHIFT);
- if(CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_ON == reg)
+ reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG(idx));
+ reg = (reg & CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK);
+ reg = (reg >> CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_PWR_STATUS_SHIFT);
+ if(CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_ON == reg)
{
break;
}
diff --git a/src/hal/cal_halCsi2Tda2ex.c b/src/hal/cal_halCsi2Tda2ex.c
+++ /dev/null
@@ -1,408 +0,0 @@
-/* =============================================================================
- * Copyright (c) Texas Instruments Incorporated 2018
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * \file cal_halCsi2Tda2ex.c
- *
- * \brief This file the function to initialize CSI2 PHY for TDA2ex platform
- *
- * TODO / TBD
- * TDA2EX_CAL_TODO i913 errata for CSI2 / CAL.
- */
-
-/* ========================================================================== */
-/* Include Files */
-/* ========================================================================== */
-
-#include <stdint.h>
-#include <stddef.h>
-
-#include <ti/csl/soc.h>
-#include <ti/csl/hw_types.h>
-#include <ti/csl/cslr_cal.h>
-
-#include <ti/drv/cal/cal.h>
-#include <ti/drv/cal/src/hal/cal_hal.h>
-
-/* ========================================================================== */
-/* Macros & Typedefs */
-/* ========================================================================== */
-
-/**< Bit feilds definition for CTRL_CORE_CAMERRX_CONTROL reg */
-#define CTRL_CORE_CAMERRX_CONTROL_CSI0_MODE_MASK (0x00020000U)
-#define CTRL_CORE_CAMERRX_CONTROL_CSI0_LANEENABLE_MASK (0x0001E000U)
-#define CTRL_CORE_CAMERRX_CONTROL_CSI0_CAMMODE_MASK (0x00001800U)
-#define CTRL_CORE_CAMERRX_CONTROL_CSI0_CTRLCLKEN_MASK (0x00000400U)
-
-#define CTRL_CORE_CAMERRX_CONTROL_CSI1_MODE_MASK (0x00000020U)
-#define CTRL_CORE_CAMERRX_CONTROL_CSI1_LANEENABLE_MASK (0x00000018U)
-#define CTRL_CORE_CAMERRX_CONTROL_CSI1_CAMMODE_MASK (0x00000006U)
-#define CTRL_CORE_CAMERRX_CONTROL_CSI1_CTRLCLKEN_MASK (0x00000001U)
-
-/**< Bit 2 set, used to compute register values for lanes enabled. */
-#define CSI1_X_LANE_ENABLED ((uint32_t)0x2U)
-/**< Bit 12 set, used to compute register values for lanes enabled. */
-#define CSI0_X_LANE_ENABLED ((uint32_t)0x800U)
-
-
-/**< Functional PHY clock is expected to be 96 MHz
- Period of PHY clock in nS is 10.41666
- ((1/<PHY Clock) / 1e-9) */
-#define DPHY_FUNCTIONAL_CLK_PERIOD (10.41666)
-
-/* ========================================================================== */
-/* Structure Declarations */
-/* ========================================================================== */
-
-/* None */
-
-/* ========================================================================== */
-/* Constants */
-/* ========================================================================== */
-
-/* None */
-
-/* ========================================================================== */
-/* Macros & Typedefs */
-/* ========================================================================== */
-
-/* None */
-
-/* ========================================================================== */
-/* Function Prototype */
-/* ========================================================================== */
-
-static void ConfigureCamRxCtrl(const Cal_CmplxIoCfg_t *pCmplxIoCfg,
- uint32_t inst);
-static void ConfigureStopStateTimeouts(uint32_t camRxCoreBaseAddr,
- uint32_t csi2Clk, uint32_t inst);
-static void ConfigureLdoi913Errata(uint32_t camRxCoreBaseAddr);
-
-/* ========================================================================== */
-/* Function Implementations */
-/* ========================================================================== */
-
-int32_t Cal_halPhyEnClockAndReset(uint32_t baseAddr,
- uint32_t cam0RxCoreBaseAddr,
- uint32_t cam1RxCoreBaseAddr,
- const Cal_HalInstCfg_t *pCfg)
-{
- int32_t rtnVal;
- uint32_t idx, rxCoreBaseAddr;
- volatile uint32_t reg, timeOut;
-
- GT_assert(CalTrace, (0U != baseAddr));
- GT_assert(CalTrace, (0U != cam0RxCoreBaseAddr));
- GT_assert(CalTrace, (0U != cam1RxCoreBaseAddr));
- GT_assert(CalTrace, (NULL != pCfg));
-
- rtnVal = FVID2_SOK;
- /* Steps
- * 1. Configure D-PHY mode and enable required lanes
- * 2. Reset complex IO - Wait for completion of reset
- * Note if the external sensor is not sending byte clock, the
- * reset will timeout
- * 3 Program Stop States
- * A. Program THS_TERM, THS_SETTLE, etc... Timings parameters in terms
- * of DDR clock periods
- * B. Enable stop state transition timeouts
- * 4.Force FORCERXMODE
- * D. Enable pull down using pad control
- * E. Power up PHY
- * F. Wait for power up completion
- * G. Wait for all enabled lane to reach stop state
- * H. Disable pull down using pad control
- */
- for(idx = 0U; ((idx < pCfg->numCmplxIoInst) &&
- (TRUE == pCfg->cmplxIoCfg[idx].enable)); idx++)
- {
- /* 1. Configure D-PHY mode and enable required lanes */
- ConfigureCamRxCtrl((const Cal_CmplxIoCfg_t *)
- &pCfg->cmplxIoCfg[idx], idx);
- rxCoreBaseAddr = cam0RxCoreBaseAddr;
- if (idx > 0U)
- {
- rxCoreBaseAddr = cam1RxCoreBaseAddr;
- if (idx >= CSL_CAL_CMPLXIO_CNT)
- {
- GT_assert(CalTrace, ((uint32_t)FALSE));
- }
- }
-
-/* C & C++ INVARIANT_CONDITION.GEN
- * Expression 'FVID2_SOK == rtnVal' used in the condition always yields the
- * same result.
- * KW State: Ignore -> Waiver -> Case by case
- * MISRAC_WAIVER:
- * In cases where value in the if condition is dependent on the return of a
- * function and currently the function is hardcoded to return a value. Code is
- * currently unreachable but as the implementation of the function changes, it
- * will not be unreachable.
- */
- if((FVID2_SOK == rtnVal) && (0U != rxCoreBaseAddr))
- {
- /* 2. Reset complex IO - Do not wait for reset completion */
- reg = reg = HW_RD_REG32(baseAddr + CAL_CSI2_COMPLEXIO_CFG(idx));
- reg |= CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK;
- HW_WR_REG32(baseAddr + CAL_CSI2_COMPLEXIO_CFG(idx), reg);
- /* Dummy read to allow SCP to complete */
- reg = HW_RD_REG32(baseAddr + CAL_CSI2_COMPLEXIO_CFG(idx));
- timeOut = 0xFFFFFU;
-
- /* Timeouts */
- ConfigureStopStateTimeouts(rxCoreBaseAddr, pCfg->csi2PhyClock[idx],
- idx);
-
- /* B. Enable stop state transition timeouts */
- reg = HW_RD_REG32(baseAddr + CAL_CSI2_TIMING(idx));
-
- reg &= ~((uint32_t) (CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK |
- CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK |
- CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK |
- CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK));
- reg |= CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK &
- (pCfg->ppiCfg[idx].csi2Cfg.stop_state_x16_I01 <<
- CAL_CSI2_TIMING_STOP_STATE_X16_IO1_SHIFT);
- reg |= CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK &
- (pCfg->ppiCfg[idx].csi2Cfg.stop_state_x4_I01 <<
- CAL_CSI2_TIMING_STOP_STATE_X4_IO1_SHIFT);
- reg |= CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK &
- (pCfg->ppiCfg[idx].csi2Cfg.stop_state_counter_I01 <<
- CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_SHIFT);
- HW_WR_REG32(baseAddr + CAL_CSI2_TIMING(idx), reg);
-
- /* 4 Force FORCERXMODE */
- reg = HW_RD_REG32(baseAddr + CAL_CSI2_TIMING(idx));
- reg |= CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK;
- HW_WR_REG32(baseAddr + CAL_CSI2_TIMING(idx), reg);
-
- /* E. Power up the PHY using the complex IO */
- reg = HW_RD_REG32(baseAddr + CAL_CSI2_COMPLEXIO_CFG(idx));
- reg |= CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK &
- ((uint32_t) CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON <<
- CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_SHIFT);
- HW_WR_REG32(baseAddr + CAL_CSI2_COMPLEXIO_CFG(idx), reg);
-
- /* F. Wait for power up completion */
- timeOut = 0xFFFFFFU;
- while(timeOut)
- {
- reg = HW_RD_REG32(baseAddr + CAL_CSI2_COMPLEXIO_CFG(idx));
- reg = (reg & CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK);
- reg = (reg >> CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_SHIFT);
- if(CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_ON == reg)
- {
- break;
- }
- timeOut--;
- }
- if(0U == timeOut)
- {
- /* Could not power up the PHY... */
- rtnVal = FVID2_ETIMEOUT;
- GT_assert(CalTrace, ((uint32_t)FALSE));
- break;
- }
- ConfigureLdoi913Errata(rxCoreBaseAddr);
- }
- }
-
- return rtnVal;
-}
-
-
-/**************************Function Separator**********************************/
-
-static void ConfigureCamRxCtrl(const Cal_CmplxIoCfg_t *pCmplxIoCfg,
- uint32_t inst)
-{
- volatile uint32_t reg, enabledLanes;
- uint32_t modeMask, camModeMask, ctrlClkEnMask, laneEnMask;
- uint32_t laneEn;
-
- modeMask = CTRL_CORE_CAMERRX_CONTROL_CSI0_MODE_MASK;
- laneEnMask = CTRL_CORE_CAMERRX_CONTROL_CSI0_LANEENABLE_MASK;
- camModeMask = CTRL_CORE_CAMERRX_CONTROL_CSI0_CAMMODE_MASK;
- ctrlClkEnMask = CTRL_CORE_CAMERRX_CONTROL_CSI0_CTRLCLKEN_MASK;
- laneEn = CSI0_X_LANE_ENABLED;
-
- if (1U == inst)
- {
- modeMask = CTRL_CORE_CAMERRX_CONTROL_CSI1_MODE_MASK;
- laneEnMask = CTRL_CORE_CAMERRX_CONTROL_CSI1_LANEENABLE_MASK;
- camModeMask = CTRL_CORE_CAMERRX_CONTROL_CSI1_CAMMODE_MASK;
- ctrlClkEnMask = CTRL_CORE_CAMERRX_CONTROL_CSI1_CTRLCLKEN_MASK;
- laneEn = CSI1_X_LANE_ENABLED;
- }
-
- reg = HW_RD_REG32(SOC_CTRL_MODULE_CORE_CORE_PAD_REGISTERS_BASE +
- CTRL_CORE_CAMERRX_CONTROL);
- reg &= ~((uint32_t) (modeMask | laneEnMask | camModeMask | ctrlClkEnMask));
-
- /* Enable mode */
- reg |= modeMask;
-
- /* Enable Required lanes */
- enabledLanes = 0x0;
- if((uint32_t)TRUE == pCmplxIoCfg->enable)
- {
- /* All lane modules requires to be enabled, when operting with 1, 2
- 3 lane mode */
-
- /* Clock lane is fixed at position 1 */
- enabledLanes = (enabledLanes | (laneEn << 2U));
- enabledLanes = (enabledLanes | (laneEn << 3U));
-
- /* Second PHY has only 2 lanes */
- if (0U == inst)
- {
- enabledLanes = (enabledLanes | (laneEn << 4U));
- enabledLanes = (enabledLanes | (laneEn << 5U));
- }
-
- reg |= (laneEnMask & enabledLanes);
- }
-
- /* Enable DPHY Mode */
- reg &= ~camModeMask;
-
- /* Enable CTRL CLK */
- reg |= ctrlClkEnMask;
-
- HW_WR_REG32(SOC_CTRL_MODULE_CORE_CORE_PAD_REGISTERS_BASE +
- CTRL_CORE_CAMERRX_CONTROL, reg);
-}
-
-/**************************Function Separator**********************************/
-
-static void ConfigureStopStateTimeouts(uint32_t camRxCoreBaseAddr,
- uint32_t csi2Clk, uint32_t inst)
-{
- volatile uint32_t reg;
- uint32_t thsTerm, thsSettle, tclkTerm, tclkSettle;
- Float32 ddrClkPeriod, temp;
-
- /* A. Setup the timings parameters in terms of DDR &
- PHY functional clock */
- reg = HW_RD_REG32(camRxCoreBaseAddr + CAL_CSI2_PHY_REG0);
- reg &= ~((uint32_t) (CAL_CSI2_PHY_REG0_THS_TERM_MASK |
- CAL_CSI2_PHY_REG0_THS_SETTLE_MASK));
-
- /* Effective time for enabling of termination = synchronizer delay
- + timer delay + LPRX delay + combinational routing delay
- THS_TERM = Floor (20/DDR Clock) */
-
- /* Get DDR clock period in nS */
- ddrClkPeriod = (Float32)((Float32)csi2Clk * (Float32)1000000U);
- ddrClkPeriod = (Float32)((Float32)1U / ddrClkPeriod);
- ddrClkPeriod = (Float32)(ddrClkPeriod * (Float32)1000000000U);
- GT_assert(CalTrace, ((uint32_t)ddrClkPeriod > 0U));
- temp = ((Float32)20U / ddrClkPeriod);
- thsTerm = (uint32_t)temp;
-
- /* Effective Ths-settle seen on line
- (starting to look for sync pattern) THS_SETTLE =
- synchronizer delay + timer delay + LPRX delay + combinational
- routing delay - pipeline delay in HS data path.
- (105 / DDR Clock) + 4
- */
- temp = (Float32)(((Float32)105 / ddrClkPeriod) + (Float32)4U);
- thsSettle = (uint32_t)temp;
-
- reg |= thsTerm << CAL_CSI2_PHY_REG0_THS_TERM_SHIFT;
-
- reg |= thsSettle << CAL_CSI2_PHY_REG0_THS_SETTLE_SHIFT;
-
- HW_WR_REG32(camRxCoreBaseAddr + CAL_CSI2_PHY_REG0, reg);
-
- reg = HW_RD_REG32(camRxCoreBaseAddr + CAL_CSI2_PHY_REG1);
- reg &= ~(CAL_CSI2_PHY_REG1_TCLK_TERM_MASK |
- CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK);
- /* Requirement from D-PHY spec= (Dn Voltage < 450 mV) - 38 ns
- Effective time for enabling of termination (TCLK_TERM) =
- synchronizer delay + timer delay + LPRX delay +
- combinational routing delay
- TCLK_TERM = 23 / Functional clock period - 2
- */
- temp = (((Float32)23U / (Float32)DPHY_FUNCTIONAL_CLK_PERIOD) - (Float32)2U);
- tclkTerm = (uint32_t)temp;
-
- /* Derived requirement from D-PHY spec = 100 ns to 300ns.
- Effective Ths-settle = synchronizer delay + timer delay +
- LPRX delay + combinational routing delay
-
- Average of minimum delay + maximum delay / 2
-
- TCLK_SETTLE = floor(260/<Functional PHY Clock in nS>) - 2
- */
- temp = (((Float32)260U /
- (Float32)DPHY_FUNCTIONAL_CLK_PERIOD) - (Float32)2U);
- tclkSettle = (uint32_t)temp;
-
- reg |= CAL_CSI2_PHY_REG1_TCLK_TERM_MASK &
- (tclkTerm << CAL_CSI2_PHY_REG1_TCLK_TERM_SHIFT);
-
- reg |= CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK &
- (tclkSettle << CAL_CSI2_PHY_REG1_TCLK_SETTLE_SHIFT);
-
- HW_WR_REG32(camRxCoreBaseAddr + CAL_CSI2_PHY_REG1, reg);
-}
-
-static void ConfigureLdoi913Errata(uint32_t camRxCoreBaseAddr)
-{
- /* Extracts from the errata
- i913 CSI2 LDO Needs to Be Disabled when Module Is Powered On.
- CRITICALITY: High
- DESCRIPTION: Enabling CSI2 LDO shorts it to core supply. It is crucial
- the 2 CSI2 LDOs on the device are disabled if CSI-2
- module is powered on
- ((0x4845 B304 | 0x4845 B384) [28:27] = 0x1)
- or in ULPS (0x4845 B304 | 0x4845 B384 [28:27] = 0x2).
- Common concerns include: high current draw on the module supply in
- active mode.
- Errata does not apply when CSI-2 module is powered off
- ((0x4845 B304 | 0x4845 B384)[28:27] = 0x0).
- WORKAROUND
- NOTE: DRA71x CSI2 interface do not support CSI2_PHY2.
- CSI-2 module enabled:
- Set the following register bits to disable the LDO:
- • For CSI2_PHY1: Set bit 6 of 0x4845 B828
- • For CSI2_PHY2: Set bit 6 of 0x4845 B928
- */
- volatile uint32_t reg;
-
- reg = HW_RD_REG32(camRxCoreBaseAddr + CAL_CSI2_PHY_REG10);
-
- reg = (uint32_t)(reg & ~(uint32_t)CAL_CSI2_PHY_REG10_LDO_DISABLE_MASK);
-
- HW_WR_REG32(camRxCoreBaseAddr + CAL_CSI2_PHY_REG10, reg);
-}
index 47aedb5d0d20a1bda655aea568f116ff27abd0f3..e2054c98b1796b4c6592f7f3e6ebf72b72c82ff7 100755 (executable)
--- a/src/hal/src_files_hal.mk
+++ b/src/hal/src_files_hal.mk
SRCS_COMMON += cal_hal.c
-ifeq ($(SOC),$(filter $(SOC), tda2ex))
- SRCS_COMMON += cal_halCsi2Tda2ex.c
-endif
ifeq ($(SOC),$(filter $(SOC), am65xx))
SRCS_COMMON += cal_halCsi2Am65xx.c
endif