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raw | patch | inline | side by side (parent: 8ace98c)
author | John Dowdal <jdowdal@ti.com> | |
Fri, 30 May 2014 15:00:44 +0000 (11:00 -0400) | ||
committer | John Dowdal <jdowdal@ti.com> | |
Fri, 30 May 2014 15:00:44 +0000 (11:00 -0400) |
index f0b1d8f58ec4d0c9be1f15d431f4e88bd0b2acf8..9e5424c423bfc9f46ffe079dec2a7e6d6bffc8da 100644 (file)
/** CPDMA this configuration belongs to */
Cppi_CpDma_XGE_CPDMA,
/** Maximum supported Rx Channels */
- 0u,
+ 16u,
/** Maximum supported Tx Channels */
- 0u,
+ 8u,
/** Maximum supported Rx Flows */
- 0u,
+ 32u,
/** Priority for all Rx transactions of this CPDMA */
0u,
/** Priority for all Tx transactions of this CPDMA */
/** Base address for the CPDMA overlay registers */
/** Global Config registers */
- (CSL_Cppidma_global_configRegs *) NULL,
+ (CSL_Cppidma_global_configRegs *) CSL_XGE_CFG_PKTDMA_GLOBAL_CFG_REGS,
/** Tx Channel Config registers */
- (CSL_Cppidma_tx_channel_configRegs *) NULL,
+ (CSL_Cppidma_tx_channel_configRegs *) CSL_XGE_CFG_PKTDMA_TX_CFG_REGS,
/** Rx Channel Config registers */
- (CSL_Cppidma_rx_channel_configRegs *) NULL,
+ (CSL_Cppidma_rx_channel_configRegs *) CSL_XGE_CFG_PKTDMA_RX_CFG_REGS,
/** Tx Channel Scheduler registers */
- (CSL_Cppidma_tx_scheduler_configRegs *) NULL,
+ (CSL_Cppidma_tx_scheduler_configRegs *) CSL_XGE_CFG_PKTDMA_TX_SCHEDULER_CFG_REGS,
/** Rx Flow Config registers */
- (CSL_Cppidma_rx_flow_configRegs *) NULL,
+ (CSL_Cppidma_rx_flow_configRegs *) CSL_XGE_CFG_PKTDMA_RX_FLOW_CFG_REGS,
/** RM DTS resource name for CPDMA rx channels */
"xge-rx-ch",
/** Base address for second 4K queues */
CSL_QMSS_DATA_QM1_QUEUE_MANAGEMENT_REGS + 0x10000,
/** Base address for third 4K queues */
- CSL_QMSS_DATA_QM2_QUEUE_MANAGEMENT_REGS,
+ NULL,
/** Base address for fourth 4K queues */
- CSL_QMSS_DATA_QM2_QUEUE_MANAGEMENT_REGS + 0x10000
+ NULL
};
/**
index 56e9904527116ee561d0fd9200a3dd0a57ff0888..0cda9e33bfe3a553c4bb7e35475f0685ad2e6942 100644 (file)
/** Base address for second 4K queues */
CSL_QMSS_DATA_QM1_QUEUE_MANAGEMENT_REGS + 0x10000,
/** Base address for third 4K queues */
- CSL_QMSS_DATA_QM2_QUEUE_MANAGEMENT_REGS,
+ NULL,
/** Base address for fourth 4K queues */
- CSL_QMSS_DATA_QM2_QUEUE_MANAGEMENT_REGS + 0x10000
+ NULL
};
/**
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