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32 */
34 /**
35 * @defgroup DFE_FL_BB_API BB
36 * @ingroup DFE_FL_API
37 */
39 /** @file dfe_fl_bb.h
40 *
41 * @path $(CSLPATH)\inc
42 *
43 * @brief Header file for functional layer of DFE_BB CSL
44 *
45 * Description
46 * - Function level symbolic constants, enumerations, structure definitions
47 * and function prototype declarations
48 *
49 */
50 /* =============================================================================
51 * Revision History
52 * ===============
53 *
54 *
55 * =============================================================================
56 */
58 /**
59 * @defgroup DFE_FL_BB_SYMBOL DFE Bb Symbols
60 * @ingroup DFE_FL_BB_API
61 */
63 /**
64 * @defgroup DFE_FL_BB_DATASTRUCT DFE Bb Data Structures
65 * @ingroup DFE_FL_BB_API
66 */
68 /**
69 * @defgroup DFE_FL_BB_ENUM DFE Bb Enumverated Data Types
70 * @ingroup DFE_FL_BB_API
71 */
73 /**
74 * @defgroup DFE_FL_BB_FUNCTION DFE Bb Functions
75 * @ingroup DFE_FL_BB_API
76 */
78 #ifndef _DFE_FL_BB_H_
79 #define _DFE_FL_BB_H_
81 #ifdef __cplusplus
82 extern "C" {
83 #endif
85 //#include <ti/csl/csl.h>
86 #include <ti/csl/cslr_dfe_bb.h>
87 #include <ti/drv/dfe/dfe_fl.h>
89 /**
90 * @addtogroup DFE_FL_BB_SYMBOL
91 * @{
92 */
94 #define DFE_FL_BB_MAX_AID_STREAM_ID 256
95 #define DFE_FL_BB_MAX_SLOTS 256
96 #define DFE_FL_BB_MAX_DL_XLATES 256
97 #define DFE_FL_BB_MAX_UL_XLATES 48
98 /// max supported carrier types
99 #define DFE_FL_BB_MAX_CARRIER_TYPES 16
100 #define DFE_FL_BB_AXC_MAX_SLOTS 16
101 /// max supported BB power meters each direction
102 #define DFE_FL_BB_MAX_POWMTRS 16
103 /// max supported AxCs per antenna
104 #define DFE_FL_BB_ANTENNA_MAX_AXCS 16
106 /**
107 * @}
108 */
110 /**
111 * @addtogroup DFE_FL_BB_ENUM
112 * @{
113 */
114 /** @brief control commands
115 */
116 typedef enum
117 {
118 /// BB inits
119 DFE_FL_BB_CMD_CFG_INITS,
120 /// enable aid loopback
121 DFE_FL_BB_CMD_ENB_AID_LOOPBACK,
122 /// disable aid loopback
123 DFE_FL_BB_CMD_DIS_AID_LOOPBACK,
124 /// buf loopback config
125 DFE_FL_BB_CMD_CFG_LOOPBACK,
126 /// capture buffer config
127 DFE_FL_BB_CMD_CFG_CAPBUFF,
128 /// test signal generation config
129 DFE_FL_BB_CMD_CFG_TESTGEN,
130 /// test signal generation sync selection
131 DFE_FL_BB_CMD_SET_TESTGEN_SSEL,
132 /// config chksum
133 DFE_FL_BB_CMD_CFG_CHKSUM,
134 /// select checksum sync source
135 DFE_FL_BB_CMD_SET_CHKSUM_SSEL,
136 /// select carrier type UL sync strobe
137 DFE_FL_BB_CMD_CFG_CT_UL_SYNC_STROBE,
138 /// set AID UL strobe delay
139 DFE_FL_BB_CMD_CFG_AID_ULSTROBE_DLY,
141 /// config TXIF_AXC
142 DFE_FL_BB_CMD_CFG_TXIF_AXC,
143 /// config RXIF_AXC
144 DFE_FL_BB_CMD_CFG_RXIF_AXC,
145 /// config sync selection for tx gain update
146 DFE_FL_BB_CMD_SET_TXGAIN_SSEL,
147 /// update TX gain of axc
148 DFE_FL_BB_CMD_UPD_TXGAIN,
149 /// enable txgain update interrupt
150 DFE_FL_BB_CMD_ENB_TXGAIN_INTR,
151 /// disable txgain update interrupt
152 DFE_FL_BB_CMD_DIS_TXGAIN_INTR,
153 /// clear txgain update interrupt status
154 DFE_FL_BB_CMD_CLR_TXGAIN_INTR_STATUS,
155 /// force set txgain update interrupt
156 DFE_FL_BB_CMD_SET_FORCE_TXGAIN_INTR,
157 /// clear set txgain update interrupt
158 DFE_FL_BB_CMD_CLR_FORCE_TXGAIN_INTR,
160 /// TX TDD timer config
161 DFE_FL_BB_CMD_CFG_TXTDD,
162 /// TX TDD timer config sync selection
163 DFE_FL_BB_CMD_SET_TXTDD_SSEL,
164 /// RX TDD timer config
165 DFE_FL_BB_CMD_CFG_RXTDD,
166 /// RX TDD timer config sync selection
167 DFE_FL_BB_CMD_SET_RXTDD_SSEL,
169 /** TX power meter commands
170 */
171 /// config a tx power meter
172 DFE_FL_BB_CMD_CFG_TXPM,
173 /// config a tx power meter ssel
174 DFE_FL_BB_CMD_SET_TXPM_SSEL,
175 /// disable update of a tx power meter
176 DFE_FL_BB_CMD_DIS_TXPM_UPDATE,
177 /// enable interrupt of a tx power meter
178 DFE_FL_BB_CMD_ENB_TXPM_INTR,
179 /// enable interrupt of a tx power meter
180 DFE_FL_BB_CMD_DIS_TXPM_INTR,
181 /// clear interrupt status of a tx power meter
182 DFE_FL_BB_CMD_CLR_TXPM_INTR_STATUS,
183 /// force setting interrupt status of a tx power meter
184 DFE_FL_BB_CMD_SET_FORCE_TXPM_INTR,
185 /// clear forcing interrupt status of a tx power meter
186 DFE_FL_BB_CMD_CLR_FORCE_TXPM_INTR,
187 /// enable interrupt to the cpp
188 DFE_FL_BB_CMD_ENB_TXPM_AUXINTR,
189 /// disable interrupt to the cpp
190 DFE_FL_BB_CMD_DIS_TXPM_AUXINTR,
192 /** RX power meter commands
193 */
194 /// config a BBRX power meter
195 DFE_FL_BB_CMD_CFG_RXPM,
196 /// select sync source for BBRX power meter
197 DFE_FL_BB_CMD_SET_RXPM_SSEL,
198 /// disable a BBRX power meter update
199 DFE_FL_BB_CMD_DIS_RXPM_UPDATE,
200 /// enable a BBRX power meter interrupt
201 DFE_FL_BB_CMD_ENB_RXPM_INTR,
202 /// disable a BBRX power meter interrupt
203 DFE_FL_BB_CMD_DIS_RXPM_INTR,
204 /// clear status of a BBRX power mter interrupt
205 DFE_FL_BB_CMD_CLR_RXPM_INTR_STATUS,
206 /// force generating a BBRX power meter interrupt
207 DFE_FL_BB_CMD_SET_FORCE_RXPM_INTR,
208 /// clear force generating a BBRX power meter interrupt
209 DFE_FL_BB_CMD_CLR_FORCE_RXPM_INTR,
210 /// enable BBRX aux interrupts
211 DFE_FL_BB_CMD_ENB_RXPM_AUXINTR,
212 /// disable BBRX aux interrupts
213 DFE_FL_BB_CMD_DIS_RXPM_AUXINTR,
215 /** Antenna Calibration
216 */
217 /// config antenna calibration global
218 DFE_FL_BB_CMD_CFG_ANTCAL_GLOBAL,
219 /// config antenna calibration
220 DFE_FL_BB_CMD_CFG_ANTCAL,
224 /** Rx gain control
225 */
226 /// config sync selection for tx gain update
227 DFE_FL_BB_CMD_SET_RXGAIN_SSEL,
228 /// update RX gain of axc
229 DFE_FL_BB_CMD_UPD_RXGAIN,
230 /// enable rx gain update interrupt
231 DFE_FL_BB_CMD_ENB_RXGAIN_INTR,
232 /// disable rx gain update interrupt
233 DFE_FL_BB_CMD_DIS_RXGAIN_INTR,
234 /// clear rx gain update interrupt status
235 DFE_FL_BB_CMD_CLR_RXGAIN_INTR_STATUS,
236 /// force setting rx gain update interrupt status
237 DFE_FL_BB_CMD_SET_FORCE_RXGAIN_INTR,
238 /// clear force setting rx gain update interrupt status
239 DFE_FL_BB_CMD_CLR_FORCE_RXGAIN_INTR,
241 /** beAGC control
242 */
243 /// config beAGC globals
244 DFE_FL_BB_CMD_CFG_BEAGC_GLOBAL,
245 /// config a beAGC control loop
246 DFE_FL_BB_CMD_CFG_BEAGC,
247 /// config a beAGC control loop ssel
248 DFE_FL_BB_CMD_SET_BEAGC_SSEL,
250 /** Rx Notch filter
251 */
252 /// config Rx Notch filter globals
253 DFE_FL_BB_CMD_CFG_RXNOTCH_GLOBAL,
254 /// Rx Notch ssel
255 DFE_FL_BB_CMD_SET_RXNOTCH_SSEL,
256 /// config a Rx Notch filter
257 DFE_FL_BB_CMD_CFG_RXNOTCH,
259 /** BB general interrupts
260 */
261 /// enable a BB general interrupt
262 DFE_FL_BB_CMD_ENB_GENERAL_INTR,
263 /// disable a BB general interrupt
264 DFE_FL_BB_CMD_DIS_GENERAL_INTR,
265 /// clear status of a BB general interrupt
266 DFE_FL_BB_CMD_CLR_GENERAL_INTR_STATUS,
267 /// force generating a BB general interrupt
268 DFE_FL_BB_CMD_SET_FORCE_GENERAL_INTR,
269 /// clear force generating a BB general interrupt
270 DFE_FL_BB_CMD_CLR_FORCE_GENERAL_INTR,
271 /// enable group of BB general interrupts
272 DFE_FL_BB_CMD_ENB_GENERAL_INTRGRP,
273 /// disable group of BB general interrupts
274 DFE_FL_BB_CMD_DIS_GENERAL_INTRGRP,
275 /// clear status of group of BB general interrupts
276 DFE_FL_BB_CMD_CLR_GENERAL_INTRGRP_STATUS,
277 /// force generating group of BB general interrupts
278 DFE_FL_BB_CMD_SET_FORCE_GENERAL_INTRGRP,
279 /// clear force generating group of BB general interrupts
280 DFE_FL_BB_CMD_CLR_FORCE_GENERAL_INTRGRP,
283 DFE_FL_BB_CMD_MAX_VALUE
284 } DfeFl_BbHwControlCmd;
286 /** @brief query commands
287 */
288 typedef enum
289 {
290 /// AID loopback config
291 DFE_FL_BB_QUERY_AID_LOOPBACK_CFG = 0,
292 /// loopback config
293 DFE_FL_BB_QUERY_LOOPBACK_CFG,
294 /// capture buffer config
295 DFE_FL_BB_QUERY_CAPBUFF_CFG,
296 /// test signal generation config
297 DFE_FL_BB_QUERY_TESTGEN_CFG,
298 /// test signal generation sync selection
299 DFE_FL_BB_QUERY_TESTGEN_SSEL,
300 /// chksum ssel
301 DFE_FL_BB_QUERY_CHKSUM_SSEL,
302 /// chksum result
303 DFE_FL_BB_QUERY_CHKSUM_RESULT,
304 /// get carrier type UL sync strobe
305 DFE_FL_BB_QUERY_CT_UL_SYNC_STROBE,
306 // get BB AID UL strobe delay
307 DFE_FL_BB_QUERY_AID_ULSTROBE_DLY,
309 /// TX GAIN upadte status
310 DFE_FL_BB_QUERY_TXGAIN_UPDATE_STATUS,
311 /// config sync selection for tx gain update
312 DFE_FL_BB_QUERY_TXGAIN_SSEL,
313 /// TX gain config
314 DFE_FL_BB_QUERY_TXGAIN_INTR_STATUS,
316 /// TX TDD timer config
317 DFE_FL_BB_QUERY_TXTDD_CFG,
318 /// TX TDD timer sync selection
319 DFE_FL_BB_QUERY_TXTDD_SSEL,
320 /// RX TDD timer config
321 DFE_FL_BB_QUERY_RXTDD_CFG,
322 /// RX TDD timer sync selection
323 DFE_FL_BB_QUERY_RXTDD_SSEL,
325 /** TX power meter queries
326 */
327 /// get BBTX power meter config
328 DFE_FL_BB_QUERY_TXPM_CFG,
329 /// get BBTX power meter sync select
330 DFE_FL_BB_QUERY_TXPM_SSEL,
331 /// get if BBTX power meter update disabled
332 DFE_FL_BB_QUERY_DIS_TXPM_UPDATE,
333 /// get status of BBTX power meter
334 DFE_FL_BB_QUERY_TXPM_INTR_STATUS,
335 /// get result of BBTX power meter
336 DFE_FL_BB_QUERY_TXPM_RESULT,
338 /** RX power meter queries
339 */
340 /// get BBRX power meter config
341 DFE_FL_BB_QUERY_RXPM_CFG,
342 /// get BBRX power meter sync select
343 DFE_FL_BB_QUERY_RXPM_SSEL,
344 /// get if BBRX power meter update disabled
345 DFE_FL_BB_QUERY_DIS_RXPM_UPDATE,
346 /// get status of BBRX power meter
347 DFE_FL_BB_QUERY_RXPM_INTR_STATUS,
348 /// get result of BBRX power meter
349 DFE_FL_BB_QUERY_RXPM_RESULT,
351 /** Antenna Calibration queries
352 */
353 /// get global config of antenna calibration
354 DFE_FL_BB_QUERY_ANTCAL_GLOBAL_CFG,
355 /// get config of antenna calibration
356 DFE_FL_BB_QUERY_ANTCAL_CFG,
357 /// get result of antenna calibration
358 DFE_FL_BB_QUERY_ANTCAL_RESULT,
360 /// RX GAIN upadte status
361 DFE_FL_BB_QUERY_RXGAIN_UPDATE_STATUS,
362 /// config sync selection for rx gain update
363 DFE_FL_BB_QUERY_RXGAIN_SSEL,
364 /// query rx gain update interrupt status
365 DFE_FL_BB_QUERY_RXGAIN_INTR_STATUS,
366 /// config beAGC globals
367 DFE_FL_BB_QUERY_BEAGC_GLOBAL_CFG,
368 /// config a beAGC control loop
369 DFE_FL_BB_QUERY_BEAGC_CFG,
370 /// config a beAGC control loop ssel
371 DFE_FL_BB_QUERY_BEAGC_SSEL,
373 /** Rx Notch filter
374 */
375 /// config Rx Notch filter globals
376 DFE_FL_BB_QUERY_RXNOTCH_GLOBAL_CFG,
377 /// Rx Notch ssel
378 DFE_FL_BB_QUERY_RXNOTCH_SSEL,
379 /// config a Rx Notch filter
380 DFE_FL_BB_QUERY_RXNOTCH_CFG,
382 /// get status of BB general interrupt
383 DFE_FL_BB_QUERY_GENERAL_INTR_STATUS,
384 /// get status of group of BB general interrupts
385 DFE_FL_BB_QUERY_GENERAL_INTRGRP_STATUS,
387 DFE_FL_BB_QUERY_MAX_VALUE
388 } DfeFl_BbHwStatusQuery;
390 /** @brief carrier type */
391 typedef enum
392 {
393 /// carrier type 0
394 DFE_FL_BB_CARRIER_TYPE_0 = 0,
395 /// carrier type 1
396 DFE_FL_BB_CARRIER_TYPE_1,
397 /// carrier type 2
398 DFE_FL_BB_CARRIER_TYPE_2,
399 /// carrier type 3
400 DFE_FL_BB_CARRIER_TYPE_3,
401 /// carrier type 4
402 DFE_FL_BB_CARRIER_TYPE_4,
403 /// carrier type 5
404 DFE_FL_BB_CARRIER_TYPE_5,
405 /// carrier type 6
406 DFE_FL_BB_CARRIER_TYPE_6,
407 /// carrier type 7
408 DFE_FL_BB_CARRIER_TYPE_7,
409 /// carrier type 8
410 DFE_FL_BB_CARRIER_TYPE_8,
411 /// carrier type 9
412 DFE_FL_BB_CARRIER_TYPE_9,
413 /// carrier type 10
414 DFE_FL_BB_CARRIER_TYPE_10,
415 /// carrier type 11
416 DFE_FL_BB_CARRIER_TYPE_11,
417 /// carrier type 12
418 DFE_FL_BB_CARRIER_TYPE_12,
419 /// carrier type 13
420 DFE_FL_BB_CARRIER_TYPE_13,
421 /// carrier type 14
422 DFE_FL_BB_CARRIER_TYPE_14,
423 /// carrier type 15
424 DFE_FL_BB_CARRIER_TYPE_15,
426 /// carrier type ALL
427 DFE_FL_BB_CARRIER_TYPE_ALL = 0xffff
428 } DfeFl_BbCarrierType;
430 /** @brief test_cb_control selection */
431 typedef enum
432 {
433 /// BB testbus probe, disabled (normal)
434 DFE_FL_BB_TEST_CB_CTRL_DISABLE = 0x00,
435 /// BB testbus probe, BBTX AID AxC single
436 DFE_FL_BB_TEST_CB_CTRL_TX_AID_S = 0x01,
437 /// BB testbus probe, BBTX AID AxC all
438 DFE_FL_BB_TEST_CB_CTRL_TX_AID_A = 0x03,
439 /// BB testbus probe, BBTX buffer memory single
440 DFE_FL_BB_TEST_CB_CTRL_TX_BUFMEM_S = 0x05,
441 /// BB testbus probe, BBTX buffer memory all
442 DFE_FL_BB_TEST_CB_CTRL_TX_BUFMEM_A = 0x07,
443 /// BB testbus probe, BBTX DDUC interface single
444 DFE_FL_BB_TEST_CB_CTRL_TX_DDUCIF_S = 0x09,
445 /// BB testbus probe, BBTX DDUC interface all
446 DFE_FL_BB_TEST_CB_CTRL_TX_DDUCIF_A = 0x0B,
447 /// BB testbus probe, BB JESDTX AxC single
448 DFE_FL_BB_TEST_CB_CTRL_JTX_AID_S = 0x0D,
449 /// BB testbus probe, BB JESDTX AxC all
450 DFE_FL_BB_TEST_CB_CTRL_JTX_AID_A = 0x0F,
452 /// BB testbus probe, BBRX AID AxC single
453 DFE_FL_BB_TEST_CB_CTRL_RX_AID_S = 0x21,
454 /// BB testbus probe, BBRX AID AxC all
455 DFE_FL_BB_TEST_CB_CTRL_RX_AID_A = 0x23,
456 /// BB testbus probe, BBRX buffer memory single
457 DFE_FL_BB_TEST_CB_CTRL_RX_BUFMEM_S = 0x25,
458 /// BB testbus probe, BBRX buffer memory all
459 DFE_FL_BB_TEST_CB_CTRL_RX_BUFMEM_A = 0x27,
460 /// BB testbus probe, BBRX DDUC interface single
461 DFE_FL_BB_TEST_CB_CTRL_RX_DDUCIF_S = 0x29,
462 /// BB testbus probe, BBRX DDUC interface all
463 DFE_FL_BB_TEST_CB_CTRL_RX_DDUCIF_A = 0x2B,
464 /// BB testbus probe, BB JESDRX AID AxC single
465 DFE_FL_BB_TEST_CB_CTRL_JRX_AID_S = 0x2D,
466 /// BB testbus probe, BB JESDRX AID AxC all
467 DFE_FL_BB_TEST_CB_CTRL_JRX_AID_A = 0x2F
469 } DfeFl_BbTestCbCtrl;
471 /** @brief BB general interrupt */
472 typedef enum
473 {
474 /// BB general interrupt, TXPM_LDERR
475 DFE_FL_BB_GENERAL_INTR_TXPM_LDERR = 0,
476 /// BB general interrupt, RXPM_LDERR
477 DFE_FL_BB_GENERAL_INTR_RXPM_LDERR = 1,
478 /// BB general interrupt, ANTCAL
479 DFE_FL_BB_GENERAL_INTR_ANTCAL = 2,
480 /// BB general interrupt, RXNOTCH_DONE
481 DFE_FL_BB_GENERAL_INTR_RXNOTCH_DONE = 3,
482 /// BB general interrupt, RXNOTCH_ERR
483 DFE_FL_BB_GENERAL_INTR_RXNOTCH_ERR = 4,
485 /// BB general interrupt, BUFMEM0_OUF (overflow/underflow)
486 DFE_FL_BB_GENERAL_INTR_BUFMEM0_OUF = 8,
487 /// BB general interrupt, BUFMEM1_OUF (overflow/underflow)
488 DFE_FL_BB_GENERAL_INTR_BUFMEM1_OUF = 9,
489 /// BB general interrupt, BUFMEM2_OUF (overflow/underflow)
490 DFE_FL_BB_GENERAL_INTR_BUFMEM2_OUF = 10,
491 /// BB general interrupt, BUFMEM3_OUF (overflow/underflow)
492 DFE_FL_BB_GENERAL_INTR_BUFMEM3_OUF = 11,
493 /// BB general interrupt, BUFMEM4_OUF (overflow/underflow)
494 DFE_FL_BB_GENERAL_INTR_BUFMEM4_OUF = 12,
495 /// BB general interrupt, BUFMEM5_OUF (overflow/underflow)
496 DFE_FL_BB_GENERAL_INTR_BUFMEM5_OUF = 13,
497 /// BB general interrupt, BUFMEM6_OUF (overflow/underflow)
498 DFE_FL_BB_GENERAL_INTR_BUFMEM6_OUF = 14,
499 /// BB general interrupt, BUFMEM7_OUF (overflow/underflow)
500 DFE_FL_BB_GENERAL_INTR_BUFMEM7_OUF = 15,
501 /// BB general interrupt, RXAID_SYNCERR
502 DFE_FL_BB_GENERAL_INTR_RXAID_SYNCERR = 16,
503 /// BB general interrupt, TXAID_UDF (under flow)
504 DFE_FL_BB_GENERAL_INTR_TXAID_UDF = 17,
505 /// BB general interrupt, TXAID_OVF (over flow)
506 DFE_FL_BB_GENERAL_INTR_TXAID_OVF = 18,
507 /// BB general interrupt, JESDRX_SYNCERR
508 DFE_FL_BB_GENERAL_INTR_JESDRX_SYNCERR = 19,
509 /// BB general interrupt, JESDTX_UDF (under flow)
510 DFE_FL_BB_GENERAL_INTR_JESDTX_UDF = 20,
511 /// BB general interrupt, JESDTX_OVF (over flow)
512 DFE_FL_BB_GENERAL_INTR_JESDTX_OVF = 21
514 } DfeFl_BbGeneralIntr;
516 /** @brief BB Test Signal Generation Device
517 */
518 typedef enum
519 {
520 /// TESTGEN for DDUC0 buffer
521 DFE_FL_BB_DDUC_TESTGEN_0 = 0,
522 /// TESTGEN for DDUC1 buffer
523 DFE_FL_BB_DDUC_TESTGEN_1,
524 /// TESTGEN for DDUC2 buffer
525 DFE_FL_BB_DDUC_TESTGEN_2,
526 /// TESTGEN for DDUC3 buffer
527 DFE_FL_BB_DDUC_TESTGEN_3,
528 /// TESTGEN for DDUC4 buffer
529 DFE_FL_BB_DDUC_TESTGEN_4,
530 /// TESTGEN for DDUC5 buffer
531 DFE_FL_BB_DDUC_TESTGEN_5,
532 /// TESTGEN for DDUC6 buffer
533 DFE_FL_BB_DDUC_TESTGEN_6,
534 /// TESTGEN for DDUC7 buffer
535 DFE_FL_BB_DDUC_TESTGEN_7,
537 /// TESTGEN for AID A buffer
538 DFE_FL_BB_AID_TESTGEN_A = 8,
539 /// TESTGEN for AID B buffer
540 DFE_FL_BB_AID_TESTGEN_B = 9,
542 DFE_FL_BB_MAX_TESTGENS = 10
543 } DfeFl_BbTestGenDev;
545 /** @brief BB Test Signal Generation ramp mode
546 */
547 typedef enum
548 {
549 /// LFSR
550 DFE_FL_BB_TESTGEN_RAMP_MODE_LFSR = 0,
551 /// RAMP
552 DFE_FL_BB_TESTGEN_RAMP_MODE_RAMP = 1
553 } DfeFl_BbTestGenRampMode;
555 /** @brief BB checksum device
556 */
557 typedef enum
558 {
559 /// CHKSUM for DDUC0 buffer
560 DFE_FL_BB_DDUC_CHKSUM_0 = 0,
561 /// CHKSUM for DDUC1 buffer
562 DFE_FL_BB_DDUC_CHKSUM_1,
563 /// CHKSUM for DDUC2 buffer
564 DFE_FL_BB_DDUC_CHKSUM_2,
565 /// CHKSUM for DDUC3 buffer
566 DFE_FL_BB_DDUC_CHKSUM_3,
567 /// CHKSUM for DDUC4 buffer
568 DFE_FL_BB_DDUC_CHKSUM_4,
569 /// CHKSUM for DDUC5 buffer
570 DFE_FL_BB_DDUC_CHKSUM_5,
571 /// CHKSUM for DDUC6 buffer
572 DFE_FL_BB_DDUC_CHKSUM_6,
573 /// CHKSUM for DDUC7 buffer
574 DFE_FL_BB_DDUC_CHKSUM_7,
576 /// CHKSUM for AID A buffer
577 DFE_FL_BB_AID_CHKSUM_A = 8,
578 /// CHKSUM for AID B buffer
579 DFE_FL_BB_AID_CHKSUM_B = 9,
581 DFE_FL_BB_MAX_CHKSUMS = 10
582 } DfeFl_BbChksumDev;
584 /** @brief BB checksum return mode */
585 typedef enum
586 {
587 /// BB checksum return checksum value
588 DFE_FL_BB_CHKSUM_MODE_RETURN_CHKSUM = 0,
589 /// BB checksum return latency value
590 DFE_FL_BB_CHKSUM_MODE_RETURN_LATENCY
591 } DfeFl_BbChksumMode;
593 /** @brief data mode for Tx/Rx TDD
594 */
595 typedef enum
596 {
597 /// TX: UL data passthru unchanged
598 DFE_FL_BB_TXTDD_DATAMODE_PASSTHRU = 0,
599 /// TX: UL data is zeroed and buffer memory stalled
600 DFE_FL_BB_TXTDD_DATAMODE_ZEROED = 1,
602 /// RX: DL data is zeroed at notch filter input
603 DFE_FL_BB_RXTDD_DATAMODE_ZEROED_AT_NOTCHFILETR_INPUT = 0,
604 /// RX: DL data is zeroed at formatter
605 DFE_FL_BB_RXTDD_DATAMODE_ZEROED_AT_FORMATTER = 1,
606 /// RX: DL data is zeroed at input of BB and buffer memory stalled
607 DFE_FL_BB_RXTDD_DATAMODE_ZEROED_AT_BUFFER_INPUT = 2
608 } DfeFl_BbTddDataMode;
610 /** @brief BB power meter enable mode
611 */
612 typedef enum
613 {
614 /// power meter is off
615 DFE_FL_BB_POWMETR_OFF = 0,
616 /// run one interval and then stop per sync
617 DFE_FL_BB_POWMETR_SINGLE_POWER_MEASUREMENT,
618 /// run multi intervals and then stop per sync
619 DFE_FL_BB_POWMETR_SINGLE_POWER_UPDATE_INTERVAL,
620 /// run continuouslly, restart per sync
621 DFE_FL_BB_POWMETR_CONTINUOUS_POWER_MESURE
622 } DfeFl_BbPowMtrEnable;
623 /** @brief BB power meter result or output format
624 */
625 typedef enum
626 {
627 /// float format, 10.16e6
628 DFE_FL_BB_POWMTR_OUTFMT_FLOAT_10P16E6 = 0,
629 /// starting from 0, in 0.1dB unit step
630 DFE_FL_BB_POWMTR_OUTFMT_STEP_0P1DB = 2
631 } DfeFl_BbPowMtrOutFormat;
632 /** @brief BB power meter input source
633 */
634 typedef enum
635 {
636 /// at BB input
637 /// tx: before tx gain
638 /// rx: before notch filter
639 DFE_FL_BB_POWMTR_INSRC_INPUT = 0,
640 /// at BB output
641 /// tx: after circular clipper
642 /// rx: after beAGC
643 DFE_FL_BB_POWMTR_INSRC_OUTPUT,
644 /// at tx gain output
645 DFE_FL_BB_POWMTR_INSRC_TX_GAIN_OUTPUT = 2,
646 /// at rx notch filter output
647 DFE_FL_BB_POWMTR_INSRC_RX_FILTER_OUTPUT = 2
648 } DfeFl_BbPowMtrInSource;
649 /** @brief BB power meter tdd mode
650 */
651 typedef enum
652 {
653 /// tdd mode disabled
654 DFE_FL_BB_POWMTR_TDDMODE_DISABLED = 0,
655 /// txpm: halt when UL period
656 DFE_FL_BB_POWMTR_TDDMODE_TX_HALT_UL = 1,
657 /// rxpm: halt when DL period
658 DFE_FL_BB_POWMTR_TDDMODE_RX_HALT_DL = 1,
659 /// txpm: reset when UL period
660 DFE_FL_BB_POWMTR_TDDMODE_TX_RESET_UL = 2,
661 /// rxpm: reset when DL period
662 DFE_FL_BB_POWMTR_TDDMODE_RX_RESET_DL = 2
663 } DfeFl_BbPowMtrTddMode;
665 /**
666 * @}
667 */
669 /**
670 * @addtogroup DFE_FL_BB_DATASTRUCT
671 * @{
672 */
674 /** @brief argument for runtime control,
675 * DFE_FL_BB_CMD_CFG_LOOPBACK
676 * DFE_FL_BB_QUERY_LOOPBACK_CFG
677 */
678 typedef struct
679 {
680 /// BB buf loopback, dduc0 to dduc1
681 uint32_t duc0ToDdc1;
682 /// BB buf loopback, dduc1 to dduc2
683 uint32_t duc1ToDdc2;
684 /// BB buf loopback, dduc0 to dduc3
685 uint32_t duc0ToDdc3;
686 /// BB buf loopback, dduc3 to dduc4
687 uint32_t duc3ToDdc4;
688 /// BB buf loopback, dduc2 to dduc5
689 uint32_t duc2ToDdc5;
690 /// BB buf loopback, dduc1 to dduc6
691 uint32_t duc1ToDdc6;
692 /// BB buf loopback, dduc0 to dduc7
693 uint32_t duc0ToDdc7;
694 } DfeFl_BbLoopbackConfig;
696 /** @brief argument for runtime control,
697 * DFE_FL_BB_CMD_CFG_CAPBUFF
698 * DFE_FL_BB_QUERY_CAPBUFF_CFG
699 */
700 typedef struct
701 {
702 #ifdef _BIG_ENDIAN
703 /// BIG ENDIAN format
704 /// rsvd1
705 uint32_t rsvd1 : 16;
706 /// axc# or buf# for single mode
707 uint32_t testCbAxc : 8;
708 /// rsvd0
709 uint32_t rsvd0 : 2;
710 /// testbus probe
711 uint32_t testCbCtrl : 6;
712 #else
713 /// LITTLE ENDIAN format
714 /// testbus probe
715 uint32_t testCbCtrl : 6;
716 /// rsvd0
717 uint32_t rsvd0 : 2;
718 /// axc# or buf# for single mode
719 uint32_t testCbAxc : 8;
720 /// rsvd1
721 uint32_t rsvd1 : 16;
722 #endif
723 } DfeFl_BbCapBuffConfig;
725 /** @brief argument for runtime control,
726 * DFE_FL_BB_CMD_CFG_TESTGEN
727 * DFE_FL_BB_QUERY_TESTGEN_CFG
728 */
729 typedef struct
730 {
731 /// test gen device
732 DfeFl_BbTestGenDev tgDev;
733 /// only valid for AID
734 uint32_t testEnable;
735 /// enable data generation
736 uint32_t genData;
737 /// enbale frame generation
738 uint32_t genFrame;
739 /// ramp (1), or LFSR (0)
740 DfeFl_BbTestGenRampMode rampMode;
741 /// seed
742 uint32_t seed;
743 /// number of clocks per frame minus 1
744 uint32_t frameLenM1;
745 /// ramp starting value
746 uint32_t rampStart;
747 /// ramp stop value
748 uint32_t rampStop;
749 /// ramp slop value
750 uint32_t slope;
751 /// 0 = generate data forever, n = generate data for n clock cycles
752 uint32_t genTimer;
753 /// number of data bits inverted (read-only)
754 uint32_t numDataBits;
755 } DfeFl_BbTestGenConfig;
757 /** @brief argument for runtime control,
758 * DFE_FL_BB_CMD_SET_TESTGEN_SSEL
759 * DFE_FL_BB_QUERY_TESTGEN_SSEL
760 */
761 typedef struct
762 {
763 /// test gen device
764 DfeFl_BbTestGenDev tgDev;
765 /// sync select
766 uint32_t ssel;
767 } DfeFl_BbTestGenSsel;
769 /** @brief argument for runtime control,
770 * DFE_FL_BB_CMD_CFG_CHKSUM
771 */
772 typedef struct
773 {
774 /// checksum device
775 uint32_t chksumDev;
776 /// checksum mode
777 uint32_t chksumMode;
778 /// latency mode config
779 struct
780 {
781 /// stable length
782 uint32_t stableLen;
783 /// signal length
784 uint32_t signalLen;
785 /// channel select
786 uint32_t chanSel;
787 } latencyMode;
788 } DfeFl_BbChksumConfig;
790 /** @brief argument for runtime control,
791 * DFE_FL_BB_CMD_SET_CHKSUM_SSEL
792 */
793 typedef struct
794 {
795 /// checksum device
796 uint32_t chksumDev;
797 /// sync selection
798 uint32_t ssel;
799 } DfeFl_BbChksumSsel;
801 /** @brief argument for runtime control,
802 * DFE_FL_BB_QUERY_CHKSUM_RESULT
803 */
804 typedef struct
805 {
806 /// checksum device
807 uint32_t chksumDev;
808 /// result
809 uint32_t result;
810 } DfeFl_BbChksumResult;
812 /** @brief argument for runtime control,
813 * DFE_FL_BB_CMD_CFG_CT_UL_SYNC_STROBE
814 * DFE_FL_BB_QUERY_CT_UL_SYNC_STROBE
815 */
816 typedef struct
817 {
818 /// carrier type
819 uint32_t ct;
820 /// UL sync strobe
821 uint32_t strobe;
822 } DfeFl_BbCarrierTypeUlSyncStrobeConfig;
824 /** @brief argument for runtime control,
825 * DFE_FL_BB_CMD_CFG_AID_ULSTROBE_DLY
826 * DFE_FL_BB_QUERY_AID_ULSTROBE_DLY
827 */
828 typedef struct
829 {
830 /// carrier type
831 uint32_t ct;
832 /// UL strobe delay
833 uint32_t dly;
834 } DfeFl_BbAidUlStrobeDelayConfig;
836 /** @brief argument for runtime control,
837 * DFE_FL_BB_CMD_CFG_TXIF_AXC
838 */
839 typedef struct
840 {
841 /// Per antenna carrier index into buffer memory the carrier is assigned to
842 uint32_t bufferIndex;
843 /// Per antenna carrier buffer the carrier is assigned to
844 uint32_t bufferNum;
845 /// Per antenna carrier selection of 1 of 16 power meter configurations the carrier is assigned to.
846 uint32_t pmConfigSel;
847 /// Per antenna carrier enable of power meter function
848 uint32_t pmEn;
849 /// Per antenna carrier enable of the circular clipper function
850 uint32_t clEn;
851 /// Per antenna carrier enable of the gain function (otherwise unity gain)
852 uint32_t gainEn;
853 /// Per antenna carrier enable. When disabled carrier is ignored
854 uint32_t axcValid;
855 /// Per antenna carrier 1/T value to be used when circular clipper is enabled.
856 uint32_t cl1OverT;
857 /// Per antenna carrier antenna calibration select.
858 uint32_t antcalSel;
859 /// Per antenna carrier antenna calibration enable
860 uint32_t antcalEn;
861 /// Per antenna carrier enable of autoCP mode.
862 uint32_t autocpEn;
863 /// Per antenna carrier selection of autoCP timer (one of two choices).
864 uint32_t autocpSel;
865 } DfeFl_BbTxifAxc;
866 typedef struct
867 {
868 /// total AxCs for array of txifAxc[]
869 uint32_t numAxCs;
870 struct {
871 /// axc id#
872 uint32_t axc;
873 /// per antenna carrier config
874 DfeFl_BbTxifAxc txif;
875 } txifAxc[DFE_FL_BB_ANTENNA_MAX_AXCS];
876 } DfeFl_BbTxifAxcConfig;
878 /** @brief argument for runtime control,
879 * DFE_FL_BB_CMD_CFG_RXIF_AXC
880 */
881 typedef struct
882 {
883 /// Per antenna carrier index into buffer memory the carrier is assigned to
884 uint32_t bufferIndex;
885 /// Per antenna carrier buffer the carrier is assigned to
886 uint32_t bufferNum;
887 /// Per antenna carrier assignment of the carrier type.
888 uint32_t carrierType;
889 /// Per antenna carrier selection of AGC mode.
890 uint32_t beagcMode;
891 /// Per antenna carrier enable. When disabled carrier is ignored even if there is a slot assigned to it.
892 uint32_t axcValid;
893 /// Per antenna carrier selection of 1 of 16 power meter configurations the carrier is assigned to.
894 uint32_t pmConfigSel;
895 /// Per antenna carrier enable of power meter function
896 uint32_t pmEn;
897 /// Per antenna carrier selection of input notch filter configuration
898 uint32_t notchEn;
899 /// Per antenna carrier selection of 16 bit output packing (instead of 32 bit format)
900 uint32_t outPacked;
901 /// Per antenna carrier selection of number of floating point bits when in float mode (set by fixedorfloat)
902 uint32_t outFloatMode;
903 /// Per antenna carrier selection of floating point mode for output
904 uint32_t fixedOrFloat;
905 /// Per antenna carrier selection of number of mantissa bits +1 the output will be rounded to.
906 uint32_t outNumBits;
907 /// Selects which of 16 antenna calibration configurations to use for the carrier
908 uint32_t antcalSel;
909 /// Per antenna carrier enable of antenna calibration noise enable
910 uint32_t antcalEn;
911 /// Per antenna carrier power backoff value used when in power managed gain control mode
912 uint32_t beagcPowerBackoff;
914 /// Per antenna carrier force output to zero when tdd is in DL
915 uint32_t tdd0;
916 /// Per antenna carrier number of t3 intervals to run gain loop. 0=forever
917 uint32_t beagcT3ActvCnt;
918 /// Per antenna carrier selection of 1 of 8 beagc loop configurations to be used when in beagc mode
919 uint32_t beagcConfigSel;
920 /// Per antenna carrier t1 interval when in beagc closed loop gain mode
921 uint32_t beagcT1Interval;
922 /// Per antenna carrier t2 interval when in beagc closed loop gain mode
923 uint32_t beagcT2Interval;
924 } DfeFl_BbRxifAxc;
925 typedef struct
926 {
927 /// total AxCs for array of rxifAxc[]
928 uint32_t numAxCs;
929 struct {
930 /// axc id#
931 uint32_t axc;
932 /// per antenna carrier config
933 DfeFl_BbRxifAxc rxif;
934 } rxifAxc[DFE_FL_BB_ANTENNA_MAX_AXCS];
935 } DfeFl_BbRxifAxcConfig;
937 /** @brief argument for runtime control,
938 * DFE_FL_BB_CMD_UPD_TXIF_AXC_GAIN
939 */
940 typedef struct
941 {
942 /// number of AxCs whose gains need updating
943 uint32_t numAxCs;
944 /// axc gain update table
945 struct
946 {
947 /// axc id#
948 uint32_t axc;
949 /// real part gain word for the axc
950 uint32_t gainI;
951 /// image part gain word for the axc
952 uint32_t gainQ;
953 } axcGain[DFE_FL_BB_ANTENNA_MAX_AXCS];
954 } DfeFl_BbTxGainConfig;
956 /** @brief argument for runtime control,
957 * DFE_FL_BB_QUERY_TXGAIN_INTR_STATUS
958 * DFE_FL_BB_QUERY_RXGAIN_INTR_STATUS
959 * DFE_FL_BB_QUERY_TXGAIN_UPDATE_STATUS
960 * DFE_FL_BB_QUERY_RXGAIN_UPDATE_STATUS
961 * DFE_FL_BB_CMD_SET_RXGAIN_SSEL
962 * DFE_FL_BB_CMD_SET_TXGAIN_SSEL
963 * DFE_FL_BB_QUERY_TXGAIN_SSEL
964 * DFE_FL_BB_QUERY_RXGAIN_SSEL
965 */
966 typedef struct
967 {
968 /// carrier type
969 uint32_t ct;
970 /// set/get value
971 uint32_t data;
972 } DfeFl_BbTxRxGainCarrierTypeData;
975 /** @brief argument for runtime control,
976 * DFE_FL_BB_CMD_CFG_TXTDD
977 * DFE_FL_BB_CMD_CFG_RXTDD
978 * DFE_FL_BB_QUERY_TXTDD_CFG
979 * DFE_FL_BB_QUERY_RXTDD_CFG
980 */
981 typedef struct
982 {
983 /// enable
984 uint32_t enable;
985 /// data mode
986 DfeFl_BbTddDataMode dataMode;
987 /// carrier type
988 uint32_t carrierType;
989 /// delay from sync
990 uint32_t syncDly;
991 /// DL1 interval
992 uint32_t dl1Interval;
993 /// UL1 interval
994 uint32_t ul1Interval;
995 /// DL2 interval
996 uint32_t dl2Interval;
997 /// UL2 interval
998 uint32_t ul2Interval;
999 /// DL3 interval
1000 uint32_t dl3Interval;
1001 /// UL3 interval
1002 uint32_t ul3Interval;
1003 } DfeFl_BbTddConfig;
1006 /** @brief argument for runtime control,
1007 * DFE_FL_BB_CMD_CFG_TXPM
1008 * DFE_FL_BB_CMD_CFG_RXPM
1009 * DFE_FL_BB_QUERY_TXPM_CFG
1010 * DFE_FL_BB_QUERY_RXPM_CFG
1011 */
1012 typedef struct
1013 {
1014 /// power meter Id
1015 uint32_t pmId;
1016 /// enable power meter function
1017 DfeFl_BbPowMtrEnable enable;
1018 /// result output format
1019 DfeFl_BbPowMtrOutFormat outFormat;
1020 /// carrier type
1021 uint32_t countSource;
1022 /// power meter input source
1023 DfeFl_BbPowMtrInSource inSource;
1024 /// tdd mode
1025 DfeFl_BbPowMtrTddMode tddMode;
1026 /// delay from sync
1027 uint32_t syncDly;
1028 /// meter interval
1029 uint32_t interval;
1030 /// integration period
1031 uint32_t intgPd;
1032 /// count of measurements, i.e. count of intervals
1033 uint32_t pwrUpdate;
1034 /// for RXPM only, max dB value assuming full power of power interval
1035 uint32_t maxDb;
1036 } DfeFl_BbPowerMeterConfig;
1038 /** @brief argument for runtime control,
1039 * DFE_FL_BB_CMD_SET_TXPM_SSEL
1040 * DFE_FL_BB_CMD_SET_RXPM_SSEL
1041 * DFE_FL_BB_QUERY_TXPM_SSEL
1042 * DFE_FL_BB_QUERY_RXPM_SSEL
1043 */
1044 typedef struct
1045 {
1046 /// power meter Id
1047 uint32_t pmId;
1048 /// sync selection
1049 uint32_t ssel;
1050 } DfeFl_BbPowerMeterSsel;
1052 /** @brief argument for runtime control,
1053 * DFE_FL_BB_CMD_DIS_TXPM_UPDATE
1054 * DFE_FL_BB_CMD_DIS_RXPM_UPDATE
1055 * DFE_FL_BB_QUERY_DIS_TXPM_UPDATE
1056 * DFE_FL_BB_QUERY_DIS_RXPM_UPDATE
1057 */
1058 typedef struct
1059 {
1060 /// power meter Id
1061 uint32_t pmId;
1062 /// disable update
1063 uint32_t disableUpdate;
1064 } DfeFl_BbDisablePowMterUpdateConfig;
1067 /** @brief argument for runtime control,
1068 * DFE_FL_BB_QUERY_TXPM_INTR_STATUS
1069 * DFE_FL_BB_QUERY_RXPM_INTR_STATUS
1070 */
1071 typedef struct
1072 {
1073 /// power meter Id
1074 uint32_t pmId;
1075 /// complete status
1076 uint32_t status;
1077 } DfeFl_BbPowMtrIntrStatus;
1079 /** @brief argument for runtime control,
1080 * DFE_FL_BB_QUERY_TXPM_RESULT
1081 * DFE_FL_BB_QUERY_RXPM_RESULT
1082 */
1083 typedef struct
1084 {
1085 /// power meter Id
1086 uint32_t pmId;
1087 /// peak power main value
1088 uint32_t peakPower;
1089 /// peak power extended value
1090 uint32_t peakPower_extend;
1091 /// RMS power main value
1092 uint32_t rmsPower;
1093 /// RMS power extended value
1094 uint32_t rmsPower_extend;
1095 } DfeFl_BbPowMtrResult;
1097 /** @brief argument for runtime control,
1098 * DFE_FL_BB_CMD_CFG_ANTCAL_GLOBAL
1099 * DFE_FL_BB_QUERY_ANTCAL_GLOBAL_CFG
1100 */
1101 typedef struct
1102 {
1103 /// tx carrier type selection
1104 uint32_t txCarrierTypeSel;
1105 /// rx carrier type selection
1106 uint32_t rxCarrierTypeSel;
1107 /// tx sync selection
1108 uint32_t txSsel;
1109 /// rx sync selection
1110 uint32_t rxSsel;
1111 /// enable antenna calibartion
1112 uint32_t enable;
1113 /// number of samples to collect noise correlation values
1114 uint32_t interval;
1115 } DfeFl_BbAntCalGlobalConfig;
1117 /** @brief argument for runtime control,
1118 * DFE_FL_BB_CMD_CFG_ANTCAL
1119 * DFE_FL_BB_QUERY_ANTCAL_CFG
1120 */
1121 typedef struct
1122 {
1123 /// antenna calibration device
1124 uint32_t antcal;
1125 /// Antenna Calibration PN sequencer Initial value
1126 uint32_t pnInit;
1127 /// Antenna Calibration PN sequencer tap configuration
1128 uint32_t pnTapConfig;
1129 /// Antenna Calibration TX noise level
1130 uint32_t txNoise;
1131 /// Antenna Calibration RX correlation delay in samples
1132 uint32_t rxCorrDelay;
1133 /// Antenna Calibration RX oversampled. When 1 AxC is 2x oversampled
1134 uint32_t rxOverSample;
1135 } DfeFl_BbAntCalConfig;
1137 /** @brief argument for runtime control,
1138 * DFE_FL_BB_QUERY_GENERAL_INTR_STATUS
1139 */
1140 typedef struct
1141 {
1142 /// general interrupt
1143 uint32_t intr;
1144 /// result
1145 uint32_t result;
1146 } DfeFl_BbGeneralIntrQuery;
1148 /** @brief argument for runtime control,
1149 * DFE_FL_BB_CMD_ENB_GENERAL_INTRGRP
1150 * DFE_FL_BB_CMD_DIS_GENERAL_INTRGRP
1151 * DFE_FL_BB_CMD_CLR_GENERAL_INTRGRP_STATUS
1152 * DFE_FL_BB_CMD_SET_FORCE_GENERAL_INTRGRP
1153 * DFE_FL_BB_CMD_CLR_FORCE_GENERAL_INTRGRP
1154 * DFE_FL_BB_QUERY_GENERAL_INTRGRP_STATUS
1155 */
1156 typedef struct
1157 {
1158 /// BB general interrupt, TXPM_LDERR
1159 uint32_t txpmLoadErr;
1160 /// BB general interrupt, RXPM_LDERR
1161 uint32_t rxpmLoadErr;
1162 /// BB general interrupt, ANTCAL
1163 uint32_t antcal;
1164 /// BB general interrupt, RXNOTCH_DONE
1165 uint32_t rxNotchDone;
1166 /// BB general interrupt, RXNOTCH_ERR
1167 uint32_t rxNotchErr;
1169 /// BB general interrupt, BUFMEM_OUF (overflow/underflow)
1170 uint32_t bufErr[8];
1171 /// BB general interrupt, RXAID_SYNCERR
1172 uint32_t rxaidSyncErr;
1173 /// BB general interrupt, TXAID_UDF (under flow)
1174 uint32_t txaidUnderflow;
1175 /// BB general interrupt, TXAID_OVF (over flow)
1176 uint32_t txaidOverflow;
1177 /// BB general interrupt, JESDRX_SYNCERR
1178 uint32_t jesdrxSyncErr;
1179 /// BB general interrupt, JESDTX_UDF (under flow)
1180 uint32_t jesdtxUnderflow;
1181 /// BB general interrupt, JESDTX_OVF (over flow)
1182 uint32_t jesdtxOverflow;
1183 } DfeFl_BbGeneralIntrGroup;
1186 /** @brief argument for runtime control,
1187 * DFE_FL_BB_CMD_UPD_RXGAIN
1188 */
1189 typedef struct
1190 {
1191 /// number of AxCs whose gains need updating
1192 uint32_t numAxCs;
1193 /// axc gain update table
1194 struct
1195 {
1196 /// axc id#
1197 uint32_t axc;
1198 /// integer part gain word for the axc
1199 uint32_t gainInteger;
1200 /// fractional part gain word for the axc
1201 uint32_t gainFraction;
1202 } axcGain[DFE_FL_BB_ANTENNA_MAX_AXCS];
1203 } DfeFl_BbRxGainConfig;
1206 /** @brief argument for runtime control,
1207 * DFE_FL_BB_CMD_CFG_BEAGC_GLOBAL
1208 * DFE_FL_BB_QUERY_BEAGC_GLOBAL_CFG
1209 */
1210 typedef struct
1211 {
1212 /// When set beagc gain loop emphasizes saturation by incrementing sat counter by 1 when I or Q is sat
1213 uint32_t loop_config_sat;
1214 /// TDD timer configuration for beAGC. 0:tdd halt on DL, 1: tdd reset on DL
1215 uint32_t tdd_config;
1216 } DfeFl_BbBeagcGlobalConfig;
1218 /** @brief argument for runtime control,
1219 * DFE_FL_BB_CMD_CFG_BEAGC
1220 * DFE_FL_BB_QUERY_BEAGC_CFG
1221 */
1222 typedef struct
1223 {
1224 /// beagc device id
1225 uint32_t beagc;
1226 /// Select which buffer sync is the source of the interval counter for configuration 0 in closed loop mode.
1227 uint32_t intervalSource;
1228 /// master t3 interval
1229 uint32_t t3Interval;
1230 /// enable/disbale tdd mode
1231 uint32_t tdd_enable;
1232 /// beagc control loop configuration threshold value of AGC unsigned
1233 uint32_t thresh;
1234 /// beagc control loop configuration zero_mask masks lower 4 bits for zero count, a 0 will mask off zero calculation
1235 uint32_t zeroMask;
1236 /// beagc control loop configuration zero count threshold
1237 uint32_t zeroCountThresh;
1238 /// beagc control loop configuration saturation count threshold;
1239 uint32_t satCountThresh;
1240 /// beagc control loop configuration shift value for below threshold. 0=shift of 2 ... 15=shift of 17
1241 uint32_t dBelow;
1242 /// beagc control loop configuration shift value for above threshold. 0=shift of 2 ... 15=shift of 17
1243 uint32_t dAbove;
1244 /// beagc control loop configuration shift value for saturation case. 0=shift of 2 ... 15=shift of 17
1245 uint32_t dSat;
1246 /// beagc control loop configuration shift value for zero case. 0=shift of 2 ... 15=shift of 17
1247 uint32_t dZero;
1248 /// beagc control loop configuration maximum allowed gain adjustment value. Adjustment stops at g(k)=G + amax Amax format is signed (1,16,7)
1249 uint32_t amax;
1250 /// beagc control loop configuration minimum allowed gain adjustment value. Adjustment stops at g(k)=G + amin. Amin format is signed (1,16,7)
1251 uint32_t amin;
1252 } DfeFl_BbBeagcConfig;
1254 /** @brief argument for runtime control,
1255 * DFE_FL_BB_CMD_SET_BEAGC_SSEL
1256 * DFE_FL_BB_QUERY_BEAGC_SSEL
1257 */
1258 typedef struct
1259 {
1260 /// beagc device id
1261 uint32_t beagc;
1262 /// sync selection
1263 uint32_t ssel;
1264 } DfeFl_BbBeagcSsel;
1266 /** @brief argument for runtime control,
1267 * DFE_FL_BB_CMD_CFG_RXNOTCH_GLOBAL
1268 * DFE_FL_BB_QUERY_RXNOTCH_GLOBAL_CFG
1269 */
1270 typedef struct
1271 {
1272 /// carrier type
1273 uint32_t carrierType;
1274 /// tdd mode
1275 uint32_t tddMode;
1276 } DfeFl_BbRxNotchGlobalConfig;
1278 /** @brief argument for runtime control,
1279 * DFE_FL_BB_CMD_CFG_RXNOTCH
1280 * DFE_FL_BB_QUERY_RXNOTCH_CFG
1281 */
1282 typedef struct
1283 {
1284 /// axc Id
1285 uint32_t axc;
1286 /// filter mode
1287 uint32_t mode;
1288 /// filter1 tap select
1289 uint32_t filter1;
1290 /// filter2 tap select
1291 uint32_t filter2;
1292 /// filter3 tap select
1293 uint32_t filter3;
1294 /// filter4 tap select
1295 uint32_t filter4;
1296 /// Notch filter 0
1297 uint32_t tap0I;
1298 uint32_t tap0Q;
1299 uint32_t tap0Width;
1300 /// Notch filter 1
1301 uint32_t tap1I;
1302 uint32_t tap1Q;
1303 uint32_t tap1Width;
1304 } DfeFl_BbRxNotch;
1306 /** @brief AID DL translate
1307 */
1308 typedef struct
1309 {
1310 #ifdef _BIG_ENDIAN
1311 uint32_t rsvd0 : 22;
1312 uint32_t strobeType : 3;
1313 uint32_t axc : 7;
1314 #else
1315 uint32_t axc : 7;
1316 uint32_t strobeType : 3;
1317 uint32_t rsvd0 : 22;
1318 #endif
1319 } DfeFl_BbAidDlXlate;
1321 /** @brief AID UL translate
1322 */
1323 typedef struct
1324 {
1325 #ifdef _BIG_ENDIAN
1326 uint32_t rsvd1 : 20;
1327 uint32_t carrierType : 4;
1328 uint32_t rsvd0 : 2;
1329 uint32_t axc : 6;
1330 #else
1331 uint32_t axc : 6;
1332 uint32_t rsvd0 : 2;
1333 uint32_t carrierType : 4;
1334 uint32_t rsvd1 : 20;
1335 #endif
1336 } DfeFl_BbAidUlXlate;
1338 /** @brief TXIF slot map
1339 */
1340 typedef struct
1341 {
1342 #ifdef _BIG_ENDIAN
1343 uint32_t rsvd0 : 20;
1344 uint32_t carrierType : 4;
1345 uint32_t unassigned : 1;
1346 uint32_t axc : 7;
1347 #else
1348 uint32_t axc : 7;
1349 uint32_t unassigned : 1;
1350 uint32_t carrierType : 4;
1351 uint32_t rsvd0 : 20;
1352 #endif
1353 } DfeFl_BbTxifSlot;
1355 /** @brief RXIF slot map
1356 */
1357 typedef struct
1358 {
1359 #ifdef _BIG_ENDIAN
1360 uint32_t rsvd0 : 25;
1361 uint32_t unassigned : 1;
1362 uint32_t axc : 6;
1363 #else
1364 uint32_t axc : 6;
1365 uint32_t unassigned : 1;
1366 uint32_t rsvd0 : 25;
1367 #endif
1368 } DfeFl_BbRxifSlot;
1370 /** @brief overlay register pointer to BB instance
1371 */
1372 typedef CSL_DFE_BB_REGS *DfeFl_BbRegsOvly;
1374 /** @brief a BaseBand (BB) Object of Digital radio Front End (DFE) */
1375 typedef struct
1376 {
1377 /// handle to DFE global
1378 DfeFl_Handle hDfe;
1380 /// pointer to register base address of a BB instance
1381 DfeFl_BbRegsOvly regs;
1383 /// This is the instance of BB being referred to by this object
1384 DfeFl_InstNum perNum;
1386 } DfeFl_BbObj;
1388 /** @brief handle pointer to BB object
1389 */
1390 typedef DfeFl_BbObj *DfeFl_BbHandle;
1392 /**
1393 * @}
1394 */
1396 /**
1397 * @addtogroup DFE_FL_BB_FUNCTION
1398 * @{
1399 */
1401 DfeFl_BbHandle dfeFl_BbOpen
1402 (
1403 DfeFl_Handle hDfe,
1404 DfeFl_BbObj *pDfeBbObj,
1405 DfeFl_InstNum bbNum,
1406 DfeFl_Status *pStatus
1407 );
1409 DfeFl_Status dfeFl_BbClose(DfeFl_BbHandle hDfeBb);
1411 DfeFl_Status dfeFl_BbHwControl
1412 (
1413 DfeFl_BbHandle hDfeBb,
1414 DfeFl_BbHwControlCmd ctrlCmd,
1415 void *arg
1416 );
1418 DfeFl_Status dfeFl_BbGetHwStatus
1419 (
1420 DfeFl_BbHandle hDfeBb,
1421 DfeFl_BbHwStatusQuery queryId,
1422 void *arg
1423 );
1425 /**
1426 * @}
1427 */
1429 #ifdef __cplusplus
1430 }
1431 #endif
1433 #endif /* _DFE_FL_BB_H_ */