1 /********************************************************************
2 * Copyright (C) 2012-2013 Texas Instruments Incorporated.
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32 */
34 /**
35 * @defgroup DFE_FL_DPD_API DPD
36 * @ingroup DFE_FL_API
37 */
39 /** @file dfe_fl_dpd.h
40 *
41 * @path $(CSLPATH)\inc
42 *
43 * @brief Header file for functional layer of DFE_DPD CSL
44 *
45 * Description
46 * - Function level symbolic constants, enumerations, structure definitions
47 * and function prototype declarations
48 *
49 */
50 /* =============================================================================
51 * Revision History
52 * ===============
53 *
54 *
55 * =============================================================================
56 */
58 /**
59 * @defgroup DFE_FL_DPD_DATASTRUCT DFE Dpd Data Structures
60 * @ingroup DFE_FL_DPD_API
61 */
63 /**
64 * @defgroup DFE_FL_DPD_ENUM DFE Dpd Enumverated Data Types
65 * @ingroup DFE_FL_DPD_API
66 */
68 /**
69 * @defgroup DFE_FL_DPD_FUNCTION DFE Dpd Functions
70 * @ingroup DFE_FL_DPD_API
71 */
73 #ifndef _DFE_FL_DPD_H_
74 #define _DFE_FL_DPD_H_
76 #ifdef __cplusplus
77 extern "C" {
78 #endif
80 //#include <ti/csl/csl.h>
81 #include <ti/csl/cslr_dfe_dpd.h>
82 #include <ti/drv/dfe/dfe_fl.h>
83 #include <ti/drv/dfe/dfe_fl_dpdParams.h>
85 /**
86 * @addtogroup DFE_FL_DPD_ENUM
87 * @{
88 */
90 /** @brief control commands
91 */
92 typedef enum
93 {
94 /// configure DPD inits, including ssel, clk_gate, init_state and clear_data
95 DFE_FL_DPD_CMD_CFG_INITS = 0,
96 /// subchip_mode
97 DFE_FL_DPD_CMD_UPD_SUBCHIP_MODE,
98 /// subsample
99 DFE_FL_DPD_CMD_UPD_SUBSAMPLE,
100 /// mux square root
101 DFE_FL_DPD_CMD_UPD_MUX_SQRT,
102 /// mux complex signal
103 DFE_FL_DPD_CMD_UPD_MUX_COMPLX,
104 /// mux real magnitude
105 DFE_FL_DPD_CMD_UPD_MUX_REAL_MAG,
106 /// mux dpd output
107 DFE_FL_DPD_CMD_UPD_MUX_OUTPUT,
108 /// dpdadapt update mode
109 DFE_FL_DPD_CMD_UPD_DPDADAPT_MODE,
110 /// dpdadapt mux fsync
111 DFE_FL_DPD_CMD_UPD_DPDADAPT_FSYNC,
112 /// dpdadapt mux csync
113 DFE_FL_DPD_CMD_UPD_DPDADAPT_CSYNC,
114 /// config f_sync selection for each block
115 DFE_FL_DPD_CMD_UPD_BLK_F_SSEL,
116 /// config f_sync selection for all blocks
117 DFE_FL_DPD_CMD_UPD_SUBCHIP_F_SSEL,
118 /// config c_sync selection for each block
119 DFE_FL_DPD_CMD_UPD_BLK_C_SSEL,
120 /// config c_sync selection for all blocks
121 DFE_FL_DPD_CMD_UPD_SUBCHIP_C_SSEL,
122 /// diable dpd
123 DFE_FL_DPD_CMD_SET_DPD_DISABLE,
124 /// config sync selection for syncB
125 DFE_FL_DPD_CMD_UPD_SYNCB_SSEL,
127 /// update dpd input scale
128 DFE_FL_DPD_CMD_UPD_DPDINPUT_SCALE,
130 /// test signal generation config
131 DFE_FL_DPD_CMD_CFG_TESTGEN,
132 /// test signal generation sync selection
133 DFE_FL_DPD_CMD_SET_TESTGEN_SSEL,
134 /// chksum
135 DFE_FL_DPD_CMD_CFG_CHKSUM,
136 /// chksum sync selection
137 DFE_FL_DPD_CMD_SET_CHKSUM_SSEL,
139 /// clk gate delay
140 DFE_FL_DPD_CMD_CLK_GATE_DELAY,
141 /// test bus control
142 DFE_FL_DPD_CMD_TEST_BUS_CTRL,
144 /// update mux_blk in each dpd block
145 DFE_FL_DPD_CMD_UPD_MUX_BLK,
146 /// update mux_blk_row in each dpd row
147 DFE_FL_DPD_CMD_UPD_MUX_BLK_ROW,
149 /// update lut init for each row
150 DFE_FL_DPD_CMD_UPD_ROW_LUT_INIT,
151 /// update lut init for all rows of one block
152 DFE_FL_DPD_CMD_UPD_BLK_LUT_INIT,
153 /// update lut toggle for each row
154 DFE_FL_DPD_CMD_UPD_ROW_LUT_TOGGLE,
155 /// update lut toggle for all rows of one block
156 DFE_FL_DPD_CMD_UPD_BLK_LUT_TOGGLE,
157 /// config sync selection for each cell
158 DFE_FL_DPD_CMD_UPD_CELL_SYNC,
159 /// config sync selection for all cells of one row
160 DFE_FL_DPD_CMD_UPD_ROW_SYNC,
161 /// config sync selection for all cells of one block
162 DFE_FL_DPD_CMD_UPD_BLK_SYNC,
164 /// update lut value for each entry
165 DFE_FL_DPD_CMD_UPD_ENTRY_LUT,
166 /// update lut value for each cell
167 DFE_FL_DPD_CMD_UPD_CELL_LUT,
168 /// update lut value for each row
169 DFE_FL_DPD_CMD_UPD_ROW_LUT,
170 /// update lut value for each block
171 DFE_FL_DPD_CMD_UPD_BLK_LUT,
173 DFE_FL_DPD_CMD_MAX_VALUE
174 } DfeFl_DpdHwControlCmd;
176 /** @brief query commands
177 */
178 typedef enum
179 {
180 /// subchip_mode
181 DFE_FL_DPD_QUERY_SUBCHIP_MODE = 0,
182 /// subsample
183 DFE_FL_DPD_QUERY_SUBSAMPLE,
184 /// mux square root
185 DFE_FL_DPD_QUERY_MUX_SQRT,
186 /// mux complex signal
187 DFE_FL_DPD_QUERY_MUX_COMPLX,
188 /// mux real magnitude
189 DFE_FL_DPD_QUERY_MUX_REAL_MAG,
190 /// mux dpd output
191 DFE_FL_DPD_QUERY_MUX_OUTPUT,
192 /// dpdadapt update mode
193 DFE_FL_DPD_QUERY_DPDADAPT_MODE,
194 /// dpdadapt mux fsync
195 DFE_FL_DPD_QUERY_DPDADAPT_FSYNC,
196 /// dpdadapt mux csync
197 DFE_FL_DPD_QUERY_DPDADAPT_CSYNC,
198 /// f_sync selection for each block
199 DFE_FL_DPD_QUERY_BLK_F_SSEL,
200 /// f_sync selection for each subchip
201 DFE_FL_DPD_QUERY_SUBCHIP_F_SSEL,
202 /// c_sync selection for each block
203 DFE_FL_DPD_QUERY_BLK_C_SSEL,
204 /// c_sync selection for each subchip
205 DFE_FL_DPD_QUERY_SUBCHIP_C_SSEL,
206 /// diable dpd
207 DFE_FL_DPD_QUERY_DPD_DISABLE,
208 /// sync selection for syncB
209 DFE_FL_DPD_QUERY_SYNCB_SSEL,
210 /// inits ssel
211 DFE_FL_DPD_QUERY_INITS_SSEL,
212 /// init clk gate
213 DFE_FL_DPD_QUERY_INIT_CLK_GATE,
214 /// init state
215 DFE_FL_DPD_QUERY_INIT_STATE,
216 /// clear data
217 DFE_FL_DPD_QUERY_CLEAR_DATA,
219 /// dpd input scale
220 DFE_FL_DPD_QUERY_DPDINPUT_SCALE,
222 /// test signal generation config
223 DFE_FL_DPD_QUERY_TESTGEN_CFG,
224 /// test signal generation sync selection
225 DFE_FL_DPD_QUERY_TESTGEN_SSEL,
226 /// chksum
227 DFE_FL_DPD_QUERY_CHKSUM_RESULT,
229 /// clk gate delay
230 DFE_FL_DPD_QUERY_CLK_GATE_DELAY,
231 /// test bus control
232 DFE_FL_DPD_QUERY_TEST_BUS_CTRL,
234 /// mux_blk in each dpd block
235 DFE_FL_DPD_QUERY_MUX_BLK,
236 /// mux_blk_row in each dpd row
237 DFE_FL_DPD_QUERY_MUX_BLK_ROW,
239 /// lut init for each row
240 DFE_FL_DPD_QUERY_ROW_LUT_INIT,
241 /// lut init for each block
242 DFE_FL_DPD_QUERY_BLK_LUT_INIT,
243 /// lut toggle for each row
244 DFE_FL_DPD_QUERY_ROW_LUT_TOGGLE,
245 ///lut toggle for each block
246 DFE_FL_DPD_QUERY_BLK_LUT_TOGGLE,
247 /// sync selection for each cell
248 DFE_FL_DPD_QUERY_CELL_SYNC,
249 /// sync selection for each row
250 DFE_FL_DPD_QUERY_ROW_SYNC,
251 /// sync selection for each blk,
252 DFE_FL_DPD_QUERY_BLK_SYNC,
253 /// current lut mpu for each cell
254 DFE_FL_DPD_QUERY_CELL_CURRENT_LUT_MPU,
255 /// current lut mpu for each row
256 DFE_FL_DPD_QUERY_ROW_CURRENT_LUT_MPU,
257 /// current lut mpu for each blk
258 DFE_FL_DPD_QUERY_BLK_CURRENT_LUT_MPU,
260 /// lut value for each entry
261 DFE_FL_DPD_QUERY_ENTRY_LUT,
262 /// lut value for each cell
263 DFE_FL_DPD_QUERY_CELL_LUT,
264 /// lut value for each row
265 DFE_FL_DPD_QUERY_ROW_LUT,
266 /// lut value for each block
267 DFE_FL_DPD_QUERY_BLK_LUT,
269 DFE_FL_DPD_QUERY_MAX_VALUE
270 } DfeFl_DpdHwStatusQuery;
272 /** @brief DPD Test Signal Generation Device
273 */
274 typedef enum
275 {
276 /// TESTGEN0 for DPD
277 DFE_FL_DPD_TESTGEN_0 = 0,
278 /// TESTGEN1 for DPD
279 DFE_FL_DPD_TESTGEN_1,
280 /// TESTGEN2 for DPD
281 DFE_FL_DPD_TESTGEN_2,
282 /// TESTGEN3 for DPD
283 DFE_FL_DPD_TESTGEN_3,
284 /// TESTGEN4 for DPD
285 DFE_FL_DPD_TESTGEN_4,
286 /// TESTGEN5 for DPD
287 DFE_FL_DPD_TESTGEN_5,
288 /// TESTGEN6 for DPD
289 DFE_FL_DPD_TESTGEN_6,
290 /// TESTGEN7 for DPD
291 DFE_FL_DPD_TESTGEN_7
292 } DfeFl_DpdTestGenDev;
294 /** @brief DPD Test Signal Generation ramp mode
295 */
296 typedef enum
297 {
298 /// LFSR
299 DFE_FL_DPD_TESTGEN_RAMP_MODE_LFSR = 0,
300 /// RAMP
301 DFE_FL_DPD_TESTGEN_RAMP_MODE_RAMP = 1
302 } DfeFl_DpdTestGenRampMode;
304 /** @brief DPD checksum return mode */
305 typedef enum
306 {
307 /// return checksum
308 DFE_FL_DPD_CHKSUM_MODE_RETURN_CHKSUM = 0,
309 /// return latency
310 DFE_FL_DPD_CHKSUM_MODE_RETURN_LATENCY
311 } DfeFl_DpdChksumMode;
313 /** @brief DPD Block
314 */
315 typedef enum
316 {
317 /// dpd block 0
318 DFE_FL_DPD_B0 = 0,
319 /// dpd block 1
320 DFE_FL_DPD_B1,
321 /// dpd block 2
322 DFE_FL_DPD_B2,
323 /// dpd block 3
324 DFE_FL_DPD_B3
325 }DfeFl_DPDBlk;
327 /** @brief DPD Row
328 */
329 typedef enum
330 {
331 /// dpd row 0
332 DFE_FL_DPD_R0 = 0,
333 /// dpd row 1
334 DFE_FL_DPD_R1,
335 /// dpd row 2
336 DFE_FL_DPD_R2,
337 /// dpd row 3
338 DFE_FL_DPD_R3,
339 /// dpd row 4
340 DFE_FL_DPD_R4,
341 /// dpd row 5
342 DFE_FL_DPD_R5
343 }DfeFl_DPDRow;
345 /** @brief DPD Cell
346 */
347 typedef enum
348 {
349 /// dpd cell 0
350 DFE_FL_DPD_C0 = 0,
351 /// dpd cell 1
352 DFE_FL_DPD_C1,
353 /// dpd cell 2
354 DFE_FL_DPD_C2
355 }DfeFl_DPDCell;
357 /** @brief mux sqrt type
358 */
359 typedef enum
360 {
361 /// dpd mux sqrt r00
362 DFE_FL_DPD_MUX_SQRT_R00 = 0,
363 /// dpd mux sqrt r01
364 DFE_FL_DPD_MUX_SQRT_R01,
365 /// dpd mux sqrt r1
366 DFE_FL_DPD_MUX_SQRT_R1,
367 /// dpd mux sqrt r2
368 DFE_FL_DPD_MUX_SQRT_R2,
369 /// dpd mux sqrt r31
370 DFE_FL_DPD_MUX_SQRT_R31,
371 /// dpd mux sqrt r32
372 DFE_FL_DPD_MUX_SQRT_R32,
373 /// dpd mux sqrt r33
374 DFE_FL_DPD_MUX_SQRT_R33,
375 /// dpd mux sqrt magx2
376 DFE_FL_DPD_MUX_SQRT_MAGX2,
377 /// dpd mux sqrt magx3
378 DFE_FL_DPD_MUX_SQRT_MAGX3
379 } DfeFl_DpdMuxSqrtType;
381 /** @brief DPD EVEN Or ODD
382 */
383 typedef enum
384 {
385 /// dpd even
386 DFE_FL_DPD_EVEN = 0,
387 /// dpd odd
388 DFE_FL_DPD_ODD
389 } DfeFl_DPDEvenOdd;
391 /**
392 * @}
393 */
395 /**
396 * @addtogroup DFE_FL_DPD_DATASTRUCT
397 * @{
398 */
400 /** @brief argument for runtime control,
401 * DFE_FL_DPD_CMD_CFG_TESTGEN
402 * DFE_FL_DPD_QUERY_TESTGEN_CFG
403 */
404 typedef struct
405 {
406 /// test gen device
407 DfeFl_DpdTestGenDev tgDev;
408 /// enable data generation
409 uint32_t genData;
410 /// enbale frame generation
411 uint32_t genFrame;
412 /// ramp (1), or LFSR (0)
413 DfeFl_DpdTestGenRampMode rampMode;
414 /// seed
415 uint32_t seed;
416 /// number of clocks per frame minus 1
417 uint32_t frameLenM1;
418 /// ramp starting value
419 uint32_t rampStart;
420 /// ramp stop value
421 uint32_t rampStop;
422 /// ramp slop value
423 uint32_t slope;
424 /// 0 = generate data forever, n = generate data for n clock cycles
425 uint32_t genTimer;
426 /// number of data bits inverted (read-only)
427 uint32_t numDataBits;
428 } DfeFl_DpdTestGenConfig;
430 /** @brief argument for runtime control,
431 * DFE_FL_DPD_CMD_SET_TESTGEN_SSEL
432 * DFE_FL_DPD_QUERY_TESTGEN_SSEL
433 */
434 typedef struct
435 {
436 /// test gen device
437 DfeFl_DpdTestGenDev tgDev;
438 /// sync select
439 uint32_t ssel;
440 } DfeFl_DpdTestGenSsel;
442 /** @brief argument for runtime control,
443 * DFE_FL_DPD_CMD_CFG_CHKSUM
444 */
445 typedef struct
446 {
447 /// checksum mode
448 uint32_t chksumMode;
449 /// latency mode config
450 struct
451 {
452 /// stable length
453 uint32_t stableLen;
454 /// signal length
455 uint32_t signalLen;
456 /// channel select
457 uint32_t chanSel;
458 } latencyMode;
459 } DfeFl_DpdChksumConfig;
461 /** @brief argument for runtime control,
462 * DFE_FL_DPD_CMD_UPD_MUX_SQRT
463 * DFE_FL_DPD_QUERY_MUX_SQRT
464 */
465 typedef struct
466 {
467 /// dpd mux sqrt type
468 DfeFl_DpdMuxSqrtType Mux;
469 /// data
470 uint32_t data;
471 } DfeFl_DpdMuxSqrt;
473 /** @brief argument for runtime control,
474 * DFE_FL_DPD_CMD_UPD_MUX_COMPLX
475 * DFE_FL_DPD_QUERY_MUX_COMPLX
476 * DFE_FL_DPD_CMD_UPD_MUX_REAL_MAG
477 * DFE_FL_DPD_QUERY_MUX_REAL_MAG
478 */
479 typedef struct
480 {
481 /// dpd block id
482 DfeFl_DPDBlk idxBlk;
483 /// dpd even or odd
484 DfeFl_DPDEvenOdd evenOrOdd;
485 /// data
486 uint32_t data;
487 } DfeFl_DpdMuxSignal;
489 /** @brief argument for runtime control,
490 * DFE_FL_DPD_CMD_UPD_MUX_OUTPUT
491 * DFE_FL_DPD_QUERY_MUX_OUTPUT
492 * DFE_FL_DPD_CMD_UPD_DPDADAPT_MODE
493 * DFE_FL_DPD_QUERY_DPDADAPT_MODE
494 * DFE_FL_DPD_CMD_UPD_DPDADAPT_FSYNC
495 * DFE_FL_DPD_QUERY_DPDADAPT_FSYNC
496 * DFE_FL_DPD_CMD_UPD_DPDADAPT_CSYNC
497 * DFE_FL_DPD_QUERY_DPDADAPT_CSYNC
498 */
499 typedef struct
500 {
501 /// dpd block id
502 DfeFl_DPDBlk idxBlk;
503 /// data
504 uint32_t data;
505 } DfeFl_DpdBlkCtrl;
507 /** @brief argument for runtime control
508 * DFE_FL_DPD_CMD_UPD_BLK_F_SSEL
509 * DFE_FL_DPD_CMD_UPD_BLK_C_SSEL
510 * DFE_FL_DPD_QUERY_BLK_F_SSEL
511 * DFE_FL_DPD_QUERY_BLK_C_SSEL
512 */
513 typedef struct
514 {
515 /// dpd block id
516 uint32_t idxBlk;
517 /// ssel value
518 uint32_t Ssel;
519 } DfeFl_DpdBlkSsel;
521 /** @brief argument for runtime control
522 * DFE_FL_DPD_CMD_UPD_SUBCHIP_F_SSEL
523 * DFE_FL_DPD_CMD_UPD_SUBCHIP_C_SSEL
524 * DFE_FL_DPD_QUERY_SUBCHIP_F_SSEL
525 * DFE_FL_DPD_QUERY_SUBCHIP_C_SSEL
526 */
527 typedef struct
528 {
529 /// number of blocks
530 uint32_t numBlks;
531 /// ssel update table
532 DfeFl_DpdBlkSsel BlkSsel[DFE_FL_DPD_NBLK];
533 } DfeFl_DpdSubchipSsel;
535 /** @brief argument for runtime control
536 * DFE_FL_DPD_CMD_UPD_MUX_BLK
537 * DFE_FL_DPD_QUERY_MUX_BLK
538 */
539 typedef struct
540 {
541 /// dpd block id
542 DfeFl_DPDBlk idxBlk;
543 /// mux 2x
544 uint32_t mux_2x;
545 /// mux dg 2x
546 uint32_t mux_dg_2x;
547 /// mux dga even
548 uint32_t mux_dga_e;
549 /// mux dga odd
550 uint32_t mux_dga_o;
551 /// mux dg even
552 uint32_t mux_dg_e;
553 /// mux dg odd
554 uint32_t mux_dg_o;
555 /// mux dgaxo even
556 uint32_t mux_dgaxo_e;
557 /// mux dgaxo odd
558 uint32_t mux_dgaxo_o;
559 /// mux dgxo even
560 uint32_t mux_dgxo_e;
561 /// mux dgxo odd
562 uint32_t mux_dgxo_o;
563 } DfeFl_DpdMuxBlk;
565 /** @brief argument for runtime control
566 * DFE_FL_DPD_CMD_UPD_MUX_BLK_ROW
567 * DFE_FL_DPD_QUERY_MUX_BLK_ROW
568 */
569 typedef struct
570 {
571 /// dpd block id
572 DfeFl_DPDBlk idxBlk;
573 /// dpd row id
574 DfeFl_DPDRow idxRow;
575 /// mux dgaxi
576 uint32_t mux_dgaxi;
577 /// mux dgxi
578 uint32_t mux_dgxi;
579 /// mux real
580 uint32_t mux_real;
581 /// mux complex
582 uint32_t mux_complex;
583 /// mux daxi
584 uint32_t mux_daxi;
585 /// mux dxi
586 uint32_t mux_dxi;
587 } DfeFl_DpdMuxBlkRow;
589 /** @brief argument for runtime control
590 * DFE_FL_DPD_CMD_UPD_ROW_LUT_INIT
591 * DFE_FL_DPD_CMD_UPD_ROW_LUT_TOGGLE
592 * DFE_FL_DPD_QUERY_ROW_LUT_INIT
593 * DFE_FL_DPD_QUERY_ROW_LUT_TOGGLE
594 */
595 typedef struct
596 {
597 /// dpd block id
598 uint32_t idxBlk;
599 /// dpd row id
600 uint32_t idxRow;
601 /// value
602 uint32_t data;
603 } DfeFl_DpdRowLutInit, DfeFl_DpdRowLutToggle;
605 typedef struct
606 {
607 /// dpd row id
608 uint32_t idxRow;
609 /// value
610 uint32_t data;
611 } RowLutInit;
613 /** @brief argument for runtime control
614 * DFE_FL_DPD_CMD_UPD_BLK_LUT_INIT
615 * DFE_FL_DPD_QUERY_BLK_LUT_INIT
616 */
617 typedef struct
618 {
619 /// dpd block id
620 uint32_t idxBlk;
621 /// number of rows
622 uint32_t numRows;
623 /// values
624 RowLutInit LutInit[DFE_FL_DPD_NROW];
625 } DfeFl_DpdBlkLutInit;
627 /** @brief argument for runtime control
628 * DFE_FL_DPD_CMD_UPD_BLK_LUT_TOGGLE
629 * DFE_FL_DPD_QUERY_BLK_LUT_TOGGLE
630 */
631 typedef struct
632 {
633 /// dpd block id
634 uint32_t idxBlk;
635 /// number of rows
636 uint32_t numRows;
637 /// values
638 RowLutInit LutToggle[DFE_FL_DPD_NROW];
639 } DfeFl_DpdBlkLutToggle;
641 /** @brief argument for runtime control
642 * DFE_FL_DPD_CMD_UPD_CELL_SYNC
643 * DFE_FL_DPD_QUERY_CELL_SYNC
644 */
645 typedef struct
646 {
647 /// dpd block id
648 uint32_t idxBlk;
649 /// dpd row id
650 uint32_t idxRow;
651 /// dpd cell id
652 uint32_t idxCell;
653 /// values
654 uint32_t Ssel;
655 } DfeFl_DpdCellSync;
657 typedef struct
658 {
659 /// dpd cell id
660 uint32_t idxCell;
661 /// value
662 uint32_t data;
663 } RowData;
665 /** @brief argument for runtime control
666 * DFE_FL_DPD_CMD_UPD_ROW_SYNC
667 * DFE_FL_DPD_QUERY_ROW_SYNC
668 */
669 typedef struct
670 {
671 /// dpd block id
672 uint32_t idxBlk;
673 /// dpd row id#
674 uint32_t idxRow;
675 /// number of cells
676 uint32_t numCells;
677 /// values
678 RowData CellSync[DFE_FL_DPD_NCEL];
679 } DfeFl_DpdRowSync;
681 typedef struct
682 {
683 /// dpd row id
684 uint32_t idxRow;
685 /// dpd cell id
686 uint32_t idxCell;
687 /// value
688 uint32_t data;
689 } BlkData;
691 /** @brief argument for runtime control
692 * DFE_FL_DPD_CMD_UPD_BLK_SYNC
693 * DFE_FL_DPD_QUERY_BLK_SYNC
694 */
695 typedef struct
696 {
697 /// dpd block id
698 uint32_t idxBlk;
699 /// number of rows
700 uint32_t numRows;
701 /// values
702 BlkData CellSync[DFE_FL_DPD_NROW][DFE_FL_DPD_NCEL];
703 } DfeFl_DpdBlkSync;
705 /** @brief argument for runtime control
706 * DFE_FL_DPD_QUERY_CELL_CURRENT_LUT_MPU
707 */
708 typedef struct
709 {
710 /// dpd block id
711 uint32_t idxBlk;
712 /// dpd row id
713 uint32_t idxRow;
714 /// dpd cell id
715 uint32_t idxCell;
716 /// values
717 uint32_t CurLutMpu;
718 } DfeFl_DpdCellCurLutMpu;
720 /** @brief argument for runtime control
721 * DFE_FL_DPD_QUERY_ROW_CURRENT_LUT_MPU
722 */
723 typedef struct
724 {
725 /// dpd block id
726 uint32_t idxBlk;
727 /// dpd row id
728 uint32_t idxRow;
729 /// number of cells
730 uint32_t numCells;
731 /// values
732 RowData CurLutMpu[DFE_FL_DPD_NCEL];
733 } DfeFl_DpdRowCurLutMpu;
735 /** @brief argument for runtime control
736 * DFE_FL_DPD_QUERY_BLK_CURRENT_LUT_MPU
737 */
738 typedef struct
739 {
740 /// dpd block id
741 uint32_t idxBlk;
742 /// number of rows
743 uint32_t numRows;
744 /// values
745 BlkData CurLutMpu[DFE_FL_DPD_NROW][DFE_FL_DPD_NCEL];
746 } DfeFl_DpdBlkCurLutMpu;
748 /** @brief dpd complex int
749 */
750 typedef struct
751 {
752 /// real data
753 uint16_t real;
754 /// image data
755 uint16_t imag;
757 } DfeFl_DpdComplexInt;
759 /** @brief argument for runtime control
760 * DFE_FL_DPD_CMD_UPD_ENTRY_LUT
761 * DFE_FL_DPD_QUERY_ENTRY_LUT
762 */
763 typedef struct
764 {
765 /// dpd block id
766 uint32_t idxBlk;
767 /// dpd row id
768 uint32_t idxRow;
769 /// dpd cell id
770 uint32_t idxCell;
771 /// dpd lut entry id
772 uint32_t idxEntry;
773 /// lutGain
774 DfeFl_DpdComplexInt lutGain;
775 /// lutSlope
776 DfeFl_DpdComplexInt lutSlope;
777 } DfeFl_DpdEntryLUT;
779 typedef struct
780 {
781 /// dpd lut entry id
782 uint32_t idxEntry;
783 /// lutGain
784 DfeFl_DpdComplexInt lutGain;
785 /// lutSlope
786 DfeFl_DpdComplexInt lutSlope;
787 } EntryLUTData;
789 /** @brief argument for runtime control
790 * DFE_FL_DPD_CMD_UPD_CELL_LUT
791 * DFE_FL_DPD_QUERY_CELL_LUT
792 */
793 typedef struct
794 {
795 /// dpd block id
796 uint32_t idxBlk;
797 /// dpd row id
798 uint32_t idxRow;
799 /// dpd cell id
800 uint32_t idxCell;
801 /// number of entries
802 uint32_t numEntries;
803 /// values
804 EntryLUTData LUTval[DFE_FL_DPD_MAX_LUT_SIZE];
805 } DfeFl_DpdCellLUT;
807 typedef struct
808 {
809 /// dpd cell id
810 uint32_t idxCell;
811 /// dpd entry id
812 uint32_t idxEntry;
813 /// lutGain
814 DfeFl_DpdComplexInt lutGain;
815 /// lutSlope
816 DfeFl_DpdComplexInt lutSlope;
817 } CellLUTData;
819 /** @brief argument for runtime control
820 * DFE_FL_DPD_CMD_UPD_ROW_LUT
821 * DFE_FL_DPD_QUERY_ROW_LUT
822 */
823 typedef struct
824 {
825 /// dpd block id
826 uint32_t idxBlk;
827 /// dpd row id
828 uint32_t idxRow;
829 /// number of cells
830 uint32_t numCells;
831 /// values
832 CellLUTData LUTval[DFE_FL_DPD_NCEL][DFE_FL_DPD_MAX_LUT_SIZE];
833 } DfeFl_DpdRowLUT;
835 typedef struct
836 {
837 /// dpd row id
838 uint32_t idxRow;
839 /// dpd cell id
840 uint32_t idxCell;
841 /// dpd entry id
842 uint32_t idxEntry;
843 /// lutGain
844 DfeFl_DpdComplexInt lutGain;
845 /// lutSlope
846 DfeFl_DpdComplexInt lutSlope;
847 } RowLUTData;
849 /** @brief argument for runtime control
850 * DFE_FL_DPD_CMD_UPD_BLK_LUT
851 * DFE_FL_DPD_QUERY_BLK_LUT
852 */
853 typedef struct
854 {
855 /// dpd block id
856 uint32_t idxBlk;
857 /// number of rows
858 uint32_t numRows;
859 /// values
860 RowLUTData LUTval[DFE_FL_DPD_NROW][DFE_FL_DPD_NCEL][DFE_FL_DPD_MAX_LUT_SIZE];
861 } DfeFl_DpdBlkLUT;
864 /** @brief overlay register pointer to DPD instance
865 */
866 typedef CSL_DFE_DPD_REGS *DfeFl_DpdRegsOvly;
868 /** @brief a DPD Object of Digital radio Front End (DFE) */
869 typedef struct
870 {
871 /// handle to DFE global
872 DfeFl_Handle hDfe;
874 /// pointer to register base address of a DPD instance
875 DfeFl_DpdRegsOvly regs;
877 /// This is the instance of DPD being referred to by this object
878 DfeFl_InstNum perNum;
880 } DfeFl_DpdObj;
882 /** @brief handle pointer to DPD object
883 */
884 typedef DfeFl_DpdObj *DfeFl_DpdHandle;
886 /**
887 * @}
888 */
890 /**
891 * @addtogroup DFE_FL_DPD_FUNCTION
892 * @{
893 */
895 //DfeFl_Status dfeFl_DpdInit();
897 DfeFl_DpdHandle dfeFl_DpdOpen
898 (
899 DfeFl_Handle hDfe,
900 DfeFl_DpdObj *pDfeDpdObj,
901 DfeFl_InstNum perNum,
902 DfeFl_Status *pStatus
903 );
905 DfeFl_Status dfeFl_DpdClose(DfeFl_DpdHandle hDfeDpd);
907 DfeFl_Status dfeFl_DpdHwControl
908 (
909 DfeFl_DpdHandle hDfeDpd,
910 DfeFl_DpdHwControlCmd ctrlCmd,
911 void *arg
912 );
914 DfeFl_Status dfeFl_DpdGetHwStatus
915 (
916 DfeFl_DpdHandle hDfeDpd,
917 DfeFl_DpdHwStatusQuery queryId,
918 void *arg
919 );
921 /**
922 * @}
923 */
925 #ifdef __cplusplus
926 }
927 #endif
929 #endif /* _DFE_FL_DPD_H_ */