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raw | patch | inline | side by side (parent: c18f752)
author | Laurent Gauthier <l-gauthier@ti.com> | |
Fri, 23 Jan 2015 14:14:55 +0000 (15:14 +0100) | ||
committer | Laurent Gauthier <l-gauthier@ti.com> | |
Fri, 23 Jan 2015 14:14:55 +0000 (15:14 +0100) |
dfe_drv.h | patch | blob | history | |
src/dfelld/DFE_cfr.c | patch | blob | history | |
src/dfelld/DFE_jesd.c | patch | blob | history | |
src/dfelld/DFE_rx.c | patch | blob | history |
diff --git a/dfe_drv.h b/dfe_drv.h
index 4bdbf9309b56bb5315fdab27d080393369c945fe..f478ac6ecde5e2763cdba911729d698b63014ec1 100644 (file)
--- a/dfe_drv.h
+++ b/dfe_drv.h
* To properly configure DFE, the following sequence must be followed:
*
*
- * | Step | Description | DFE LLD API |
+ * | Step | Description | DFE LLD API |
* | ---- | -------------------------------------------------- | ---------------- |
- * | 1 | Program DFE PLL to correct operation rate | |
- * | 2 | Power up IQN2 and DFE power domains | |
- * | 3 | Program SERDES to corresponding rate | |
- * | 4 | Open DFE LLD | Dfe_open() |
- * | 5 | Load DFE target configuration | Dfe_loadTgtCfg() |
- * | | Soft Reset DFE peripheral | Dfe_softReset() |
- * | | Check and wait SERDES PLL_OK | |
- * | 6 | IQN2 configuration and enable | |
- * | 7 | Do DFE initialization sequence for transmit path | Dfe_initTgtTx() |
- * | 8 | Program analogue front-end which connects with DFE | |
- * | | Check and wait SERDES OK and !LOSS | |
- * | | Do DFE initialization sequence for receive path | Dfe_initTgtRx() |
- * | 9 | QMSS, CPPI configuration | |
+ * | 1 | Program DFE PLL to correct operation rate | |
+ * | 2 | Power up IQN2 and DFE power domains | |
+ * | 3 | Program SERDES to corresponding rate | |
+ * | 4 | Open DFE LLD | Dfe_open() |
+ * | 5 | Load DFE target configuration | Dfe_loadTgtCfg() |
+ * | | Soft Reset DFE peripheral | Dfe_softReset() |
+ * | | Check and wait SERDES PLL_OK | |
+ * | 6 | IQN2 configuration and enable | |
+ * | 7 | Do DFE initialization sequence for transmit path | Dfe_initTgtTx() |
+ * | 8 | Program analogue front-end which connects with DFE | |
+ * | | Check and wait SERDES OK and !LOSS | |
+ * | | Do DFE initialization sequence for receive path | Dfe_initTgtRx() |
+ * | 9 | QMSS, CPPI configuration | |
*
*/
typedef struct
{
- // square clipper threshold
- uint32_t threshold;
- // clipper counter threshold (C1)
- uint32_t cc_thr;
- // peak threshold (TH0)
- uint32_t TH0;
- // peak counter threshold (C0)
- uint32_t peak_thr;
- // peakgain counter threshold (C2)
- uint32_t peakgain_thr;
+ // square clipper threshold
+ uint32_t threshold;
+ // clipper counter threshold (C1)
+ uint32_t cc_thr;
+ // peak threshold (TH0)
+ uint32_t TH0;
+ // peak counter threshold (C0)
+ uint32_t peak_thr;
+ // peakgain counter threshold (C2)
+ uint32_t peakgain_thr;
} DFE_TxPAprotPeak;
typedef struct
{
- // mu_p for IIR
- uint32_t mu0;
- // mu_q for IIR
- uint32_t mu1;
- // RMS threshold to reduce CFR gain(TH1)
- uint32_t TH1;
- // RMS threshold to shut down (TH2)
- uint32_t TH2;
- // RMS threshold to peak approaching saturation (TH4)
- uint32_t TH4;
- // threshold selection for a1
- uint32_t th1Sel;
- // threshold selection for a2
- uint32_t th2Sel;
- // threshold selection for a6
- uint32_t th6Sel;
+ // mu_p for IIR
+ uint32_t mu0;
+ // mu_q for IIR
+ uint32_t mu1;
+ // RMS threshold to reduce CFR gain(TH1)
+ uint32_t TH1;
+ // RMS threshold to shut down (TH2)
+ uint32_t TH2;
+ // RMS threshold to peak approaching saturation (TH4)
+ uint32_t TH4;
+ // threshold selection for a1
+ uint32_t th1Sel;
+ // threshold selection for a2
+ uint32_t th2Sel;
+ // threshold selection for a6
+ uint32_t th6Sel;
} DFE_TxPAprotRms;
typedef struct
{
- // maximum magnitude of D3
- uint32_t mag;
- // IIR output at D50
- uint32_t d50;
- // IIR output at D51
- uint32_t d51;
+ // maximum magnitude of D3
+ uint32_t mag;
+ // IIR output at D50
+ uint32_t d50;
+ // IIR output at D51
+ uint32_t d51;
} DFE_TxPAprotPwrStatus;
// Jesd Tx bus to lane map
// Rx Equalizer Taps
typedef struct
{
- float taps_ii[DFE_FL_RX_EQR_LEN];
- float taps_iq[DFE_FL_RX_EQR_LEN];
- float taps_qi[DFE_FL_RX_EQR_LEN];
- float taps_qq[DFE_FL_RX_EQR_LEN];
+ float taps_ii[DFE_FL_RX_EQR_LEN];
+ float taps_iq[DFE_FL_RX_EQR_LEN];
+ float taps_qi[DFE_FL_RX_EQR_LEN];
+ float taps_qq[DFE_FL_RX_EQR_LEN];
} DFE_RxEqrTaps;
// Fb Equalizer Taps
typedef struct
{
- float taps_ii[DFE_FL_FB_EQR_LEN];
- float taps_iq[DFE_FL_FB_EQR_LEN];
- float taps_qi[DFE_FL_FB_EQR_LEN];
- float taps_qq[DFE_FL_FB_EQR_LEN];
+ float taps_ii[DFE_FL_FB_EQR_LEN];
+ float taps_iq[DFE_FL_FB_EQR_LEN];
+ float taps_qi[DFE_FL_FB_EQR_LEN];
+ float taps_qq[DFE_FL_FB_EQR_LEN];
} DFE_FbEqrTaps;
// CB buf configuration
typedef struct
{
- // cb buf mode set
- DfeFl_CbModeSet cbSet;
- // cb buf delay from sync
- uint32_t dly;
- // 0 = 1s/1c mode; 1 = 2s/1c mode
- uint32_t rate_mode;
- // capture buffer A fractional counter length minus 1; range 0-15; value depends on the relative sampling rates for different buffers
- uint32_t frac_cnt;
- // fractional counter sync select
- uint32_t frac_cnt_ssel;
- // length counter sync select
- uint32_t len_cnt_ssel;
- // cb buf length, upto 8192 complex data
- uint32_t length;
+ // cb buf mode set
+ DfeFl_CbModeSet cbSet;
+ // cb buf delay from sync
+ uint32_t dly;
+ // 0 = 1s/1c mode; 1 = 2s/1c mode
+ uint32_t rate_mode;
+ // capture buffer A fractional counter length minus 1; range 0-15; value depends on the relative sampling rates for different buffers
+ uint32_t frac_cnt;
+ // fractional counter sync select
+ uint32_t frac_cnt_ssel;
+ // length counter sync select
+ uint32_t len_cnt_ssel;
+ // cb buf length, upto 8192 complex data
+ uint32_t length;
} DFE_CbBufCfg;
/**
*/
typedef struct
{
- /// I data
- uint32_t Idata;
- /// Q data
- uint32_t Qdata;
+ /// I data
+ uint32_t Idata;
+ /// Q data
+ uint32_t Qdata;
} DFE_CbData;
/**
typedef struct _DFE_DpdData
{
- /// lutGain
- DfeFl_DpdComplexInt lutGain;
- /// lutSlope
- DfeFl_DpdComplexInt lutSlope;
+ /// lutGain
+ DfeFl_DpdComplexInt lutGain;
+ /// lutSlope
+ DfeFl_DpdComplexInt lutSlope;
} DFE_DpdData;
typedef struct _DFE_DpdCfg
{
- /// subchip mode
- uint32_t subchip_mode;
- /// subsample
- uint32_t subsample;
- /// dpd input scale
- uint32_t dpdInputScale;
- /// x2 sqrt
- uint32_t x2_sqrt;
+ /// subchip mode
+ uint32_t subchip_mode;
+ /// subsample
+ uint32_t subsample;
+ /// dpd input scale
+ uint32_t dpdInputScale;
+ /// x2 sqrt
+ uint32_t x2_sqrt;
} DFE_DpdCfg;
/**
* @ingroup DFE_LLD_DATASTRUCT
*/
typedef struct _DFE_EeCountObj {
- /** Holds counters for dfe BB error interrupts */
- DfeFl_BbGeneralIntrGroup bbErr;
- /** Holds counters for dfe Tx power meter error interrupts */
- uint32_t bbtxpmErr[16];
- /** Holds counters for dfe Tx gain update error interrupts */
- uint32_t bbtxgainErr[16];
- /** Holds counters for dfe Tx power meter error interrupts */
- uint32_t bbrxpmErr[16];
- /** Holds counters for dfe Tx gain update error interrupts */
- uint32_t bbrxgainErr[16];
- /** Holds counters for dfe DDUC error interrupts */
- DFE_EeDducStatus dducErr[4];
- /** Holds counters for dfe CFR error interrupts */
- DFE_EeCfrStatus cfrErr[2];
- /** tx X antenna Y power is approaching saturation error interrupt */
- uint32_t txPaPowerErr[2][2];
+ /** Holds counters for dfe BB error interrupts */
+ DfeFl_BbGeneralIntrGroup bbErr;
+ /** Holds counters for dfe Tx power meter error interrupts */
+ uint32_t bbtxpmErr[16];
+ /** Holds counters for dfe Tx gain update error interrupts */
+ uint32_t bbtxgainErr[16];
+ /** Holds counters for dfe Tx power meter error interrupts */
+ uint32_t bbrxpmErr[16];
+ /** Holds counters for dfe Tx gain update error interrupts */
+ uint32_t bbrxgainErr[16];
+ /** Holds counters for dfe DDUC error interrupts */
+ DFE_EeDducStatus dducErr[4];
+ /** Holds counters for dfe CFR error interrupts */
+ DFE_EeCfrStatus cfrErr[2];
+ /** tx X antenna Y power is approaching saturation error interrupt */
+ uint32_t txPaPowerErr[2][2];
/** tx X antenna Y peak is approaching saturation error interrupt */
uint32_t txPaPeakErr[2][2];
- /** Holds counters for dfe Jesd Tx SysRef error interrupts */
+ /** Holds counters for dfe Jesd Tx SysRef error interrupts */
DfeFl_JesdTxSysrefIntrs jesdTxSysref;
/** Holds counters for dfe Jesd Rx SysRef error interrupts */
DfeFl_JesdRxSysrefIntrs jesdRxSysref;
DFE_EeJesdTxlaneStatus jesdTxLaneErr[4];
/** Holds counters for dfe Jesd Rx lane error interrupts */
DFE_EeJesdRxlaneStatus jesdRxLaneErr[4];
- /** Holds counters for dfe Dpda error interrupts */
- DfeFl_DpdaIntrStatus dpdaErr;
- /** Holds counters for dfe Rx Ibpm error interrupts */
- uint32_t rxIbpmInt[4];
- /** Holds counters for dfe Misc error interrupts */
- DFE_EeMiscCppIntStatus miscErr;
- /** Holds counters for dfe Misc error interrupts */
- DfeFl_MiscMasterHiPriIntrGroup masterHiPrioErr;
- /** Holds a flag telling whether any of the enabled exceptions occurred, 0 if none, 1 if any */
- uint32_t eeFlag;
+ /** Holds counters for dfe Dpda error interrupts */
+ DfeFl_DpdaIntrStatus dpdaErr;
+ /** Holds counters for dfe Rx Ibpm error interrupts */
+ uint32_t rxIbpmInt[4];
+ /** Holds counters for dfe Misc error interrupts */
+ DFE_EeMiscCppIntStatus miscErr;
+ /** Holds counters for dfe Misc error interrupts */
+ DfeFl_MiscMasterHiPriIntrGroup masterHiPrioErr;
+ /** Holds a flag telling whether any of the enabled exceptions occurred, 0 if none, 1 if any */
+ uint32_t eeFlag;
} DFE_EeCountObj, *DFE_EeCountHandle;
/** @brief DFE device instance context
DFE_Err Dfe_progDducMixerNCO
(
DFE_Handle hDfe,
- uint32_t dducDev,
- float refClock,
+ uint32_t dducDev,
+ float refClock,
float freq[12]
);
// Program Summer map
DFE_Err Dfe_progSummerMap
(
- DFE_Handle hDfe,
- uint32_t cfrId,
- uint32_t strId,
+ DFE_Handle hDfe,
+ uint32_t cfrId,
+ uint32_t strId,
uint32_t sumMap[4]
);
DFE_Err Dfe_progCfrCoeff
(
DFE_Handle hDfe,
- uint32_t cfrDev,
- uint32_t numCoeffs,
+ uint32_t cfrDev,
+ uint32_t numCoeffs,
uint32_t *cfrCoeff_i,
uint32_t *cfrCoeff_q
);
DFE_Err Dfe_issueSyncUpdateCfrCoeff
(
DFE_Handle hDfe,
- uint32_t cfrDev,
- uint32_t coeffType,
+ uint32_t cfrDev,
+ uint32_t coeffType,
DfeFl_MiscSyncGenSig ssel
);
// Program Cfr preGain
DFE_Err Dfe_progCfrPreGain
(
- DFE_Handle hDfe,
- uint32_t cfrDev,
- DfeFl_CfrPath cfrPath,
- float gain
+ DFE_Handle hDfe,
+ uint32_t cfrDev,
+ DfeFl_CfrPath cfrPath,
+ float gain
);
// Issue Sync Update Cfr preGain
DFE_Err Dfe_issueSyncUpdatCfrPreGain
(
DFE_Handle hDfe,
- uint32_t cfrDev,
- DfeFl_CfrPath cfrPath,
+ uint32_t cfrDev,
+ DfeFl_CfrPath cfrPath,
DfeFl_MiscSyncGenSig ssel
);
// Program Cfr postGain
DFE_Err Dfe_progCfrPostGain
(
- DFE_Handle hDfe,
- uint32_t cfrDev,
- DfeFl_CfrPath cfrPath,
- float gain
+ DFE_Handle hDfe,
+ uint32_t cfrDev,
+ DfeFl_CfrPath cfrPath,
+ float gain
);
// Issue Sync Update Cfr postGain
DFE_Err Dfe_issueSyncUpdatCfrPostGain
(
DFE_Handle hDfe,
- uint32_t cfrDev,
- DfeFl_CfrPath cfrPath,
+ uint32_t cfrDev,
+ DfeFl_CfrPath cfrPath,
DfeFl_MiscSyncGenSig ssel
);
// Program Cfr protection gain
DFE_Err Dfe_progCfrProtGain
(
- DFE_Handle hDfe,
- uint32_t cfrDev,
- DfeFl_CfrPath cfrPath,
- float gain
+ DFE_Handle hDfe,
+ uint32_t cfrDev,
+ DfeFl_CfrPath cfrPath,
+ float gain
);
// Program Tx Mixer
DFE_Err Dfe_progTxMixer
(
- DFE_Handle hDfe,
- DfeFl_TxPath txPath,
- float refClock,
+ DFE_Handle hDfe,
+ DfeFl_TxPath txPath,
+ float refClock,
float freq[2]
);
// Issue sync to update Tx Mixer
DFE_Err Dfe_issueSyncUpdateTxMixer
(
- DFE_Handle hDfe,
- DfeFl_TxPath txPath,
+ DFE_Handle hDfe,
+ DfeFl_TxPath txPath,
DfeFl_MiscSyncGenSig ssel
);
// Program Tx PA protection
DFE_Err Dfe_progTxPaProtection
(
- DFE_Handle hDfe,
- DfeFl_TxDev txDev,
- DFE_TxPAprotPeak txPAprotPeak,
- DFE_TxPAprotRms txPAprotRms,
- uint32_t mask
+ DFE_Handle hDfe,
+ DfeFl_TxDev txDev,
+ DFE_TxPAprotPeak txPAprotPeak,
+ DFE_TxPAprotRms txPAprotRms,
+ uint32_t mask
);
// Get Tx PA protection interrupt status
// Program Rx Equalizer
DFE_Err Dfe_progRxEqr
(
- DFE_Handle hDfe,
- uint32_t rxDev,
- uint32_t shift,
- uint32_t numCoeff,
- DFE_RxEqrTaps *RxEqrTaps
+ DFE_Handle hDfe,
+ uint32_t rxDev,
+ uint32_t shift,
+ uint32_t numCoeff,
+ DFE_RxEqrTaps *RxEqrTaps
);
// Issue Sync to update Rx Equalizer
DFE_Err Dfe_progRxMixerNCO
(
DFE_Handle hDfe,
- uint32_t rxDev,
- float refClock,
+ uint32_t rxDev,
+ float refClock,
float freq
);
DFE_Err Dfe_progRxTestbus
(
DFE_Handle hDfe,
- uint32_t top_ctrl,
- uint32_t imb_ctrl,
- uint32_t feagc_dc_ctrl
+ uint32_t top_ctrl,
+ uint32_t imb_ctrl,
+ uint32_t feagc_dc_ctrl
);
// Program Fb Equalizer
DFE_Err Dfe_progFbEqr
(
- DFE_Handle hDfe,
- DfeFl_FbBlk FbBlkId,
- uint32_t numCoeff,
+ DFE_Handle hDfe,
+ DfeFl_FbBlk FbBlkId,
+ uint32_t numCoeff,
DFE_FbEqrTaps *FbEqrTaps
);
// Program Fb Mixer NCO
DFE_Err Dfe_progFbMixerNCO
(
- DFE_Handle hDfe,
- DfeFl_FbBlk FbBlkId,
- float refClock,
+ DFE_Handle hDfe,
+ DfeFl_FbBlk FbBlkId,
+ float refClock,
float freq
);
// Program Fb IO Mux
DFE_Err Dfe_progFbIOMux
(
- DFE_Handle hDfe,
+ DFE_Handle hDfe,
DfeFl_FbIoMux ioMux
);
// Program Fb pre-cb gain
DFE_Err Dfe_progFbGain
(
- DFE_Handle hDfe,
- DfeFl_FbBlk FbBlkId,
+ DFE_Handle hDfe,
+ DfeFl_FbBlk FbBlkId,
float FbGain[2]
);
// Get CB done status
DFE_Err Dfe_getCbDoneStatus
(
- DFE_Handle hDfe,
- DfeFl_CbArm *cbDoneStatus
+ DFE_Handle hDfe,
+ DfeFl_CbArm *cbDoneStatus
);
// Read Cb Buf and Status
DFE_Err Dfe_readCbBuf
(
DFE_Handle hDfe,
- DfeFl_CbBuf cbBufId,
- uint32_t cbLength,
- uint32_t flag_18bit,
- DfeFl_CbComplexInt *cbTemp,
+ DfeFl_CbBuf cbBufId,
+ uint32_t cbLength,
+ uint32_t flag_18bit,
+ DfeFl_CbComplexInt *cbTemp,
DfeFl_CbStatus *cbStatus,
DFE_CbData *cbData
);
// Open CB buf DMA for reading CB buf
DFE_Err Dfe_openCbBufDma
(
- DFE_Handle hDfe,
- uint32_t flag_18bit,
- uint32_t cppDmaId,
- uint32_t cppDescripId[8],
- uint32_t iqnChnl
+ DFE_Handle hDfe,
+ uint32_t flag_18bit,
+ uint32_t cppDmaId,
+ uint32_t cppDescripId[8],
+ uint32_t iqnChnl
);
// Close CB buf DMA
// Enable CB buf DMA
DFE_Err Dfe_enableCbBufDma
(
- DFE_Handle hDfe
+ DFE_Handle hDfe
);
// Disable CB buf DMA
DFE_Err Dfe_disableCbBufDma
(
- DFE_Handle hDfe
+ DFE_Handle hDfe
);
// Disable All Testbus Probes
diff --git a/src/dfelld/DFE_cfr.c b/src/dfelld/DFE_cfr.c
index 5abb04b265f323b047a10e19a730a7d267a53e0e..858e3526eae078a5adaad0344fc00b89eea36935 100644 (file)
--- a/src/dfelld/DFE_cfr.c
+++ b/src/dfelld/DFE_cfr.c
* @brief Program CFR Coefficients
* @ingroup DFE_LLD_CFR_FUNCTION
*
- * Write new Cfr coefficients to the shadow memory. The range of each coefficient is 0 ~ 4095. The maximum number of coefficients is 256 for each Cfr instance. It is shared by all antennas in each Cfr instance.
- * NOTE, Dfe_issueSyncUpdateCfrCoeff () should be called later to let hardware copy gains from shadow to working memory.
+ * Write new Cfr coefficients to the shadow memory. The range of each coefficient
+ * is 0 ~ 4095. The maximum number of coefficients is 256 for each Cfr instance.
+ * It is shared by all antennas in each Cfr instance.
+ *
+ * NOTE, Dfe_issueSyncUpdateCfrCoeff () should be called later to let hardware
+ * copy gains from shadow to working memory.
*
* @param hDfe [in] DFE device handle
* @param cfrDev [in] Cfr device Id, 0 - 1
* - hDfe should be a valid handle opened by Dfe_open().
* - DFE PLL and PSCs shall be already up running.
* - DFE has loaded target config and completed initialize sequence.
- * - Dfe_issueSyncUpdateCfrCoeff () should be called later to copy gains to working memory.
+ * - Dfe_issueSyncUpdateCfrCoeff () should be called later to copy gains
+ * to working memory.
*
* @post
* - None.
* @brief Issue Sync Update CFR Coefficients
* @ingroup DFE_LLD_CFR_FUNCTION
*
- * Issue sync update Cfr coefficients. Dfe_getSyncStatus() can be called later to check if the sync has come.
+ * Issue sync update Cfr coefficients. Dfe_getSyncStatus() can be
+ * called later to check if the sync has come.
*
* @param hDfe [in] DFE device handle
* @param cfrDev [in] Cfr device Id, 0 - 1
* @brief Issue Sync Update CFR preGain
* @ingroup DFE_LLD_CFR_FUNCTION
*
- * Issue sync to copy CFR pre gain from shadow to working memory. Dfe_getSyncStatus() should be called later to check if the sync has come.
+ * Issue sync to copy CFR pre gain from shadow to working memory.
+ * Dfe_getSyncStatus() should be called later to check if the sync has come.
*
* @param hDfe [in] DFE device handle
* @param cfrDev [in] Cfr device Id, 0 - 1
* @ingroup DFE_LLD_CFR_FUNCTION
*
* Write new Cfr postGain to shadow memory. The range is -Inf ~ 6dB.
- * NOTE, Dfe_issueSyncUpdateCfrPostGain () should be called later to let hardware copy gains from shadow to working memory.
+ *
+ * NOTE, Dfe_issueSyncUpdateCfrPostGain () should be called later to
+ * let hardware copy gains from shadow to working memory.
*
* @param hDfe [in] DFE device handle
* @param cfrDev [in] Cfr device Id, 0 - 1
* - hDfe should be a valid handle opened by Dfe_open().
* - DFE PLL and PSCs shall be already up running.
* - DFE has loaded target config and completed initialize sequence.
- * - Dfe_issueSyncUpdateCfrPostGain() should be called later to let hardware take new configuration.
+ * - Dfe_issueSyncUpdateCfrPostGain() should be called later to let
+ * hardware take new configuration.
*
* @post
* - None.
* @brief Issue Sync Update CFR postGain
* @ingroup DFE_LLD_CFR_FUNCTION
*
- * Issue sync to copy CFR pre gain from shadow to working memory. Dfe_getSyncStatus() should be called later to check if the sync has come.
+ * Issue sync to copy CFR pre gain from shadow to working memory.
+ * Dfe_getSyncStatus() should be called later to check if the sync has come.
*
* @param hDfe [in] DFE device handle
* @param cfrDev [in] Cfr device Id, 0 - 1
* @brief Program CFR Protection Gain
* @ingroup DFE_LLD_CFR_FUNCTION
*
- * Write new Cfr protection gain. It is a backoff gain when PA protection is in alarm mode. The range is -Inf ~ 6dB.
+ * Write new Cfr protection gain. It is a backoff gain when PA protection
+ * is in alarm mode. The range is -Inf ~ 6dB.
*
* @param hDfe [in] DFE device handle
* @param cfrDev [in] Cfr device Id, 0 - 1
diff --git a/src/dfelld/DFE_jesd.c b/src/dfelld/DFE_jesd.c
index f91d21b6b7deddfc37d3d84a6cb7c260742d933f..804332a3e191e7194eceade4ba695a296400d340 100644 (file)
--- a/src/dfelld/DFE_jesd.c
+++ b/src/dfelld/DFE_jesd.c
* @ingroup DFE_LLD_JESD_FUNCTION
*
* Program how to fill time slots of a lane with Tx bus time slots.
- * A Tx bus consists of four time slots. A Tx bus time slot, an element of laneMap[], is selected by the bus# and slot# of the bus.
- *
- * @verbatim
- // Jesd Tx bus to lane map
- typedef struct
- {
- // bus#, one of DfeFl_JesdTxTxBus (I0, Q0, I1, Q1)
- Uint32 bus;
- // slot#, 0 ~ 3
- Uint32 busPos;
- } DFE_JesdTxLaneMapPos;
- @endverbatim
+ *
+ * A Tx bus consists of four time slots. A Tx bus time slot, an element
+ * of laneMap[], is selected by the bus# and slot# of the bus.
+ *
+ * ~~~{.c}
+ * // Jesd Tx bus to lane map
+ * typedef struct
+ * {
+ * // bus#, one of DfeFl_JesdTxTxBus (I0, Q0, I1, Q1)
+ * uint32_t bus;
+ * // slot#, 0 ~ 3
+ * uint32_t busPos;
+ * } DFE_JesdTxLaneMapPos;
+ * ~~~
*
* A lane also consists of four time slots:
* - laneMap[0] is mapping to lane time slot 0
* - laneMap[2] is mapping to lane time slot 2
* - laneMap[3] is mapping to lane time slot 3
*
- * For example, TX0 has two interleaved antenna streams, A0 and A1, which are mapping to two lanes, lane0 and lane1, A0 => lane0, A1 => lane1.
+ * For example, TX0 has two interleaved antenna streams, A0 and A1,
+ * which are mapping to two lanes, lane0 and lane1, A0 => lane0, A1 => lane1.
+ *
* TX0 bus format:
*
* | Bus# | Slot0 | Slot1 | Slot2 | Slot3 |
* @brief Program JESD Tx SigGen Ramp
* @ingroup DFE_LLD_JESD_FUNCTION
*
- * Program a JESDTX signal generator to produce a ramp. The following rules should be followed:
+ * Program a JESDTX signal generator to produce a ramp. The following
+ * rules should be followed:
* - start <= stop
* - (stop - start) % slope = 0
* - Start/stop/slope range, -131072 ~ 131071
* @brief Issue Sync Update JESDTX SigGen
* @ingroup DFE_LLD_JESD_FUNCTION
*
- * Issue sync update JESDTX SigGen. Dfe_getSyncStatus() can be called later to check if the sync has come.
- * When sync ssel comes, the ramp restarts from start value and step up the slope value per clock. When accumulated value equal to stop value, the ramp restarts again.
+ * Issue sync update JESDTX SigGen. Dfe_getSyncStatus() can be called
+ * later to check if the sync has come.
+ *
+ * When sync ssel comes, the ramp restarts from start value and step up
+ * the slope value per clock. When accumulated value equal to stop value,
+ * the ramp restarts again.
*
* @param hDfe [in] DFE device handle
* @param sigGenDev [in] BB SigGen device
* @brief Program JESD Tx Testbus
* @ingroup DFE_LLD_JESD_FUNCTION
*
- * DFE has many test probe points scattered over all sub-modules. CB can be used to capture a train of IQ bus signals at the probe.
+ * DFE has many test probe points scattered over all sub-modules.
+ * CB can be used to capture a train of IQ bus signals at the probe.
* The API enables the specified JESDTX test probe to CB interface.
- * NOTE, all test probes "AND together" shares single CB interface. So software should enable no more than one probe at any time. LLD internally disables all probes first before arm a new one.
+ *
+ * NOTE, all test probes "AND together" shares single CB interface.
+ * So software should enable no more than one probe at any time.
+ * LLD internally disables all probes first before arm a new one.
*
* @param hDfe [in] DFE device handle
* @param tp [in] probe position
* @brief Get JESD Tx Link Status
* @ingroup DFE_LLD_JESD_FUNCTION
*
- * The API get back following Tx link status,
+ * The API get back following Tx link status.
* @verbatim
// Jesd Tx link status
typedef struct
* @ingroup DFE_LLD_JESD_FUNCTION
*
* Program how to fill time slots of a RX bus with lane time slots.
- * A Rx lane consists of four time slots. A Rx bus time slot, an element of busMap[], is selected by the lane# and slot# of the lane.
+ *
+ * A Rx lane consists of four time slots. A Rx bus time slot, an
+ * element of busMap[], is selected by the lane# and slot# of the lane.
+ *
+ * ~~~{.c}
* // Jesd Rx lane to bus map
* typedef struct
* {
* // if zero data
* Uint32 zeroBits;
* } DFE_JesdRxBusMapPos;
- @endverbatim
+ * ~~~
*
* A Rx bus also consists of four time slots:
* - busMap[0] is mapping to bus time slot 0
* - busMap[2] is mapping to bus time slot 2
* - busMap[3] is mapping to bus time slot 3
*
- * For example, two Rx lanes, lane0 and lane, are mapping to RX0, which will carry two interleaved antenna streams A0 and A1, lane0 => A0, lane1 => A1.
+ * For example, two Rx lanes, lane0 and lane, are mapping to RX0,
+ * which will carry two interleaved antenna streams A0 and A1,
+ * lane0 => A0, lane1 => A1.
*
* RX0 bus format:
*
* @brief Program JESD Rx Testbus
* @ingroup DFE_LLD_JESD_FUNCTION
*
- * DFE has many test probe points scattered over all sub-modules. CB can be used to capture a train of IQ bus signals at the probe.
+ * DFE has many test probe points scattered over all sub-modules.
+ * CB can be used to capture a train of IQ bus signals at the probe.
* The API enables the specified JESDRX test probe to CB interface.
*
- * NOTE, all test probes "AND together" shares single CB interface. So software should enable no more than one probe at any time. LLD internally disables all probes first before arm a new one.
+ * NOTE, all test probes "AND together" shares single CB interface.
+ * So software should enable no more than one probe at any time.
+ * LLD internally disables all probes first before arm a new one.
*
* @param hDfe [in] DFE device handle
* @param testCbCtrl [in] probe position
* @ingroup DFE_LLD_JESD_FUNCTION
*
* The API get back following Rx link status,
+ * ~~~{.c}
* // Jesd Rx link status
* typedef struct
* {
* // 1 - sysref error
* Uint32 sysrefErr[DFE_FL_JESD_NUM_LINK];
* } DFE_JesdRxLinkStatus;
+ * ~~~
*
* @param hDfe [in] DFE device handle
* @param linkStatus [out] pointer to link status buffer
* @ingroup DFE_LLD_JESD_FUNCTION
*
* The API get back following Tx lane status,
+ * ~~~{.c}
* // Jesd Rx lane status
* typedef struct
* {
* // 0 - normal; 1 - test sequence verification failed
* Uint32 testSeqErr[DFE_FL_JESD_NUM_LANE];
* } DFE_JesdRxLaneStatus;
+ * ~~~
*
* @param hDfe [in] DFE device handle
* @param laneStatus [out] pointer to lane status buffer
diff --git a/src/dfelld/DFE_rx.c b/src/dfelld/DFE_rx.c
index 82953c03b187a39f48bbd00b0607ec6dc728aa2b..dd294d717c75b9ef14d9624b2e91c1673e4d4e03 100644 (file)
--- a/src/dfelld/DFE_rx.c
+++ b/src/dfelld/DFE_rx.c
* @brief Program RX IBPM Global
* @ingroup DFE_LLD_RX_FUNCTION
*
- * Program global settings of RX IBPM. The power meters measure RMS and peak powers at Rx block input. There're total 4 IBPMs, which can be individually configured by Dfe_progRxIbpm() to meter one antenna.
- * IBPM has two reading modes, hardware interrupt mode and software handshake mode.
- * In the hardware interrupt mode, the power meters run per the programmed configuration and set interrupts on a per antenna basis when a new set of results have been computed and captured in the read registers. It is the responsibility of the user to read the results before the next set of results are computed and captured in the read registers.
- * In the software handshake mode, the power meters run per the programmed configuration. The user makes a request to read a current set of results and waits until receiving an acknowledge signal from DFE hardware before reading. Upon receiving the request DFE completes the current power meter cycle, stores the results for reading, sets the acknowledge and halts any further updates until the user resets the request.
- * Each IBPM has two histogram counters to count number of samples whose magnitude is above the specified histThresh.
- * To convert between raw register values to friendly floatings in dB, LLD needs knowing the raw value of unity magnitude square (unityMagSq), i.e. I^2 + Q^2.
+ * Program global settings of RX IBPM. The power meters measure RMS and
+ * peak powers at Rx block input.
+ *
+ * There're total 4 IBPMs, which can be individually configured by
+ * Dfe_progRxIbpm() to meter one antenna.
+ *
+ * IBPM has two reading modes, hardware interrupt mode and software
+ * handshake mode.
+ *
+ * - In the hardware interrupt mode, the power meters run per the
+ * programmed configuration and set interrupts on a per antenna
+ * basis when a new set of results have been computed and captured
+ * in the read registers.
+ *
+ * It is the responsibility of the user to read the results before
+ * the next set of results are computed and captured in the read
+ * registers.
+ *
+ * - In the software handshake mode, the power meters run per the
+ * programmed configuration. The user makes a request to read a
+ * current set of results and waits until receiving an acknowledge
+ * signal from DFE hardware before reading.
+ *
+ * Upon receiving the request DFE completes the current power meter
+ * cycle, stores the results for reading, sets the acknowledge and
+ * halts any further updates until the user resets the request.
+ *
+ * Each IBPM has two histogram counters to count number of samples
+ * whose magnitude is above the specified histThresh.
+ *
+ * To convert between raw register values to friendly floatings in dB,
+ * LLD needs knowing the raw value of unity magnitude square (unityMagSq),
+ * i.e. I^2 + Q^2.
*
* @param hDfe [in] DFE device handle
* @param readMode [in] meter reading mode
* @brief Program RX IBPM
* @ingroup DFE_LLD_RX_FUNCTION
*
- * Program settings of an individual RX IBPM, which meters RMS and peak power at Rx block input for one antenna.
- * When a sync event comes, IBPM starts a new meter cycle after syncDelay samples. The cycle completes at integration time of nSamples. When oneShot is enabled(1), IBPM does no more measurement until next sync event; when oneShot is disabled(0), IBPM starts a new measure after interval samples elapsed, and this repeats every interval. The interval shall be no less than integration time + syncDelay, otherwise IBPM never completes.
- * When meterMode is 0, IBPM is disabled; when meterMode is 1, IBPM is running according to configuration of sync delay, integration period and interval; when meter mode is 2, IBPM is running over a gated stream.
+ * Program settings of an individual RX IBPM, which meters RMS and
+ * peak power at Rx block input for one antenna.
+ *
+ * When a sync event comes, IBPM starts a new meter cycle after
+ * syncDelay samples. The cycle completes at integration time of
+ * nSamples.
+ *
+ * When oneShot is enabled(1), IBPM does no more measurement until
+ * next sync event.
+ *
+ * When oneShot is disabled(0), IBPM starts a new measure after
+ * interval samples elapsed, and this repeats every interval.
+ * The interval shall be no less than integration time + syncDelay,
+ * otherwise IBPM never completes.
+ *
+ * When meterMode is 0, IBPM is disabled; when meterMode is 1, IBPM
+ * is running according to configuration of sync delay, integration
+ * period and interval.
+ *
+ * When meter mode is 2, IBPM is running over a gated stream.
*
* @param hDfe [in] DFE device handle
* @param pmId [in] power meter device ID
* @param oneShot [in] one shot mode
* @param meterMode [in] meter operational mode
- * - - 0 = off
- * - - 1 = normal mode
- * - - 2 = gated mode
+ * - 0 = off
+ * - 1 = normal mode
+ * - 2 = gated mode
* @param syncDelay [in] delay from sync event, in samples
* @param nSamples [in] integration period, in samples
* @param interval [in] interval period, in samples
* @brief Issue Sync Update RX IBPM
* @ingroup DFE_LLD_RX_FUNCTION
*
- * Issue sync update a RX IBPM. Dfe_getSyncStatus() can be called later to check if the sync has come.
+ * Issue sync update a RX IBPM. Dfe_getSyncStatus() can be called later
+ * to check if the sync has come.
+ *
* When sync ssel comes, the power meter starts a new measurement cycle.
*
* @param hDfe [in] DFE device handle
* @brief Issue RX IBPM Read Request
* @ingroup DFE_LLD_RX_FUNCTION
*
- * The API is applied for the software handshake mode only. In this mode, the user makes a request (via this API) to read a current set of results and waits until receiving an acknowledge signal (via polling Dfe_getRxIbpmReadAck()) from DFE hardware before reading. Upon receiving the request DFE completes the current power meter cycle, stores the results for reading, sets the acknowledge and halts any further updates until the user resets the request (via Dfe_readRxIbpmResult()).
+ * The API is used for the software handshake mode only. In this mode,
+ * the user makes a request (via this API) to read a current set of
+ * results and waits until receiving an acknowledge signal (via polling
+ * Dfe_getRxIbpmReadAck()) from DFE hardware before reading.
+ *
+ * Upon receiving the request DFE completes the current power meter
+ * cycle, stores the results for reading, sets the acknowledge and
+ * halts any further updates until the user resets the request
+ * (via Dfe_readRxIbpmResult()).
*
* @param hDfe [in] DFE device handle
* @param pmId [in] Rx IBPM device Id
* @brief Get RX IBPM Read Ack
* @ingroup DFE_LLD_RX_FUNCTION
*
- * The API is applied for the software handshake mode only. In this mode, the user makes a request (via Dfe_issueRxIbpmReadRequest()) to read a current set of results and waits until receiving an acknowledge signal (via polling this API) from DFE hardware before reading. Upon receiving the request DFE completes the current power meter cycle, stores the results for reading, sets the acknowledge and halts any further updates until the user resets the request (via Dfe_readRxIbpmResult()).
+ * The API is used for the software handshake mode only. In this mode,
+ * the user makes a request (via Dfe_issueRxIbpmReadRequest()) to read
+ * a current set of results and waits until receiving an acknowledge
+ * signal (via polling this API) from DFE hardware before reading.
+ *
+ * Upon receiving the request DFE completes the current power meter
+ * cycle, stores the results for reading, sets the acknowledge and
+ * halts any further updates until the user resets the request (via
+ * Dfe_readRxIbpmResult()).
*
* @param hDfe [in] DFE device handle
* @param pmId [in] Rx IBPM device Id
* @brief Read RX IBPM Result
* @ingroup DFE_LLD_RX_FUNCTION
*
- * Read back results of a running RX IBPM. After retrieves all results, for hardware interrupt mode, the API writes done reading flag to DFE; for software handshake mode, the API clears read request, which was set by Dfe_IssueRxIbpmReadRequest().
+ * Read back results of a running RX IBPM and after all the results are
+ * retrieved:
+ * - for hardware interrupt mode, the API writes done reading flag to DFE.
+ * - for software handshake mode, the API clears read request, which was
+ * set by Dfe_IssueRxIbpmReadRequest().
*
* @param hDfe [in] DFE device handle
* @param pmId [in] Rx IBPM device Id
- * @param power [out] Power value
- * @param peak [out] peak value
+ * @param power [out] Power value
+ * @param peak [out] peak value
* @param histCount1 [out] the number of samples which power is greater than the histogram one threshold
* @param histCount2 [out] the number of samples which power is greater than the histogram two threshold
*
* @brief Program RX Equalizer
* @ingroup DFE_LLD_RX_FUNCTION
*
- * Write new RX Equalizer to shadow memory. The range of each tap is -1 ~ 0.9998. Eqr bypass needs to be disabled.
- * NOTE, Dfe_issueSyncUpdateRxEqr () should be called later to let hardware copy gains from shadow to working memory.
+ * Write new RX Equalizer to shadow memory. The range of each tap
+ * is -1 ~ 0.9998. Eqr bypass needs to be disabled.
+ *
+ * NOTE, Dfe_issueSyncUpdateRxEqr () should be called later to let
+ * hardware copy gains from shadow to working memory.
+ *
+ * ~~~{.c}
* typedef struct
* {
* // ii taps
* // qq taps
* float taps_qq[DFE_FL_RX_EQR_LEN];
* } DFE_RxEqrTaps;
+ * ~~~
*
* @param hDfe [in] DFE device handle
* @param rxDev [in] Rx Id, 0 ~ 3
* @brief Issue Sync Update RX Equalizer
* @ingroup DFE_LLD_RX_FUNCTION
*
- * Issue sync to copy Rx equalizer from shadow to working memory. Dfe_getSyncStatus() should be called later to check if the sync has come.
+ * Issue sync to copy Rx equalizer from shadow to working memory.
+ * Dfe_getSyncStatus() should be called later to check if the sync has come.
*
* @param hDfe [in] DFE device handle
* @param rxDev [in] Rx Id, 0 ~ 3
* @brief Program RX Mixer NCO
* @ingroup DFE_LLD_RX_FUNCTION
*
- * Write new RX Mixer NCO to shadow memory. The precision of the frequency is refClock/2^48. NCO bypass needs to be disabled.
- * NOTE, Dfe_issueSyncUpdateRxMixerNCO () should be called later to let hardware copy gains from shadow to working memory.
+ * Write new RX Mixer NCO to shadow memory. The precision of the frequency
+ * is refClock/2^48. NCO bypass needs to be disabled.
+ *
+ * NOTE, Dfe_issueSyncUpdateRxMixerNCO () should be called later to let
+ * hardware copy gains from shadow to working memory.
*
* @param hDfe [in] DFE device handle
* @param rxDev [in] Rx Id, 0 ~ 3
* @brief Issue Sync Update RX Mixer NCO Frequency
* @ingroup DFE_LLD_RX_FUNCTION
*
- * Issue sync to copy RX Mixer NCO frequency from shadow to working memory. Dfe_getSyncStatus() should be called later to check if the sync has come.
+ * Issue sync to copy RX Mixer NCO frequency from shadow to working memory.
+ * Dfe_getSyncStatus() should be called later to check if the sync has come.
*
* @param hDfe [in] DFE device handle
* @param ssel [in] sync select to copy gains from shadow to working memory.