author | Rishabh Garg <rishabh@ti.com> | |
Thu, 7 Mar 2019 11:14:41 +0000 (16:44 +0530) | ||
committer | Rishabh Garg <rishabh@ti.com> | |
Thu, 7 Mar 2019 11:14:41 +0000 (16:44 +0530) | ||
commit | fec1bf18ad2b0fceebcce77c4e93765d2d4bfa54 | |
tree | cce192dcd862b7d7af7efdebce63369e52092449 | tree | snapshot (tar.xz tar.gz zip) |
parent | 22624f39d2fd1b65ba4d5ff6fc7db178b3e0f1ae | commit | diff |
Updated master ISR
- ASTC has updated VLAB to use correct sequence for clearing DSS interrupts
- Hence removed workaround code for simulator
Signed-off-by: Rishabh Garg <rishabh@ti.com>
- ASTC has updated VLAB to use correct sequence for clearing DSS interrupts
- Hence removed workaround code for simulator
Signed-off-by: Rishabh Garg <rishabh@ti.com>
src/common/dss_evtMgr.c | diff | blob | history |