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raw | patch | inline | side by side (parent: 101254e)
| author | Subhajit Paul <subhajit_paul@ti.com> | |
| Tue, 27 Aug 2019 12:09:37 +0000 (17:39 +0530) | ||
| committer | Subhajit Paul <subhajit_paul@ti.com> | |
| Tue, 3 Sep 2019 07:43:30 +0000 (13:13 +0530) |
DCTRL to DP interface modifications
Major changes in this patch:
- HPD for non-blocking initialisation of DP
- Enforced link trainig for each HPD for better usability / compatibility
- Code cleanup
Signed-off-by: Subhajit Paul <subhajit_paul@ti.com>
Major changes in this patch:
- HPD for non-blocking initialisation of DP
- Enforced link trainig for each HPD for better usability / compatibility
- Code cleanup
Signed-off-by: Subhajit Paul <subhajit_paul@ti.com>
diff --git a/soc/V1/dss_soc.h b/soc/V1/dss_soc.h
index 23cb02ed8df2ec392067e58b7a435610220dbafe..497453f4544135e4657f124b6568f293a1a027aa 100755 (executable)
--- a/soc/V1/dss_soc.h
+++ b/soc/V1/dss_soc.h
/**< Ids for available video ports */
} Dss_RmInfo;
+/**
+ * \brief Structure containing Display Port init parameters
+ */
+typedef struct
+{
+ uint32_t isAvailable;
+ /**< Flag to indicate whether eDP module is available */
+} Dss_DpInitParams;
+
/**
* \brief DSS SOC parameters.
*/
/**< DSS interrupt information */
Dss_RmInfo rmInfo;
/**< DSS resource information */
+ Dss_DpInitParams dpInitParams;
+ /**< DSS DP init information */
} Dss_SocParams;
/* ========================================================================== */
*/
static inline void Dss_rmInfoInit(Dss_RmInfo *rmInfo);
+/**
+ * \brief Dss_DpInfo structure init function.
+ *
+ * \param dpInfo Pointer to #Dss_DpInfo structure.
+ *
+ * \return None
+ */
+static inline void Dss_dpInitParamsInit(Dss_DpInitParams *dpInitParams);
+
/**
* \brief Dss_SocParams structure init function.
*
}
}
+static inline void Dss_dpInitParamsInit(Dss_DpInitParams *dpInitParams)
+{
+ if(NULL != dpInitParams)
+ {
+ dpInitParams->isAvailable = TRUE;
+ }
+}
+
static inline void Dss_socParamsInit(Dss_SocParams *socParams)
{
if(NULL != socParams)
{
Dss_irqParamsInit(&(socParams->irqParams));
Dss_rmInfoInit(&(socParams->rmInfo));
+ Dss_dpInitParamsInit(&(socParams->dpInitParams));
}
}
index d64e52198d7e847e30fb44665e2295b3dec4fe53..b9f1ae26bbba6302975b48569660e79400ff6f27 100755 (executable)
dctrlInitParams.numAvailablePorts++;
}
}
+
+#if defined(SOC_J721E)
+ dctrlInitParams.dpInitParams.isAvailable = initParams->socParams.dpInitParams.isAvailable;
+#endif
retVal = Dss_dctrlDrvInit(&dctrlInitParams);
}
index 44a84d8cfbe64703771af9d564f9794852e4cf26..6fce4a0e1655a070fe94062233f1ee1af3ed6a6c 100755 (executable)
Dss_DctrlDrvInstObj *instObj,
const Dss_DctrlOldiParams *oldiParams);
#endif
+#if defined (SOC_J721E)
+static uint32_t Dss_dctrlDrvIsOutputDP(uint32_t vpId);
+#endif
+
static void Dss_dctrlVpSetGoBit(uint32_t vpId);
static void Dss_dctrlVpReset(uint32_t vpId);
static void Dss_dctrlVpEnable(uint32_t vpId, uint32_t enable);
}
}
+#if defined (SOC_J721E)
+ if((FVID2_SOK == retVal) &&
+ (TRUE == drvInitParams->dpInitParams.isAvailable))
+ {
+ retVal = Dss_dctrlDrvInitDp();
+ }
+#endif
+
if(FVID2_SOK == retVal)
{
/* Initialize Driver operations */
Dss_dctrlVpEnable(vpId, TRUE);
}
+#if defined (SOC_J721E)
+ if((FVID2_SOK == retVal) &&
+ (TRUE == Dss_dctrlDrvIsOutputDP(vpId)))
+ {
+ retVal = Dss_dctrlDrvEnableVideoDP(&lcdOpTimingCfg->mInfo,
+ lcdPolarityCfg->hsPolarity,
+ lcdPolarityCfg->vsPolarity);
+ }
+#endif
+
if(FVID2_SOK != retVal)
{
GT_0trace(DssTrace, GT_ERR, "Set VP parameters IOCTL failed\r\n");
return retVal;
}
+#if defined (SOC_J721E)
+static uint32_t Dss_dctrlDrvIsOutputDP(uint32_t vpId)
+{
+ uint32_t retVal, i;
+ uint32_t nodeId, vpFound = FALSE;
+ Fvid2_GraphEdgeInfo *currEdge;
+
+ retVal = Dss_convModuletoNode(&nodeId, vpId, DSS_DCTRL_NODE_TYPE_VP);
+ GT_assert(DssTrace,
+ ((DSS_DCTRL_NODE_INVALID != nodeId) ||
+ (FVID2_SOK == retVal)));
+
+ for(i=0U; i<gDss_DctrlDrvGraphObj.dctrlEdgeList.numEdges; i++)
+ {
+ currEdge = &gDss_DctrlDrvGraphObj.dctrlEdgeList.list[i];
+ if((DSS_DCTRL_NODE_EDP_DPI0 == currEdge->endNode) &&
+ (nodeId == currEdge->startNode))
+ {
+ vpFound = TRUE;
+ break;
+ }
+ }
+
+ return vpFound;
+}
+#endif
+
+
static int32_t Dss_dctrlDrvSetOverlayParamsIoctl(
Dss_DctrlDrvInstObj *instObj,
const Dss_DctrlOverlayParams *overlayParams)
if(FVID2_SOK == retVal)
{
+
+#if defined (SOC_J721E)
+ if(TRUE == Dss_dctrlDrvIsOutputDP(vpId))
+ {
+ Dss_dctrlDrvDisableVideoDP();
+ }
+#endif
+
cookie = HwiP_disable();
Dss_dctrlVpEnable(vpId, FALSE);
HwiP_restore(cookie);
GT_assert(DssTrace, (FVID2_SOK == retVal));
}
-#if defined (SOC_J721E)
- if(DSS_DCTRL_NODE_EDP_DPI0 == outNode)
- {
- retVal = Dss_dctrlDrvProgDP();
- GT_assert(DssTrace, (FVID2_SOK == retVal));
- }
-#endif
-
return (retVal);
}
index 0367fd50e0bf317c4e7ada21ea4549a5db9e4089..6d68e015ede9d269fd2142efaf018f5566261564 100755 (executable)
/**< Number of video ports available to driver */
uint32_t availablePortId[CSL_DSS_VP_ID_MAX];
/**< Id of available video ports */
+#if defined(SOC_J721E)
+ Dss_DpInitParams dpInitParams;
+ /**< DP init parameters */
+#endif
} Dss_DctrlDrvInitParams;
/* ========================================================================== */
index 4450b6ed135186642841a49ba4dc691a3704a933..2b7c0a8954fc2934845fb9d1270e0006acf1377a 100755 (executable)
#include <ti/drv/dss/src/drv/dctrl/dss_dctrlPriv.h>
#include <dss_soc_priv.h>
+#include <ti/osal/SwiP.h>
+
/* ========================================================================== */
/* Macros & Typedefs */
/* ========================================================================== */
-#define STATIC_PD_SIZE 131072
-#define STATIC_PHY_PD_SIZE 1024
+typedef enum
+{
+ DP_VIDEO_STATE_IDLE = 0U,
+ DP_VIDEO_STATE_REQUESTED = 1U,
+ DP_VIDEO_STATE_RUNNING = 2U,
+} Dss_DctrlDisplayPortVideoState;
+
+#define DP_PRIVATE_DATA_SIZE (131072U)
+#define DP_PHY_PRIVATE_DATA_SIZE (1024U)
+#define DP_INTR (64U)
+#define ADDR_AFE (0x05050000)
/* ========================================================================== */
/* Structure Declarations */
/* ========================================================================== */
-/* None */
+typedef struct
+{
+ uint32_t width;
+ uint32_t height;
+ uint32_t hfp;
+ uint32_t hsw;
+ uint32_t hbp;
+ uint32_t vfp;
+ uint32_t vsw;
+ uint32_t vbp;
+ uint32_t pclk;
+ uint32_t scanMode;
+ uint32_t hsyncPol;
+ uint32_t vsyncPol;
+} Dss_DctrlDisplayPortVideoMode;
+
+typedef struct
+{
+ DP_Config dpCfg;
+ DP_SD0801_Config dpPhyCfg;
+ DP_FirmwareImage dpFWImage;
+ DP_PrivateData *dpPrivData;
+ DP_SD0801_PrivateData *dpPhyPrivData;
+ DP_Callbacks dpCbInfo;
+ DP_UcpuClock dpClkInfo;
+ DP_SourceDeviceCapabilities srcCaps;
+ HwiP_Handle intrHandle;
+ SwiP_Handle swiHandle;
+ uint32_t isConnected;
+ Dss_DctrlDisplayPortVideoState videoState;
+ Dss_DctrlDisplayPortVideoMode videoMode;
+} Dss_DctrlDisplayPortDrvObj;
/* ========================================================================== */
/* Function Declarations */
extern uint8_t gDctrlDpDram[DCTRL_DP_DMEM_SIZE];
extern uint8_t gDctrlDpIram[DCTRL_DP_IMEM_SIZE];
+static uint8_t gDssDctrlDisplayPortDpPrivateData[DP_PRIVATE_DATA_SIZE];
+static uint8_t gDssDctrlDisplayPortDpPhyPrivateData[DP_PHY_PRIVATE_DATA_SIZE];
+
+static Dss_DctrlDisplayPortDrvObj gDssDctrlDisplayPortDrvObj;
+
+Fvid2_ModeInfo gDpStdModeInfo[] = {
+ {FVID2_STD_1080P_60, 1920, 1080, FVID2_SF_PROGRESSIVE, 148500, 60,
+ 88, 148, 44, 4, 36, 5}
+};
+
/* ========================================================================== */
/* Internal/Private Function Declarations */
/* ========================================================================== */
-static int32_t Dss_dctrlSetDPConfig(int32_t *status);
+static int32_t Dss_dctrlDrvInitDPTX(void);
+static void Dss_dctrlDrvDpIntr(uintptr_t arg);
+static void Dss_dctrlDrvDpHpdWork(uintptr_t arg0, uintptr_t arg1);
+static int32_t Dss_dctrlDrvDpStartVideo(Dss_DctrlDisplayPortDrvObj *pObj);
+static int32_t Dss_dctrlDrvDpStopVideo(Dss_DctrlDisplayPortDrvObj *pObj);
/* ========================================================================== */
/* Function Definitions */
/* ========================================================================== */
+int32_t Dss_dctrlDrvDisableVideoDP(void)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t cookie;
+ Dss_DctrlDisplayPortDrvObj *pObj = &gDssDctrlDisplayPortDrvObj;
+
+ cookie = HwiP_disable();
+
+ /*
+ * We cannot be IDLE when this function is called.
+ * Valid states are REQUESTED || RUNNING
+ *
+ * If state == REQUESTED, HPD never happened, and we
+ * never went to RUNNING. So just go back to IDLE
+ *
+ * If state == RUNNING, we stop video and go to IDLE
+ *
+ * There is nothing we can do if stopVideo fails, so
+ * dont bother
+ */
+ if((DP_VIDEO_STATE_REQUESTED == pObj->videoState) ||
+ (DP_VIDEO_STATE_RUNNING == pObj->videoState))
+ {
+ if(DP_VIDEO_STATE_RUNNING == pObj->videoState)
+ {
+ Dss_dctrlDrvDpStopVideo(pObj);
+ }
+ pObj->videoState = DP_VIDEO_STATE_IDLE;
+ }
+
+ HwiP_restore(cookie);
-static int gDctrlEdpInit = 0U;
+ return retVal;
+}
-int32_t Dss_dctrlDrvProgDP(void)
+int32_t Dss_dctrlDrvEnableVideoDP(const Fvid2_ModeInfo *mInfo,
+ uint32_t hsyncPolarity,
+ uint32_t vsyncPolarity)
{
int32_t retVal = FVID2_SOK;
- if(gDctrlEdpInit == 0U)
+ uint32_t cookie;
+ Dss_DctrlDisplayPortDrvObj *pObj = &gDssDctrlDisplayPortDrvObj;
+ uint32_t numStdModes, modeCnt;
+
+ cookie = HwiP_disable();
+
+ /*
+ * Copy the video mode parameters to be
+ * used by subsequent videoStart calls
+ *
+ * XXX bring in EDID support so that we can validate
+ * params passed by app, and when all parameters not
+ * provided, make a good guess whether to continue or not
+ */
+ if(FVID2_STD_CUSTOM != mInfo->standard)
{
- gDctrlEdpInit = 1U;
-
- /* HPD Pin Mux */
- CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG0 + 0x1c4, 0x00040005);
-
- /* Select EDP PHY CLK source */
- CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_EDP_PHY0_CLKSEL, 0x0);
-
- /* Set DPTX_SRC_CFG, 0:vif0_en, 1:vif_1_en, 2:vif_2_en, 3: vif_3_en, 4: vif_0_sel, TBD */
- CSL_REG32_WR(CSL_DSS_EDP0_INTG_CFG_VP_BASE + CSL_DPTX_DPTX_SRC_CFG, 0x1F);
-
- /* WIZ PHY */
- #define ADDR_AFE (0x05050000)
- CSL_REG32_WR(ADDR_AFE + 0x408, 0x30000000);
- CSL_REG32_WR(ADDR_AFE + 0x40c, 0x39000000);
- CSL_REG32_WR(ADDR_AFE + 0x480, 0x70000000);
- CSL_REG32_WR(ADDR_AFE + 0x4c0, 0x80000000);
- CSL_REG32_WR(ADDR_AFE + 0x500, 0x80000000);
- CSL_REG32_WR(ADDR_AFE + 0x540, 0x80000000);
- CSL_REG32_WR(ADDR_AFE + 0x484, 0x10001 );
- CSL_REG32_WR(ADDR_AFE + 0x4c4, 0x10001 );
- CSL_REG32_WR(ADDR_AFE + 0x504, 0x10001 );
- CSL_REG32_WR(ADDR_AFE + 0x544, 0x10001 );
-
- uint32_t memReq, memReqPhy;
- DP_Config dpConfig = {.regBase = (struct MHDP_ApbRegs_s *)CSL_DSS_EDP0_V2A_CORE_VP_REGS_APB_BASE,
- .regBaseSapb = (struct MHDP_ApbRegs_s *)CSL_DSS_EDP0_V2A_S_CORE_VP_REGS_SAPB_BASE};
-
- DP_SD0801_Config phyCfg = {.regBase = (uint32_t*)CSL_SERDES_10G0_BASE,
- .regBaseDp = (struct DP_Regs_s *)CSL_DSS_EDP0_V2A_CORE_VP_REGS_APB_BASE};
- DP_Probe(&dpConfig, &memReq);
- DP_SD0801_Probe(&phyCfg, &memReqPhy);
-
- DP_PrivateData* pD = NULL;
-
- static uint8_t pdMem[STATIC_PD_SIZE] = { 0 };
- volatile uint8_t pdPhyMem[STATIC_PHY_PD_SIZE] = { 0 };
- if ((memReq > sizeof(pdMem)) || (memReqPhy > sizeof(pdPhyMem)))
+ numStdModes = sizeof (gDpStdModeInfo) / sizeof (Fvid2_ModeInfo);
+ for (modeCnt = 0U; modeCnt < numStdModes; modeCnt++)
+ {
+ if (mInfo->standard == gDpStdModeInfo[modeCnt].standard)
+ {
+ pObj->videoMode.width = gDpStdModeInfo[modeCnt].width;
+ pObj->videoMode.height = gDpStdModeInfo[modeCnt].height;
+ pObj->videoMode.hfp = gDpStdModeInfo[modeCnt].hFrontPorch;
+ pObj->videoMode.hsw = gDpStdModeInfo[modeCnt].hSyncLen;
+ pObj->videoMode.hbp = gDpStdModeInfo[modeCnt].hBackPorch;
+ pObj->videoMode.vfp = gDpStdModeInfo[modeCnt].vFrontPorch;
+ pObj->videoMode.vsw = gDpStdModeInfo[modeCnt].vSyncLen;
+ pObj->videoMode.vbp = gDpStdModeInfo[modeCnt].vBackPorch;
+ pObj->videoMode.pclk = gDpStdModeInfo[modeCnt].pixelClock;
+ pObj->videoMode.scanMode = gDpStdModeInfo[modeCnt].scanFormat;
+ break;
+ }
+ }
+ if (modeCnt == numStdModes)
{
retVal = FVID2_EFAIL;
}
+ }
+ else
+ {
+ pObj->videoMode.width = mInfo->width;
+ pObj->videoMode.height = mInfo->height;
+ pObj->videoMode.hfp = mInfo->hFrontPorch;
+ pObj->videoMode.hsw = mInfo->hSyncLen;
+ pObj->videoMode.hbp = mInfo->hBackPorch;
+ pObj->videoMode.vfp = mInfo->vFrontPorch;
+ pObj->videoMode.vsw = mInfo->vSyncLen;
+ pObj->videoMode.vbp = mInfo->vBackPorch;
+ pObj->videoMode.pclk = mInfo->pixelClock;
+ pObj->videoMode.scanMode = mInfo->scanFormat;
+ }
- pD = (void*)&pdMem[0];
- DP_FirmwareImage image = {.iMem = gDctrlDpIram,
- .iMemSize = DCTRL_DP_IMEM_SIZE,
- .dMem = gDctrlDpDram,
- .dMemSize = DCTRL_DP_DMEM_SIZE};
-
- if (DP_Init(pD, &dpConfig, &(DP_Callbacks){.event = NULL}))
+ pObj->videoMode.hsyncPol = hsyncPolarity;
+ pObj->videoMode.vsyncPol = vsyncPolarity;
+
+ /*
+ * We are supposed to be IDLE when this function is called
+ *
+ * If HPD didnt happen yet, we set to REQUESTED, HDP will
+ * start video later if this flag is set, and then set us
+ * to RUNNING
+ *
+ * If HPD happend, and LT was successful, we start video
+ * and set to RUNNING
+ *
+ * If startVideo fails, we stay at REQUESTED. reason:
+ * startVideo can fail because the connected monitor
+ * does not support the timings provided. So we hope
+ * that when another monitor is connected, we are at
+ * REQUESTED, and HPD takes us to RUNNING
+ *
+ * XXX check the timings, match with EDID and print a trace
+ * accordingly
+ */
+ if((FVID2_SOK == retVal) &&
+ (DP_VIDEO_STATE_IDLE == pObj->videoState))
+ {
+ pObj->videoState = DP_VIDEO_STATE_REQUESTED;
+ if(TRUE == pObj->isConnected)
{
- retVal = FVID2_EFAIL;
+ retVal = Dss_dctrlDrvDpStartVideo(pObj);
+ if(FVID2_SOK == retVal)
+ {
+ pObj->videoState = DP_VIDEO_STATE_RUNNING;
+ }
}
+ }
- DP_LoadFirmware(pD, &image);
+ HwiP_restore(cookie);
+
+ return retVal;
+}
+
+int32_t Dss_dctrlDrvInitDp(void)
+{
+ uint32_t retVal = FVID2_SOK;
+
+ /*
+ * XXX push this things to some CSL kind of functions
+ */
+
+ /* HPD Pin Mux */
+ CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG0 + 0x1c4, 0x00040005);
+
+ /* Select EDP PHY CLK source */
+ CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_EDP_PHY0_CLKSEL, 0x0);
+
+ /* Set DPTX_SRC_CFG, 0:vif0_en, 1:vif_1_en, 2:vif_2_en, 3: vif_3_en, 4: vif_0_sel, TBD */
+ CSL_REG32_WR(CSL_DSS_EDP0_INTG_CFG_VP_BASE + CSL_DPTX_DPTX_SRC_CFG, 0x1F);
+
+ /* WIZ PHY */
+ CSL_REG32_WR(ADDR_AFE + 0x408, 0x30000000);
+ CSL_REG32_WR(ADDR_AFE + 0x40c, 0x39000000);
+ CSL_REG32_WR(ADDR_AFE + 0x480, 0x70000000);
+ CSL_REG32_WR(ADDR_AFE + 0x4c0, 0x80000000);
+ CSL_REG32_WR(ADDR_AFE + 0x500, 0x80000000);
+ CSL_REG32_WR(ADDR_AFE + 0x540, 0x80000000);
+ CSL_REG32_WR(ADDR_AFE + 0x484, 0x10001 );
+ CSL_REG32_WR(ADDR_AFE + 0x4c4, 0x10001 );
+ CSL_REG32_WR(ADDR_AFE + 0x504, 0x10001 );
+ CSL_REG32_WR(ADDR_AFE + 0x544, 0x10001 );
+
+ retVal = Dss_dctrlDrvInitDPTX();
- Dss_dctrlSetDPConfig(&retVal);
- }
return retVal;
}
/* Static Function Definitions */
/* ========================================================================== */
-static int32_t Dss_dctrlSetDPConfig(int32_t *status)
+
+static void Dss_dctrlDrvDpIntr(uintptr_t arg)
{
- uint32_t ret;
- unsigned char resp;
- uint8_t echo_msg[] = "echo test";
- uint8_t echo_resp[sizeof(echo_msg) + 1];
-
- // Set Host capabilities
- // Max Link Rate: 06h (1.62Gbps), 0Ah (2.7Gbps), 14h (5.4Gbps), 1Eh // (8.1Gbps)
- uint8_t max_link_rate;
-
- // Number of lanes and SSC
- uint8_t num_lanes; // number of lanes
-
- // Bits per component (bpc)
- uint8_t bits_per_component;
-
- //VIC MODE
- uint8_t vicMode;
-
- // Pixel formats: 1 (RGB), 2 (YCbCr444), 3 (YCbCr420)
- DP_PixelEncodingFormat pixel_format;
-
- bool aux_hpd;
- unsigned int evt;
- unsigned char HPDevents;
-
- uint32_t memReq, memReqPhy;
- DP_Config dpConfig = {.regBase = (struct MHDP_ApbRegs_s *)CSL_DSS_EDP0_V2A_CORE_VP_REGS_APB_BASE,
- .regBaseSapb = (struct MHDP_ApbRegs_s *)CSL_DSS_EDP0_V2A_S_CORE_VP_REGS_SAPB_BASE};
-
- DP_SD0801_Config phyCfg = {.regBase = (uint32_t*)CSL_SERDES_10G0_BASE,
- .regBaseDp = (struct DP_Regs_s *)CSL_DSS_EDP0_V2A_CORE_VP_REGS_APB_BASE};
-
- DP_PrivateData* pD = NULL;
- DP_SD0801_PrivateData* pDPhy = NULL;
- static uint8_t pdMem[STATIC_PD_SIZE] = { 0 };
- static uint8_t pdPhyMem[STATIC_PHY_PD_SIZE] = { 0 };
-
- *status = 0;
-
- num_lanes = 4;
- max_link_rate = 3;
- pixel_format = (DP_PixelEncodingFormat)1;
- bits_per_component = 8;
- vicMode = 130;
-
- DP_AudioVideoClkCfg audioVideoClkCfg = {
- .videoClockEnable = true,
- .audioClockEnable = true,
- .pktDataClockEnable = true
- };
-
- DP_VideoParameters videoParams = {
- .bitsPerSubpixel = bits_per_component,
- .pxEncFormat = pixel_format,
- .stereoVidAttr = DP_STEREO_VIDEO_LEFT,
- .btType = DP_BT_601,
- .forceMiscIgnoreBit = false,
- .alignment = DP_ALIGN_MSB, /* TI changed LSB to MSB */
- .dscEnable = 0
- };
- DP_FillVideoFormat(&videoParams.vicParams, (DP_VicModes)vicMode);
-
- DP_SourceDeviceCapabilities sourceCaps = {
- .maxLinkRate = (DP_LinkRate)max_link_rate,
- .laneCount = num_lanes,
- .ssc = false,
- .scramblerDisable = false,
- .tps3 = true,
- .tps4 = true,
- .fastLinkTraining = false,
- .maxVoltageSwing = 3,
- .maxPreemphasis = 2,
- .forceVoltageSwing = false,
- .forcePreemphasis = false,
- .laneMapping = DP_LANE_MAPPING_SINGLE_REGULAR,
- .controllersPerPhy = DP_SINGLE_CONTROLLER
- };
-
- DP_Probe(&dpConfig, &memReq);
- DP_SD0801_Probe(&phyCfg, &memReqPhy);
- if (memReq > sizeof(pdMem)) {
- *status = FVID2_EFAIL;
- }
- if (memReqPhy > sizeof(pdPhyMem)) {
- *status = FVID2_EFAIL;
- }
- pD = (void*)&pdMem[0];
- pDPhy = (void*)&pdPhyMem[0];
+ Dss_DctrlDisplayPortDrvObj *pObj = (Dss_DctrlDisplayPortDrvObj *)arg;
+ uint32_t evt;
+ uint32_t retVal;
- if (DP_Init(pD, &dpConfig, &(DP_Callbacks){.event = NULL})) {
- *status = FVID2_EFAIL;
- }
- if (DP_SD0801_Init(pDPhy, &phyCfg)) {
- *status = FVID2_EFAIL;
- }
- if (DP_SetPhyPd(pD, pDPhy)) {
- *status = FVID2_EFAIL;
+ retVal = DP_GetEvent(pObj->dpPrivData, &evt);
+ if((CDN_EOK == retVal) &&
+ (0 != (evt & DP_TX_HPD_EVENT)))
+ {
+ SwiP_post(pObj->swiHandle);
}
+}
- DP_SetClock(pD, &(DP_UcpuClock){.mhz = 125});
+static void Dss_dctrlDrvDpHpdWork(uintptr_t arg0, uintptr_t arg1)
+{
+ uint32_t retVal;
+ uint8_t hpdEvents;
+ uint32_t cookie;
+ uint32_t needLinkTraining = FALSE;
+ Dss_DctrlDisplayPortDrvObj *pObj = (Dss_DctrlDisplayPortDrvObj *)arg0;
+ DP_TrainingStatus trainingResult;
- // Run CPU
- DP_StartUcpu(pD);
+ cookie = HwiP_disable();
- ret = DP_WaitAlive(pD);
- if (EOK != ret)
+ /* We do not support HPD PULSE yet */
+ retVal = DP_ReadHpdEvent(pObj->dpPrivData, &hpdEvents);
+ if(CDN_EOK == retVal)
{
- *status = FVID2_EFAIL;
+ if((0U != (hpdEvents & DP_HPD_STATE)) &&
+ (0U != (hpdEvents & DP_HPD_TO_HIGH)))
+ {
+ /* we set connected = TRUE if LT passes */
+ pObj->isConnected = FALSE;
+ needLinkTraining = TRUE;
+ }
+ else
+ {
+ pObj->isConnected = FALSE;
+ }
}
- // Activate DisplayPort controller through mailbox
- ret = DP_MainControl(pD, 1, &resp);
- if (EOK != ret)
+ if((CDN_EOK == retVal) &&
+ (TRUE == needLinkTraining))
{
- *status = FVID2_EFAIL;
+ retVal = DP_LinkTraining(pObj->dpPrivData, &trainingResult);
+ if ((CDN_EOK == retVal) &&
+ (trainingResult == DP_LT_OK))
+ {
+ pObj->isConnected = TRUE;
+ }
}
- ret = DP_TestEchoExt(pD, echo_msg, echo_resp, sizeof(echo_msg), DP_BUS_TYPE_APB);
- if (EOK != ret)
+ /*
+ * If we just connected, check if REQUESTED or RUNNING
+ *
+ * If RUNNING, then start video
+ * If startVideo fails, go back to REQUESTED, so that we
+ * do not do anything unexpected when stopVideo is called
+ *
+ * If REQUESTED, then start video, and if it passes,
+ * set to RUNNING
+ *
+ * If we just disconnected, and we were previously RUNNING,
+ * we set to REQUESTED and stop video
+ */
+ if(TRUE == pObj->isConnected)
+ {
+ if((DP_VIDEO_STATE_REQUESTED == pObj->videoState) ||
+ (DP_VIDEO_STATE_RUNNING == pObj->videoState))
+ {
+ retVal = Dss_dctrlDrvDpStartVideo(pObj);
+ if(FVID2_SOK == retVal)
+ {
+ if(DP_VIDEO_STATE_REQUESTED == pObj->videoState)
+ {
+ pObj->videoState = DP_VIDEO_STATE_RUNNING;
+ }
+ }
+ else
+ {
+ if(DP_VIDEO_STATE_RUNNING == pObj->videoState)
+ {
+ pObj->videoState = DP_VIDEO_STATE_REQUESTED;
+ }
+ }
+ }
+ }
+ else
{
- *status = FVID2_EFAIL;
+ if(DP_VIDEO_STATE_RUNNING == pObj->videoState)
+ {
+ Dss_dctrlDrvDpStopVideo(pObj);
+ pObj->videoState = DP_VIDEO_STATE_REQUESTED;
+ }
}
+ HwiP_restore(cookie);
+}
- DP_ConfigurePhyAuxCtrl(pD);
+static int32_t Dss_dctrlDrvDpStopVideo(Dss_DctrlDisplayPortDrvObj *pObj)
+{
+ /* XXX framer off */
+ return FVID2_SOK;
+}
+
+static int32_t Dss_dctrlDrvDpStartVideo(Dss_DctrlDisplayPortDrvObj *pObj)
+{
+ int32_t retVal = FVID2_SOK;
+ int32_t dpApiRet = CDN_EOK;
+ DP_AudioVideoClkCfg clkCfg;
+ DP_VideoParameters videoParams;
+
+ clkCfg.videoClockEnable = true;
+ clkCfg.audioClockEnable = true;
+ clkCfg.pktDataClockEnable = true;
+
+ videoParams.bitsPerSubpixel = 8;
+ videoParams.pxEncFormat = DP_PXENC_PXL_RGB;
+ videoParams.stereoVidAttr = DP_STEREO_VIDEO_LEFT;
+ videoParams.btType = DP_BT_601;
+ videoParams.forceMiscIgnoreBit = false;
+ videoParams.alignment = DP_ALIGN_MSB;
+ videoParams.dscEnable = 0;
+
+ /* fill the ones the driver does not care about */
+ videoParams.vicParams.vic = 0U;
+ videoParams.vicParams.hFreq = 0.0;
+ videoParams.vicParams.vFreq = 0,0;
+ videoParams.vicParams.vicR = 0;
+ videoParams.vicParams.vicPR = 0;
+
+ /* and, now the actually important ones */
+ videoParams.vicParams.hActive = pObj->videoMode.width;
+ videoParams.vicParams.hSync = pObj->videoMode.hsw;
+ videoParams.vicParams.hFrontPorch = pObj->videoMode.hfp;
+ videoParams.vicParams.hBackPorch = pObj->videoMode.hbp;
+ videoParams.vicParams.hBlank = pObj->videoMode.hbp + pObj->videoMode.hfp + pObj->videoMode.hsw;
+ videoParams.vicParams.hTotal = videoParams.vicParams.hBlank + videoParams.vicParams.hActive;
+ videoParams.vicParams.vActive = pObj->videoMode.height;
+ videoParams.vicParams.vSync = pObj->videoMode.vsw;
+ videoParams.vicParams.vFrontPorch = pObj->videoMode.vfp;
+ videoParams.vicParams.vBackPorch = pObj->videoMode.vbp;
+ videoParams.vicParams.vBlank = pObj->videoMode.vbp + pObj->videoMode.vfp + pObj->videoMode.vsw;
+ videoParams.vicParams.vTotal = videoParams.vicParams.vBlank + videoParams.vicParams.vActive;
+ videoParams.vicParams.pxlFreq = pObj->videoMode.pclk / (float64_t)1000;
+ videoParams.vicParams.scanMode = ((FVID2_SF_PROGRESSIVE == pObj->videoMode.scanMode) ? DP_SM_PROGRESSIVE : DP_SM_INTERLACED);
+ videoParams.vicParams.hSyncPolarity = ((FVID2_POL_HIGH == pObj->videoMode.hsyncPol) ? DP_SP_ACTIVE_HIGH : DP_SP_ACTIVE_LOW);
+ videoParams.vicParams.vSyncPolarity = ((FVID2_POL_HIGH == pObj->videoMode.vsyncPol) ? DP_SP_ACTIVE_HIGH : DP_SP_ACTIVE_LOW);
+
+ if(CDN_EOK == dpApiRet)
+ {
+ dpApiRet = DP_SetVic(pObj->dpPrivData, 0, &videoParams);
+ if(CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_SetVic\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(CDN_EOK == dpApiRet)
+ {
+ dpApiRet = DP_SetAudioVideoClkCfg(pObj->dpPrivData, 0, &clkCfg);
+ if(CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_SetAudioVideoClkCfg\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
- do
+ if(CDN_EOK == dpApiRet)
{
- ret = DP_GetEvent(pD, &evt);
+ dpApiRet = DP_SetFramerEnable(pObj->dpPrivData, true);
+ if(CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_SetFramerEnable\r\n");
+ retVal = FVID2_EFAIL;
+ }
}
- while ((evt & 1) == 0);
- ret = DP_ReadHpdEvent(pD, &HPDevents);
- if ((ret = DP_GetHpdStatus(pD, &aux_hpd)) != EOK)
+ if(CDN_EOK == dpApiRet)
{
- *status = FVID2_EFAIL;
+ dpApiRet = DP_SetVideoSst(pObj->dpPrivData, true);
+ if(CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_SetVideoSst\r\n");
+ retVal = FVID2_EFAIL;
+ }
}
- DP_AuxStatus aux_sts;
- DP_DpcdTransfer transfer = {0};
+ return retVal;
+}
- uint8_t dpcd_resp_buff[16];
- transfer.buff = dpcd_resp_buff;
- DP_ReadEdidResponse edidResp;
- uint8_t edidBuff[128];
- edidResp.buff = edidBuff;
- unsigned char cs = 0;
+static int32_t Dss_dctrlDrvInitDPTX(void)
+{
+ Dss_DctrlDisplayPortDrvObj *pObj;
+ uint32_t memReqDp, memReqDpPhy;
+ HwiP_Params hwiParams;
+ SwiP_Params swiParams;
+ uint32_t dpApiRet;
+ int32_t retVal = FVID2_SOK;
- // Read 16 bytes of DPCD data from address 0x0000 through AUX interface
- // This fields represent the capability of sink device
+ pObj = &gDssDctrlDisplayPortDrvObj;
- transfer.size = 0x10;
- transfer.addr = 0x00;
- ret = DP_ReadDpcd(pD, &transfer);
+ pObj->dpCfg.regBase = (struct MHDP_ApbRegs_s *)CSL_DSS_EDP0_V2A_CORE_VP_REGS_APB_BASE;
+ pObj->dpCfg.regBaseSapb = (struct MHDP_ApbRegs_s *)CSL_DSS_EDP0_V2A_S_CORE_VP_REGS_SAPB_BASE;
- if (ret != EOK) {
- *status = FVID2_EFAIL;
- }
+ pObj->dpPhyCfg.regBase = (uint32_t*)CSL_SERDES_10G0_BASE;
+ pObj->dpPhyCfg.regBaseDp = (struct DP_Regs_s *)CSL_DSS_EDP0_V2A_CORE_VP_REGS_APB_BASE;
- // Example response: 12 0a c4 01 00 00 01 00 00 00 00 00 00 02 00 00
+ pObj->dpFWImage.iMem = gDctrlDpIram;
+ pObj->dpFWImage.iMemSize = DCTRL_DP_IMEM_SIZE;
+ pObj->dpFWImage.dMem = gDctrlDpDram;
+ pObj->dpFWImage.dMemSize = DCTRL_DP_DMEM_SIZE;
- ret = DP_GetAuxStatus(pD, &aux_sts);
- if (EOK != ret)
+ pObj->dpCbInfo.event = NULL;
+ pObj->dpClkInfo.mhz = 125;
+
+ pObj->srcCaps.maxLinkRate = DP_LINK_RATE_8_10;
+ pObj->srcCaps.laneCount = 4;
+ pObj->srcCaps.ssc = false;
+ pObj->srcCaps.scramblerDisable = false;
+ pObj->srcCaps.tps3 = true;
+ pObj->srcCaps.tps4 = true;
+ pObj->srcCaps.fastLinkTraining = false;
+ pObj->srcCaps.maxVoltageSwing = 3;
+ pObj->srcCaps.maxPreemphasis = 3;
+ pObj->srcCaps.forceVoltageSwing = false;
+ pObj->srcCaps.forcePreemphasis = false;
+ pObj->srcCaps.laneMapping = DP_LANE_MAPPING_SINGLE_REGULAR;
+ pObj->srcCaps.controllersPerPhy = DP_SINGLE_CONTROLLER;
+
+ pObj->isConnected = FALSE;
+ pObj->videoState = DP_VIDEO_STATE_IDLE;
+
+ if(FVID2_SOK == retVal)
{
- *status = FVID2_EFAIL;
+ dpApiRet = DP_Probe(&pObj->dpCfg, &memReqDp);
+ if((CDN_EOK != dpApiRet) ||
+ (memReqDp > DP_PRIVATE_DATA_SIZE))
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_Probe\r\n");
+ retVal = FVID2_EFAIL;
+ }
}
- // Sink response (0 ACK, 1 NACK, 2 DEFER,3 sink error (when there is no stop
- // condition), 4 bus error incorrect bus selected: regular or secure
-
- // Read EDID parameters of sink device through AUX interface
- if ((ret = DP_ReadEdid(pD, 0, 0, &edidResp)) != EOK) {
- *status = FVID2_EFAIL;
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_SD0801_Probe(&pObj->dpPhyCfg, &memReqDpPhy);
+ if ((CDN_EOK != dpApiRet) ||
+ (memReqDpPhy > DP_PHY_PRIVATE_DATA_SIZE))
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_SD0801_Probe\r\n");
+ retVal = FVID2_EFAIL;
+ }
}
- if (edidResp.size < 128) {
- *status = FVID2_EFAIL;
+ if(FVID2_SOK == retVal)
+ {
+ pObj->dpPrivData = (DP_PrivateData *)(&gDssDctrlDisplayPortDpPrivateData[0]);
+ pObj->dpPhyPrivData = (DP_SD0801_PrivateData *)(&gDssDctrlDisplayPortDpPhyPrivateData[0]);
+
+ dpApiRet = DP_Init(pObj->dpPrivData, &pObj->dpCfg, &pObj->dpCbInfo);
+ if (CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_Init\r\n");
+ retVal = FVID2_EFAIL;
+ }
}
- uint32_t i;
- for (i = 0; i < edidResp.size; i++) {
- cs += edidResp.buff[i];
+
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_SD0801_Init(pObj->dpPhyPrivData, &pObj->dpPhyCfg);
+ if (CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_SD0801_Init\r\n");
+ retVal = FVID2_EFAIL;
+ }
}
- if (cs != 0) {
- *status = FVID2_EFAIL;
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_SetPhyPd(pObj->dpPrivData, pObj->dpPhyPrivData);
+ if (CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_SetPhyPd\r\n");
+ retVal = FVID2_EFAIL;
+ }
}
- if (memcmp("\x00\xff\xff\xff\xff\xff\xff\x00", &edidResp.buff[0], 8) != 0) {
- *status = FVID2_EFAIL;
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_LoadFirmware(pObj->dpPrivData, &pObj->dpFWImage);
+ if (CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_LoadFirmware\r\n");
+ retVal = FVID2_EFAIL;
+ }
}
-
- DP_ConfigurePhyStartUp(pD, num_lanes,(DP_LinkRate)max_link_rate);
- // Settings DisplayPort controller capability
- ret = DP_SetSourceCapabilities(pD, &sourceCaps);
- if (EOK != ret)
+ if(FVID2_SOK == retVal)
{
- *status = FVID2_EFAIL;
+ dpApiRet = DP_SetClock(pObj->dpPrivData, &pObj->dpClkInfo);
+ if (CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_SetClock\r\n");
+ retVal = FVID2_EFAIL;
+ }
}
- DP_TrainingStatus trainingResult;
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_StartUcpu(pObj->dpPrivData);
+ if(CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_StartUcpu\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
- DP_SetPowerMode(pD, DP_POWER_NORMAL_OPERATION);
- ret = DP_LinkTraining(pD, &trainingResult);
- if (EOK != ret)
+ if(FVID2_SOK == retVal)
{
- *status = FVID2_EFAIL;
+ dpApiRet = DP_WaitAlive(pObj->dpPrivData);
+ if (CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_WaitAlive\r\n");
+ retVal = FVID2_EFAIL;
+ }
}
- switch (trainingResult) {
- case DP_LT_OK:
- break;
- case DP_LT_CR_FAIL:
- *status = -1;
- break;
- case DP_LT_EQ_FAIL:
- *status = -1;
- break;
- default:
- *status = -1;
+
+ if(FVID2_SOK == retVal)
+ {
+ uint8_t mainCtrlResp;
+
+ dpApiRet = DP_MainControl(pObj->dpPrivData, true, &mainCtrlResp);
+ if (CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_MainControl\r\n");
+ retVal = FVID2_EFAIL;
+ }
}
- if (0 != *status)
+
+ if(FVID2_SOK == retVal)
{
- return -1;
+ dpApiRet = DP_ConfigurePhyAuxCtrl(pObj->dpPrivData);
+ if (CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_ConfigurePhyAuxCtrl\r\n");
+ retVal = FVID2_EFAIL;
+ }
}
- Osal_delay(1000);
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_ConfigurePhyStartUp(pObj->dpPrivData,
+ pObj->srcCaps.laneCount,
+ pObj->srcCaps.maxLinkRate);
+ if(CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_ConfigurePhyStartUp\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
- ret = DP_SetVic(pD, 0, &videoParams);
- if (EOK != ret)
+ if(FVID2_SOK == retVal)
{
- *status = FVID2_EFAIL;
+ dpApiRet = DP_SetSourceCapabilities(pObj->dpPrivData, &pObj->srcCaps);
+ if (CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_SetSourceCapabilities\r\n");
+ retVal = FVID2_EFAIL;
+ }
}
- ret = DP_SetAudioVideoClkCfg(pD, 0, &audioVideoClkCfg);
- if (EOK != ret) {
- *status = FVID2_EFAIL;
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_SetPowerMode(pObj->dpPrivData, DP_POWER_NORMAL_OPERATION);
+ if (CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_SetPowerMode\r\n");
+ retVal = FVID2_EFAIL;
+ }
}
- // Enable framer
- ret = DP_SetFramerEnable(pD, true);
- if (EOK != ret)
+ if(FVID2_SOK == retVal)
{
- *status = FVID2_EFAIL;
+ dpApiRet = DP_Start(pObj->dpPrivData);
+ if(CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_Start\r\n");
+ retVal = FVID2_EFAIL;
+ }
}
- // Set video on
- ret = DP_SetVideoSst(pD, true);
- if (EOK != ret)
+ if(FVID2_SOK == retVal)
{
- *status = FVID2_EFAIL;
+ SwiP_Params_init(&swiParams);
+ swiParams.arg0 = (uintptr_t)pObj;
+
+ pObj->swiHandle = SwiP_create(Dss_dctrlDrvDpHpdWork, &swiParams);
+
+ if(NULL == pObj->swiHandle)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Cannot create HPD SWI");
+ retVal = FVID2_EALLOC;
+ }
}
- return 0;
+ if(FVID2_SOK == retVal)
+ {
+ HwiP_clearInterrupt(DP_INTR);
+
+ HwiP_Params_init(&hwiParams);
+ hwiParams.arg = (uintptr_t) pObj;
+
+ pObj->intrHandle = HwiP_create(DP_INTR,
+ &Dss_dctrlDrvDpIntr,
+ &hwiParams);
+ if(NULL == pObj->intrHandle)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Cannot Register IRQ");
+ retVal = FVID2_EALLOC;
+ }
+ }
+
+ return retVal;
}
index 7ab681bfd603fcf36d520e1c5459d3b9cf9c5ebe..f1692e9e37badfb089e401a3a31691516743f526 100755 (executable)
void Dss_dctrlDrvFreeEdgeList(Dss_DctrlDrvGraphObj *graphObj);
-int32_t Dss_dctrlDrvProgDP(void);
+#if defined(SOC_J721E)
+int32_t Dss_dctrlDrvDisableVideoDP(void);
+int32_t Dss_dctrlDrvEnableVideoDP(const Fvid2_ModeInfo *mInfo,
+ uint32_t hsyncPolarity,
+ uint32_t vsyncPolarity);
-uint32_t Dss_dctrlDrvProgDSI(void);
+int32_t Dss_dctrlDrvInitDp(void);
+#endif
/* ========================================================================== */
/* Static Function Definitions */