37ace553f134e2152664c4635cda952cc74004ab
1 /******************************************************************************\
2 * Copyright (C) 2000 Texas Instruments Incorporated.
3 * All Rights Reserved
4 *------------------------------------------------------------------------------
5 * FILENAME...... csl_chiphal.h
6 * DATE CREATED.. 14 Aug 2000
7 * LAST MODIFIED. 14 Jan 2004 Adding support for DRI300 versions (6410, 6413)
8 * 05 Aug 2003 Removing external control cregisters EM,ER,IN,OUT and DIER.
9 * 26 Jun 2003 Added support for 6411
10 * 17 Jun 2003 Added support for 6712C
11 * 28 May 2003 Added support for 6711C
12 * 05 Nov 2001 DM642 , 6411 remove 6400
13 * 03 Oct 2001 - CHIP_6713 - MCASP_SUPPORT - IIC_SUPPORT
14 * - PERCFG register
15 * - redefinition of CHIP_RSET() / CHIP_RGET()
16 * - new CHIP_CRSET() / CHIP_CRGET() => modification of csl_irq.h
17 * 04 Apr 2004- Removing external control cregisters EM,ER,IN,OUT and DIER.
18 * 12 Jan 2005- Removing external control cregisters FMCR,FADCR,FAUCR and GFPGFR
19 * 06 Apr 2005- Removing the macros ATLEN,ATLMEN and ADIV according to data manual
20 * tms320c6410(13)-sprs247 dated: Feb26 2004 specifications.
21 * 26 Jul 2005- Added C++ support.
22 *------------------------------------------------------------------------------
23 * REGISTERS
24 *
25 * CSR - control/status register
26 * IFR - interrupt flag register
27 * ISR - interrupt set register
28 * ICR - interrupt clear register
29 * IER - interrupt enable register
30 * ISTP - interrupt service table pointer register
31 * IRP - interrupt return pointer
32 * NRP - non-maskable interrupt return pointer
33 * AMR - addressing mode reister
34 * PERCFG - Device Configuration register (4)
35 * DEVSTAT - Device Status Register (5)
36 * JTAGID - JTAG ID register (5)
37 *
38 * (1) only supported on 67xx
39 * (2) only supported on floating point devices
40 * (3) only supported on 6411/14/15/16 devices
41 * (4) only supported on 6713/DA610/DM642/6412/6711C/6712C devices
42 * (5) only supported on DM642/6412/6410/6413 devices
43 *
44 \******************************************************************************/
45 #ifndef _CSL_CHIPHAL_H_
46 #define _CSL_CHIPHAL_H_
48 #include <csl_stdinc.h>
50 #ifdef __cplusplus
51 extern "C" {
52 #endif
55 /******************************************************************************\
56 * CHIP identification section
57 \******************************************************************************/
58 #ifdef CHIP_BASELINE
59 #undef CHIP_BASELINE
60 #define CHIP_BASELINE 1
61 #else
62 #define CHIP_BASELINE 0
63 #endif
65 #if (CHIP_BASELINE)
66 #define CHIP_6201 1
67 #endif
69 #ifdef CHIP_6201
70 #undef CHIP_6201
71 #define CHIP_6201 1
72 #else
73 #define CHIP_6201 0
74 #endif
76 #ifdef CHIP_6202
77 #undef CHIP_6202
78 #define CHIP_6202 1
79 #else
80 #define CHIP_6202 0
81 #endif
83 #ifdef CHIP_6203
84 #undef CHIP_6203
85 #define CHIP_6203 1
86 #else
87 #define CHIP_6203 0
88 #endif
90 #ifdef CHIP_6204
91 #undef CHIP_6204
92 #define CHIP_6204 1
93 #else
94 #define CHIP_6204 0
95 #endif
97 #ifdef CHIP_6205
98 #undef CHIP_6205
99 #define CHIP_6205 1
100 #else
101 #define CHIP_6205 0
102 #endif
104 #ifdef CHIP_6211
105 #undef CHIP_6211
106 #define CHIP_6211 1
107 #else
108 #define CHIP_6211 0
109 #endif
111 #ifdef CHIP_6701
112 #undef CHIP_6701
113 #define CHIP_6701 1
114 #else
115 #define CHIP_6701 0
116 #endif
118 #ifdef CHIP_6711
119 #undef CHIP_6711
120 #define CHIP_6711 1
121 #else
122 #define CHIP_6711 0
123 #endif
125 #ifdef CHIP_6712
126 #undef CHIP_6712
127 #define CHIP_6712 1
128 #else
129 #define CHIP_6712 0
130 #endif
133 #ifdef CHIP_6713
134 #undef CHIP_6713
135 #define CHIP_6713 1
136 #else
137 #define CHIP_6713 0
138 #endif
140 #ifdef CHIP_DA610
141 #undef CHIP_DA610
142 #define CHIP_DA610 1
143 #else
144 #define CHIP_DA610 0
145 #endif
147 #ifdef CHIP_DM642
148 #undef CHIP_DM642
149 #define CHIP_DM642 1
150 #else
151 #define CHIP_DM642 0
152 #endif
154 #ifdef CHIP_DM641
155 #undef CHIP_DM641
156 #define CHIP_DM641 1
157 #else
158 #define CHIP_DM641 0
159 #endif
161 #ifdef CHIP_DM640
162 #undef CHIP_DM640
163 #define CHIP_DM640 1
164 #else
165 #define CHIP_DM640 0
166 #endif
168 #ifdef CHIP_6412
169 #undef CHIP_6412
170 #define CHIP_6412 1
171 #else
172 #define CHIP_6412 0
173 #endif
175 #ifdef CHIP_6414
176 #undef CHIP_6414
177 #define CHIP_6414 1
178 #else
179 #define CHIP_6414 0
180 #endif
182 #ifdef CHIP_6415
183 #undef CHIP_6415
184 #define CHIP_6415 1
185 #else
186 #define CHIP_6415 0
187 #endif
189 #ifdef CHIP_6416
190 #undef CHIP_6416
191 #define CHIP_6416 1
192 #else
193 #define CHIP_6416 0
194 #endif
196 #ifdef CHIP_6711C
197 #undef CHIP_6711C
198 #define CHIP_6711C 1
199 #else
200 #define CHIP_6711C 0
201 #endif
203 #ifdef CHIP_6712C
204 #undef CHIP_6712C
205 #define CHIP_6712C 1
206 #else
207 #define CHIP_6712C 0
208 #endif
210 #ifdef CHIP_6411
211 #undef CHIP_6411
212 #define CHIP_6411 1
213 #else
214 #define CHIP_6411 0
215 #endif
217 /* next two are DRI300 versions */
218 #ifdef CHIP_6410
219 #undef CHIP_6410
220 #define CHIP_6410 1
221 #else
222 #define CHIP_6410 0
223 #endif
225 #ifdef CHIP_6413
226 #undef CHIP_6413
227 #define CHIP_6413 1
228 #else
229 #define CHIP_6413 0
230 #endif
232 #ifdef CHIP_6418
233 #undef CHIP_6418
234 #define CHIP_6418 1
235 #else
236 #define CHIP_6418 0
237 #endif\r
238 \r
239 /* Adding for DM6446 */\r
240 #ifdef CHIP_DM6446
241 #undef CHIP_DM6446
242 #define CHIP_DM6446 1
243 #else
244 #define CHIP_DM6446 0
245 #endif\r
248 #define CHIP_OROFALL (\
249 CHIP_6201 | \
250 CHIP_6202 | \
251 CHIP_6203 | \
252 CHIP_6204 | \
253 CHIP_6205 | \
254 CHIP_6211 | \
255 CHIP_6701 | \
256 CHIP_6711 | \
257 CHIP_6712 | \
258 CHIP_6713 | \
259 CHIP_DA610 | \
260 CHIP_DM642 | \
261 CHIP_DM641 | \
262 CHIP_DM640 | \
263 CHIP_6412 | \
264 CHIP_6414 | \
265 CHIP_6415 | \
266 CHIP_6416 | \
267 CHIP_6711C | \
268 CHIP_6712C | \
269 CHIP_6411 |\
270 CHIP_6410 |\
271 CHIP_6413 |\
272 CHIP_6418 \
273 )
275 #if (CHIP_OROFALL==0)
276 #error NO CHIP DEFINED (use -dCHIP_XXXX where XXXX is chip number, i.e. 6201)
277 #endif
279 #define CHIP_NONE 0
281 #define CHIP_SUPPORT(c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22,c23,c24) ( \
282 ( c0*CHIP_6201) | \
283 ( c1*CHIP_6202) | \
284 ( c2*CHIP_6203) | \
285 ( c3*CHIP_6204) | \
286 ( c4*CHIP_6205) | \
287 ( c5*CHIP_6211) | \
288 ( c6*CHIP_6701) | \
289 ( c7*CHIP_6711) | \
290 ( c8*CHIP_6712) | \
291 ( c9*CHIP_6713) | \
292 ( c10*CHIP_DA610)| \
293 ( c11*CHIP_DM642)| \
294 ( c12*CHIP_DM641)| \
295 ( c13*CHIP_DM640)| \
296 ( c14*CHIP_6412) | \
297 ( c15*CHIP_6414) | \
298 ( c16*CHIP_6415) | \
299 ( c17*CHIP_6416) | \
300 ( c18*CHIP_6711C) | \
301 ( c19*CHIP_6712C) | \
302 ( c20*CHIP_6411) | \
303 ( c21*CHIP_6410) | \
304 ( c22*CHIP_6413) | \
305 ( c23*CHIP_6418) | \
306 ( c24*CHIP_NONE) \
307 )
309 /*---------------------------------------------------------------------------------------*/
310 /* 6 6 6 6 6 6 6 6 6 6 D D D D 6 6 6 6 6 6 6 6 6 6 N */
311 /* 2 2 2 2 2 2 7 7 7 7 A M M M 4 4 4 4 7 7 4 4 4 4 O */
312 /* 0 0 0 0 0 1 0 1 1 1 6 6 6 6 1 1 1 1 1 1 1 1 1 1 N */
313 /* 1 2 3 4 5 1 1 1 2 3 1 4 4 4 2 4 5 6 1 2 1 0 3 8 E */
314 /* 0 2 1 0 C C */
315 /*---------------------------------------------------------------------------------------*/
316 #define CACHE_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
317 #define DMA_SUPPORT CHIP_SUPPORT(1,1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
318 #define EDMA_SUPPORT CHIP_SUPPORT(0,0,0,0,0,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
319 #define EMIF_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,0,0,0,0,0)
320 #define EMIFA_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0,1,1,1,1,0)
321 #define EMIFB_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0)
322 #define GPIO_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
323 #define HPI_SUPPORT CHIP_SUPPORT(1,0,0,0,0,1,1,1,0,1,1,1,1,0,1,1,1,1,1,0,1,1,1,1,0)
324 #define I2C_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0,0,0,0,0,1,1,1,0)
325 #define IRQ_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
326 #define MCASP_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,0)
327 #define MCBSP_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
328 #define PLL_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,1,1,0,0,0,0,0,0,0,1,1,0,0,0,0,0)
329 #define TIMER_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
330 #define XBUS_SUPPORT CHIP_SUPPORT(0,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
331 #define PCI_SUPPORT CHIP_SUPPORT(0,0,0,0,1,0,0,0,0,0,0,1,0,0,1,0,1,1,0,0,1,0,0,0,0)
332 /*---------------------------------------------------------------------------------------*/
333 /* 6 6 6 6 6 6 6 6 6 6 D D D D 6 6 6 6 6 6 6 6 6 6 N */
334 /* 2 2 2 2 2 2 7 7 7 7 A M M M 4 4 4 4 7 7 4 4 4 4 O */
335 /* 0 0 0 0 0 1 0 1 1 1 6 6 6 6 1 1 1 1 1 1 1 1 1 1 N */
336 /* 1 2 3 4 5 1 1 1 2 3 1 4 4 4 2 4 5 6 1 2 1 0 3 8 E */
337 /* 0 2 1 0 C C */
338 /*---------------------------------------------------------------------------------------*/
339 #define VP_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,0)
340 #define VIC_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,0)
341 #define DAT_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
342 #define PWR_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
343 #define UTOP_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,0,0,0,0,0,0,0)
344 #define TCP_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0)
345 #define VCP_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,1,0)
346 #define EMAC_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,0,0,0,0,0,0,0,0,0,0)
347 #define MDIO_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,0,0,0,0,0,0,0,0,0,0)
348 #define EMU_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0)
350 #define L2CACHE_SUPPORT CHIP_SUPPORT(0,0,0,0,0,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
351 #define TC_SUPPORT CHIP_SUPPORT(0,0,0,0,0,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
352 #define FPU_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,1,1,1,1,1,0,0,0,0,0,0,0,1,1,0,0,0,0,0)
353 #define C01_SUPPORT CHIP_SUPPORT(1,1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
354 #define C11_SUPPORT CHIP_SUPPORT(0,0,0,0,0,1,0,1,1,1,1,0,0,0,0,0,0,0,1,1,0,0,0,0,0)
355 #define C64_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0,1,1,1,1,0)
356 #define ATL_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,0)
358 #define CACHE_L2_SUPPORT L2CACHE_SUPPORT
359 /*----------------------------------------------------------------------*/
362 /******************************************************************************\
363 * module level register/field access macros
364 \******************************************************************************/
366 /* ----------------- */
367 /* FIELD MAKE MACROS */
368 /* ----------------- */
370 #define CHIP_FMK(REG,FIELD,x)\
371 _PER_FMK(CHIP,##REG,##FIELD,x)
373 #define CHIP_FMKS(REG,FIELD,SYM)\
374 _PER_FMKS(CHIP,##REG,##FIELD,##SYM)
377 /* -------------------------------- */
378 /* RAW REGISTER/FIELD ACCESS MACROS */
379 /* -------------------------------- */
381 #define CHIP_CRGET(REG)\
382 _PER_CRGET(CHIP,##REG)
384 #define CHIP_CRSET(REG,x)\
385 _PER_CRSET(CHIP,##REG,x)
387 #define CHIP_RGET(REG)\
388 _PER_RGET(_CHIP_##REG##_ADDR,CHIP,##REG)
390 #define CHIP_RSET(REG,x)\
391 _PER_RSET(_CHIP_##REG##_ADDR,CHIP,##REG,x)
394 #define CHIP_FGET(REG,FIELD)\
395 _CHIP_##REG##_FGET(##FIELD)
397 #define CHIP_FSET(REG,FIELD,x)\
398 _CHIP_##REG##_FSET(##FIELD,x)
400 #define CHIP_FSETS(REG,FIELD,SYM)\
401 _CHIP_##REG##_FSETS(##FIELD,##SYM)
404 /******************************************************************************\
405 * _____________________
406 * | |
407 * | C S R |
408 * |___________________|
409 *
410 * CSR - control/status register
411 *
412 * FIELDS (msb -> lsb)
413 * (r) CPUID
414 * (r) REVID
415 * (rw) PWRD
416 * (rc) SAT
417 * (r) EN
418 * (rw) PCC
419 * (rw) DCC
420 * (rw) PGIE
421 * (rw) GIE
422 *
423 \******************************************************************************/
424 extern far cregister volatile unsigned int CSR;
426 #define _CHIP_CSR_CPUID_MASK 0xFF000000u
427 #define _CHIP_CSR_CPUID_SHIFT 0x00000018u
428 #define CHIP_CSR_CPUID_DEFAULT 0x00000000u
429 #define CHIP_CSR_CPUID_OF(x) _VALUEOF(x)
430 #define CHIP_CSR_CPUID_C62X 0x00000000u
431 #define CHIP_CSR_CPUID_C67X 0x00000002u
432 #define CHIP_CSR_CPUID_C64X 0x00000004u
434 #define _CHIP_CSR_REVID_MASK 0x00FF0000u
435 #define _CHIP_CSR_REVID_SHIFT 0x00000010u
436 #define CHIP_CSR_REVID_DEFAULT 0x00000000u
437 #define CHIP_CSR_REVID_OF(x) _VALUEOF(x)
438 #define CHIP_CSR_REVID_620120 0x00000001u
439 #define CHIP_CSR_REVID_620121 0x00000001u
440 #define CHIP_CSR_REVID_620130 0x00000002u
441 #define CHIP_CSR_REVID_670100 0x00000201u
442 #define CHIP_CSR_REVID_670110 0x00000202u
443 #define CHIP_CSR_REVID_621110 0x00000002u
444 #define CHIP_CSR_REVID_640010 0x00000801u
445 #define CHIP_CSR_REVID_6202 0x00000002u
446 #define CHIP_CSR_REVID_6202B 0x00000003u
447 #define CHIP_CSR_REVID_6711 0x00000002u
448 #define CHIP_CSR_REVID_6711C 0x00000003u
449 #define CHIP_CSR_REVID_6712 0x00000002u
450 #define CHIP_CSR_REVID_6712C 0x00000003u
452 #define _CHIP_CSR_PWRD_MASK 0x0000FC00u
453 #define _CHIP_CSR_PWRD_SHIFT 0x0000000Au
454 #define CHIP_CSR_PWRD_DEFAULT 0x00000000u
455 #define CHIP_CSR_PWRD_OF(x) _VALUEOF(x)
456 #define CHIP_CSR_PWRD_NONE 0x00000000u
457 #define CHIP_CSR_PWRD_PD1A 0x00000009u
458 #define CHIP_CSR_PWRD_PD1B 0x00000011u
459 #define CHIP_CSR_PWRD_PD2 0x0000001Au
460 #define CHIP_CSR_PWRD_PD3 0x0000001Cu
462 #define _CHIP_CSR_SAT_MASK 0x00000200u
463 #define _CHIP_CSR_SAT_SHIFT 0x00000009u
464 #define CHIP_CSR_SAT_DEFAULT 0x00000000u
465 #define CHIP_CSR_SAT_OF(x) _VALUEOF(x)
466 #define CHIP_CSR_SAT_0 0x00000000u
467 #define CHIP_CSR_SAT_1 0x00000001u
469 #define _CHIP_CSR_EN_MASK 0x00000100u
470 #define _CHIP_CSR_EN_SHIFT 0x00000008u
471 #define CHIP_CSR_EN_DEFAULT 0x00000000u
472 #define CHIP_CSR_EN_OF(x) _VALUEOF(x)
473 #define CHIP_CSR_EN_BIG 0x00000000u
474 #define CHIP_CSR_EN_LITTLE 0x00000001u
476 #define _CHIP_CSR_PCC_MASK 0x000000E0u
477 #define _CHIP_CSR_PCC_SHIFT 0x00000005u
478 #define CHIP_CSR_PCC_DEFAULT 0x00000000u
479 #define CHIP_CSR_PCC_OF(x) _VALUEOF(x)
480 #define CHIP_CSR_PCC_MAPPED 0x00000000u
481 #define CHIP_CSR_PCC_ENABLE 0x00000002u
482 #define CHIP_CSR_PCC_FREEZE 0x00000003u
483 #define CHIP_CSR_PCC_BYPASS 0x00000004u
485 #define _CHIP_CSR_DCC_MASK 0x0000001Cu
486 #define _CHIP_CSR_DCC_SHIFT 0x00000002u
487 #define CHIP_CSR_DCC_DEFAULT 0x00000000u
488 #define CHIP_CSR_DCC_OF(x) _VALUEOF(x)
489 #define CHIP_CSR_DCC_MAPPED 0x00000000u
490 #define CHIP_CSR_DCC_ENABLE 0x00000002u
491 #define CHIP_CSR_DCC_FREEZE 0x00000003u
492 #define CHIP_CSR_DCC_BYPASS 0x00000004u
494 #define _CHIP_CSR_PGIE_MASK 0x00000002u
495 #define _CHIP_CSR_PGIE_SHIFT 0x00000001u
496 #define CHIP_CSR_PGIE_DEFAULT 0x00000000u
497 #define CHIP_CSR_PGIE_OF(x) _VALUEOF(x)
498 #define CHIP_CSR_PGIE_0 0x00000000u
499 #define CHIP_CSR_PGIE_1 0x00000001u
501 #define _CHIP_CSR_GIE_MASK 0x00000001u
502 #define _CHIP_CSR_GIE_SHIFT 0x00000000u
503 #define CHIP_CSR_GIE_DEFAULT 0x00000000u
504 #define CHIP_CSR_GIE_OF(x) _VALUEOF(x)
505 #define CHIP_CSR_GIE_0 0x00000000u
506 #define CHIP_CSR_GIE_1 0x00000001u
508 #define CHIP_CSR_OF(x) _VALUEOF(x)
510 #define CHIP_CSR_DEFAULT (Uint32)( \
511 _PER_FDEFAULT(CHIP,CSR,CPUID) \
512 |_PER_FDEFAULT(CHIP,CSR,REVID) \
513 |_PER_FDEFAULT(CHIP,CSR,PWRD) \
514 |_PER_FDEFAULT(CHIP,CSR,SAT) \
515 |_PER_FDEFAULT(CHIP,CSR,EN) \
516 |_PER_FDEFAULT(CHIP,CSR,PCC) \
517 |_PER_FDEFAULT(CHIP,CSR,DCC) \
518 |_PER_FDEFAULT(CHIP,CSR,PGIE) \
519 |_PER_FDEFAULT(CHIP,CSR,GIE) \
520 )
522 #define CHIP_CSR_RMK(pwrd,pcc,dcc,pgie,gie) (Uint32)( \
523 _PER_FMK(CHIP,CSR,PWRD,pwrd) \
524 |_PER_FMK(CHIP,CSR,PCC,pcc) \
525 |_PER_FMK(CHIP,CSR,DCC,dcc) \
526 |_PER_FMK(CHIP,CSR,PGIE,pgie) \
527 |_PER_FMK(CHIP,CSR,GIE,gie) \
528 )
530 #define _CHIP_CSR_FGET(FIELD)\
531 _PER_CFGET(CHIP,CSR,##FIELD)
533 #define _CHIP_CSR_FSET(FIELD,field)\
534 _PER_CFSET(CHIP,CSR,##FIELD,field)
536 #define _CHIP_CSR_FSETS(FIELD,SYM)\
537 _PER_CFSETS(CHIP,CSR,##FIELD,##SYM)
540 /******************************************************************************\
541 * _____________________
542 * | |
543 * | I F R |
544 * |___________________|
545 *
546 * IFR - interruppt flag register
547 *
548 * FIELDS (msb -> lsb)
549 * (rw) IF
550 *
551 \******************************************************************************/
552 extern far cregister volatile unsigned int IFR;
554 #define _CHIP_IFR_IF_MASK 0x0000FFFFu
555 #define _CHIP_IFR_IF_SHIFT 0x00000000u
556 #define CHIP_IFR_IF_DEFAULT 0x00000000u
557 #define CHIP_IFR_IF_OF(x) _VALUEOF(x)
559 #define CHIP_IFR_OF(x) _VALUEOF(x)
561 #define CHIP_IFR_DEFAULT (Uint32)( \
562 _PER_FDEFAULT(CHIP,IFR,IF)\
563 )
565 #define CHIP_IFR_RMK(if) (Uint32)( \
566 _PER_FMK(CHIP,IFR,IF,if)\
567 )
569 #define _CHIP_IFR_FGET(FIELD)\
570 _PER_CFGET(CHIP,IFR,##FIELD)
572 #define _CHIP_IFR_FSET(FIELD,field)\
573 _PER_CFSET(CHIP,IFR,##FIELD,field)
575 #define _CHIP_IFR_FSETS(FIELD,SYM)\
576 _PER_CFSETS(CHIP,IFR,##FIELD,##SYM)
579 /******************************************************************************\
580 * _____________________
581 * | |
582 * | I S R |
583 * |___________________|
584 *
585 * ISR - interruppt set register
586 *
587 * FIELDS (msb -> lsb)
588 * (w) IS
589 *
590 \******************************************************************************/
591 extern far cregister volatile unsigned int ISR;
593 #define _CHIP_ISR_IS_MASK 0x0000FFFFu
594 #define _CHIP_ISR_IS_SHIFT 0x00000000u
595 #define CHIP_ISR_IS_DEFAULT 0x00000000u
596 #define CHIP_ISR_IS_OF(x) _VALUEOF(x)
598 #define CHIP_ISR_OF(x) _VALUEOF(x)
600 #define CHIP_ISR_DEFAULT (Uint32)( \
601 _PER_FDEFAULT(CHIP,ISR,IS)\
602 )
604 #define CHIP_ISR_RMK(is) (Uint32)( \
605 _PER_FMK(CHIP,ISR,IS,is)\
606 )
608 #define _CHIP_ISR_FGET(FIELD)\
609 _PER_CFGET(CHIP,ISR,##FIELD)
611 #define _CHIP_ISR_FSET(FIELD,field)\
612 _PER_CFSET(CHIP,ISR,##FIELD,field)
614 #define _CHIP_ISR_FSETS(FIELD,SYM)\
615 _PER_CFSETS(CHIP,ISR,##FIELD,##SYM)
618 /******************************************************************************\
619 * _____________________
620 * | |
621 * | I C R |
622 * |___________________|
623 *
624 * ICR - interruppt clear register
625 *
626 * FIELDS (msb -> lsb)
627 * (w) IC
628 *
629 \******************************************************************************/
630 extern far cregister volatile unsigned int ICR;
632 #define _CHIP_ICR_IC_MASK 0x0000FFFFu
633 #define _CHIP_ICR_IC_SHIFT 0x00000000u
634 #define CHIP_ICR_IC_DEFAULT 0x00000000u
635 #define CHIP_ICR_IC_OF(x) _VALUEOF(x)
637 #define CHIP_ICR_OF(x) _VALUEOF(x)
639 #define CHIP_ICR_DEFAULT (Uint32)( \
640 _PER_FDEFAULT(CHIP,ICR,IC)\
641 )
643 #define CHIP_ICR_RMK(ic) (Uint32)( \
644 _PER_FMK(CHIP,ICR,IC,ic)\
645 )
647 #define _CHIP_ICR_FGET(FIELD)\
648 _PER_CFGET(CHIP,ICR,##FIELD)
650 #define _CHIP_ICR_FSET(FIELD,field)\
651 _PER_CFSET(CHIP,ICR,##FIELD,field)
653 #define _CHIP_ICR_FSETS(FIELD,SYM)\
654 _PER_CFSETS(CHIP,ICR,##FIELD,##SYM)
657 /******************************************************************************\
658 * _____________________
659 * | |
660 * | I E R |
661 * |___________________|
662 *
663 * IER - interruppt enable register
664 *
665 * FIELDS (msb -> lsb)
666 * (rw) IE
667 *
668 \******************************************************************************/
669 extern far cregister volatile unsigned int IER;
671 #define _CHIP_IER_IE_MASK 0x0000FFFFu
672 #define _CHIP_IER_IE_SHIFT 0x00000000u
673 #define CHIP_IER_IE_DEFAULT 0x00000000u
674 #define CHIP_IER_IE_OF(x) _VALUEOF(x)
676 #define CHIP_IER_OF(x) _VALUEOF(x)
678 #define CHIP_IER_DEFAULT (Uint32)( \
679 _PER_FDEFAULT(CHIP,IER,IE)\
680 )
682 #define CHIP_IER_RMK(ie) (Uint32)( \
683 _PER_FMK(CHIP,IER,IE,ie)\
684 )
686 #define _CHIP_IER_FGET(FIELD)\
687 _PER_CFGET(CHIP,IER,##FIELD)
689 #define _CHIP_IER_FSET(FIELD,field)\
690 _PER_CFSET(CHIP,IER,##FIELD,field)
692 #define _CHIP_IER_FSETS(FIELD,SYM)\
693 _PER_CFSETS(CHIP,IER,##FIELD,##SYM)
696 /******************************************************************************\
697 * _____________________
698 * | |
699 * | I S T P |
700 * |___________________|
701 *
702 * ISTP - interrupt service table pointer
703 *
704 * FIELDS (msb -> lsb)
705 * (r) HPEINT
706 * (rw) ISTB
707 *
708 \******************************************************************************/
709 extern far cregister volatile unsigned int ISTP;
711 #define _CHIP_ISTP_ISTB_MASK 0xFFFFFC00u
712 #define _CHIP_ISTP_ISTB_SHIFT 0x0000000Au
713 #define CHIP_ISTP_ISTB_DEFAULT 0x00000000u
714 #define CHIP_ISTP_ISTB_OF(x) _VALUEOF(x)
716 #define _CHIP_ISTP_HPEINT_MASK 0x000003E0u
717 #define _CHIP_ISTP_HPEINT_SHIFT 0x00000005u
718 #define CHIP_ISTP_HPEINT_DEFAULT 0x00000000u
719 #define CHIP_ISTP_HPEINT_OF(x) _VALUEOF(x)
721 #define CHIP_ISTP_OF(x) _VALUEOF(x)
723 #define CHIP_ISTP_DEFAULT (Uint32)( \
724 _PER_FDEFAULT(CHIP,ISTP,ISTB)\
725 |_PER_FDEFAULT(CHIP,ISTP,HPEINT)\
726 )
728 #define CHIP_ISTP_RMK(istb) (Uint32)( \
729 _PER_FMK(CHIP,ISTP,ISTB,istb)\
730 )
732 #define _CHIP_ISTP_FGET(FIELD)\
733 _PER_CFGET(CHIP,ISTP,##FIELD)
735 #define _CHIP_ISTP_FSET(FIELD,field)\
736 _PER_CFSET(CHIP,ISTP,##FIELD,field)
738 #define _CHIP_ISTP_FSETS(FIELD,SYM)\
739 _PER_CFSETS(CHIP,ISTP,##FIELD,##SYM)
742 /******************************************************************************\
743 * _____________________
744 * | |
745 * | I R P |
746 * |___________________|
747 *
748 * IRP - interrupt return pointer
749 *
750 * FIELDS (msb -> lsb)
751 * (rw) IRP
752 *
753 \******************************************************************************/
754 extern far cregister volatile unsigned int IRP;
756 #define _CHIP_IRP_IRP_MASK 0xFFFFFFFFu
757 #define _CHIP_IRP_IRP_SHIFT 0x00000000u
758 #define CHIP_IRP_IRP_DEFAULT 0x00000000u
759 #define CHIP_IRP_IRP_OF(x) _VALUEOF(x)
761 #define CHIP_IRP_OF(x) _VALUEOF(x)
763 #define CHIP_IRP_DEFAULT (Uint32)( \
764 _PER_FDEFAULT(CHIP,IRP,IRP)\
765 )
767 #define CHIP_IRP_RMK(irp) (Uint32)( \
768 _PER_FMK(CHIP,IRP,IRP,irp)\
769 )
771 #define _CHIP_IRP_FGET(FIELD)\
772 _PER_CFGET(CHIP,IRP,##FIELD)
774 #define _CHIP_IRP_FSET(FIELD,field)\
775 _PER_CFSET(CHIP,IRP,##FIELD,field)
777 #define _CHIP_IRP_FSETS(FIELD,SYM)\
778 _PER_CFSETS(CHIP,IRP,##FIELD,##SYM)
781 /******************************************************************************\
782 * _____________________
783 * | |
784 * | N R P |
785 * |___________________|
786 *
787 * NRP - non-maskable interrupt return pointer
788 *
789 * FIELDS (msb -> lsb)
790 * (rw) NRP
791 *
792 \******************************************************************************/
793 extern far cregister volatile unsigned int NRP;
795 #define _CHIP_NRP_NRP_MASK 0xFFFFFFFFu
796 #define _CHIP_NRP_NRP_SHIFT 0x00000000u
797 #define CHIP_NRP_NRP_DEFAULT 0x00000000u
798 #define CHIP_NRP_NRP_OF(x) _VALUEOF(x)
800 #define CHIP_NRP_OF(x) _VALUEOF(x)
802 #define CHIP_NRP_DEFAULT (Uint32)( \
803 _PER_FDEFAULT(CHIP,NRP,NRP)\
804 )
806 #define CHIP_NRP_RMK(nrp) (Uint32)( \
807 _PER_FMK(CHIP,NRP,NRP,nrp)\
808 )
810 #define _CHIP_NRP_FGET(FIELD)\
811 _PER_CFGET(CHIP,NRP,##FIELD)
813 #define _CHIP_NRP_FSET(FIELD,field)\
814 _PER_CFSET(CHIP,NRP,##FIELD,field)
816 #define _CHIP_NRP_FSETS(FIELD,SYM)\
817 _PER_CFSETS(CHIP,NRP,##FIELD,##SYM)
820 /******************************************************************************\
821 * _____________________
822 * | |
823 * | A M R |
824 * |___________________|
825 *
826 * AMR - addressing mode register
827 *
828 * FIELDS (msb -> lsb)
829 * (rw) BK1
830 * (rw) BK0
831 * (rw) B7MODE
832 * (rw) B6MODE
833 * (rw) B5MODE
834 * (rw) B4MODE
835 * (rw) A7MODE
836 * (rw) A6MODE
837 * (rw) A5MODE
838 * (rw) A4MODE
839 *
840 \******************************************************************************/
841 extern far cregister volatile unsigned int AMR;
843 #define _CHIP_AMR_BK1_MASK 0x02E00000u
844 #define _CHIP_AMR_BK1_SHIFT 0x00000015u
845 #define CHIP_AMR_BK1_DEFAULT 0x00000000u
846 #define CHIP_AMR_BK1_OF(x) _VALUEOF(x)
847 #define CHIP_AMR_BK1_2 0x00000000u
848 #define CHIP_AMR_BK1_4 0x00000001u
849 #define CHIP_AMR_BK1_8 0x00000002u
850 #define CHIP_AMR_BK1_16 0x00000003u
851 #define CHIP_AMR_BK1_32 0x00000004u
852 #define CHIP_AMR_BK1_64 0x00000005u
853 #define CHIP_AMR_BK1_128 0x00000006u
854 #define CHIP_AMR_BK1_256 0x00000007u
855 #define CHIP_AMR_BK1_512 0x00000008u
856 #define CHIP_AMR_BK1_1K 0x00000009u
857 #define CHIP_AMR_BK1_2K 0x0000000Au
858 #define CHIP_AMR_BK1_4K 0x0000000Bu
859 #define CHIP_AMR_BK1_8K 0x0000000Cu
860 #define CHIP_AMR_BK1_16K 0x0000000Du
861 #define CHIP_AMR_BK1_32K 0x0000000Eu
862 #define CHIP_AMR_BK1_64K 0x0000000Fu
863 #define CHIP_AMR_BK1_128K 0x00000010u
864 #define CHIP_AMR_BK1_256K 0x00000011u
865 #define CHIP_AMR_BK1_512K 0x00000012u
866 #define CHIP_AMR_BK1_1M 0x00000013u
867 #define CHIP_AMR_BK1_2M 0x00000014u
868 #define CHIP_AMR_BK1_4M 0x00000015u
869 #define CHIP_AMR_BK1_8M 0x00000016u
870 #define CHIP_AMR_BK1_16M 0x00000017u
871 #define CHIP_AMR_BK1_32M 0x00000018u
872 #define CHIP_AMR_BK1_64M 0x00000019u
873 #define CHIP_AMR_BK1_128M 0x0000001Au
874 #define CHIP_AMR_BK1_256M 0x0000001Bu
875 #define CHIP_AMR_BK1_512M 0x0000001Cu
876 #define CHIP_AMR_BK1_1G 0x0000001Du
877 #define CHIP_AMR_BK1_2G 0x0000001Eu
878 #define CHIP_AMR_BK1_4G 0x0000001Fu
880 #define _CHIP_AMR_BK0_MASK 0x001F0000u
881 #define _CHIP_AMR_BK0_SHIFT 0x00000010u
882 #define CHIP_AMR_BK0_DEFAULT 0x00000000u
883 #define CHIP_AMR_BK0_OF(x) _VALUEOF(x)
884 #define CHIP_AMR_BK0_2 0x00000000u
885 #define CHIP_AMR_BK0_4 0x00000001u
886 #define CHIP_AMR_BK0_8 0x00000002u
887 #define CHIP_AMR_BK0_16 0x00000003u
888 #define CHIP_AMR_BK0_32 0x00000004u
889 #define CHIP_AMR_BK0_64 0x00000005u
890 #define CHIP_AMR_BK0_128 0x00000006u
891 #define CHIP_AMR_BK0_256 0x00000007u
892 #define CHIP_AMR_BK0_512 0x00000008u
893 #define CHIP_AMR_BK0_1K 0x00000009u
894 #define CHIP_AMR_BK0_2K 0x0000000Au
895 #define CHIP_AMR_BK0_4K 0x0000000Bu
896 #define CHIP_AMR_BK0_8K 0x0000000Cu
897 #define CHIP_AMR_BK0_16K 0x0000000Du
898 #define CHIP_AMR_BK0_32K 0x0000000Eu
899 #define CHIP_AMR_BK0_64K 0x0000000Fu
900 #define CHIP_AMR_BK0_128K 0x00000010u
901 #define CHIP_AMR_BK0_256K 0x00000011u
902 #define CHIP_AMR_BK0_512K 0x00000012u
903 #define CHIP_AMR_BK0_1M 0x00000013u
904 #define CHIP_AMR_BK0_2M 0x00000014u
905 #define CHIP_AMR_BK0_4M 0x00000015u
906 #define CHIP_AMR_BK0_8M 0x00000016u
907 #define CHIP_AMR_BK0_16M 0x00000017u
908 #define CHIP_AMR_BK0_32M 0x00000018u
909 #define CHIP_AMR_BK0_64M 0x00000019u
910 #define CHIP_AMR_BK0_128M 0x0000001Au
911 #define CHIP_AMR_BK0_256M 0x0000001Bu
912 #define CHIP_AMR_BK0_512M 0x0000001Cu
913 #define CHIP_AMR_BK0_1G 0x0000001Du
914 #define CHIP_AMR_BK0_2G 0x0000001Eu
915 #define CHIP_AMR_BK0_4G 0x0000001Fu
918 #define _CHIP_AMR_B7MODE_MASK 0x0000C000u
919 #define _CHIP_AMR_B7MODE_SHIFT 0x0000000Eu
920 #define CHIP_AMR_B7MODE_DEFAULT 0x00000000u
921 #define CHIP_AMR_B7MODE_OF(x) _VALUEOF(x)
922 #define CHIP_AMR_B7MODE_LINEAR 0x00000000u
923 #define CHIP_AMR_B7MODE_CIRCULAR0 0x00000001u
924 #define CHIP_AMR_B7MODE_CIRCULAR1 0x00000002u
926 #define _CHIP_AMR_B6MODE_MASK 0x00003000u
927 #define _CHIP_AMR_B6MODE_SHIFT 0x0000000Cu
928 #define CHIP_AMR_B6MODE_DEFAULT 0x00000000u
929 #define CHIP_AMR_B6MODE_OF(x) _VALUEOF(x)
930 #define CHIP_AMR_B6MODE_LINEAR 0x00000000u
931 #define CHIP_AMR_B6MODE_CIRCULAR0 0x00000001u
932 #define CHIP_AMR_B6MODE_CIRCULAR1 0x00000002u
934 #define _CHIP_AMR_B5MODE_MASK 0x00000C00u
935 #define _CHIP_AMR_B5MODE_SHIFT 0x0000000Au
936 #define CHIP_AMR_B5MODE_DEFAULT 0x00000000u
937 #define CHIP_AMR_B5MODE_OF(x) _VALUEOF(x)
938 #define CHIP_AMR_B5MODE_LINEAR 0x00000000u
939 #define CHIP_AMR_B5MODE_CIRCULAR0 0x00000001u
940 #define CHIP_AMR_B5MODE_CIRCULAR1 0x00000002u
942 #define _CHIP_AMR_B4MODE_MASK 0x00000300u
943 #define _CHIP_AMR_B4MODE_SHIFT 0x00000008u
944 #define CHIP_AMR_B4MODE_DEFAULT 0x00000000u
945 #define CHIP_AMR_B4MODE_OF(x) _VALUEOF(x)
946 #define CHIP_AMR_B4MODE_LINEAR 0x00000000u
947 #define CHIP_AMR_B4MODE_CIRCULAR0 0x00000001u
948 #define CHIP_AMR_B4MODE_CIRCULAR1 0x00000002u
950 #define _CHIP_AMR_A7MODE_MASK 0x000000C0u
951 #define _CHIP_AMR_A7MODE_SHIFT 0x00000006u
952 #define CHIP_AMR_A7MODE_DEFAULT 0x00000000u
953 #define CHIP_AMR_A7MODE_OF(x) _VALUEOF(x)
954 #define CHIP_AMR_A7MODE_LINEAR 0x00000000u
955 #define CHIP_AMR_A7MODE_CIRCULAR0 0x00000001u
956 #define CHIP_AMR_A7MODE_CIRCULAR1 0x00000002u
958 #define _CHIP_AMR_A6MODE_MASK 0x00000030u
959 #define _CHIP_AMR_A6MODE_SHIFT 0x00000004u
960 #define CHIP_AMR_A6MODE_DEFAULT 0x00000000u
961 #define CHIP_AMR_A6MODE_OF(x) _VALUEOF(x)
962 #define CHIP_AMR_A6MODE_LINEAR 0x00000000u
963 #define CHIP_AMR_A6MODE_CIRCULAR0 0x00000001u
964 #define CHIP_AMR_A6MODE_CIRCULAR1 0x00000002u
966 #define _CHIP_AMR_A5MODE_MASK 0x0000000Cu
967 #define _CHIP_AMR_A5MODE_SHIFT 0x00000002u
968 #define CHIP_AMR_A5MODE_DEFAULT 0x00000000u
969 #define CHIP_AMR_A5MODE_OF(x) _VALUEOF(x)
970 #define CHIP_AMR_A5MODE_LINEAR 0x00000000u
971 #define CHIP_AMR_A5MODE_CIRCULAR0 0x00000001u
972 #define CHIP_AMR_A5MODE_CIRCULAR1 0x00000002u
974 #define _CHIP_AMR_A4MODE_MASK 0x00000003u
975 #define _CHIP_AMR_A4MODE_SHIFT 0x00000000u
976 #define CHIP_AMR_A4MODE_DEFAULT 0x00000000u
977 #define CHIP_AMR_A4MODE_OF(x) _VALUEOF(x)
978 #define CHIP_AMR_A4MODE_LINEAR 0x00000000u
979 #define CHIP_AMR_A4MODE_CIRCULAR0 0x00000001u
980 #define CHIP_AMR_A4MODE_CIRCULAR1 0x00000002u
982 #define CHIP_AMR_OF(x) _VALUEOF(x)
984 #define CHIP_AMR_DEFAULT (Uint32)( \
985 _PER_FDEFAULT(CHIP,AMR,BK1)\
986 |_PER_FDEFAULT(CHIP,AMR,BK0)\
987 |_PER_FDEFAULT(CHIP,AMR,B7MODE)\
988 |_PER_FDEFAULT(CHIP,AMR,B6MODE)\
989 |_PER_FDEFAULT(CHIP,AMR,B5MODE)\
990 |_PER_FDEFAULT(CHIP,AMR,B4MODE)\
991 |_PER_FDEFAULT(CHIP,AMR,A7MODE)\
992 |_PER_FDEFAULT(CHIP,AMR,A6MODE)\
993 |_PER_FDEFAULT(CHIP,AMR,A5MODE)\
994 |_PER_FDEFAULT(CHIP,AMR,A4MODE)\
995 )
997 #define CHIP_AMR_RMK(bk1,bk0,b7mode,b6mode,b5mode,b4mode,a7,ode,\
998 a6mode,a5mode,a4mode) (Uint32)( \
999 _PER_FMK(CHIP,AMR,BK1,bk1)\
1000 |_PER_FMK(CHIP,AMR,BK0,bk0)\
1001 |_PER_FMK(CHIP,AMR,B7MODE,b7mode)\
1002 |_PER_FMK(CHIP,AMR,B6MODE,b6mode)\
1003 |_PER_FMK(CHIP,AMR,B5MODE,b5mode)\
1004 |_PER_FMK(CHIP,AMR,B4MODE,b4mode)\
1005 |_PER_FMK(CHIP,AMR,A7MODE,a7mode)\
1006 |_PER_FMK(CHIP,AMR,A6MODE,a6mode)\
1007 |_PER_FMK(CHIP,AMR,A5MODE,a5mode)\
1008 |_PER_FMK(CHIP,AMR,A4MODE,a4mode)\
1009 )
1011 #define _CHIP_AMR_FGET(FIELD)\
1012 _PER_CFGET(CHIP,AMR,##FIELD)
1014 #define _CHIP_AMR_FSET(FIELD,field)\
1015 _PER_CFSET(CHIP,AMR,##FIELD,field)
1017 #define _CHIP_AMR_FSETS(FIELD,SYM)\
1018 _PER_CFSETS(CHIP,AMR,##FIELD,##SYM)
1022 /******************************************************************************\
1023 * _____________________
1024 * | |
1025 * | D E V C F G |
1026 * |___________________|
1027 *
1028 * PERCFG - Device Configuration register (1)
1029 *
1030 * FIELDS (msb -> lsb) CHIP_6713/CHIP_DA610
1031 * (rw) EKSRC
1032 * (rw) TOUT1SEL
1033 * (rw) TOUT0SEL
1034 * (rw) MCBSP0DIS
1035 * (rw) MCBSP1DIS
1036 * (rw) GPIO1EN (only for CHIP_DA610)
1037 *
1038 * FIELDS (msb -> lsb) CHIP_DM642
1039 * (rw) VP2EN
1040 * (rw) VP1EN
1041 * (rw) VP0EN
1042 * (rw) I2C0EN
1043 * (rw) MCBSP1EN
1044 * (rw) MCBSP0EN
1045 * (rw) MCASP0EN
1046 *
1047 * FIELDS (msb -> lsb) CHIP_6412
1048 * (rw) I2C0EN
1049 * (rw) MCBSP1EN
1050 * (rw) MCBSP0EN
1051 *
1052 * FIELDS (msb -> lsb) CHIP_6711C/CHIP_6712C
1053 * (rw) EKSRC
1054 *
1055 * FIELDS (msb -> lsb) CHIP_6410/CHIP_6413/CHIP_6418
1056 * (rw) AFCMUX
1057 * (rw) MCASP1EN
1058 * (rw) I2C1EN
1059 * (rw) I2C0EN
1060 * (r) MCBSP1EN
1061 * (r) MCBSP0EN
1062 * (rw) MCASP0EN
1063 *
1064 \******************************************************************************/
1066 #if (CHIP_DA610)
1068 #define _CHIP_DEVCFG_ADDR 0x019C0200u
1069 #define _CHIP_DEVCFG_OFFSET 0
1071 #define _CHIP_DEVCFG_GPIO1EN_MASK 0x00010000u
1072 #define _CHIP_DEVCFG_GPIO1EN_SHIFT 0x0000000Fu
1073 #define CHIP_DEVCFG_GPIO1EN_DEFAULT 0x00000000u
1074 #define CHIP_DEVCFG_GPIO1EN_OF(x) _VALUEOF(x)
1075 #define CHIP_DEVCFG_GPIO1EN_0 0x00000000u
1076 #define CHIP_DEVCFG_GPIO1EN_1 0x00000001u
1078 #define _CHIP_DEVCFG_EKSRC_MASK 0x00000010u
1079 #define _CHIP_DEVCFG_EKSRC_SHIFT 0x00000004u
1080 #define CHIP_DEVCFG_EKSRC_DEFAULT 0x00000000u
1081 #define CHIP_DEVCFG_EKSRC_OF(x) _VALUEOF(x)
1082 #define CHIP_DEVCFG_EKSRC_SYSCLK3 0x00000000u
1083 #define CHIP_DEVCFG_EKSRC_ECLKIN 0x00000001u
1085 #define _CHIP_DEVCFG_TOUT1SEL_MASK 0x00000008u
1086 #define _CHIP_DEVCFG_TOUT1SEL_SHIFT 0x00000003u
1087 #define CHIP_DEVCFG_TOUT1SEL_DEFAULT 0x00000000u
1088 #define CHIP_DEVCFG_TOUT1SEL_OF(x) _VALUEOF(x)
1089 #define CHIP_DEVCFG_TOUT1SEL_TOUT1PIN 0x00000000u
1090 #define CHIP_DEVCFG_TOUT1SEL_MCASPPIN 0x00000001u
1092 #define _CHIP_DEVCFG_TOUT0SEL_MASK 0x00000004u
1093 #define _CHIP_DEVCFG_TOUT0SEL_SHIFT 0x00000002u
1094 #define CHIP_DEVCFG_TOUT0SEL_DEFAULT 0x00000000u
1095 #define CHIP_DEVCFG_TOUT0SEL_OF(x) _VALUEOF(x)
1096 #define CHIP_DEVCFG_TOUT0SEL_TOUT0PIN 0x00000000u
1097 #define CHIP_DEVCFG_TOUT0SEL_MCASPPIN 0x00000001u
1099 #define _CHIP_DEVCFG_MCBSP0DIS_MASK 0x00000002u
1100 #define _CHIP_DEVCFG_MCBSP0DIS_SHIFT 0x00000001u
1101 #define CHIP_DEVCFG_MCBSP0DIS_DEFAULT 0x00000000u
1102 #define CHIP_DEVCFG_MCBSP0DIS_OF(x) _VALUEOF(x)
1103 #define CHIP_DEVCFG_MCBSP0DIS_0 0x00000000u
1104 #define CHIP_DEVCFG_MCBSP0DIS_1 0x00000001u
1106 #define _CHIP_DEVCFG_MCBSP1DIS_MASK 0x00000001u
1107 #define _CHIP_DEVCFG_MCBSP1DIS_SHIFT 0x00000000u
1108 #define CHIP_DEVCFG_MCBSP1DIS_DEFAULT 0x00000000u
1109 #define CHIP_DEVCFG_MCBSP1DIS_OF(x) _VALUEOF(x)
1110 #define CHIP_DEVCFG_MCBSP1DIS_0 0x00000000u
1111 #define CHIP_DEVCFG_MCBSP1DIS_1 0x00000001u
1114 #define CHIP_DEVCFG_OF(x) _VALUEOF(x)
1116 #define CHIP_DEVCFG_DEFAULT (Uint32)( \
1117 _PER_FDEFAULT(CHIP,DEVCFG,EKSRC) \
1118 |_PER_FDEFAULT(CHIP,DEVCFG,TOUT1SEL) \
1119 |_PER_FDEFAULT(CHIP,DEVCFG,TOUT0SEL) \
1120 |_PER_FDEFAULT(CHIP,DEVCFG,MCBSP0DIS) \
1121 |_PER_FDEFAULT(CHIP,DEVCFG,MCBSP1DIS) \
1122 |_PER_FDEFAULT(CHIP,DEVCFG,GPIO1EN) \
1123 )
1125 #define CHIP_DEVCFG_RMK(eksrc,tout1sel,tout0sel,mcbsp0dis,mcbsp1dis,\
1126 gpio1en ) (Uint32)( \
1127 _PER_FMK(CHIP,DEVCFG,EKSRC,eksrc) \
1128 |_PER_FMK(CHIP,DEVCFG,TOUT1SEL,tout1sel) \
1129 |_PER_FMK(CHIP,DEVCFG,TOUT0SEL,tout0sel) \
1130 |_PER_FMK(CHIP,DEVCFG,MCBSP0DIS,mcbsp0dis) \
1131 |_PER_FMK(CHIP,DEVCFG,MCBSP1DIS,mcbsp1dis) \
1132 |_PER_FMK(CHIP,DEVCFG,GPIO1EN,gpio1en) \
1133 )
1134 #elif (CHIP_6713)
1135 #define _CHIP_DEVCFG_ADDR 0x019C0200u
1136 #define _CHIP_DEVCFG_OFFSET 0
1138 #define _CHIP_DEVCFG_EKSRC_MASK 0x00000010u
1139 #define _CHIP_DEVCFG_EKSRC_SHIFT 0x00000004u
1140 #define CHIP_DEVCFG_EKSRC_DEFAULT 0x00000000u
1141 #define CHIP_DEVCFG_EKSRC_OF(x) _VALUEOF(x)
1142 #define CHIP_DEVCFG_EKSRC_SYSCLK3 0x00000000u
1143 #define CHIP_DEVCFG_EKSRC_ECLKIN 0x00000001u
1145 #define _CHIP_DEVCFG_TOUT1SEL_MASK 0x00000008u
1146 #define _CHIP_DEVCFG_TOUT1SEL_SHIFT 0x00000003u
1147 #define CHIP_DEVCFG_TOUT1SEL_DEFAULT 0x00000000u
1148 #define CHIP_DEVCFG_TOUT1SEL_OF(x) _VALUEOF(x)
1149 #define CHIP_DEVCFG_TOUT1SEL_TOUT1PIN 0x00000000u
1150 #define CHIP_DEVCFG_TOUT1SEL_MCASPPIN 0x00000001u
1152 #define _CHIP_DEVCFG_TOUT0SEL_MASK 0x00000004u
1153 #define _CHIP_DEVCFG_TOUT0SEL_SHIFT 0x00000002u
1154 #define CHIP_DEVCFG_TOUT0SEL_DEFAULT 0x00000000u
1155 #define CHIP_DEVCFG_TOUT0SEL_OF(x) _VALUEOF(x)
1156 #define CHIP_DEVCFG_TOUT0SEL_TOUT0PIN 0x00000000u
1157 #define CHIP_DEVCFG_TOUT0SEL_MCASPPIN 0x00000001u
1159 #define _CHIP_DEVCFG_MCBSP0DIS_MASK 0x00000002u
1160 #define _CHIP_DEVCFG_MCBSP0DIS_SHIFT 0x00000001u
1161 #define CHIP_DEVCFG_MCBSP0DIS_DEFAULT 0x00000000u
1162 #define CHIP_DEVCFG_MCBSP0DIS_OF(x) _VALUEOF(x)
1163 #define CHIP_DEVCFG_MCBSP0DIS_0 0x00000000u
1164 #define CHIP_DEVCFG_MCBSP0DIS_1 0x00000001u
1166 #define _CHIP_DEVCFG_MCBSP1DIS_MASK 0x00000001u
1167 #define _CHIP_DEVCFG_MCBSP1DIS_SHIFT 0x00000000u
1168 #define CHIP_DEVCFG_MCBSP1DIS_DEFAULT 0x00000000u
1169 #define CHIP_DEVCFG_MCBSP1DIS_OF(x) _VALUEOF(x)
1170 #define CHIP_DEVCFG_MCBSP1DIS_0 0x00000000u
1171 #define CHIP_DEVCFG_MCBSP1DIS_1 0x00000001u
1174 #define CHIP_DEVCFG_OF(x) _VALUEOF(x)
1176 #define CHIP_DEVCFG_DEFAULT (Uint32)( \
1177 _PER_FDEFAULT(CHIP,DEVCFG,EKSRC) \
1178 |_PER_FDEFAULT(CHIP,DEVCFG,TOUT1SEL) \
1179 |_PER_FDEFAULT(CHIP,DEVCFG,TOUT0SEL) \
1180 |_PER_FDEFAULT(CHIP,DEVCFG,MCBSP0DIS) \
1181 |_PER_FDEFAULT(CHIP,DEVCFG,MCBSP1DIS) \
1182 )
1184 #define CHIP_DEVCFG_RMK(eksrc,tout1sel,tout0sel,mcbsp0dis,mcbsp1dis\
1185 ) (Uint32)( \
1186 _PER_FMK(CHIP,DEVCFG,EKSRC,eksrc) \
1187 |_PER_FMK(CHIP,DEVCFG,TOUT1SEL,tout1sel) \
1188 |_PER_FMK(CHIP,DEVCFG,TOUT0SEL,tout0sel) \
1189 |_PER_FMK(CHIP,DEVCFG,MCBSP0DIS,mcbsp0dis) \
1190 |_PER_FMK(CHIP,DEVCFG,MCBSP1DIS,mcbsp1dis) \
1191 )
1193 #endif
1195 #if (CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412)
1197 #define _CHIP_PERCFG_ADDR 0x01B3F000u
1198 #define _CHIP_PERCFG_OFFSET 0
1200 #if (CHIP_DM642)
1201 #define _CHIP_PERCFG_VP2EN_MASK 0x00000040u
1202 #define _CHIP_PERCFG_VP2EN_SHIFT 0x00000006u
1203 #define CHIP_PERCFG_VP2EN_DEFAULT 0x00000000u
1204 #define CHIP_PERCFG_VP2EN_OF(x) _VALUEOF(x)
1205 #define CHIP_PERCFG_VP2EN_DISABLE 0x00000000u
1206 #define CHIP_PERCFG_VP2EN_ENABLE 0x00000001u
1207 #endif
1209 #if (CHIP_DM642 | CHIP_DM641)
1210 #define _CHIP_PERCFG_VP1EN_MASK 0x00000020u
1211 #define _CHIP_PERCFG_VP1EN_SHIFT 0x00000005u
1212 #define CHIP_PERCFG_VP1EN_DEFAULT 0x00000000u
1213 #define CHIP_PERCFG_VP1EN_OF(x) _VALUEOF(x)
1214 #define CHIP_PERCFG_VP1EN_DISABLE 0x00000000u
1215 #define CHIP_PERCFG_VP1EN_ENABLE 0x00000001u
1216 #endif
1218 #if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640)
1219 #define _CHIP_PERCFG_VP0EN_MASK 0x00000010u
1220 #define _CHIP_PERCFG_VP0EN_SHIFT 0x00000004u
1221 #define CHIP_PERCFG_VP0EN_DEFAULT 0x00000000u
1222 #define CHIP_PERCFG_VP0EN_OF(x) _VALUEOF(x)
1223 #define CHIP_PERCFG_VP0EN_DISABLE 0x00000000u
1224 #define CHIP_PERCFG_VP0EN_ENABLE 0x00000001u
1225 #endif
1227 #define _CHIP_PERCFG_I2C0EN_MASK 0x00000008u
1228 #define _CHIP_PERCFG_I2C0EN_SHIFT 0x00000003u
1229 #define CHIP_PERCFG_I2C0EN_DEFAULT 0x00000000u
1230 #define CHIP_PERCFG_I2C0EN_OF(x) _VALUEOF(x)
1231 #define CHIP_PERCFG_I2C0EN_DISABLE 0x00000000u
1232 #define CHIP_PERCFG_I2C0EN_ENABLE 0x00000001u
1234 #define _CHIP_PERCFG_MCBSP1EN_MASK 0x00000004u
1235 #define _CHIP_PERCFG_MCBSP1EN_SHIFT 0x00000002u
1236 #define CHIP_PERCFG_MCBSP1EN_DEFAULT 0x00000001u
1237 #define CHIP_PERCFG_MCBSP1EN_OF(x) _VALUEOF(x)
1238 #define CHIP_PERCFG_MCBSP1EN_DISABLE 0x00000000u
1239 #define CHIP_PERCFG_MCBSP1EN_ENABLE 0x00000001u
1241 #define _CHIP_PERCFG_MCBSP0EN_MASK 0x00000002u
1242 #define _CHIP_PERCFG_MCBSP0EN_SHIFT 0x00000001u
1243 #define CHIP_PERCFG_MCBSP0EN_DEFAULT 0x00000001u
1244 #define CHIP_PERCFG_MCBSP0EN_OF(x) _VALUEOF(x)
1245 #define CHIP_PERCFG_MCBSP0EN_DISABLE 0x00000000u
1246 #define CHIP_PERCFG_MCBSP0EN_ENABLE 0x00000001u
1248 #if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640)
1249 #define _CHIP_PERCFG_MCASP0EN_MASK 0x00000001u
1250 #define _CHIP_PERCFG_MCASP0EN_SHIFT 0x00000000u
1251 #define CHIP_PERCFG_MCASP0EN_DEFAULT 0x00000000u
1252 #define CHIP_PERCFG_MCASP0EN_OF(x) _VALUEOF(x)
1253 #define CHIP_PERCFG_MCASP0EN_DISABLE 0x00000000u
1254 #define CHIP_PERCFG_MCASP0EN_ENABLE 0x00000001u
1255 #endif
1258 #define CHIP_PERCFG_OF(x) _VALUEOF(x)
1260 #if (CHIP_DM642)
1261 #define CHIP_PERCFG_DEFAULT (Uint32)( \
1262 _PER_FDEFAULT(CHIP,PERCFG,VP2EN) \
1263 |_PER_FDEFAULT(CHIP,PERCFG,VP1EN) \
1264 |_PER_FDEFAULT(CHIP,PERCFG,VP0EN) \
1265 |_PER_FDEFAULT(CHIP,PERCFG,I2C0EN) \
1266 |_PER_FDEFAULT(CHIP,PERCFG,MCBSP1EN) \
1267 |_PER_FDEFAULT(CHIP,PERCFG,MCBSP0EN) \
1268 |_PER_FDEFAULT(CHIP,PERCFG,MCASP0EN) \
1269 )
1272 #define CHIP_PERCFG_RMK(vp2en,vp1en,vp0en,i2c0en,mcbsp1en,mcbsp0en,mcasp0en) (Uint32)( \
1273 _PER_FMK(CHIP,PERCFG,VP2EN,vp2en) \
1274 |_PER_FMK(CHIP,PERCFG,VP1EN,vp1en) \
1275 |_PER_FMK(CHIP,PERCFG,VP0EN,vp0en) \
1276 |_PER_FMK(CHIP,PERCFG,I2C0EN,i2c0en) \
1277 |_PER_FMK(CHIP,PERCFG,MCBSP1EN,mcbsp1en) \
1278 |_PER_FMK(CHIP,PERCFG,MCBSP0EN,mcbsp0en) \
1279 |_PER_FMK(CHIP,PERCFG,MCASP0EN,mcasp0en) \
1280 )
1281 #endif
1283 #if (CHIP_DM641)
1284 #define CHIP_PERCFG_DEFAULT (Uint32)( \
1285 _PER_FDEFAULT(CHIP,PERCFG,VP1EN) \
1286 |_PER_FDEFAULT(CHIP,PERCFG,VP0EN) \
1287 |_PER_FDEFAULT(CHIP,PERCFG,I2C0EN) \
1288 |_PER_FDEFAULT(CHIP,PERCFG,MCBSP1EN) \
1289 |_PER_FDEFAULT(CHIP,PERCFG,MCBSP0EN) \
1290 |_PER_FDEFAULT(CHIP,PERCFG,MCASP0EN) \
1291 )
1294 #define CHIP_PERCFG_RMK(vp1en,vp0en,i2c0en,mcbsp1en,mcbsp0en,mcasp0en) (Uint32)( \
1295 _PER_FMK(CHIP,PERCFG,VP1EN,vp1en) \
1296 |_PER_FMK(CHIP,PERCFG,VP0EN,vp0en) \
1297 |_PER_FMK(CHIP,PERCFG,I2C0EN,i2c0en) \
1298 |_PER_FMK(CHIP,PERCFG,MCBSP1EN,mcbsp1en) \
1299 |_PER_FMK(CHIP,PERCFG,MCBSP0EN,mcbsp0en) \
1300 |_PER_FMK(CHIP,PERCFG,MCASP0EN,mcasp0en) \
1301 )
1302 #endif
1304 #if (CHIP_DM640)
1305 #define CHIP_PERCFG_DEFAULT (Uint32)( \
1306 _PER_FDEFAULT(CHIP,PERCFG,VP0EN) \
1307 |_PER_FDEFAULT(CHIP,PERCFG,I2C0EN) \
1308 |_PER_FDEFAULT(CHIP,PERCFG,MCBSP1EN) \
1309 |_PER_FDEFAULT(CHIP,PERCFG,MCBSP0EN) \
1310 |_PER_FDEFAULT(CHIP,PERCFG,MCASP0EN) \
1311 )
1314 #define CHIP_PERCFG_RMK(vp0en,i2c0en,mcbsp1en,mcbsp0en,mcasp0en) (Uint32)( \
1315 _PER_FMK(CHIP,PERCFG,VP0EN,vp0en) \
1316 |_PER_FMK(CHIP,PERCFG,I2C0EN,i2c0en) \
1317 |_PER_FMK(CHIP,PERCFG,MCBSP1EN,mcbsp1en) \
1318 |_PER_FMK(CHIP,PERCFG,MCBSP0EN,mcbsp0en) \
1319 |_PER_FMK(CHIP,PERCFG,MCASP0EN,mcasp0en) \
1320 )
1321 #endif
1323 #if (CHIP_6412)
1324 #define CHIP_PERCFG_DEFAULT (Uint32)( \
1325 _PER_FDEFAULT(CHIP,PERCFG,I2C0EN) \
1326 |_PER_FDEFAULT(CHIP,PERCFG,MCBSP1EN) \
1327 |_PER_FDEFAULT(CHIP,PERCFG,MCBSP0EN) \
1328 )
1331 #define CHIP_PERCFG_RMK(i2c0en,mcbsp1en,mcbsp0en) (Uint32)( \
1332 |_PER_FMK(CHIP,PERCFG,I2C0EN,i2c0en) \
1333 |_PER_FMK(CHIP,PERCFG,MCBSP1EN,mcbsp1en) \
1334 |_PER_FMK(CHIP,PERCFG,MCBSP0EN,mcbsp0en) \
1335 )
1336 #endif
1338 #endif /* CHIP_DM642 || CHIP_6412 */
1340 #if (CHIP_6410 || CHIP_6413 || CHIP_6418)
1342 #define _CHIP_PERCFG_ADDR 0x01B3F000u
1343 #define _CHIP_PERCFG_OFFSET 0
1345 #define _CHIP_PERCFG_AFCMUX_MASK 0x00000600u
1346 #define _CHIP_PERCFG_AFCMUX_SHIFT 0x00000009u
1347 #define CHIP_PERCFG_AFCMUX_DEFAULT 0x00000000u
1348 #define CHIP_PERCFG_AFCMUX_OF(x) _VALUEOF(x)
1349 #define CHIP_PERCFG_AFCMUX_PIN0 0x00000000u
1350 #define CHIP_PERCFG_AFCMUX_PIN1 0x00000001u
1351 #define CHIP_PERCFG_AFCMUX_PIN2 0x00000002u
1352 #define CHIP_PERCFG_AFCMUX_PIN3 0x00000003u
1354 #define _CHIP_PERCFG_MCASP1EN_MASK 0x00000100u
1355 #define _CHIP_PERCFG_MCASP1EN_SHIFT 0x00000008u
1356 #define CHIP_PERCFG_MCASP1EN_DEFAULT 0x00000000u
1357 #define CHIP_PERCFG_MCASP1EN_OF(x) _VALUEOF(x)
1358 #define CHIP_PERCFG_MCASP1EN_DISABLE 0x00000000u
1359 #define CHIP_PERCFG_MCASP1EN_ENABLE 0x00000001u
1361 #define _CHIP_PERCFG_I2C1EN_MASK 0x00000080u
1362 #define _CHIP_PERCFG_I2C1EN_SHIFT 0x00000007u
1363 #define CHIP_PERCFG_I2C1EN_DEFAULT 0x00000000u
1364 #define CHIP_PERCFG_I2C1EN_OF(x) _VALUEOF(x)
1365 #define CHIP_PERCFG_I2C1EN_DISABLE 0x00000000u
1366 #define CHIP_PERCFG_I2C1EN_ENABLE 0x00000001u
1368 #define _CHIP_PERCFG_I2C0EN_MASK 0x00000008u
1369 #define _CHIP_PERCFG_I2C0EN_SHIFT 0x00000003u
1370 #define CHIP_PERCFG_I2C0EN_DEFAULT 0x00000000u
1371 #define CHIP_PERCFG_I2C0EN_OF(x) _VALUEOF(x)
1372 #define CHIP_PERCFG_I2C0EN_DISABLE 0x00000000u
1373 #define CHIP_PERCFG_I2C0EN_ENABLE 0x00000001u
1375 #define _CHIP_PERCFG_MCBSP1EN_MASK 0x00000004u
1376 #define _CHIP_PERCFG_MCBSP1EN_SHIFT 0x00000002u
1377 #define CHIP_PERCFG_MCBSP1EN_DEFAULT 0x00000001u
1378 #define CHIP_PERCFG_MCBSP1EN_OF(x) _VALUEOF(x)
1379 #define CHIP_PERCFG_MCBSP1EN_DISABLE 0x00000000u
1380 #define CHIP_PERCFG_MCBSP1EN_ENABLE 0x00000001u
1382 #define _CHIP_PERCFG_MCBSP0EN_MASK 0x00000002u
1383 #define _CHIP_PERCFG_MCBSP0EN_SHIFT 0x00000001u
1384 #define CHIP_PERCFG_MCBSP0EN_DEFAULT 0x00000001u
1385 #define CHIP_PERCFG_MCBSP0EN_OF(x) _VALUEOF(x)
1386 #define CHIP_PERCFG_MCBSP0EN_DISABLE 0x00000000u
1387 #define CHIP_PERCFG_MCBSP0EN_ENABLE 0x00000001u
1389 #define _CHIP_PERCFG_MCASP0EN_MASK 0x00000001u
1390 #define _CHIP_PERCFG_MCASP0EN_SHIFT 0x00000000u
1391 #define CHIP_PERCFG_MCASP0EN_DEFAULT 0x00000000u
1392 #define CHIP_PERCFG_MCASP0EN_OF(x) _VALUEOF(x)
1393 #define CHIP_PERCFG_MCASP0EN_DISABLE 0x00000000u
1394 #define CHIP_PERCFG_MCASP0EN_ENABLE 0x00000001u
1396 #define CHIP_PERCFG_OF(x) _VALUEOF(x)
1398 #define CHIP_PERCFG_DEFAULT (Uint32)( \
1399 _PER_FDEFAULT(CHIP,PERCFG,AFCMUX) \
1400 |_PER_FDEFAULT(CHIP,PERCFG,MCASP1EN) \
1401 |_PER_FDEFAULT(CHIP,PERCFG,I2C1EN) \
1402 |_PER_FDEFAULT(CHIP,PERCFG,I2C0EN) \
1403 |_PER_FDEFAULT(CHIP,PERCFG,MCBSP1EN) \
1404 |_PER_FDEFAULT(CHIP,PERCFG,MCBSP0EN) \
1405 |_PER_FDEFAULT(CHIP,PERCFG,MCASP0EN) \
1406 )
1409 #define CHIP_PERCFG_RMK(afcmux,mcasp1en,i2c1en,i2c0en,mcasp0en) (Uint32)( \
1410 _PER_FMK(CHIP,PERCFG,AFCMUX,afcmux) \
1411 |_PER_FMK(CHIP,PERCFG,MCASP1EN,mcasp1en) \
1412 |_PER_FMK(CHIP,PERCFG,I2C1EN,i2c1en) \
1413 |_PER_FMK(CHIP,PERCFG,I2C0EN,i2c0en) \
1414 |_PER_FMK(CHIP,PERCFG,MCASP0EN,mcasp0en) \
1415 )
1417 #endif /* CHIP_6410 || CHIP_6413 || CHIP_6418 */
1419 #if (CHIP_6711C || CHIP_6712C)
1420 #define _CHIP_DEVCFG_ADDR 0x019C0200u
1421 #define _CHIP_DEVCFG_OFFSET 0
1423 #define _CHIP_DEVCFG_EKSRC_MASK 0x00000010u
1424 #define _CHIP_DEVCFG_EKSRC_SHIFT 0x00000004u
1425 #define CHIP_DEVCFG_EKSRC_DEFAULT 0x00000000u
1426 #define CHIP_DEVCFG_EKSRC_OF(x) _VALUEOF(x)
1427 #define CHIP_DEVCFG_EKSRC_SYSCLK3 0x00000000u
1428 #define CHIP_DEVCFG_EKSRC_ECLKIN 0x00000001u
1430 #define CHIP_DEVCFG_OF(x) _VALUEOF(x)
1432 #define CHIP_DEVCFG_DEFAULT (Uint32)( \
1433 _PER_FDEFAULT(CHIP,DEVCFG,EKSRC) \
1434 )
1436 #define CHIP_PERCFG_RMK(eksrc) (Uint32)( \
1437 _PER_FMK(CHIP,PERCFG,EKSRC,eksrc) \
1438 )
1440 #endif /* CHIP_6711C || CHIP_6712C */
1442 #if (CHIP_6711C || CHIP_6712C || CHIP_DA610 || CHIP_6713)
1443 #define _CHIP_DEVCFG_FGET(FIELD)\
1444 _PER_FGET(_CHIP_DEVCFG_ADDR,CHIP,DEVCFG,##FIELD)
1446 #define _CHIP_DEVCFG_FSET(FIELD,field)\
1447 _PER_FSET(_CHIP_DEVCFG_ADDR,CHIP,DEVCFG,##FIELD,field)
1449 #define _CHIP_DEVCFG_FSETS(FIELD,SYM)\
1450 _PER_FSETS(_CHIP_DEVCFG_ADDR,CHIP,DEVCFG,##FIELD,##SYM)
1452 #else
1454 #define _CHIP_PERCFG_FGET(FIELD)\
1455 _PER_FGET(_CHIP_PERCFG_ADDR,CHIP,PERCFG,##FIELD)
1457 #define _CHIP_PERCFG_FSET(FIELD,field)\
1458 _PER_FSET(_CHIP_PERCFG_ADDR,CHIP,PERCFG,##FIELD,field)
1460 #define _CHIP_PERCFG_FSETS(FIELD,SYM)\
1461 _PER_FSETS(_CHIP_PERCFG_ADDR,CHIP,PERCFG,##FIELD,##SYM)
1462 #endif
1464 /*----------------------------------------------------------------------------*/
1465 /******************************************************************************\
1466 * _____________________
1467 * | |
1468 * | D E V S T A T |
1469 * |___________________|
1470 *
1471 * DEVSTAT - Device Status Register (1)
1472 *
1473 * FIELDS (msb -> lsb)
1474 * DM642
1475 * (r) MACEN
1476 * (r) HPIWIDTH
1477 * (r) PCIEEAI
1478 * (r) PCIEN
1479 * (r) CLKMODE
1480 * (r) LENDIAN
1481 * (r) BOOTMODE
1482 * (r) AECLKINSEL
1483 *
1484 * DRI300
1485 * (r) PLLM
1486 * (r) OSCEXTRES
1487 * (r) CLKINSEL
1488 * (r) CLKMODE3
1489 * (r) HPIWIDTH
1490 * (r) HPIENZ
1491 * (r) CLKMODE2
1492 * (r) CLKMODE1
1493 * (r) CLKMODE0
1494 * (r) LENDIAN
1495 * (r) BOOTMODE
1496 * (r) AECLKINSEL
1497 *
1498 *
1499 \******************************************************************************/
1500 #if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640 | CHIP_6412)
1502 #define _CHIP_DEVSTAT_ADDR 0x01B3F004u
1503 #define _CHIP_DEVSTAT_OFFSET 0
1505 #define _CHIP_DEVSTAT_MACEN_MASK 0x00000800u
1506 #define _CHIP_DEVSTAT_MACEN_SHIFT 0x0000000Bu
1507 #define CHIP_DEVSTAT_MACEN_DEFAULT 0x00000000u
1508 #define CHIP_DEVSTAT_MACEN_OF(x) _VALUEOF(x)
1509 #define CHIP_DEVSTAT_MACEN_DISABLE 0x00000000u
1510 #define CHIP_DEVSTAT_MACEN_ENABLE 0x00000001u
1512 #if !(CHIP_DM640)
1513 #define _CHIP_DEVSTAT_HPIWIDTH_MASK 0x00000400u
1514 #define _CHIP_DEVSTAT_HPIWIDTH_SHIFT 0x0000000Au
1515 #define CHIP_DEVSTAT_HPIWIDTH_DEFAULT 0x00000000u
1516 #define CHIP_DEVSTAT_HPIWIDTH_OF(x) _VALUEOF(x)
1517 #define CHIP_DEVSTAT_HPIWIDTH_16 0x00000000u
1518 #define CHIP_DEVSTAT_HPIWIDTH_32 0x00000001u
1519 #endif
1521 #if !(CHIP_DM641 | CHIP_DM640)
1522 #define _CHIP_DEVSTAT_PCIEEAI_MASK 0x00000200u
1523 #define _CHIP_DEVSTAT_PCIEEAI_SHIFT 0x00000009u
1524 #define CHIP_DEVSTAT_PCIEEAI_DEFAULT 0x00000000u
1525 #define CHIP_DEVSTAT_PCIEEAI_OF(x) _VALUEOF(x)
1526 #define CHIP_DEVSTAT_PCIEEAI_NONE 0x00000000u
1527 #define CHIP_DEVSTAT_PCIEEAI_INIT 0x00000001u
1529 #define _CHIP_DEVSTAT_PCIEN_MASK 0x00000100u
1530 #define _CHIP_DEVSTAT_PCIEN_SHIFT 0x00000008u
1531 #define CHIP_DEVSTAT_PCIEN_DEFAULT 0x00000000u
1532 #define CHIP_DEVSTAT_PCIEN_OF(x) _VALUEOF(x)
1533 #define CHIP_DEVSTAT_PCIEN_DISABLE 0x00000000u
1534 #define CHIP_DEVSTAT_PCIEN_ENABLE 0x00000001u
1535 #endif
1537 #define _CHIP_DEVSTAT_CLKMODE_MASK 0x00000060u
1538 #define _CHIP_DEVSTAT_CLKMODE_SHIFT 0x00000005u
1539 #define CHIP_DEVSTAT_CLKMODE_DEFAULT 0x00000001u
1540 #define CHIP_DEVSTAT_CLKMODE_OF(x) _VALUEOF(x)
1541 #define CHIP_DEVSTAT_CLKMODE_X1 0x00000000u
1542 #define CHIP_DEVSTAT_CLKMODE_X6 0x00000001u
1543 #define CHIP_DEVSTAT_CLKMODE_X12 0x00000002u
1544 #define CHIP_DEVSTAT_CLKMODE_X20 0x00000003u
1546 #define _CHIP_DEVSTAT_LENDIAN_MASK 0x00000010u
1547 #define _CHIP_DEVSTAT_LENDIAN_SHIFT 0x00000004u
1548 #define CHIP_DEVSTAT_LENDIAN_DEFAULT 0x00000001u
1549 #define CHIP_DEVSTAT_LENDIAN_OF(x) _VALUEOF(x)
1550 #define CHIP_DEVSTAT_LENDIAN_BIG 0x00000000u
1551 #define CHIP_DEVSTAT_LENDIAN_LITTLE 0x00000001u
1553 #define _CHIP_DEVSTAT_BOOTMODE_MASK 0x0000000Cu
1554 #define _CHIP_DEVSTAT_BOOTMODE_SHIFT 0x00000002u
1555 #define CHIP_DEVSTAT_BOOTMODE_DEFAULT 0x00000000u
1556 #define CHIP_DEVSTAT_BOOTMODE_OF(x) _VALUEOF(x)
1557 #define CHIP_DEVSTAT_BOOTMODE_NONE 0x00000000u
1558 #define CHIP_DEVSTAT_BOOTMODE_HPIPCI 0x00000001u
1559 #define CHIP_DEVSTAT_BOOTMODE_EMIFA 0x00000003u
1561 #define _CHIP_DEVSTAT_AECLKINSEL_MASK 0x00000003u
1562 #define _CHIP_DEVSTAT_AECLKINSEL_SHIFT 0x00000000u
1563 #define CHIP_DEVSTAT_AECLKINSEL_DEFAULT 0x00000000u
1564 #define CHIP_DEVSTAT_AECLKINSEL_OF(x) _VALUEOF(x)
1565 #define CHIP_DEVSTAT_AECLKINSEL_ECLKIN 0x00000000u
1566 #define CHIP_DEVSTAT_AECLKINSEL_CLKOUT4 0x00000001u
1567 #define CHIP_DEVSTAT_AECLKINSEL_CLKOUT6 0x00000002u
1568 #define CHIP_DEVSTAT_OF(x) _VALUEOF(x)
1570 #define CHIP_DEVSTAT_OF(x) _VALUEOF(x)
1572 /* Read only Register */
1574 #define _CHIP_DEVSTAT_FGET(FIELD)\
1575 _PER_FGET(_CHIP_DEVSTAT_ADDR,CHIP,DEVSTAT,##FIELD)
1578 #endif /* CHIP_DM642 | CHIP_6412 */
1580 #if (CHIP_6410 || CHIP_6413 || CHIP_6418)
1582 #define _CHIP_DEVSTAT_ADDR 0x01B3F004u
1583 #define _CHIP_DEVSTAT_OFFSET 0
1585 #define _CHIP_DEVSTAT_PLLM_MASK 0x00F10000u
1586 #define _CHIP_DEVSTAT_PLLM_SHIFT 0x00000013u
1587 #define CHIP_DEVSTAT_PLLM_DEFAULT 0x00000000u
1588 #define CHIP_DEVSTAT_PLLM_OF(x) _VALUEOF(x)
1589 #define CHIP_DEVSTAT_PLLM_BYPASS 0x00000000u
1590 #define CHIP_DEVSTAT_PLLM_5 0x00000001u
1591 #define CHIP_DEVSTAT_PLLM_6 0x00000002u
1592 #define CHIP_DEVSTAT_PLLM_7 0x00000003u
1593 #define CHIP_DEVSTAT_PLLM_8 0x00000004u
1594 #define CHIP_DEVSTAT_PLLM_9 0x00000005u
1595 #define CHIP_DEVSTAT_PLLM_10 0x00000006u
1596 #define CHIP_DEVSTAT_PLLM_11 0x00000007u
1597 #define CHIP_DEVSTAT_PLLM_12 0x00000008u
1598 #define CHIP_DEVSTAT_PLLM_16 0x00000009u
1599 #define CHIP_DEVSTAT_PLLM_18 0x0000000Au
1600 #define CHIP_DEVSTAT_PLLM_19 0x0000000Bu
1601 #define CHIP_DEVSTAT_PLLM_20 0x0000000Cu
1602 #define CHIP_DEVSTAT_PLLM_21 0x0000000Du
1603 #define CHIP_DEVSTAT_PLLM_22 0x0000000Eu
1604 #define CHIP_DEVSTAT_PLLM_24 0x0000000Fu
1606 #define _CHIP_DEVSTAT_OSCEXTRES_MASK 0x00020000u
1607 #define _CHIP_DEVSTAT_OSCEXTRES_SHIFT 0x00000011u
1608 #define CHIP_DEVSTAT_OSCEXTRES_DEFAUL 0x00000001u
1609 #define CHIP_DEVSTAT_OSCEXTRES_OF(x) _VALUEOF(x)
1610 #define CHIP_DEVSTAT_OSCEXTRES_DISABL 0x00000000u
1611 #define CHIP_DEVSTAT_OSCEXTRES_ENABLE 0x00000001u
1613 #define _CHIP_DEVSTAT_CLKINSEL_MASK 0x00010000u
1614 #define _CHIP_DEVSTAT_CLKINSEL_SHIFT 0x00000010u
1615 #define CHIP_DEVSTAT_CLKINSEL_DEFAULT 0x00000000u
1616 #define CHIP_DEVSTAT_CLKINSEL_OF(x) _VALUEOF(x)
1617 #define CHIP_DEVSTAT_CLKINSEL_DISABLE 0x00000000u
1618 #define CHIP_DEVSTAT_CLKINSEL_ENABLE 0x00000001u
1620 #define _CHIP_DEVSTAT_HPIWIDTH_MASK 0x00000400u
1621 #define _CHIP_DEVSTAT_HPIWIDTH_SHIFT 0x0000000Au
1622 #define CHIP_DEVSTAT_HPIWIDTH_DEFAUL 0x00000000u
1623 #define CHIP_DEVSTAT_HPIWIDTH_OF(x) _VALUEOF(x)
1624 #define CHIP_DEVSTAT_HPIWIDTH_16 0x00000000u
1625 #define CHIP_DEVSTAT_HPIWIDTH_32 0x00000001u
1627 #define _CHIP_DEVSTAT_HPIENZ_MASK 0x00000100u
1628 #define _CHIP_DEVSTAT_HPIENZ_SHIFT 0x00000008u
1629 #define CHIP_DEVSTAT_HPIENZ_DEFAULT 0x00000000u
1630 #define CHIP_DEVSTAT_HPIENZ_OF(x) _VALUEOF(x)
1631 #define CHIP_DEVSTAT_HPIENZ_ENABLE 0x00000000u
1632 #define CHIP_DEVSTAT_HPIENZ_DISABLE 0x00000001u
1634 #define _CHIP_DEVSTAT_CLKMODE_MASK 0x000010E0u
1635 #define _CHIP_DEVSTAT_CLKMODE_SHIFT 0x00000005u
1636 #define CHIP_DEVSTAT_CLKMODE_DEFAULT 0x00000001u
1637 #define CHIP_DEVSTAT_CLKMODE_OF(x) _VALUEOF(x)
1638 #define CHIP_DEVSTAT_CLKMODE_0 0x00000000u
1639 #define CHIP_DEVSTAT_CLKMODE_1 0x00000001u
1640 #define CHIP_DEVSTAT_CLKMODE_2 0x00000002u
1641 #define CHIP_DEVSTAT_CLKMODE_3 0x00000003u
1642 #define CHIP_DEVSTAT_CLKMODE_4 0x00000004u
1643 #define CHIP_DEVSTAT_CLKMODE_5 0x00000005u
1644 #define CHIP_DEVSTAT_CLKMODE_6 0x00000006u
1645 #define CHIP_DEVSTAT_CLKMODE_7 0x00000007u
1646 #define CHIP_DEVSTAT_CLKMODE_8 0x00000080u
1647 #define CHIP_DEVSTAT_CLKMODE_9 0x00000081u
1648 #define CHIP_DEVSTAT_CLKMODE_10 0x00000082u
1649 #define CHIP_DEVSTAT_CLKMODE_11 0x00000083u
1650 #define CHIP_DEVSTAT_CLKMODE_12 0x00000084u
1651 #define CHIP_DEVSTAT_CLKMODE_13 0x00000085u
1652 #define CHIP_DEVSTAT_CLKMODE_14 0x00000086u
1653 #define CHIP_DEVSTAT_CLKMODE_15 0x00000087u
1655 #define _CHIP_DEVSTAT_LENDIAN_MASK 0x00000010u
1656 #define _CHIP_DEVSTAT_LENDIAN_SHIFT 0x00000004u
1657 #define CHIP_DEVSTAT_LENDIAN_DEFAULT 0x00000001u
1658 #define CHIP_DEVSTAT_LENDIAN_OF(x) _VALUEOF(x)
1659 #define CHIP_DEVSTAT_LENDIAN_BIG 0x00000000u
1660 #define CHIP_DEVSTAT_LENDIAN_LITTLE 0x00000001u
1662 #define _CHIP_DEVSTAT_BOOTMODE_MASK 0x0000000Cu
1663 #define _CHIP_DEVSTAT_BOOTMODE_SHIFT 0x00000002u
1664 #define CHIP_DEVSTAT_BOOTMODE_DEFAULT 0x00000000u
1665 #define CHIP_DEVSTAT_BOOTMODE_OF(x) _VALUEOF(x)
1666 #define CHIP_DEVSTAT_BOOTMODE_NONE 0x00000000u
1667 #define CHIP_DEVSTAT_BOOTMODE_HPI 0x00000001u
1668 #define CHIP_DEVSTAT_BOOTMODE_EMIFA 0x00000003u
1670 #define _CHIP_DEVSTAT_AECLKINSEL_MASK 0x00000003u
1671 #define _CHIP_DEVSTAT_AECLKINSEL_SHIFT 0x00000000u
1672 #define CHIP_DEVSTAT_AECLKINSEL_DEFAULT 0x00000000u
1673 #define CHIP_DEVSTAT_AECLKINSEL_OF(x) _VALUEOF(x)
1674 #define CHIP_DEVSTAT_AECLKINSEL_ECLKIN 0x00000000u
1675 #define CHIP_DEVSTAT_AECLKINSEL_CLKOUT4 0x00000001u
1676 #define CHIP_DEVSTAT_AECLKINSEL_CLKOUT6 0x00000002u
1678 #define CHIP_DEVSTAT_OF(x) _VALUEOF(x)
1680 /* Read only Register */
1682 #define _CHIP_DEVSTAT_FGET(FIELD)\
1683 _PER_FGET(_CHIP_DEVSTAT_ADDR,CHIP,DEVSTAT,##FIELD)
1686 #endif /* CHIP_6410 || CHIP_6413 || CHIP_6418 */
1688 /******************************************************************************\
1689 * _____________________
1690 * | |
1691 * | J T A G I D |
1692 * |___________________|
1693 *
1694 * JTAGID - JTAG ID register (1)
1695 *
1696 * FIELDS (msb -> lsb)
1697 * (r) VARIANT
1698 * (r) PART
1699 * (r) MANNUFACTURE
1700 * (r) LSB
1701 *
1702 * (1) Only for DM642
1703 *
1704 \******************************************************************************/
1707 #if (CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412 )
1709 #define _CHIP_JTAGID_ADDR 0x01B3F008u
1710 #define _CHIP_JTAGID_OFFSET 0
1712 #define _CHIP_JTAGID_VARIANT_MASK 0xF0000000u
1713 #define _CHIP_JTAGID_VARIANT_SHIFT 0x0000001Cu
1714 #define CHIP_JTAGID_VARIANT_DEFAULT 0x00000000u
1715 #define CHIP_JTAGID_VARIANT_OF(x) _VALUEOF(x)
1717 #define _CHIP_JTAGID_PART_MASK 0x0FFFF000u
1718 #define _CHIP_JTAGID_PART_SHIFT 0x0000000Cu
1719 #define CHIP_JTAGID_PART_DEFAULT 0x00000079u
1720 #define CHIP_JTAGID_PART_OF(x) _VALUEOF(x)
1722 #define _CHIP_JTAGID_MANUFACTURE_MASK 0x00000FFEu
1723 #define _CHIP_JTAGID_MANUFACTURE_SHIFT 0x00000001u
1724 #define CHIP_JTAGID_MANUFACTURE_DEFAULT 0x00000017u
1725 #define CHIP_JTAGID_MANUFACTURE_OF(x) _VALUEOF(x)
1727 #define _CHIP_JTAGID_LSB_MASK 0x00000001u
1728 #define _CHIP_JTAGID_LSB_SHIFT 0x00000000u
1729 #define CHIP_JTAGID_LSB_DEFAULT 0x00000001u
1730 #define CHIP_JTAGID_LSB_OF(x) _VALUEOF(x)
1732 #define CHIP_JTAGID_OF(x) _VALUEOF(x)
1734 #define _CHIP_JTAGID_FGET(FIELD)\
1735 _PER_FGET(_CHIP_JTAGID_ADDR,CHIP,JTAGID,##FIELD)
1737 #endif /* CHIP_DM642 || CHIP_6412 */
1739 /******************************************************************************\
1740 * _____________________
1741 * | |
1742 * | P C F G L O C K |
1743 * |___________________|
1744 *
1745 * PCFGLOCK - Peripheral Configuration Lock register (1)
1746 *
1747 * FIELDS (msb -> lsb)
1748 * (r) LOCKSTAT
1749 * (w) LOCK
1750 *
1751 * (1) Only for DM642
1752 *
1753 \******************************************************************************/
1755 #if (CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412 || CHIP_6410 || CHIP_6413 || CHIP_6418)
1757 #define _CHIP_PCFGLOCK_ADDR 0x01B3F018u
1758 #define _CHIP_PCFGLOCK_OFFSET 0
1760 #define _CHIP_PCFGLOCK_LOCKSTAT_MASK 0x00000001u
1761 #define _CHIP_PCFGLOCK_LOCKSTAT_SHIFT 0x00000000u
1762 #define CHIP_PCFGLOCK_LOCKSTAT_DEFAULT 0x00000001u
1763 #define CHIP_PCFGLOCK_LOCKSTAT_OF(x) _VALUEOF(x)
1764 #define CHIP_PCFGLOCK_LOCKSTAT_UNLOCK 0x00000000u
1765 #define CHIP_PCFGLOCK_LOCKSTAT_LOCK 0x00000001u
1767 #define _CHIP_PCFGLOCK_LOCK_MASK 0xFFFFFFFFu
1768 #define _CHIP_PCFGLOCK_LOCK_SHIFT 0x00000000u
1769 #define CHIP_PCFGLOCK_LOCK_DEFAULT 0x00000000u
1770 #define CHIP_PCFGLOCK_LOCK_OF(x) _VALUEOF(x)
1771 #define CHIP_PCFGLOCK_LOCK_UNLOCK 0x10C0010Cu
1772 #define CHIP_PCFGLOCK_LOCK_DISABLE 0x10C0010Cu
1774 #define CHIP_PCFGLOCK_OF(x) _VALUEOF(x)
1776 #define _CHIP_PCFGLOCK_FGET(FIELD)\
1777 _PER_FGET(_CHIP_PCFGLOCK_ADDR,CHIP,PCFGLOCK,##FIELD)
1779 #define _CHIP_PCFGLOCK_FSET(FIELD,field)\
1780 _PER_FSET(_CHIP_PCFGLOCK_ADDR,CHIP,PCFGLOCK,##FIELD,field)
1782 #define _CHIP_PCFGLOCK_FSETS(FIELD,SYM)\
1783 _PER_FSETS(_CHIP_PCFGLOCK_ADDR,CHIP,PCFGLOCK,##FIELD,##SYM)
1786 #endif /* CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412 || CHIP_6410 || CHIP_6413 || CHIP_6418*/
1788 #ifdef __cplusplus
1789 }
1790 #endif
1792 /*----------------------------------------------------------------------------*/
1793 #endif /* _CSL_CHIPHAL_H_ */
1794 /******************************************************************************\
1795 * End of csl_chiphal.h
1796 \******************************************************************************/