1 /******************************************************************************\
2 * Copyright (C) 1999-2000 Texas Instruments Incorporated.
3 * All Rights Reserved
4 *------------------------------------------------------------------------------
5 * FILENAME...... csl_edma.h
6 * DATE CREATED.. 06/11/1999
7 * LAST MODIFIED. 14/9/2005 Modified EDMA_getChannel and EDMA_setEvtPolarity to return
8 * proper values and can set polarities properly respectively.
9 * 08/13/2004 Modified tccAllocTable type from static to global fn.
10 * 08/02/2004 - Adding support for C6418
11 * 04/16/2004 Modified tccAllocTable[0] entry to 0.
12 * 02/09/2004 Removed volatile variable type from EDMA_chain inline fn.
13 * 06/17/2003 added support for 6712C
14 * 05/28/2003 added support for 6711C
15 * 02/15/2002 added EDMA channel events 6713/DM642 - EDMA_map()
16 * 04/16/2001
17 \******************************************************************************/
18 #ifndef _CSL_EDMA_H_
19 #define _CSL_EDMA_H_
21 #include <csl_chip.h>
22 #include <csl_irq.h>
23 #include <csl_edmahal.h>
26 #if (EDMA_SUPPORT)
27 /******************************************************************************\
28 * scope and inline control macros
29 \******************************************************************************/
30 #ifdef __cplusplus
31 #define CSLAPI extern "C" far
32 #else
33 #define CSLAPI extern far
34 #endif
36 #undef USEDEFS
37 #undef IDECL
38 #undef IDEF
40 #ifdef _EDMA_MOD_
41 #define IDECL CSLAPI
42 #define USEDEFS
43 #define IDEF
44 #else
45 #ifdef _INLINE
46 #define IDECL static inline
47 #define USEDEFS
48 #define IDEF static inline
49 #else
50 #define IDECL CSLAPI
51 #endif
52 #endif
55 /******************************************************************************\
56 * global macro declarations
57 \******************************************************************************/
58 #define EDMA_CHA_CNT (_EDMA_CHA_CNT)
59 #define EDMA_TABLE_CNT (_EDMA_LINK_CNT)
60 #define EDMA_ALLOC_ANY (-1)
62 #define EDMA_OPEN_RESET (0x00000001)
63 #define EDMA_OPEN_ENABLE (0x00000002)
66 #if(CHIP_6201|CHIP_6202|CHIP_6203|CHIP_6204|CHIP_6205|CHIP_6701|C11_SUPPORT)
67 #define EDMA_CHA_ANY -1
68 #define EDMA_CHA_DSPINT 0
69 #define EDMA_CHA_TINT0 1
70 #define EDMA_CHA_TINT1 2
71 #define EDMA_CHA_SDINT 3
72 #define EDMA_CHA_EXTINT4 4
73 #define EDMA_CHA_EXTINT5 5
74 #define EDMA_CHA_EXTINT6 6
75 #define EDMA_CHA_EXTINT7 7
76 #define EDMA_CHA_TCC8 8
77 #define EDMA_CHA_TCC9 9
78 #define EDMA_CHA_TCC10 10
79 #define EDMA_CHA_TCC11 11
80 #define EDMA_CHA_XEVT0 12
81 #define EDMA_CHA_REVT0 13
82 #define EDMA_CHA_XEVT1 14
83 #define EDMA_CHA_REVT1 15
84 #endif
85 #if (CHIP_6711C || CHIP_6712C)
86 #define EDMA_CHA_GPINT4 4
87 #define EDMA_CHA_GPINT5 5
88 #define EDMA_CHA_GPINT6 6
89 #define EDMA_CHA_GPINT7 7
90 #define EDMA_CHA_GPINT2 10
91 #endif
93 #if (CHIP_6713 | CHIP_DA610 | CHIP_6414 | CHIP_6415 | CHIP_6416 | \
94 CHIP_6411 | CHIP_6410 | CHIP_6413 | CHIP_6418)
95 #define EDMA_CHA_ANY -1
96 #define EDMA_CHA_DSPINT 0
97 #define EDMA_CHA_TINT0 1
98 #define EDMA_CHA_TINT1 2
99 #define EDMA_CHA_SDINT 3
100 #define EDMA_CHA_EXTINT4 4
101 #define EDMA_CHA_GPINT4 4
102 #define EDMA_CHA_EXTINT5 5
103 #define EDMA_CHA_GPINT5 5
104 #define EDMA_CHA_EXTINT6 6
105 #define EDMA_CHA_GPINT6 6
106 #define EDMA_CHA_EXTINT7 7
107 #define EDMA_CHA_GPINT7 7
108 #define EDMA_CHA_TCC8 8
109 #define EDMA_CHA_GPINT0 8
110 #define EDMA_CHA_TCC9 9
111 #define EDMA_CHA_GPINT1 9
112 #define EDMA_CHA_TCC10 10
113 #define EDMA_CHA_GPINT2 10
114 #define EDMA_CHA_TCC11 11
115 #define EDMA_CHA_GPINT3 11
116 #define EDMA_CHA_XEVT0 12
117 #define EDMA_CHA_REVT0 13
118 #define EDMA_CHA_XEVT1 14
119 #define EDMA_CHA_REVT1 15
121 /* Individual mappings for next few events are specified under #ifdefs below. */
123 #define EDMA_CHA_GPINT8 48
124 #define EDMA_CHA_GPINT9 49
125 #define EDMA_CHA_GPINT10 50
126 #define EDMA_CHA_GPINT11 51
127 #define EDMA_CHA_GPINT12 52
128 #define EDMA_CHA_GPINT13 53
129 #define EDMA_CHA_GPINT14 54
130 #define EDMA_CHA_GPINT15 55
131 #endif
134 /* 3rd MCBSP/ PCI / UTOPIA / VCP / TCP channel numbers for EDMA_open() */
135 #if (CHIP_6414 || CHIP_6415 || CHIP_6416 )
136 #define EDMA_CHA_XEVT2 17
137 #define EDMA_CHA_REVT2 18
138 #define EDMA_CHA_TINT2 19
139 #define EDMA_CHA_SDINTB 20
140 #define EDMA_CHA_PCI 21
141 #define EDMA_CHA_VCPREVT 28
142 #define EDMA_CHA_VCPXEVT 29
143 #define EDMA_CHA_TCPREVT 30
144 #define EDMA_CHA_TCPXEVT 31
145 #define EDMA_CHA_UREVT 32
146 #define EDMA_CHA_UREVT0 32
147 #define EDMA_CHA_UREVT1 33
148 #define EDMA_CHA_UREVT2 34
149 #define EDMA_CHA_UREVT3 35
150 #define EDMA_CHA_UREVT4 36
151 #define EDMA_CHA_UREVT5 37
152 #define EDMA_CHA_UREVT6 38
153 #define EDMA_CHA_UREVT7 39
154 #define EDMA_CHA_UXEVT 40
155 #define EDMA_CHA_UXEVT0 40
156 #define EDMA_CHA_UXEVT1 41
157 #define EDMA_CHA_UXEVT2 42
158 #define EDMA_CHA_UXEVT3 43
159 #define EDMA_CHA_UXEVT4 44
160 #define EDMA_CHA_UXEVT5 45
161 #define EDMA_CHA_UXEVT6 46
162 #define EDMA_CHA_UXEVT7 47
163 #endif
165 /* 2 MCASPs - 2 I2Cs channels */
166 #if (CHIP_6713 || CHIP_DA610)
167 #define EDMA_CHA_AXEVTE0 32
168 #define EDMA_CHA_AXEVTO0 33
169 #define EDMA_CHA_AXEVT0 34
170 #define EDMA_CHA_AREVTE0 35
171 #define EDMA_CHA_AREVTO0 36
172 #define EDMA_CHA_AREVT0 37
173 #define EDMA_CHA_AXEVTE1 38
174 #define EDMA_CHA_AXEVTO1 39
175 #define EDMA_CHA_AXEVT1 40
176 #define EDMA_CHA_AREVTE1 41
177 #define EDMA_CHA_AREVTO1 42
178 #define EDMA_CHA_AREVT1 43
179 #define EDMA_CHA_ICREVT0 44
180 #define EDMA_CHA_ICXEVT0 45
181 #define EDMA_CHA_ICREVT1 46
182 #define EDMA_CHA_ICXEVT1 47
183 #endif
185 #if (CHIP_6410 || CHIP_6413| CHIP_6418)
186 #define EDMA_CHA_TINT2 19
188 #if (CHIP_6418)
189 #define EDMA_CHA_VCPREVT0 28
190 #define EDMA_CHA_VCPXEVT0 29
191 #endif
193 #define EDMA_CHA_AXEVTE0 32
194 #define EDMA_CHA_AXEVTO0 33
195 #define EDMA_CHA_AXEVT0 34
196 #define EDMA_CHA_AREVTE0 35
197 #define EDMA_CHA_AREVTO0 36
198 #define EDMA_CHA_AREVT0 37
199 #define EDMA_CHA_AXEVTE1 38
200 #define EDMA_CHA_AXEVTO1 39
201 #define EDMA_CHA_AXEVT1 40
202 #define EDMA_CHA_AREVTE1 41
203 #define EDMA_CHA_AREVTO1 42
204 #define EDMA_CHA_AREVT1 43
205 #define EDMA_CHA_ICREVT0 44
206 #define EDMA_CHA_ICXEVT0 45
207 #define EDMA_CHA_ICREVT1 46
208 #define EDMA_CHA_ICXEVT1 47
209 #endif
211 #if (CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412)
212 #define EDMA_CHA_ANY -1
214 #if !(CHIP_DM640)
215 #define EDMA_CHA_DSPINT 0
216 #endif
218 #define EDMA_CHA_TINT0 1
219 #define EDMA_CHA_TINT1 2
220 #define EDMA_CHA_SDINT 3
221 #define EDMA_CHA_EXTINT4 4
222 #define EDMA_CHA_GPINT4 4
223 #define EDMA_CHA_EXTINT5 5
224 #define EDMA_CHA_GPINT5 5
225 #define EDMA_CHA_EXTINT6 6
226 #define EDMA_CHA_GPINT6 6
227 #define EDMA_CHA_EXTINT7 7
228 #define EDMA_CHA_GPINT7 7
229 #define EDMA_CHA_GPINT0 8
230 #define EDMA_CHA_TCC8 8
231 #define EDMA_CHA_GPINT1 9
232 #define EDMA_CHA_TCC9 9
233 #define EDMA_CHA_GPINT2 10
234 #define EDMA_CHA_TCC10 10
235 #define EDMA_CHA_GPINT3 11
236 #define EDMA_CHA_TCC11 11
237 #define EDMA_CHA_XEVT0 12
238 #define EDMA_CHA_REVT0 13
239 #define EDMA_CHA_XEVT1 14
240 #define EDMA_CHA_REVT1 15
242 /* Note: EDMA_CHA_TCC8, EDMA_CHA_TCC9, EDMA_CHA_TCC10 and EDMA_CHA_TCC11 are
243 NOT defined here, but they are included here for C64x consistency purposes */
245 #if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640)
246 #define EDMA_CHA_VP0EVTYA 16
247 #define EDMA_CHA_VP0EVTUA 17
248 #define EDMA_CHA_VP0EVTVA 18
249 #endif
251 #define EDMA_CHA_TINT2 19
253 #if (CHIP_DM642)
254 #define EDMA_CHA_VP0EVTYB 24
255 #define EDMA_CHA_VP0EVTUB 25
256 #define EDMA_CHA_VP0EVTVB 26
257 #endif
259 #if !(CHIP_6412)
260 #define EDMA_CHA_AXEVTE0 32
261 #define EDMA_CHA_AXEVTO0 33
262 #define EDMA_CHA_AXEVT0 34
263 #define EDMA_CHA_AREVTE0 35
264 #define EDMA_CHA_AREVTO0 36
265 #define EDMA_CHA_AREVT0 37
266 #endif
268 #if (CHIP_DM642)
269 #define EDMA_CHA_VP1EVTYB 38
270 #define EDMA_CHA_VP1EVTUB 39
271 #define EDMA_CHA_VP1EVTVB 40
272 #define EDMA_CHA_VP2EVTYB 41
273 #define EDMA_CHA_VP2EVTUB 42
274 #define EDMA_CHA_VP2EVTVB 43
275 #endif
277 #define EDMA_CHA_ICREVT0 44
278 #define EDMA_CHA_ICXEVT0 45
280 #define EDMA_CHA_GPINT8 48
281 #define EDMA_CHA_GPINT9 49
282 #define EDMA_CHA_GPINT10 50
283 #define EDMA_CHA_GPINT11 51
284 #define EDMA_CHA_GPINT12 52
285 #define EDMA_CHA_GPINT13 53
286 #define EDMA_CHA_GPINT14 54
287 #define EDMA_CHA_GPINT15 55
290 #if (CHIP_DM642 | CHIP_DM641)
291 #define EDMA_CHA_VP1EVTYA 56
292 #define EDMA_CHA_VP1EVTUA 57
293 #define EDMA_CHA_VP1EVTVA 58
294 #endif
296 #if (CHIP_DM642)
297 #define EDMA_CHA_VP2EVTYA 59
298 #define EDMA_CHA_VP2EVTUA 60
299 #define EDMA_CHA_VP2EVTVA 61
300 #endif
302 #endif
304 #define _EDMA_TYPE_C (0x80000000)
305 #define _EDMA_TYPE_T (0x40000000)
306 #define _EDMA_TYPE_Q (0x20000000)
307 #define _EDMA_TYPE_S (0x10000000)
310 #define _EDMA_MK_HANDLE(base,index,flags) (EDMA_Handle)(\
311 ((base)&0x0000FFFF)|(((index)<<16)&0x00FF0000)|((flags)&0xFF000000)\
312 )
314 #define EDMA_HQDMA _EDMA_MK_HANDLE(0x00000000,0,_EDMA_TYPE_Q)
315 #define EDMA_HQSDMA _EDMA_MK_HANDLE(0x00000000,0,_EDMA_TYPE_S)
316 #define EDMA_HINV _EDMA_MK_HANDLE(0x00000000,0,0)
318 #define EDMA_HNULL _EDMA_MK_HANDLE(_EDMA_NULL_PARAM,0,_EDMA_TYPE_T)
319 #define NULL_FUNC 0
321 /* Priority Queues */
322 #define EDMA_Q0 0
323 #define EDMA_Q1 1
324 #define EDMA_Q2 2
325 #define EDMA_Q3 3
327 /* Event Polarity */
328 #define EDMA_EVT_LOWHIGH 0
329 #define EDMA_EVT_HIGHLOW 1
331 /* Chaining Flag */
332 #define EDMA_TCC_SET 1
333 #define EDMA_ATCC_SET 1
335 /******************************************************************************\
336 * global typedef declarations
337 \******************************************************************************/
338 typedef Uint32 EDMA_Handle;
340 typedef struct {
341 Uint32 opt;
342 Uint32 src;
343 Uint32 cnt;
344 Uint32 dst;
345 Uint32 idx;
346 Uint32 rld;
347 } EDMA_Config;
349 typedef void (*EDMA_IntHandler)(int tccNum);
351 /******************************************************************************\
352 * global variable declarations
353 \******************************************************************************/
354 #define EDMA_hNull EDMA_HNULL
356 extern far Uint8 tccAllocTable[64];
358 /******************************************************************************\
359 * global function declarations
360 \******************************************************************************/
361 CSLAPI void EDMA_reset(EDMA_Handle hEdma);
362 CSLAPI void EDMA_resetAll();
364 CSLAPI EDMA_Handle EDMA_open(int chaNum, Uint32 flags);
365 CSLAPI void EDMA_close(EDMA_Handle hEdma);
366 CSLAPI EDMA_Handle EDMA_allocTable(int tableNum);
367 CSLAPI void EDMA_freeTable(EDMA_Handle hEdma);
369 CSLAPI int EDMA_allocTableEx(int cnt, EDMA_Handle *array);
370 CSLAPI void EDMA_freeTableEx(int cnt, EDMA_Handle *array);
372 CSLAPI void EDMA_clearPram(Uint32 val);
374 CSLAPI int EDMA_intAlloc(int tcc);
375 CSLAPI void EDMA_intFree(int tcc);
376 /* 6713? */
378 #if (CHIP_6713 || CHIP_DA610 || CHIP_6711C || CHIP_6712C)
379 CSLAPI int EDMA_map(int eventNum,int chaNum);
380 #endif
382 CSLAPI EDMA_IntHandler EDMA_intHook(int tccNum, EDMA_IntHandler funcAddr);
383 CSLAPI void EDMA_intDefaultHandler(int tccNum);
384 CSLAPI void EDMA_intDispatcher();
386 /******************************************************************************\
387 * inline function declarations
388 \******************************************************************************/
389 IDECL Uint32 EDMA_getScratchAddr();
390 IDECL Uint32 EDMA_getScratchSize();
391 IDECL Uint32 EDMA_getPriQStatus();
392 #if (C64_SUPPORT)
393 IDECL void EDMA_setPriQLength(Uint32 priNum, Uint32 length);
394 IDECL void EDMA_resetPriQLength(Uint32 priNum);
395 #endif
397 IDECL void EDMA_enableChannel(EDMA_Handle hEdma);
398 IDECL void EDMA_disableChannel(EDMA_Handle hEdma);
399 IDECL void EDMA_setChannel(EDMA_Handle hEdma);
400 IDECL Uint32 EDMA_getChannel(EDMA_Handle hEdma);
401 IDECL void EDMA_clearChannel(EDMA_Handle hEdma);
402 #if (C64_SUPPORT)
403 IDECL void EDMA_setEvtPolarity(EDMA_Handle hEdma,int polarity);
404 #endif
405 IDECL Uint32 EDMA_getTableAddress(EDMA_Handle hEdma);
407 IDECL void EDMA_intEnable(Uint32 tccIntNum);
408 IDECL void EDMA_intDisable(Uint32 tccIntNum);
409 IDECL void EDMA_intClear(Uint32 tccIntNum);
410 IDECL Uint32 EDMA_intTest(Uint32 tccIntNum);
411 IDECL void EDMA_intReset(Uint32 tccIntNum);
412 IDECL void EDMA_intResetAll();
414 IDECL void EDMA_link(EDMA_Handle parent, EDMA_Handle child);
416 IDECL void EDMA_config(EDMA_Handle hEdma, EDMA_Config *config);
417 IDECL void EDMA_configArgs(EDMA_Handle hEdma, Uint32 opt, Uint32 src,
418 Uint32 cnt, Uint32 dst, Uint32 idx, Uint32 rld);
419 IDECL void EDMA_getConfig(EDMA_Handle hEdma, EDMA_Config *config);
421 IDECL void EDMA_qdmaConfig(EDMA_Config *config);
422 IDECL void EDMA_qdmaConfigArgs(Uint32 opt, Uint32 src, Uint32 cnt, Uint32 dst,
423 Uint32 idx);
424 IDECL void EDMA_qdmaGetConfig(EDMA_Config *config);
426 IDECL void EDMA_enableChaining(EDMA_Handle hEdma);
427 IDECL void EDMA_disableChaining(EDMA_Handle hEdma);
428 IDECL void EDMA_chain(EDMA_Handle parent, EDMA_Handle nextChannel,int tccflag, int atccflag);
430 /******************************************************************************\
431 * inline function definitions
432 \******************************************************************************/
433 #ifdef USEDEFS
434 /*----------------------------------------------------------------------------*/
435 IDEF Uint32 EDMA_getScratchAddr() {
436 return (Uint32)_EDMA_SCRATCH_START;
437 }
438 /*----------------------------------------------------------------------------*/
439 IDEF Uint32 EDMA_getScratchSize() {
440 return (Uint32)_EDMA_SCRATCH_SIZE;
441 }
442 /*----------------------------------------------------------------------------*/
443 IDEF Uint32 EDMA_getPriQStatus() {
444 return (Uint32)EDMA_RGET(PQSR);
445 }
446 /*----------------------------------------------------------------------------*/
447 #if (C64_SUPPORT)
448 IDEF void EDMA_setPriQLength(Uint32 priNum, Uint32 length) {
449 if (priNum == 0x0) {
450 EDMA_RSET(PQAR0,(0x00000007 & length));
451 } else {
452 if (priNum == 0x1) {
453 EDMA_RSET(PQAR1,(0x00000007 & length));
454 }else {
455 if (priNum == 0x2) {
456 EDMA_RSET(PQAR2,(0x00000007 & length));
457 } else {
458 if (priNum == 0x3) {
459 EDMA_RSET(PQAR3,(0x00000007 & length));
460 }
461 }
462 }
463 }
464 }
465 /*----------------------------------------------------------------------------*/
467 IDEF void EDMA_resetPriQLength(Uint32 priNum) {
468 if (priNum == 0x0) {
469 EDMA_FSET(PQAR0,PQA,EDMA_PQAR0_PQA_DEFAULT);
470 } else {
471 if (priNum == 0x1) {
472 EDMA_FSET(PQAR1,PQA,EDMA_PQAR1_PQA_DEFAULT);
473 } else {
474 if (priNum == 0x2) {
475 EDMA_FSET(PQAR2,PQA,EDMA_PQAR2_PQA_DEFAULT);
476 }else {
477 if (priNum == 0x3) {
478 EDMA_FSET(PQAR3,PQA,EDMA_PQAR3_PQA_DEFAULT);
479 }
480 }
481 }
482 }
483 }
484 #endif
485 /*----------------------------------------------------------------------------*/
486 IDEF void EDMA_enableChannel(EDMA_Handle hEdma) {
488 int gie;
489 int chaNum = (hEdma & 0x00FF0000)>>16;
491 gie = IRQ_globalDisable();
492 #if (C64_SUPPORT)
493 if (chaNum < 32) EDMA_RSET(EERL,EDMA_RGET(EERL) | (1<<chaNum));
494 else EDMA_RSET(EERH,EDMA_RGET(EERH) | (1<<(chaNum-32)));
495 #else
496 EDMA_RSET(EER,EDMA_RGET(EER) | (1<<chaNum));
497 #endif
498 IRQ_globalRestore(gie);
499 }
500 /*----------------------------------------------------------------------------*/
501 IDEF void EDMA_enableChaining(EDMA_Handle hEdma) {
503 int gie;
504 int chaNum = (hEdma & 0x00FF0000)>>16;
506 gie = IRQ_globalDisable();
507 #if (C64_SUPPORT)
508 if (chaNum < 32) EDMA_RSET(CCERL,EDMA_RGET(CCERL) | (1<<chaNum));
509 else EDMA_RSET(CCERH,EDMA_RGET(CCERH) | (1<<(chaNum-32)));
510 #else
512 EDMA_RSET(CCER,EDMA_RGET(CCER) | (1<<chaNum));
513 #endif
514 IRQ_globalRestore(gie);
515 }
516 /*----------------------------------------------------------------------------*/
517 IDEF void EDMA_chain(EDMA_Handle parent, EDMA_Handle nextChannel,int tccflag, int atccflag) {
518 #if (C64_SUPPORT)
519 Uint32 tccm,tcc;
520 #endif
521 int TccNum = (nextChannel & 0x00FF0000)>>16;
522 int gie;
524 gie = IRQ_globalDisable();
526 if (tccflag) {
527 #if (C64_SUPPORT) /* SET TCCM and TCC fields */
528 if (TccNum < 16) { tccm = 0 ; tcc = TccNum;}
529 else {
530 if ( TccNum > 15 && TccNum < 32 ) { tccm = 1 ; tcc = TccNum-16;}
531 else {
532 if ( TccNum > 31 && TccNum < 48 ) { tccm = 2 ; tcc = TccNum-32;}
533 else { /* channel > 47 */
534 tccm = 3 ; tcc = TccNum-48;
535 }
536 }
537 }
538 EDMA_FSETH(parent,OPT,TCCM,tccm);
539 EDMA_FSETH(parent,OPT,TCC,tcc);
540 EDMA_FSETH(parent,OPT,TCINT,1);
541 #else
542 EDMA_FSETH(parent,OPT,TCC,TccNum);
543 EDMA_FSETH(parent,OPT,TCINT,1);
544 #endif
545 }
546 /* ATCC */
547 if (atccflag) {
548 #if C64_SUPPORT
549 EDMA_FSETH(parent,OPT,ATCC,TccNum);
550 EDMA_FSETH(parent,OPT,ATCINT,1);
551 #endif
552 }
553 tccAllocTable[TccNum] = 1;
554 IRQ_globalRestore(gie);
555 }
556 /*----------------------------------------------------------------------------*/
557 IDEF void EDMA_disableChannel(EDMA_Handle hEdma) {
559 int chaNum = (hEdma & 0x00FF0000)>>16;
560 int gie;
562 gie = IRQ_globalDisable();
564 #if (C64_SUPPORT)
565 if (chaNum < 32) EDMA_RSET(EERL,EDMA_RGET(EERL) & ~(1<<chaNum));
566 else EDMA_RSET(EERH,EDMA_RGET(EERH) & ~(1<<(chaNum-32)));
567 #else
568 EDMA_RSET(EER,EDMA_RGET(EER) & ~(1<<chaNum));
569 #endif
570 IRQ_globalRestore(gie);
571 }
572 /*----------------------------------------------------------------------------*/
573 IDEF void EDMA_disableChaining(EDMA_Handle hEdma) {
575 int chaNum = (hEdma & 0x00FF0000)>>16;
576 int gie;
578 gie = IRQ_globalDisable();
579 #if (C64_SUPPORT)
580 if (chaNum < 32) EDMA_RSET(CCERL,EDMA_RGET(CCERL) & ~(1<<chaNum));
581 else EDMA_RSET(CCERH,EDMA_RGET(CCERH) & ~(1<<(chaNum-32)));
582 #else
583 EDMA_RSET(CCER,EDMA_RGET(CCER) & ~(1<<chaNum));
584 #endif
585 IRQ_globalRestore(gie);
586 }
587 /*----------------------------------------------------------------------------*/
588 IDEF void EDMA_setChannel(EDMA_Handle hEdma) {
590 int chaNum = (hEdma & 0x00FF0000)>>16;
592 #if (C64_SUPPORT)
593 if (chaNum < 32) EDMA_RSET(ESRL,1<<chaNum);
594 else EDMA_RSET(ESRH,1<<(chaNum-32));
595 #else
596 EDMA_RSET(ESR,1<<chaNum);
597 #endif
598 }
599 /*----------------------------------------------------------------------------*/
600 IDEF Uint32 EDMA_getChannel(EDMA_Handle hEdma) {
602 int chaNum = (hEdma & 0x00FF0000)>>16;
604 #if (C64_SUPPORT)
605 if (chaNum < 32) return (Uint32)(((EDMA_RGET(ERL) >> chaNum) & 1)==1);
606 else return (Uint32)(((EDMA_RGET(ERH) >> (chaNum-32)) & 1)==1);
608 #else
609 return (Uint32)(((EDMA_RGET(ER) >>chaNum) & 1)==1);
610 #endif
611 }
612 /*----------------------------------------------------------------------------*/
613 IDEF void EDMA_clearChannel(EDMA_Handle hEdma) {
615 int chaNum = (hEdma & 0x00FF0000)>>16;
617 #if (C64_SUPPORT)
618 if (chaNum < 32) EDMA_RSET(ECRL,1<<chaNum);
619 else EDMA_RSET(ECRH,1<<(chaNum-32));
620 #else
621 EDMA_RSET(ECR,1<<chaNum);
622 #endif
623 }
624 /*----------------------------------------------------------------------------*/
625 #if (C64_SUPPORT)
626 IDEF void EDMA_setEvtPolarity(EDMA_Handle hEdma,int polarity) {
628 int chaNum = (hEdma & 0x00FF0000)>>16;
630 #if (C64_SUPPORT)
631 if (chaNum < 32) EDMA_RSET(EPRL,(polarity<<chaNum) | EDMA_RGET(EPRL));
632 else EDMA_RSET(EPRH,(polarity<<(chaNum-32)) | EDMA_RGET(EPRH));
633 #endif
634 }
635 #endif
636 /*----------------------------------------------------------------------------*/
637 IDEF Uint32 EDMA_getTableAddress(EDMA_Handle hEdma) {
639 return (hEdma&0x0000FFFF)+_EDMA_PRAM_START;
640 }
641 /*----------------------------------------------------------------------------*/
642 IDEF void EDMA_intEnable(Uint32 tccIntNum) {
643 int gie;
645 gie = IRQ_globalDisable();
647 #if (C64_SUPPORT)
648 if (tccIntNum < 32) EDMA_RSET(CIERL,EDMA_RGET(CIERL) | (1<<tccIntNum));
649 else EDMA_RSET(CIERH,EDMA_RGET(CIERH) | (1<<(tccIntNum-32)));
650 #else
651 EDMA_RSET(CIER,EDMA_RGET(CIER) | (1<<tccIntNum));
652 #endif
654 IRQ_globalRestore(gie);
655 }
656 /*----------------------------------------------------------------------------*/
657 IDEF void EDMA_intDisable(Uint32 tccIntNum) {
658 int gie;
660 gie = IRQ_globalDisable();
662 #if (C64_SUPPORT)
663 if (tccIntNum < 32) EDMA_RSET(CIERL,EDMA_RGET(CIERL) & ~(1<<tccIntNum));
664 else EDMA_RSET(CIERH,EDMA_RGET(CIERH) & ~(1<<(tccIntNum-32)));
665 #else
666 EDMA_RSET(CIER,EDMA_RGET(CIER) & ~(1<<tccIntNum));
667 #endif
669 IRQ_globalRestore(gie);
670 }
671 /*----------------------------------------------------------------------------*/
672 IDEF void EDMA_intClear(Uint32 tccIntNum) {
674 #if (C64_SUPPORT)
675 if (tccIntNum < 32) EDMA_RSET(CIPRL,1<<tccIntNum);
676 else EDMA_RSET(CIPRH,1<<(tccIntNum-32));
677 #else
678 EDMA_RSET(CIPR,1<<tccIntNum);
679 #endif
680 }
681 /*----------------------------------------------------------------------------*/
682 IDEF Uint32 EDMA_intTest(Uint32 tccIntNum) {
684 #if (C64_SUPPORT)
685 if (tccIntNum < 32) return ((EDMA_RGET(CIPRL) & (1<<tccIntNum)) ? 1 : 0);
686 else return ((EDMA_RGET(CIPRH) & (1<<(tccIntNum-32))) ? 1 : 0);
687 #else
688 return ((EDMA_RGET(CIPR) & (1<<tccIntNum)) ? 1 : 0);
689 #endif
690 }
691 /*----------------------------------------------------------------------------*/
692 IDEF void EDMA_intReset(Uint32 tccIntNum) {
693 int gie;
695 gie = IRQ_globalDisable();
697 /* disable then clear interrupt */
698 #if (C64_SUPPORT)
699 if (tccIntNum < 32) {
700 EDMA_RSET(CIERL,EDMA_RGET(CIERL) & ~(1<<tccIntNum));
701 EDMA_RSET(CIPRL,1<<tccIntNum);
702 } else {
703 EDMA_RSET(CIERH,EDMA_RGET(CIERH) & ~(1<<(tccIntNum-32)));
704 EDMA_RSET(CIPRH,1<<(tccIntNum-32));
705 }
706 #else
707 EDMA_RSET(CIER,EDMA_RGET(CIER) & ~(1<<tccIntNum));
708 EDMA_RSET(CIPR,1<<tccIntNum);
709 #endif
710 IRQ_globalRestore(gie);
711 }
712 /*----------------------------------------------------------------------------*/
713 IDEF void EDMA_intResetAll() {
715 int gie = IRQ_globalDisable();
716 /* disable then clear all interrupts */
718 #if (C64_SUPPORT)
719 EDMA_RSET(CIERL, 0x00000000);
720 EDMA_RSET(CIERH, 0x00000000);
721 EDMA_RSET(CIPRL, 0xFFFFFFFF);
722 EDMA_RSET(CIPRH, 0xFFFFFFFF);
723 #else
724 EDMA_RSET(CIER, 0x00000000);
725 EDMA_RSET(CIPR, 0xFFFFFFFF);
726 #endif
728 IRQ_globalRestore(gie);
729 }
730 /*----------------------------------------------------------------------------*/
731 IDEF void EDMA_link(EDMA_Handle parent, EDMA_Handle child) {
732 EDMA_FSETH(parent,RLD,LINK,child);
733 }
734 /*----------------------------------------------------------------------------*/
735 IDEF void EDMA_config(EDMA_Handle hEdma, EDMA_Config *config) {
737 Uint32 gie;
738 volatile Uint32 *base;
739 register Uint32 x0,x1,x2,x3,x4,x5;
741 /* Test if QDMA handle was passed with CCS 1.2 */
742 if ( hEdma == (0x20000000) || hEdma == (0x10000000)) {
743 EDMA_qdmaConfig(config);
744 }else{
746 gie = IRQ_globalDisable();
748 x0 = config->opt;
749 x1 = config->src;
750 x2 = config->cnt;
751 x3 = config->dst;
752 x4 = config->idx;
753 x5 = config->rld;
755 base = (volatile Uint32 *)((hEdma&0x0000FFFF)+_EDMA_PRAM_START);
756 base[_EDMA_OPT_OFFSET] = 0x00000000;
757 base[_EDMA_SRC_OFFSET] = x1;
758 base[_EDMA_CNT_OFFSET] = x2;
759 base[_EDMA_DST_OFFSET] = x3;
760 base[_EDMA_IDX_OFFSET] = x4;
761 base[_EDMA_RLD_OFFSET] = x5;
762 base[_EDMA_OPT_OFFSET] = x0;
763 IRQ_globalRestore(gie);
764 }
765 }
766 /*----------------------------------------------------------------------------*/
767 IDEF void EDMA_configArgs(EDMA_Handle hEdma, Uint32 opt, Uint32 src,
768 Uint32 cnt, Uint32 dst, Uint32 idx, Uint32 rld) {
770 Uint32 gie;
771 volatile Uint32 *base;
772 /* Test if QDMA handle was passed with CCS 1.2 */
773 if ( hEdma == (0x20000000) || hEdma == (0x10000000)) {
774 EDMA_qdmaConfigArgs(opt, src, cnt, dst, idx);
775 }else{
776 gie = IRQ_globalDisable();
777 base = (volatile Uint32*)((hEdma&0x0000FFFF)+_EDMA_PRAM_START);
778 base[_EDMA_OPT_OFFSET] = 0x00000000;
779 base[_EDMA_SRC_OFFSET] = src;
780 base[_EDMA_CNT_OFFSET] = cnt;
781 base[_EDMA_DST_OFFSET] = dst;
782 base[_EDMA_IDX_OFFSET] = idx;
783 base[_EDMA_RLD_OFFSET] = rld;
784 base[_EDMA_OPT_OFFSET] = opt;
785 IRQ_globalRestore(gie);
786 }
787 }
788 /*----------------------------------------------------------------------------*/
789 IDEF void EDMA_getConfig(EDMA_Handle hEdma, EDMA_Config *config) {
791 Uint32 gie;
792 volatile Uint32 *base;
793 register Uint32 x0,x1,x2,x3,x4,x5;
795 gie = IRQ_globalDisable();
797 base = (volatile Uint32 *)((hEdma&0x0000FFFF)+_EDMA_PRAM_START);
798 x0 = base[_EDMA_OPT_OFFSET];
799 x1 = base[_EDMA_SRC_OFFSET];
800 x2 = base[_EDMA_CNT_OFFSET];
801 x3 = base[_EDMA_DST_OFFSET];
802 x4 = base[_EDMA_IDX_OFFSET];
803 x5 = base[_EDMA_RLD_OFFSET];
805 config->opt = x0;
806 config->src = x1;
807 config->cnt = x2;
808 config->dst = x3;
809 config->idx = x4;
810 config->rld = x5;
812 IRQ_globalRestore(gie);
813 }
814 /*----------------------------------------------------------------------------*/
815 IDEF void EDMA_qdmaConfig(EDMA_Config *config) {
817 Uint32 gie;
818 volatile Uint32 *base;
819 register Uint32 x0,x1,x2,x3,x4;
821 gie = IRQ_globalDisable();
823 x0 = config->opt;
824 x1 = config->src;
825 x2 = config->cnt;
826 x3 = config->dst;
827 x4 = config->idx;
829 base = (volatile Uint32 *)(_EDMA_QOPT_ADDR);
830 base[_EDMA_QSRC_OFFSET] = x1;
831 base[_EDMA_QCNT_OFFSET] = x2;
832 base[_EDMA_QDST_OFFSET] = x3;
833 base[_EDMA_QIDX_OFFSET] = x4;
834 base[_EDMA_QSOPT_OFFSET] = x0;
836 IRQ_globalRestore(gie);
837 }
838 /*----------------------------------------------------------------------------*/
839 IDEF void EDMA_qdmaConfigArgs(Uint32 opt, Uint32 src, Uint32 cnt, Uint32 dst,
840 Uint32 idx) {
842 Uint32 gie;
843 volatile Uint32 *base;
845 gie = IRQ_globalDisable();
847 base = (volatile Uint32*)(_EDMA_QOPT_ADDR);
848 base[_EDMA_QSRC_OFFSET] = src;
849 base[_EDMA_QCNT_OFFSET] = cnt;
850 base[_EDMA_QDST_OFFSET] = dst;
851 base[_EDMA_QIDX_OFFSET] = idx;
852 base[_EDMA_QSOPT_OFFSET] = opt;
854 IRQ_globalRestore(gie);
855 }
856 /*----------------------------------------------------------------------------*/
857 IDEF void EDMA_qdmaGetConfig(EDMA_Config *config) {
859 Uint32 gie;
860 volatile Uint32 *base;
861 volatile EDMA_Config* cfg = (volatile EDMA_Config*)config;
862 register Uint32 x0,x1,x2,x3,x4;
864 gie = IRQ_globalDisable();
866 base = (volatile Uint32 *)(_EDMA_QOPT_ADDR);
867 x0 = base[_EDMA_QOPT_OFFSET];
868 x1 = base[_EDMA_QSRC_OFFSET];
869 x2 = base[_EDMA_QCNT_OFFSET];
870 x3 = base[_EDMA_QDST_OFFSET];
871 x4 = base[_EDMA_QIDX_OFFSET];
873 cfg->opt = x0;
874 cfg->src = x1;
875 cfg->cnt = x2;
876 cfg->dst = x3;
877 cfg->idx = x4;
878 cfg->rld = 0x00000000;
880 IRQ_globalRestore(gie);
881 }
882 /*----------------------------------------------------------------------------*/
883 #endif /* USEDEFS */
886 #endif /* EDMA_SUPPORT */
887 #endif /* _CSL_EDMA_H_ */
888 /******************************************************************************\
889 * End of csl_edma.h
890 \******************************************************************************/