1 /**************************************************************************\
2 * Copyright (C) 2002 Texas Instruments Incorporated.
3 * All Rights Reserved
4 *--------------------------------------------------------------------------
5 * MODULE NAME... EMU
6 * FILENAME...... csl_emuhal.h
7 * DATE CREATED.. 05/12/2003
8 * LAST MODIFIED. 05/20/2003
9 * PROJECT....... Chip Support Library
10 * COMPONENT..... Hardware Abstraction Layer
11 * PREREQUISITES.
12 *
13 *--------------------------------------------------------------------------
14 * DESCRIPTION:
15 * CSL Hardware Abstraction Layer interface for the EMU module
16 *
17 *--------------------------------------------------------------------------
18 * REGISTERS:
19 *
20 * DBGSTAT - DBGSTAT {Debug Status Register}
21 * MFREG0 - MFREG0 {Miscellaneous Function Register}
22 \**************************************************************************/
24 #ifndef _CSL_EMUHAL_H_
25 #define _CSL_EMUHAL_H_
27 /**************************************************************************\
28 * Private Macros and Include files
29 \**************************************************************************/
30 #include <csl_stdinchal.h>
31 #include <csl_chiphal.h>
33 #if (EMU_SUPPORT)
36 /**************************************************************************\
37 * Module level register/field access macros
38 \**************************************************************************/
40 /* ----------------- */
41 /* FIELD MAKE MACROS */
42 /* ----------------- */
43 #define EMU_FMK(REG, FIELD, x) \
44 _PER_FMK(EMU, ##REG, ##FIELD, x)
45 #define EMU_FMKS(REG, FIELD, SYM) \
46 _PER_FMKS(EMU, ##REG, ##FIELD, ##SYM)
48 /* -------------------------------- */
49 /* RAW REGISTER/FIELD ACCESS MACROS */
50 /* -------------------------------- */
51 #define EMU_ADDR(REG) _EMU_##REG##_ADDR
52 #define EMU_RGET(REG) \
53 _PER_RGET(_EMU_##REG##_ADDR, EMU, ##REG)
54 #define EMU_RSET(REG, x) \
55 _PER_RSET(_EMU_##REG##_ADDR, EMU, ##REG, x)
56 #define EMU_FGET(REG, FLD) _EMU_##REG##_FGET(##FLD)
57 #define EMU_FSET(REG, FLD, x) _EMU_##REG##_FSET(##FLD, x)
58 #define EMU_FSETS(REG, FLD, SYM) \
59 _EMU_##REG##_FSETS(##FLD, ##SYM)
61 /* ------------------------------------------ */
62 /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */
63 /* ------------------------------------------ */
64 #define EMU_RGETA(addr, REG) _PER_RGET(addr, EMU, ##REG)
65 #define EMU_RSETA(addr, REG, x) _PER_RSET(addr, EMU, ##REG,x)
66 #define EMU_FGETA(addr, REG, FLD) \
67 _PER_FGET(addr, EMU, ##REG,##FLD)
68 #define EMU_FSETA(addr, REG, FLD, x) \
69 _PER_FSET(addr, EMU, ##REG, ##FLD, x)
70 #define EMU_FSETSA(addr, REG, FLD, SYM) \
71 _PER_FSETS(addr, EMU, ##REG, ##FLD, ##SYM)
73 /* ----------------------------------------- */
74 /* HANDLE BASED REGISTER/FIELD ACCESS MACROS */
75 /* ----------------------------------------- */
76 #define EMU_ADDRH(h, REG) \
77 ((void *)(&(((EMU_PrivateObj *)h)->baseAddr[_EMU_##REG##_OFFSET])))
78 #define EMU_RGETH(h, REG) \
79 EMU_RGETA(EMU_ADDRH(h, ##REG), ##REG)
80 #define EMU_RSETH(h, REG, x) \
81 EMU_RSETA(EMU_ADDRH(h, ##REG), ##REG, x)
82 #define EMU_FGETH(h, REG, FIELD) \
83 EMU_FGETA(EMU_ADDRH(h, ##REG), ##REG, ##FIELD)
84 #define EMU_FSETH(h, REG, FIELD,x) \
85 EMU_FSETA(EMU_ADDRH(h, ##REG), ##REG, ##FIELD, x)
86 #define EMU_FSETSH(h, REG, FIELD, SYM) \
87 EMU_FSETSA(EMU_ADDRH(h, ##REG), ##REG, ##FIELD, ##SYM)
90 /**************************************************************************\
91 *
92 * _____________________
93 * | |
94 * | D B G S T A T |
95 * |___________________|
96 *
97 * DBGSTAT - DBGSTAT {Debug Status Register}
98 *
99 * FIELDS (msb -> lsb)
100 * (r) DBGMST Read MFREG0:DBGM state
101 * (r) EALLOWST Read MFREG0:EALLOW state
102 \**************************************************************************/
104 #define _EMU_DBGSTAT_ADDR (0x01BC0000)
105 #define _EMU_DBGSTAT (*(Uint32 *)_EMU_DBGSTAT_ADDR)
107 #define _EMU_DBGSTAT_DBGMST_MASK (0x00020000u)
108 #define _EMU_DBGSTAT_DBGMST_SHIFT (0x00000011u)
110 #define EMU_DBGSTAT_DBGMST_OF(x) _VALUEOF(x)
112 #define _EMU_DBGSTAT_EALLOWST_MASK \
113 (0x00010000u)
114 #define _EMU_DBGSTAT_EALLOWST_SHIFT \
115 (0x00000010u)
116 #define EMU_DBGSTAT_EALLOWST_OF(x) \
117 _VALUEOF(x)
119 #define EMU_DBGSTAT_OF(x) _VALUEOF(x)
122 #define _EMU_DBGSTAT_FGET(FLD) \
123 _PER_FGET(_EMU_DBGSTAT_ADDR, EMU, DBGSTAT, ##FLD)
124 #define _EMU_DBGSTAT_FSET(FLD, f) \
125 _PER_FSET(_EMU_DBGSTAT_ADDR, EMU, DBGSTAT, ##FLD,f)
126 #define _EMU_DBGSTAT_FSETS(FLD, SYM) \
127 _PER_FSETS(_EMU_DBGSTAT_ADDR, EMU, DBGSTAT, ##FLD, ##SYM)
130 /**************************************************************************\
131 *
132 * _____________________
133 * | |
134 * | M F R E G 0 |
135 * |___________________|
136 *
137 * MFREG0 - MFREG0 {Miscellaneous Function Register}
138 *
139 * FIELDS (msb -> lsb)
140 * (w) DBGMLD Load qualifier for the DBGM bit
141 * (w) DBGM Set a mask to inhibit debug access
142 * (w) ABRTILD Load qualifier for the ABORTI bit
143 * (w) ABRTI set the bit to ABORT a lost ISR
144 * (w) EALLOWLD Load qualifier for the EALLOW bit
145 * (w) EALLOW Set the bit to allow Emulation access
146 \**************************************************************************/
148 #define _EMU_MFREG0_ADDR (0x01BC0014)
149 #define _EMU_MFREG0 (*(Uint32 *)_EMU_MFREG0_ADDR)
151 #define _EMU_MFREG0_DBGMLD_MASK (0x08000000u)
152 #define _EMU_MFREG0_DBGMLD_SHIFT (0x0000001Bu)
153 #define EMU_MFREG0_DBGMLD_OF(x) _VALUEOF(x)
155 #define _EMU_MFREG0_DBGM_MASK (0x04000000u)
156 #define _EMU_MFREG0_DBGM_SHIFT (0x0000001Au)
157 #define EMU_MFREG0_DBGM_OF(x) _VALUEOF(x)
159 #define _EMU_MFREG0_ABRTILD_MASK (0x00040000u)
160 #define _EMU_MFREG0_ABRTILD_SHIFT (0x00000012u)
161 #define EMU_MFREG0_ABRTILD_OF(x) _VALUEOF(x)
163 #define _EMU_MFREG0_ABRTI_MASK (0x00020000u)
164 #define _EMU_MFREG0_ABRTI_SHIFT (0x00000011u)
165 #define EMU_MFREG0_ABRTI_OF(x) _VALUEOF(x)
167 #define _EMU_MFREG0_EALLOWLD_MASK (0x00004000u)
168 #define _EMU_MFREG0_EALLOWLD_SHIFT \
169 (0x0000000Eu)
170 #define EMU_MFREG0_EALLOWLD_OF(x) _VALUEOF(x)
172 #define _EMU_MFREG0_EALLOW_MASK (0x00002000u)
173 #define _EMU_MFREG0_EALLOW_SHIFT (0x0000000Du)
174 #define EMU_MFREG0_EALLOW_OF(x) _VALUEOF(x)
176 #define EMU_MFREG0_OF(x) _VALUEOF(x)
178 #define EMU_MFREG0_RMK(dbgmld, dbgm, abrtild, abrti, eallowld, eallow) ((Uint32) (\
179 _PER_FMK(EMU, MFREG0, DBGMLD, dbgmld) \
180 |_PER_FMK(EMU, MFREG0, DBGM, dbgm) \
181 |_PER_FMK(EMU, MFREG0, ABRTILD, abrtild) \
182 |_PER_FMK(EMU, MFREG0, ABRTI, abrti) \
183 |_PER_FMK(EMU, MFREG0, EALLOWLD, eallowld) \
184 |_PER_FMK(EMU, MFREG0, EALLOW, eallow) \
185 ) \
186 )
188 #define _EMU_MFREG0_FGET(FLD) \
189 _PER_FGET(_EMU_MFREG0_ADDR, EMU, MFREG0, ##FLD)
190 #define _EMU_MFREG0_FSET(FLD, f) \
191 _PER_FSET(_EMU_MFREG0_ADDR, EMU, MFREG0, ##FLD,f)
192 #define _EMU_MFREG0_FSETS(FLD, SYM) \
193 _PER_FSETS(_EMU_MFREG0_ADDR, EMU, MFREG0, ##FLD, ##SYM)
197 #endif /* (EMU_SUPPORT) */
198 #endif /* _CSL_EMUHAL_H_ */
200 /**************************************************************************\
201 * End of csl_emuhal.h
202 \**************************************************************************/