1 /******************************************************************************\\r
2 * Copyright (C) 1999-2000 Texas Instruments Incorporated.\r
3 * All Rights Reserved\r
4 *------------------------------------------------------------------------------\r
5 * FILENAME...... csl_irqhal.h\r
6 * DATE CREATED.. 06/20/1999 \r
7 * LAST MODIFIED. 10/03/2000\r
8 *------------------------------------------------------------------------------\r
9 * REGISTERS\r
10 *\r
11 * MUXH - interrupt multiplexer high register\r
12 * MUXL - interrupt multiplexer low register\r
13 * EXTPOL - external interrupt polarity register\r
14 *\r
15 \******************************************************************************/\r
16 #ifndef _CSL_IRQHAL_H_\r
17 #define _CSL_IRQHAL_H_\r
18 \r
19 #include <csl_stdinchal.h>\r
20 #include <csl_chip.h>\r
21 \r
22 #if (IRQ_SUPPORT)\r
23 /******************************************************************************\\r
24 * MISC section\r
25 \******************************************************************************/\r
26 \r
27 \r
28 /******************************************************************************\\r
29 * module level register/field access macros\r
30 \******************************************************************************/\r
31 \r
32 /* ----------------- */\r
33 /* FIELD MAKE MACROS */\r
34 /* ----------------- */\r
35 \r
36 #define IRQ_FMK(REG,FIELD,x)\\r
37 _PER_FMK(IRQ,##REG,##FIELD,x)\r
38 \r
39 #define IRQ_FMKS(REG,FIELD,SYM)\\r
40 _PER_FMKS(IRQ,##REG,##FIELD,##SYM)\r
41 \r
42 \r
43 /* -------------------------------- */\r
44 /* RAW REGISTER/FIELD ACCESS MACROS */\r
45 /* -------------------------------- */\r
46 \r
47 #define IRQ_ADDR(REG)\\r
48 _IRQ_##REG##_ADDR\r
49 \r
50 #define IRQ_RGET(REG)\\r
51 _PER_RGET(_IRQ_##REG##_ADDR,IRQ,##REG)\r
52 \r
53 #define IRQ_RSET(REG,x)\\r
54 _PER_RSET(_IRQ_##REG##_ADDR,IRQ,##REG,x)\r
55 \r
56 #define IRQ_FGET(REG,FIELD)\\r
57 _IRQ_##REG##_FGET(##FIELD)\r
58 \r
59 #define IRQ_FSET(REG,FIELD,x)\\r
60 _IRQ_##REG##_FSET(##FIELD,##x)\r
61 \r
62 #define IRQ_FSETS(REG,FIELD,SYM)\\r
63 _IRQ_##REG##_FSETS(##FIELD,##SYM)\r
64 \r
65 \r
66 /* ------------------------------------------ */\r
67 /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */\r
68 /* ------------------------------------------ */\r
69 \r
70 #define IRQ_RGETA(addr,REG)\\r
71 _PER_RGET(addr,IRQ,##REG)\r
72 \r
73 #define IRQ_RSETA(addr,REG,x)\\r
74 _PER_RSET(addr,IRQ,##REG,x)\r
75 \r
76 #define IRQ_FGETA(addr,REG,FIELD)\\r
77 _PER_FGET(addr,IRQ,##REG,##FIELD)\r
78 \r
79 #define IRQ_FSETA(addr,REG,FIELD,x)\\r
80 _PER_FSET(addr,IRQ,##REG,##FIELD,x)\r
81 \r
82 #define IRQ_FSETSA(addr,REG,FIELD,SYM)\\r
83 _PER_FSETS(addr,IRQ,##REG,##FIELD,##SYM)\r
84 \r
85 \r
86 /******************************************************************************\\r
87 * _____________________\r
88 * | |\r
89 * | M U X H |\r
90 * |___________________|\r
91 *\r
92 * MUXH - interrupt multiplexer high register\r
93 *\r
94 * FIELDS (msb -> lsb)\r
95 * (rw) INTSEL15\r
96 * (rw) INTSEL14\r
97 * (rw) INTSEL13\r
98 * (rw) INTSEL12\r
99 * (rw) INTSEL11\r
100 * (rw) INTSEL10\r
101 *\r
102 \******************************************************************************/\r
103 #define _IRQ_MUXH_ADDR 0x019C0000u\r
104 \r
105 #define _IRQ_MUXH_INTSEL15_MASK 0x7C000000u\r
106 #define _IRQ_MUXH_INTSEL15_SHIFT 0x0000001Au\r
107 #define IRQ_MUXH_INTSEL15_DEFAULT 0x00000002u\r
108 #define IRQ_MUXH_INTSEL15_OF(x) _VALUEOF(x)\r
109 \r
110 #define _IRQ_MUXH_INTSEL14_MASK 0x03E00000u\r
111 #define _IRQ_MUXH_INTSEL14_SHIFT 0x00000015u\r
112 #define IRQ_MUXH_INTSEL14_DEFAULT 0x00000001u\r
113 #define IRQ_MUXH_INTSEL14_OF(x) _VALUEOF(x)\r
114 \r
115 #define _IRQ_MUXH_INTSEL13_MASK 0x001F0000u\r
116 #define _IRQ_MUXH_INTSEL13_SHIFT 0x00000010u\r
117 #define IRQ_MUXH_INTSEL13_DEFAULT 0x00000000u\r
118 #define IRQ_MUXH_INTSEL13_OF(x) _VALUEOF(x)\r
119 \r
120 #define _IRQ_MUXH_INTSEL12_MASK 0x00007C00u\r
121 #define _IRQ_MUXH_INTSEL12_SHIFT 0x0000000Au\r
122 #define IRQ_MUXH_INTSEL12_DEFAULT 0x0000000Bu\r
123 #define IRQ_MUXH_INTSEL12_OF(x) _VALUEOF(x)\r
124 \r
125 #define _IRQ_MUXH_INTSEL11_MASK 0x000003E0u\r
126 #define _IRQ_MUXH_INTSEL11_SHIFT 0x00000005u\r
127 #define IRQ_MUXH_INTSEL11_DEFAULT 0x0000000Au\r
128 #define IRQ_MUXH_INTSEL11_OF(x) _VALUEOF(x)\r
129 \r
130 #define _IRQ_MUXH_INTSEL10_MASK 0x0000001Fu\r
131 #define _IRQ_MUXH_INTSEL10_SHIFT 0x00000000u\r
132 #define IRQ_MUXH_INTSEL10_DEFAULT 0x00000003u\r
133 #define IRQ_MUXH_INTSEL10_OF(x) _VALUEOF(x)\r
134 \r
135 #define IRQ_MUXH_OF(x) _VALUEOF(x)\r
136 \r
137 #define IRQ_MUXH_DEFAULT (Uint32)( \\r
138 _PER_FDEFAULT(IRQ,MUXH,INTSEL15) \\r
139 |_PER_FDEFAULT(IRQ,MUXH,INTSEL14) \\r
140 |_PER_FDEFAULT(IRQ,MUXH,INTSEL13) \\r
141 |_PER_FDEFAULT(IRQ,MUXH,INTSEL12) \\r
142 |_PER_FDEFAULT(IRQ,MUXH,INTSEL11) \\r
143 |_PER_FDEFAULT(IRQ,MUXH,INTSEL10) \\r
144 )\r
145 \r
146 #define IRQ_MUXH_RMK(intsel15,intsel14,intsel13,intsel12,intsel11,intsel10) \\r
147 (Uint32)( \\r
148 _PER_FMK(IRQ,MUXH,INTSEL15,intsel15) \\r
149 |_PER_FMK(IRQ,MUXH,INTSEL14,intsel14) \\r
150 |_PER_FMK(IRQ,MUXH,INTSEL13,intsel13) \\r
151 |_PER_FMK(IRQ,MUXH,INTSEL12,intsel12) \\r
152 |_PER_FMK(IRQ,MUXH,INTSEL11,intsel11) \\r
153 |_PER_FMK(IRQ,MUXH,INTSEL10,intsel10) \\r
154 )\r
155 \r
156 #define _IRQ_MUXH_FGET(FIELD)\\r
157 _PER_FGET(_IRQ_MUXH_ADDR,IRQ,MUXH,##FIELD)\r
158 \r
159 #define _IRQ_MUXH_FSET(FIELD,field)\\r
160 _PER_FSET(_IRQ_MUXH_ADDR,IRQ,MUXH,##FIELD,field)\r
161 \r
162 #define _IRQ_MUXH_FSETS(FIELD,SYM)\\r
163 _PER_FSETS(_IRQ_MUXH_ADDR,IRQ,MUXH,##FIELD,##SYM)\r
164 \r
165 \r
166 /******************************************************************************\\r
167 * _____________________\r
168 * | |\r
169 * | M U X L |\r
170 * |___________________|\r
171 *\r
172 * MUXL - interrupt multiplexer low register\r
173 *\r
174 * FIELDS (msb -> lsb)\r
175 * (rw) INTSEL9\r
176 * (rw) INTSEL8\r
177 * (rw) INTSEL7\r
178 * (rw) INTSEL6\r
179 * (rw) INTSEL5\r
180 * (rw) INTSEL4\r
181 *\r
182 \******************************************************************************/\r
183 #define _IRQ_MUXL_ADDR 0x019C0004u\r
184 \r
185 #define _IRQ_MUXL_INTSEL9_MASK 0x7C000000u\r
186 #define _IRQ_MUXL_INTSEL9_SHIFT 0x0000001Au\r
187 #define IRQ_MUXL_INTSEL9_DEFAULT 0x00000009u\r
188 #define IRQ_MUXL_INTSEL9_OF(x) _VALUEOF(x)\r
189 \r
190 #define _IRQ_MUXL_INTSEL8_MASK 0x03E00000u\r
191 #define _IRQ_MUXL_INTSEL8_SHIFT 0x00000015u\r
192 #define IRQ_MUXL_INTSEL8_DEFAULT 0x00000008u\r
193 #define IRQ_MUXL_INTSEL8_OF(x) _VALUEOF(x)\r
194 \r
195 #define _IRQ_MUXL_INTSEL7_MASK 0x001F0000u\r
196 #define _IRQ_MUXL_INTSEL7_SHIFT 0x00000010u\r
197 #define IRQ_MUXL_INTSEL7_DEFAULT 0x00000007u\r
198 #define IRQ_MUXL_INTSEL7_OF(x) _VALUEOF(x)\r
199 \r
200 #define _IRQ_MUXL_INTSEL6_MASK 0x00007C00u\r
201 #define _IRQ_MUXL_INTSEL6_SHIFT 0x0000000Au\r
202 #define IRQ_MUXL_INTSEL6_DEFAULT 0x00000006u\r
203 #define IRQ_MUXL_INTSEL6_OF(x) _VALUEOF(x)\r
204 \r
205 #define _IRQ_MUXL_INTSEL5_MASK 0x000003E0u\r
206 #define _IRQ_MUXL_INTSEL5_SHIFT 0x00000005u\r
207 #define IRQ_MUXL_INTSEL5_DEFAULT 0x00000005u\r
208 #define IRQ_MUXL_INTSEL5_OF(x) _VALUEOF(x)\r
209 \r
210 #define _IRQ_MUXL_INTSEL4_MASK 0x0000001Fu\r
211 #define _IRQ_MUXL_INTSEL4_SHIFT 0x00000000u\r
212 #define IRQ_MUXL_INTSEL4_DEFAULT 0x00000004u\r
213 #define IRQ_MUXL_INTSEL4_OF(x) _VALUEOF(x)\r
214 \r
215 #define IRQ_MUXL_OF(x) _VALUEOF(x)\r
216 \r
217 #define IRQ_MUXL_DEFAULT (Uint32)( \\r
218 _PER_FDEFAULT(IRQ,MUXL,INTSEL9) \\r
219 |_PER_FDEFAULT(IRQ,MUXL,INTSEL8) \\r
220 |_PER_FDEFAULT(IRQ,MUXL,INTSEL7) \\r
221 |_PER_FDEFAULT(IRQ,MUXL,INTSEL6) \\r
222 |_PER_FDEFAULT(IRQ,MUXL,INTSEL5) \\r
223 |_PER_FDEFAULT(IRQ,MUXL,INTSEL4) \\r
224 )\r
225 \r
226 #define IRQ_MUXL_RMK(intsel9,intsel8,intsel7,intsel6,intsel5,intsel4) \\r
227 (Uint32)( \\r
228 _PER_FMK(IRQ,MUXL,INTSEL9,intsel9) \\r
229 |_PER_FMK(IRQ,MUXL,INTSEL8,intsel8) \\r
230 |_PER_FMK(IRQ,MUXL,INTSEL7,intsel7) \\r
231 |_PER_FMK(IRQ,MUXL,INTSEL6,intsel6) \\r
232 |_PER_FMK(IRQ,MUXL,INTSEL5,intsel5) \\r
233 |_PER_FMK(IRQ,MUXL,INTSEL4,intsel4) \\r
234 )\r
235 \r
236 #define _IRQ_MUXL_FGET(FIELD)\\r
237 _PER_FGET(_IRQ_MUXL_ADDR,IRQ,MUXL,##FIELD)\r
238 \r
239 #define _IRQ_MUXL_FSET(FIELD,field)\\r
240 _PER_FSET(_IRQ_MUXL_ADDR,IRQ,MUXL,##FIELD,field)\r
241 \r
242 #define _IRQ_MUXL_FSETS(FIELD,SYM)\\r
243 _PER_FSETS(_IRQ_MUXL_ADDR,IRQ,MUXL,##FIELD,##SYM)\r
244 \r
245 \r
246 /******************************************************************************\\r
247 * _____________________\r
248 * | |\r
249 * | E X T P O L |\r
250 * |___________________|\r
251 *\r
252 * EXTPOL - external interrupt polarity register\r
253 *\r
254 * FIELDS (msb -> lsb)\r
255 * (rw) XIP\r
256 *\r
257 \******************************************************************************/\r
258 #define _IRQ_EXTPOL_ADDR 0x019C0008u\r
259 \r
260 #define _IRQ_EXTPOL_XIP_MASK 0x0000000Fu\r
261 #define _IRQ_EXTPOL_XIP_SHIFT 0x00000000u\r
262 #define IRQ_EXTPOL_XIP_DEFAULT 0x00000000u\r
263 #define IRQ_EXTPOL_XIP_OF(x) _VALUEOF(x)\r
264 \r
265 #define IRQ_EXTPOL_OF(x) _VALUEOF(x)\r
266 \r
267 #define IRQ_EXTPOL_DEFAULT (Uint32)( \\r
268 _PER_FDEFAULT(IRQ,EXTPOL,XIP) \\r
269 )\r
270 \r
271 #define IRQ_EXTPOL_RMK(xip) (Uint32)( \\r
272 _PER_FMK(IRQ,EXTPOL,XIP,xip) \\r
273 )\r
274 \r
275 #define _IRQ_EXTPOL_FGET(FIELD)\\r
276 _PER_FGET(_IRQ_EXTPOL_ADDR,IRQ,EXTPOL,##FIELD)\r
277 \r
278 #define _IRQ_EXTPOL_FSET(FIELD,field)\\r
279 _PER_FSET(_IRQ_EXTPOL_ADDR,IRQ,EXTPOL,##FIELD,field)\r
280 \r
281 #define _IRQ_EXTPOL_FSETS(FIELD,SYM)\\r
282 _PER_FSETS(_IRQ_EXTPOL_ADDR,IRQ,EXTPOL,##FIELD,##SYM)\r
283 \r
284 \r
285 /*----------------------------------------------------------------------------*/\r
286 \r
287 #endif /* IRQ_SUPPORT */\r
288 #endif /* _CSL_IRQHAL_H_ */\r
289 /******************************************************************************\\r
290 * End of csl_irqhal.h\r
291 \******************************************************************************/\r
292 \r