6c53775e9587fab5b0013faa2c29f558031fada8
1 /*******************************************************************************\r
2 * *\r
3 * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/ *\r
4 * ALL RIGHTS RESERVED *\r
5 * *\r
6 ******************************************************************************/\r
7 \r
8 /*\r
9 * ======== platform.xs ========\r
10 */\r
11 \r
12 var Build = xdc.useModule('xdc.bld.BuildEnvironment'); \r
13 \r
14 var MemSegDefine = xdc.loadCapsule("mem_segment_definition.xs");\r
15 \r
16 Build.platformTable["ti.platforms.simVayu:IPU_1_0"] =\r
17 { \r
18 externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_0(),\r
19 codeMemory:"CODE_CORE_IPU1_0",\r
20 dataMemory:"PRIVATE_DATA_CORE_IPU1_0",\r
21 stackMemory:"PRIVATE_DATA_CORE_IPU1_0"\r
22 };\r
23 \r
24 Build.platformTable["ti.platforms.simVayu:IPU_1_1"] =\r
25 { \r
26 externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_1(),\r
27 codeMemory:"CODE_CORE_IPU1_1",\r
28 dataMemory:"PRIVATE_DATA_CORE_IPU1_1",\r
29 stackMemory:"PRIVATE_DATA_CORE_IPU1_1"\r
30 };\r
31 \r
32 Build.platformTable["ti.platforms.simVayu:DSP_1"] =\r
33 {\r
34 externalMemoryMap: MemSegDefine.getMemSegmentDefinitionDSP_1(),\r
35 codeMemory:"CODE_CORE_DSP1",\r
36 dataMemory:"PRIVATE_DATA_CORE_DSP1",\r
37 stackMemory:"PRIVATE_DATA_CORE_DSP1"\r
38 };\r
39 \r
40 Build.platformTable["ti.platforms.simVayu:Cortex_A15"] =\r
41 {\r
42 externalMemoryMap: MemSegDefine.getMemSegmentDefinitionHOST(),\r
43 codeMemory:"CODE_CORE_HOST",\r
44 dataMemory:"PRIVATE_DATA_CORE_HOST",\r
45 stackMemory:"PRIVATE_DATA_CORE_HOST"\r
46 };\r
47 \r
48 Build.platformTable["ti.platforms.simVayu:EVE_1"] =\r
49 {\r
50 externalMemoryMap: MemSegDefine.getMemSegmentDefinitionEVE(),\r
51 codeMemory:"CODE_CORE_EVE",\r
52 dataMemory:"PRIVATE_DATA_CORE_EVE",\r
53 stackMemory:"PRIVATE_DATA_CORE_EVE"\r
54 };\r