a8deded8dd46ccc48f18b82640f9461cbfe44fdb
[keystone-rtos/edma3_lld.git] / examples / edma3_driver / src / dma_poll_test.c
1 #include "sample.h"\r
2 \r
3 extern signed char   _srcBuff1[MAX_BUFFER_SIZE];\r
4 extern signed char   _dstBuff1[MAX_BUFFER_SIZE];\r
5 \r
6 extern signed char *srcBuff1;\r
7 extern signed char *dstBuff1;\r
8 \r
9 /**\r
10    * Test case demonstrating the poll mode scenario.\r
11    * A user has requested a data transfer without giving any\r
12    * callback function. After programming and enabling the channel,\r
13    * he uses different APIs (meant to be used in poll mode)\r
14    * to check the status of ongoing transfer.\r
15    * Interrupt will NOT occur in this case.\r
16    */\r
17 /**\r
18  *  \brief   EDMA3 mem-to-mem data copy test case, using a DMA channel.\r
19  *              This test case doesnot rely on the callback mechanism.\r
20  *              Instead, it Polls the IPR register to check the transfer\r
21  *              completion status.\r
22  *\r
23  *  \param  acnt        [IN]      Number of bytes in an array\r
24  *  \param  bcnt        [IN]      Number of arrays in a frame\r
25  *  \param  ccnt        [IN]      Number of frames in a block\r
26  *  \param  syncType    [IN]      Synchronization type (A/AB Sync)\r
27  *\r
28  *  \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
29  */\r
30 EDMA3_DRV_Result edma3_test_poll_mode(\r
31                                     unsigned int acnt,\r
32                                     unsigned int bcnt,\r
33                                     unsigned int ccnt,\r
34                                     EDMA3_DRV_SyncType syncType)\r
35     {\r
36     EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
37     unsigned int chId = 0;\r
38     unsigned int tcc = 0;\r
39     int i;\r
40     unsigned int count;\r
41     unsigned int Istestpassed = 0u;\r
42     unsigned int numenabled = 0;\r
43     unsigned int BRCnt = 0;\r
44     int srcbidx = 0, desbidx = 0;\r
45     int srccidx = 0, descidx = 0;\r
46 \r
47 \r
48     srcBuff1 = (signed char*)_srcBuff1;\r
49     dstBuff1 = (signed char*)_dstBuff1;\r
50 \r
51 \r
52     /* Initalize source and destination buffers */\r
53     for (count = 0u; count < (acnt*bcnt*ccnt); count++)\r
54         {\r
55         srcBuff1[count] = (int)count+5;\r
56         /**\r
57          * No need to initialize the destination buffer as it is being invalidated.\r
58         dstBuff1[count] = initval;\r
59         */\r
60         }\r
61 \r
62 \r
63 #ifdef EDMA3_ENABLE_DCACHE\r
64     /*\r
65     * Note: These functions are required if the buffer is in DDR.\r
66     * For other cases, where buffer is NOT in DDR, user\r
67     * may or may not require the below functions.\r
68     */\r
69     /* Flush the Source Buffer */\r
70     if (result == EDMA3_DRV_SOK)\r
71         {\r
72         result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt));\r
73         }\r
74 \r
75     /* Invalidate the Destination Buffer */\r
76     if (result == EDMA3_DRV_SOK)\r
77         {\r
78         result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt));\r
79         }\r
80 #endif  /* EDMA3_ENABLE_DCACHE */\r
81 \r
82 \r
83     /* Set B count reload as B count. */\r
84     BRCnt = bcnt;\r
85 \r
86     /* Setting up the SRC/DES Index */\r
87     srcbidx = (int)acnt;\r
88     desbidx = (int)acnt;\r
89 \r
90     if (syncType == EDMA3_DRV_SYNC_A)\r
91         {\r
92         /* A Sync Transfer Mode */\r
93         srccidx = (int)acnt;\r
94         descidx = (int)acnt;\r
95         }\r
96     else\r
97         {\r
98         /* AB Sync Transfer Mode */\r
99         srccidx = ((int)acnt * (int)bcnt);\r
100         descidx = ((int)acnt * (int)bcnt);\r
101         }\r
102 \r
103 \r
104     /* Setup for Channel 1*/\r
105     tcc = EDMA3_DRV_TCC_ANY;\r
106     chId = EDMA3_DRV_DMA_CHANNEL_ANY;\r
107 \r
108 \r
109     /* Request any DMA channel and any TCC */\r
110     if (result == EDMA3_DRV_SOK)\r
111         {\r
112         result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc,\r
113                                             (EDMA3_RM_EventQueue)0,\r
114                                             NULL, NULL);\r
115         }\r
116 \r
117     if (result == EDMA3_DRV_SOK)\r
118         {\r
119         result = EDMA3_DRV_setSrcParams (hEdma, chId, (unsigned int)(srcBuff1),\r
120                                         EDMA3_DRV_ADDR_MODE_INCR,\r
121                                         EDMA3_DRV_W8BIT);\r
122         }\r
123 \r
124     if (result == EDMA3_DRV_SOK)\r
125         {\r
126         result = EDMA3_DRV_setDestParams (hEdma, chId, (unsigned int)(dstBuff1),\r
127                                             EDMA3_DRV_ADDR_MODE_INCR,\r
128                                             EDMA3_DRV_W8BIT);\r
129         }\r
130 \r
131     if (result == EDMA3_DRV_SOK)\r
132         {\r
133         result = EDMA3_DRV_setSrcIndex (hEdma, chId, srcbidx, srccidx);\r
134         }\r
135 \r
136     if (result == EDMA3_DRV_SOK)\r
137         {\r
138         result =  EDMA3_DRV_setDestIndex (hEdma, chId, desbidx, descidx);\r
139         }\r
140 \r
141     if (result == EDMA3_DRV_SOK)\r
142         {\r
143         if (syncType == EDMA3_DRV_SYNC_A)\r
144             {\r
145             result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,\r
146                                                 BRCnt, EDMA3_DRV_SYNC_A);\r
147             }\r
148         else\r
149             {\r
150             result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,\r
151                                                 BRCnt, EDMA3_DRV_SYNC_AB);\r
152             }\r
153         }\r
154 \r
155     if (result == EDMA3_DRV_SOK)\r
156         {\r
157         result = EDMA3_DRV_setOptField (hEdma, chId,\r
158                                         EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);\r
159         }\r
160 \r
161     if (result == EDMA3_DRV_SOK)\r
162         {\r
163         result = EDMA3_DRV_setOptField (hEdma, chId,\r
164                                         EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);\r
165         }\r
166 \r
167     /*\r
168      * Since the transfer is going to happen in Manual mode of EDMA3\r
169      * operation, we have to 'Enable the Transfer' multiple times.\r
170      * Number of times depends upon the Mode (A/AB Sync)\r
171      * and the different counts.\r
172      */\r
173     if (result == EDMA3_DRV_SOK)\r
174         {\r
175         /*Need to activate next param*/\r
176         if (syncType == EDMA3_DRV_SYNC_A)\r
177             {\r
178             numenabled = bcnt * ccnt;\r
179             }\r
180         else\r
181             {\r
182             /* AB Sync Transfer Mode */\r
183             numenabled = ccnt;\r
184             }\r
185 \r
186 \r
187         for (i = 0; i < numenabled; i++)\r
188             {\r
189             /*\r
190              * Now enable the transfer as many times as calculated above.\r
191              */\r
192             result = EDMA3_DRV_enableTransfer (hEdma, chId,\r
193                                                 EDMA3_DRV_TRIG_MODE_MANUAL);\r
194             if (result != EDMA3_DRV_SOK)\r
195                 {\r
196 #ifdef EDMA3_DRV_DEBUG\r
197                 EDMA3_DRV_PRINTF ("edma3_test_poll_mode: EDMA3_DRV_enableTransfer " \\r
198                                     "Failed, error code: %d\r\n", result);\r
199 #endif  /* EDMA3_DRV_DEBUG */\r
200                 break;\r
201                 }\r
202 \r
203 \r
204             /* Wait for the Completion Bit to be SET in the IPR/IPRH register. */\r
205             result = EDMA3_DRV_waitAndClearTcc (hEdma, tcc);\r
206             if (result != EDMA3_DRV_SOK)\r
207                 {\r
208 #ifdef EDMA3_DRV_DEBUG\r
209                 EDMA3_DRV_PRINTF ("edma3_test_poll_mode: EDMA3_DRV_waitAndClearTcc " \\r
210                                     "Failed, error code: %d\r\n", result);\r
211 #endif  /* EDMA3_DRV_DEBUG */\r
212                 break;\r
213                 }\r
214             }\r
215         }\r
216 \r
217 \r
218     /* Match the Source and Destination Buffers. */\r
219     if (EDMA3_DRV_SOK == result)\r
220         {\r
221         for (i = 0; i < (acnt*bcnt*ccnt); i++)\r
222             {\r
223             if (srcBuff1[i] != dstBuff1[i])\r
224                 {\r
225                 Istestpassed = 0u;\r
226 #ifdef EDMA3_DRV_DEBUG\r
227                 EDMA3_DRV_PRINTF("edma3_test_poll_mode: Data write-read matching" \\r
228                                      "FAILED at i = %d\r\n", i);\r
229 #endif  /* EDMA3_DRV_DEBUG */\r
230                 break;\r
231                 }\r
232             }\r
233         if (i == (acnt*bcnt*ccnt))\r
234             {\r
235             Istestpassed = 1u;\r
236             }\r
237 \r
238 \r
239         /* Free the previously allocated channel. */\r
240         result = EDMA3_DRV_freeChannel (hEdma, chId);\r
241         if (result != EDMA3_DRV_SOK)\r
242             {\r
243 #ifdef EDMA3_DRV_DEBUG\r
244             EDMA3_DRV_PRINTF("edma3_test_poll_mode: EDMA3_DRV_freeChannel() FAILED, " \\r
245                                 "error code: %d\r\n", result);\r
246 #endif  /* EDMA3_DRV_DEBUG */\r
247             }\r
248         }\r
249 \r
250 \r
251     if(Istestpassed == 1u)\r
252         {\r
253 #ifdef EDMA3_DRV_DEBUG\r
254         EDMA3_DRV_PRINTF("edma3_test_poll_mode PASSED\r\n");\r
255 #endif  /* EDMA3_DRV_DEBUG */\r
256         }\r
257     else\r
258         {\r
259 #ifdef EDMA3_DRV_DEBUG\r
260         EDMA3_DRV_PRINTF("edma3_test_poll_mode FAILED\r\n");\r
261 #endif  /* EDMA3_DRV_DEBUG */\r
262         result = ((EDMA3_DRV_SOK == result) ?\r
263                                 EDMA3_DATA_MISMATCH_ERROR : result);\r
264         }\r
265 \r
266 \r
267     return result;\r
268 }\r