1 /*
2 * dma_poll_test.c
3 *
4 * Test case demonstrating the poll mode scenario. User has requested a data
5 * transfer without giving any callback function. After programming and
6 * enabling the channel, he uses different APIs (meant to be used in poll mode)
7 * to check the status of ongoing transfer. Interrupt will NOT occur in this
8 * case.
9 *
10 * Copyright (C) 2009-2018 Texas Instruments Incorporated - http://www.ti.com/
11 *
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 *
20 * Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the
23 * distribution.
24 *
25 * Neither the name of Texas Instruments Incorporated nor the names of
26 * its contributors may be used to endorse or promote products derived
27 * from this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 */
43 #include "sample.h"
45 extern signed char _srcBuff1[MAX_BUFFER_SIZE];
46 extern signed char _dstBuff1[MAX_BUFFER_SIZE];
48 extern signed char *srcBuff1;
49 extern signed char *dstBuff1;
51 #define EDMA3_DRV_DMA_CHANNEL_USR_REQ (10)
52 /**
53 * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel.
54 * This test case doesnot rely on the callback mechanism.
55 * Instead, it Polls the IPR register to check the transfer
56 * completion status.
57 *
58 * \param acnt [IN] Number of bytes in an array
59 * \param bcnt [IN] Number of arrays in a frame
60 * \param ccnt [IN] Number of frames in a block
61 * \param syncType [IN] Synchronization type (A/AB Sync)
62 *
63 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
64 */
65 EDMA3_DRV_Result edma3_test_poll_mode(
66 EDMA3_DRV_Handle hEdma,
67 uint32_t acnt,
68 uint32_t bcnt,
69 uint32_t ccnt,
70 EDMA3_DRV_SyncType syncType)
71 {
72 EDMA3_DRV_Result result = EDMA3_DRV_SOK;
73 uint32_t chId = 0;
74 uint32_t tcc = 0;
75 int i;
76 uint32_t count;
77 uint32_t Istestpassed = 0u;
78 uint32_t numenabled = 0;
79 uint32_t BRCnt = 0;
80 int srcbidx = 0, desbidx = 0;
81 int srccidx = 0, descidx = 0;
82 #ifdef EDMA3_RES_USER_REQ
83 uint32_t paRAMId = 0;
84 #endif
87 srcBuff1 = (signed char*) GLOBAL_ADDR(_srcBuff1);
88 dstBuff1 = (signed char*) GLOBAL_ADDR(_dstBuff1);
90 /* Initalize source and destination buffers */
91 for (count = 0u; count < (acnt*bcnt*ccnt); count++)
92 {
93 srcBuff1[count] = (int)count+5;
94 /**
95 * No need to initialize the destination buffer as it is being invalidated.
96 dstBuff1[count] = initval;
97 */
98 }
101 #ifdef EDMA3_ENABLE_DCACHE
102 /*
103 * Note: These functions are required if the buffer is in DDR.
104 * For other cases, where buffer is NOT in DDR, user
105 * may or may not require the below functions.
106 */
107 /* Flush the Source Buffer */
108 if (result == EDMA3_DRV_SOK)
109 {
110 result = Edma3_CacheFlush((uint32_t)srcBuff1, (acnt*bcnt*ccnt));
111 }
113 /* Invalidate the Destination Buffer */
114 if (result == EDMA3_DRV_SOK)
115 {
116 result = Edma3_CacheInvalidate((uint32_t)dstBuff1, (acnt*bcnt*ccnt));
117 }
118 #endif /* EDMA3_ENABLE_DCACHE */
121 /* Set B count reload as B count. */
122 BRCnt = bcnt;
124 /* Setting up the SRC/DES Index */
125 srcbidx = (int)acnt;
126 desbidx = (int)acnt;
128 if (syncType == EDMA3_DRV_SYNC_A)
129 {
130 /* A Sync Transfer Mode */
131 srccidx = (int)acnt;
132 descidx = (int)acnt;
133 }
134 else
135 {
136 /* AB Sync Transfer Mode */
137 srccidx = ((int)acnt * (int)bcnt);
138 descidx = ((int)acnt * (int)bcnt);
139 }
142 /* Setup for Channel 1*/
143 tcc = EDMA3_DRV_TCC_ANY;
144 chId = EDMA3_DRV_DMA_CHANNEL_ANY;
146 /* Request any DMA channel and any TCC */
147 if (result == EDMA3_DRV_SOK)
148 {
149 result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc,
150 (EDMA3_RM_EventQueue)0,
151 NULL, NULL);
152 }
154 if (result == EDMA3_DRV_SOK)
155 {
156 result = EDMA3_DRV_setSrcParams (hEdma, chId, (uint32_t)(srcBuff1),
157 EDMA3_DRV_ADDR_MODE_INCR,
158 EDMA3_DRV_W8BIT);
159 }
161 if (result == EDMA3_DRV_SOK)
162 {
163 result = EDMA3_DRV_setDestParams (hEdma, chId, (uint32_t)(dstBuff1),
164 EDMA3_DRV_ADDR_MODE_INCR,
165 EDMA3_DRV_W8BIT);
166 }
168 if (result == EDMA3_DRV_SOK)
169 {
170 result = EDMA3_DRV_setSrcIndex (hEdma, chId, srcbidx, srccidx);
171 }
173 if (result == EDMA3_DRV_SOK)
174 {
175 result = EDMA3_DRV_setDestIndex (hEdma, chId, desbidx, descidx);
176 }
178 if (result == EDMA3_DRV_SOK)
179 {
180 if (syncType == EDMA3_DRV_SYNC_A)
181 {
182 result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
183 BRCnt, EDMA3_DRV_SYNC_A);
184 }
185 else
186 {
187 result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
188 BRCnt, EDMA3_DRV_SYNC_AB);
189 }
190 }
192 if (result == EDMA3_DRV_SOK)
193 {
194 result = EDMA3_DRV_setOptField (hEdma, chId,
195 EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
196 }
198 if (result == EDMA3_DRV_SOK)
199 {
200 result = EDMA3_DRV_setOptField (hEdma, chId,
201 EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
202 }
204 /*
205 * Since the transfer is going to happen in Manual mode of EDMA3
206 * operation, we have to 'Enable the Transfer' multiple times.
207 * Number of times depends upon the Mode (A/AB Sync)
208 * and the different counts.
209 */
210 if (result == EDMA3_DRV_SOK)
211 {
212 /*Need to activate next param*/
213 if (syncType == EDMA3_DRV_SYNC_A)
214 {
215 numenabled = bcnt * ccnt;
216 }
217 else
218 {
219 /* AB Sync Transfer Mode */
220 numenabled = ccnt;
221 }
224 for (i = 0; i < numenabled; i++)
225 {
226 /*
227 * Now enable the transfer as many times as calculated above.
228 */
229 result = EDMA3_DRV_enableTransfer (hEdma, chId,
230 EDMA3_DRV_TRIG_MODE_MANUAL);
231 if (result != EDMA3_DRV_SOK)
232 {
233 #ifdef EDMA3_DRV_DEBUG
234 EDMA3_DRV_PRINTF ("edma3_test_poll_mode: EDMA3_DRV_enableTransfer " \
235 "Failed, error code: %d\r\n", result);
236 #endif /* EDMA3_DRV_DEBUG */
237 break;
238 }
241 /* Wait for the Completion Bit to be SET in the IPR/IPRH register. */
242 result = EDMA3_DRV_waitAndClearTcc (hEdma, tcc);
243 if (result != EDMA3_DRV_SOK)
244 {
245 #ifdef EDMA3_DRV_DEBUG
246 EDMA3_DRV_PRINTF ("edma3_test_poll_mode: EDMA3_DRV_waitAndClearTcc " \
247 "Failed, error code: %d\r\n", result);
248 #endif /* EDMA3_DRV_DEBUG */
249 break;
250 }
251 }
252 }
255 /* Match the Source and Destination Buffers. */
256 if (EDMA3_DRV_SOK == result)
257 {
258 for (i = 0; i < (acnt*bcnt*ccnt); i++)
259 {
260 if (srcBuff1[i] != dstBuff1[i])
261 {
262 Istestpassed = 0u;
263 #ifdef EDMA3_DRV_DEBUG
264 EDMA3_DRV_PRINTF("edma3_test_poll_mode: Data write-read matching" \
265 "FAILED at i = %d\r\n", i);
266 #endif /* EDMA3_DRV_DEBUG */
267 break;
268 }
269 }
270 if (i == (acnt*bcnt*ccnt))
271 {
272 Istestpassed = 1u;
273 }
276 /* Free the previously allocated channel. */
277 result = EDMA3_DRV_freeChannel (hEdma, chId);
278 if (result != EDMA3_DRV_SOK)
279 {
280 #ifdef EDMA3_DRV_DEBUG
281 EDMA3_DRV_PRINTF("edma3_test_poll_mode: EDMA3_DRV_freeChannel() FAILED, " \
282 "error code: %d\r\n", result);
283 #endif /* EDMA3_DRV_DEBUG */
284 }
285 }
288 if(Istestpassed == 1u)
289 {
290 #ifdef EDMA3_DRV_DEBUG
291 EDMA3_DRV_PRINTF("edma3_test_poll_mode PASSED\r\n");
292 #endif /* EDMA3_DRV_DEBUG */
293 }
294 else
295 {
296 #ifdef EDMA3_DRV_DEBUG
297 EDMA3_DRV_PRINTF("edma3_test_poll_mode FAILED\r\n");
298 #endif /* EDMA3_DRV_DEBUG */
299 result = ((EDMA3_DRV_SOK == result) ?
300 EDMA3_DATA_MISMATCH_ERROR : result);
301 }
302 return result;
303 }
306 /**
307 * \brief EDMA3 mem-to-mem data copy test case with user requested paRAMId
308 * using a DMA channel.
309 * This test case doesnot rely on the callback mechanism.
310 * Instead, it Polls the IPR register to check the transfer
311 * completion status.
312 *
313 * \param edma3Instance [IN] EDMA3 Instance number
314 * \param acnt [IN] Number of bytes in an array
315 * \param bcnt [IN] Number of arrays in a frame
316 * \param ccnt [IN] Number of frames in a block
317 * \param syncType [IN] Synchronization type (A/AB Sync)
318 *
319 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
320 */
321 EDMA3_DRV_Result edma3_test_user_req_paRAMId(
322 EDMA3_DRV_Handle hEdma,
323 uint32_t edmaInstance,
324 uint32_t acnt,
325 uint32_t bcnt,
326 uint32_t ccnt,
327 EDMA3_DRV_SyncType syncType)
328 {
329 EDMA3_DRV_Result result = EDMA3_DRV_SOK;
330 uint32_t chId = 0;
331 uint32_t tcc = 0;
332 int i;
333 uint32_t count;
334 uint32_t Istestpassed = 0u;
335 uint32_t numenabled = 0;
336 uint32_t BRCnt = 0;
337 int srcbidx = 0, desbidx = 0;
338 int srccidx = 0, descidx = 0;
339 uint32_t paRAMId = 0;
342 srcBuff1 = (signed char*) GLOBAL_ADDR(_srcBuff1);
343 dstBuff1 = (signed char*) GLOBAL_ADDR(_dstBuff1);
345 /* Initalize source and destination buffers */
346 for (count = 0u; count < (acnt*bcnt*ccnt); count++)
347 {
348 srcBuff1[count] = (int)count+5;
349 /**
350 * No need to initialize the destination buffer as it is being invalidated.
351 dstBuff1[count] = initval;
352 */
353 }
355 #ifdef EDMA3_ENABLE_DCACHE
356 /*
357 * Note: These functions are required if the buffer is in DDR.
358 * For other cases, where buffer is NOT in DDR, user
359 * may or may not require the below functions.
360 */
361 /* Flush the Source Buffer */
362 if (result == EDMA3_DRV_SOK)
363 {
364 result = Edma3_CacheFlush((uint32_t)srcBuff1, (acnt*bcnt*ccnt));
365 }
367 /* Invalidate the Destination Buffer */
368 if (result == EDMA3_DRV_SOK)
369 {
370 result = Edma3_CacheInvalidate((uint32_t)dstBuff1, (acnt*bcnt*ccnt));
371 }
372 #endif /* EDMA3_ENABLE_DCACHE */
375 /* Set B count reload as B count. */
376 BRCnt = bcnt;
378 /* Setting up the SRC/DES Index */
379 srcbidx = (int)acnt;
380 desbidx = (int)acnt;
382 if (syncType == EDMA3_DRV_SYNC_A)
383 {
384 /* A Sync Transfer Mode */
385 srccidx = (int)acnt;
386 descidx = (int)acnt;
387 }
388 else
389 {
390 /* AB Sync Transfer Mode */
391 srccidx = ((int)acnt * (int)bcnt);
392 descidx = ((int)acnt * (int)bcnt);
393 }
396 /* Setup for Channel 1*/
397 tcc = EDMA3_DRV_TCC_ANY;
399 chId = EDMA3_DRV_DMA_CHANNEL_USR_REQ;
401 /* Request any DMA channel and any TCC */
402 if (result == EDMA3_DRV_SOK)
403 {
404 result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc,
405 (EDMA3_RM_EventQueue)0,
406 NULL, NULL);
408 result = EDMA3_DRV_getAllocatedPARAMId(hEdma, chId, &paRAMId);
409 if(result == EDMA3_DRV_SOK)
410 {
411 printf("\nReserved Channel ID Test\n");
412 printf ("The Requested Channel ID: %d \nThe allocated PARAM Id:%d\n",chId,paRAMId);
414 if (chId == paRAMId)
415 {
416 printf("The Requested Param ID is allocated for the given Channel\n");
417 }
418 else
419 {
420 printf("The Requested Param ID is not allocated as same as the DMA channel\n");
421 result = EDMA3_DATA_MISMATCH_ERROR;
422 }
423 printf("\n");
424 }
425 }
427 if (result == EDMA3_DRV_SOK)
428 {
429 result = EDMA3_DRV_setSrcParams (hEdma, chId, (uint32_t)(srcBuff1),
430 EDMA3_DRV_ADDR_MODE_INCR,
431 EDMA3_DRV_W8BIT);
432 }
434 if (result == EDMA3_DRV_SOK)
435 {
436 result = EDMA3_DRV_setDestParams (hEdma, chId, (uint32_t)(dstBuff1),
437 EDMA3_DRV_ADDR_MODE_INCR,
438 EDMA3_DRV_W8BIT);
439 }
441 if (result == EDMA3_DRV_SOK)
442 {
443 result = EDMA3_DRV_setSrcIndex (hEdma, chId, srcbidx, srccidx);
444 }
446 if (result == EDMA3_DRV_SOK)
447 {
448 result = EDMA3_DRV_setDestIndex (hEdma, chId, desbidx, descidx);
449 }
451 if (result == EDMA3_DRV_SOK)
452 {
453 if (syncType == EDMA3_DRV_SYNC_A)
454 {
455 result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
456 BRCnt, EDMA3_DRV_SYNC_A);
457 }
458 else
459 {
460 result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
461 BRCnt, EDMA3_DRV_SYNC_AB);
462 }
463 }
465 if (result == EDMA3_DRV_SOK)
466 {
467 result = EDMA3_DRV_setOptField (hEdma, chId,
468 EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
469 }
471 if (result == EDMA3_DRV_SOK)
472 {
473 result = EDMA3_DRV_setOptField (hEdma, chId,
474 EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
475 }
477 /*
478 * Since the transfer is going to happen in Manual mode of EDMA3
479 * operation, we have to 'Enable the Transfer' multiple times.
480 * Number of times depends upon the Mode (A/AB Sync)
481 * and the different counts.
482 */
483 if (result == EDMA3_DRV_SOK)
484 {
485 /*Need to activate next param*/
486 if (syncType == EDMA3_DRV_SYNC_A)
487 {
488 numenabled = bcnt * ccnt;
489 }
490 else
491 {
492 /* AB Sync Transfer Mode */
493 numenabled = ccnt;
494 }
497 for (i = 0; i < numenabled; i++)
498 {
499 /*
500 * Now enable the transfer as many times as calculated above.
501 */
502 result = EDMA3_DRV_enableTransfer (hEdma, chId,
503 EDMA3_DRV_TRIG_MODE_MANUAL);
504 if (result != EDMA3_DRV_SOK)
505 {
506 #ifdef EDMA3_DRV_DEBUG
507 EDMA3_DRV_PRINTF ("edma3_test_user_req_paRAMId: EDMA3_DRV_enableTransfer " \
508 "Failed, error code: %d\r\n", result);
509 #endif /* EDMA3_DRV_DEBUG */
510 break;
511 }
514 /* Wait for the Completion Bit to be SET in the IPR/IPRH register. */
515 result = EDMA3_DRV_waitAndClearTcc (hEdma, tcc);
516 if (result != EDMA3_DRV_SOK)
517 {
518 #ifdef EDMA3_DRV_DEBUG
519 EDMA3_DRV_PRINTF ("edma3_test_user_req_paRAMId: EDMA3_DRV_waitAndClearTcc " \
520 "Failed, error code: %d\r\n", result);
521 #endif /* EDMA3_DRV_DEBUG */
522 break;
523 }
524 }
525 }
528 /* Match the Source and Destination Buffers. */
529 if (EDMA3_DRV_SOK == result)
530 {
531 for (i = 0; i < (acnt*bcnt*ccnt); i++)
532 {
533 if (srcBuff1[i] != dstBuff1[i])
534 {
535 Istestpassed = 0u;
536 #ifdef EDMA3_DRV_DEBUG
537 EDMA3_DRV_PRINTF("edma3_test_user_req_paRAMId: Data write-read matching" \
538 "FAILED at i = %d\r\n", i);
539 #endif /* EDMA3_DRV_DEBUG */
540 break;
541 }
542 }
543 if (i == (acnt*bcnt*ccnt))
544 {
545 Istestpassed = 1u;
546 }
549 /* Free the previously allocated channel. */
550 result = EDMA3_DRV_freeChannel (hEdma, chId);
551 if (result != EDMA3_DRV_SOK)
552 {
553 #ifdef EDMA3_DRV_DEBUG
554 EDMA3_DRV_PRINTF("edma3_test_user_req_paRAMId: EDMA3_DRV_freeChannel() FAILED, " \
555 "error code: %d\r\n", result);
556 #endif /* EDMA3_DRV_DEBUG */
557 }
558 }
561 if(Istestpassed == 1u)
562 {
563 #ifdef EDMA3_DRV_DEBUG
564 EDMA3_DRV_PRINTF("edma3_test_user_req_paRAMId PASSED\r\n");
565 #endif /* EDMA3_DRV_DEBUG */
566 }
567 else
568 {
569 #ifdef EDMA3_DRV_DEBUG
570 EDMA3_DRV_PRINTF("edma3_test_user_req_paRAMId FAILED\r\n");
571 #endif /* EDMA3_DRV_DEBUG */
572 result = ((EDMA3_DRV_SOK == result) ?
573 EDMA3_DATA_MISMATCH_ERROR : result);
574 }
575 return result;
576 }