Changing dos to unix format
[keystone-rtos/edma3_lld.git] / examples / edma3_driver / src / dma_poll_test.c
1 #include "sample.h"
3 extern signed char   _srcBuff1[MAX_BUFFER_SIZE];
4 extern signed char   _dstBuff1[MAX_BUFFER_SIZE];
6 extern signed char *srcBuff1;
7 extern signed char *dstBuff1;
9 /**
10    * Test case demonstrating the poll mode scenario.
11    * A user has requested a data transfer without giving any
12    * callback function. After programming and enabling the channel,
13    * he uses different APIs (meant to be used in poll mode)
14    * to check the status of ongoing transfer.
15    * Interrupt will NOT occur in this case.
16    */
17 /**
18  *  \brief   EDMA3 mem-to-mem data copy test case, using a DMA channel.
19  *              This test case doesnot rely on the callback mechanism.
20  *              Instead, it Polls the IPR register to check the transfer
21  *              completion status.
22  *
23  *  \param  acnt        [IN]      Number of bytes in an array
24  *  \param  bcnt        [IN]      Number of arrays in a frame
25  *  \param  ccnt        [IN]      Number of frames in a block
26  *  \param  syncType    [IN]      Synchronization type (A/AB Sync)
27  *
28  *  \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
29  */
30 EDMA3_DRV_Result edma3_test_poll_mode(
31                                     unsigned int acnt,
32                                     unsigned int bcnt,
33                                     unsigned int ccnt,
34                                     EDMA3_DRV_SyncType syncType)
35     {
36     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
37     unsigned int chId = 0;
38     unsigned int tcc = 0;
39     int i;
40     unsigned int count;
41     unsigned int Istestpassed = 0u;
42     unsigned int numenabled = 0;
43     unsigned int BRCnt = 0;
44     int srcbidx = 0, desbidx = 0;
45     int srccidx = 0, descidx = 0;
48     srcBuff1 = (signed char*)_srcBuff1;
49     dstBuff1 = (signed char*)_dstBuff1;
52     /* Initalize source and destination buffers */
53     for (count = 0u; count < (acnt*bcnt*ccnt); count++)
54         {
55         srcBuff1[count] = (int)count+5;
56         /**
57          * No need to initialize the destination buffer as it is being invalidated.
58         dstBuff1[count] = initval;
59         */
60         }
63 #ifdef EDMA3_ENABLE_DCACHE
64     /*
65     * Note: These functions are required if the buffer is in DDR.
66     * For other cases, where buffer is NOT in DDR, user
67     * may or may not require the below functions.
68     */
69     /* Flush the Source Buffer */
70     if (result == EDMA3_DRV_SOK)
71         {
72         result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt));
73         }
75     /* Invalidate the Destination Buffer */
76     if (result == EDMA3_DRV_SOK)
77         {
78         result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt));
79         }
80 #endif  /* EDMA3_ENABLE_DCACHE */
83     /* Set B count reload as B count. */
84     BRCnt = bcnt;
86     /* Setting up the SRC/DES Index */
87     srcbidx = (int)acnt;
88     desbidx = (int)acnt;
90     if (syncType == EDMA3_DRV_SYNC_A)
91         {
92         /* A Sync Transfer Mode */
93         srccidx = (int)acnt;
94         descidx = (int)acnt;
95         }
96     else
97         {
98         /* AB Sync Transfer Mode */
99         srccidx = ((int)acnt * (int)bcnt);
100         descidx = ((int)acnt * (int)bcnt);
101         }
104     /* Setup for Channel 1*/
105     tcc = EDMA3_DRV_TCC_ANY;
106     chId = EDMA3_DRV_DMA_CHANNEL_ANY;
109     /* Request any DMA channel and any TCC */
110     if (result == EDMA3_DRV_SOK)
111         {
112         result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc,
113                                             (EDMA3_RM_EventQueue)0,
114                                             NULL, NULL);
115         }
117     if (result == EDMA3_DRV_SOK)
118         {
119         result = EDMA3_DRV_setSrcParams (hEdma, chId, (unsigned int)(srcBuff1),
120                                         EDMA3_DRV_ADDR_MODE_INCR,
121                                         EDMA3_DRV_W8BIT);
122         }
124     if (result == EDMA3_DRV_SOK)
125         {
126         result = EDMA3_DRV_setDestParams (hEdma, chId, (unsigned int)(dstBuff1),
127                                             EDMA3_DRV_ADDR_MODE_INCR,
128                                             EDMA3_DRV_W8BIT);
129         }
131     if (result == EDMA3_DRV_SOK)
132         {
133         result = EDMA3_DRV_setSrcIndex (hEdma, chId, srcbidx, srccidx);
134         }
136     if (result == EDMA3_DRV_SOK)
137         {
138         result =  EDMA3_DRV_setDestIndex (hEdma, chId, desbidx, descidx);
139         }
141     if (result == EDMA3_DRV_SOK)
142         {
143         if (syncType == EDMA3_DRV_SYNC_A)
144             {
145             result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
146                                                 BRCnt, EDMA3_DRV_SYNC_A);
147             }
148         else
149             {
150             result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
151                                                 BRCnt, EDMA3_DRV_SYNC_AB);
152             }
153         }
155     if (result == EDMA3_DRV_SOK)
156         {
157         result = EDMA3_DRV_setOptField (hEdma, chId,
158                                         EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
159         }
161     if (result == EDMA3_DRV_SOK)
162         {
163         result = EDMA3_DRV_setOptField (hEdma, chId,
164                                         EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
165         }
167     /*
168      * Since the transfer is going to happen in Manual mode of EDMA3
169      * operation, we have to 'Enable the Transfer' multiple times.
170      * Number of times depends upon the Mode (A/AB Sync)
171      * and the different counts.
172      */
173     if (result == EDMA3_DRV_SOK)
174         {
175         /*Need to activate next param*/
176         if (syncType == EDMA3_DRV_SYNC_A)
177             {
178             numenabled = bcnt * ccnt;
179             }
180         else
181             {
182             /* AB Sync Transfer Mode */
183             numenabled = ccnt;
184             }
187         for (i = 0; i < numenabled; i++)
188             {
189             /*
190              * Now enable the transfer as many times as calculated above.
191              */
192             result = EDMA3_DRV_enableTransfer (hEdma, chId,
193                                                 EDMA3_DRV_TRIG_MODE_MANUAL);
194             if (result != EDMA3_DRV_SOK)
195                 {
196 #ifdef EDMA3_DRV_DEBUG
197                 EDMA3_DRV_PRINTF ("edma3_test_poll_mode: EDMA3_DRV_enableTransfer " \
198                                     "Failed, error code: %d\r\n", result);
199 #endif  /* EDMA3_DRV_DEBUG */
200                 break;
201                 }
204             /* Wait for the Completion Bit to be SET in the IPR/IPRH register. */
205             result = EDMA3_DRV_waitAndClearTcc (hEdma, tcc);
206             if (result != EDMA3_DRV_SOK)
207                 {
208 #ifdef EDMA3_DRV_DEBUG
209                 EDMA3_DRV_PRINTF ("edma3_test_poll_mode: EDMA3_DRV_waitAndClearTcc " \
210                                     "Failed, error code: %d\r\n", result);
211 #endif  /* EDMA3_DRV_DEBUG */
212                 break;
213                 }
214             }
215         }
218     /* Match the Source and Destination Buffers. */
219     if (EDMA3_DRV_SOK == result)
220         {
221         for (i = 0; i < (acnt*bcnt*ccnt); i++)
222             {
223             if (srcBuff1[i] != dstBuff1[i])
224                 {
225                 Istestpassed = 0u;
226 #ifdef EDMA3_DRV_DEBUG
227                 EDMA3_DRV_PRINTF("edma3_test_poll_mode: Data write-read matching" \
228                                      "FAILED at i = %d\r\n", i);
229 #endif  /* EDMA3_DRV_DEBUG */
230                 break;
231                 }
232             }
233         if (i == (acnt*bcnt*ccnt))
234             {
235             Istestpassed = 1u;
236             }
239         /* Free the previously allocated channel. */
240         result = EDMA3_DRV_freeChannel (hEdma, chId);
241         if (result != EDMA3_DRV_SOK)
242             {
243 #ifdef EDMA3_DRV_DEBUG
244             EDMA3_DRV_PRINTF("edma3_test_poll_mode: EDMA3_DRV_freeChannel() FAILED, " \
245                                 "error code: %d\r\n", result);
246 #endif  /* EDMA3_DRV_DEBUG */
247             }
248         }
251     if(Istestpassed == 1u)
252         {
253 #ifdef EDMA3_DRV_DEBUG
254         EDMA3_DRV_PRINTF("edma3_test_poll_mode PASSED\r\n");
255 #endif  /* EDMA3_DRV_DEBUG */
256         }
257     else
258         {
259 #ifdef EDMA3_DRV_DEBUG
260         EDMA3_DRV_PRINTF("edma3_test_poll_mode FAILED\r\n");
261 #endif  /* EDMA3_DRV_DEBUG */
262         result = ((EDMA3_DRV_SOK == result) ?
263                                 EDMA3_DATA_MISMATCH_ERROR : result);
264         }
267     return result;