1 #include "sample.h"
3 extern signed char _srcBuff1[MAX_BUFFER_SIZE];
4 extern signed char _dstBuff1[MAX_BUFFER_SIZE];
6 extern signed char *srcBuff1;
7 extern signed char *dstBuff1;
10 /**
11 * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel.
12 *
13 *
14 * \param acnt [IN] Number of bytes in an array
15 * \param bcnt [IN] Number of arrays in a frame
16 * \param ccnt [IN] Number of frames in a block
17 * \param syncType [IN] Synchronization type (A/AB Sync)
18 *
19 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
20 */
21 EDMA3_DRV_Result edma3_test(
22 unsigned int acnt,
23 unsigned int bcnt,
24 unsigned int ccnt,
25 EDMA3_DRV_SyncType syncType)
26 {
27 EDMA3_DRV_Result result = EDMA3_DRV_SOK;
28 EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0};
29 unsigned int chId = 0;
30 unsigned int tcc = 0;
31 int i;
32 unsigned int count;
33 unsigned int Istestpassed = 0u;
34 unsigned int numenabled = 0;
35 unsigned int BRCnt = 0;
36 int srcbidx = 0, desbidx = 0;
37 int srccidx = 0, descidx = 0;
40 srcBuff1 = (signed char*)_srcBuff1;
41 dstBuff1 = (signed char*)_dstBuff1;
44 /* Initalize source and destination buffers */
45 for (count = 0u; count < (acnt*bcnt*ccnt); count++)
46 {
47 srcBuff1[count] = (int)count;
48 /**
49 * No need to initialize the destination buffer as it is being invalidated.
50 dstBuff1[count] = initval;
51 */
52 }
55 #ifdef EDMA3_ENABLE_DCACHE
56 /*
57 * Note: These functions are required if the buffer is in DDR.
58 * For other cases, where buffer is NOT in DDR, user
59 * may or may not require the below functions.
60 */
61 /* Flush the Source Buffer */
62 if (result == EDMA3_DRV_SOK)
63 {
64 result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt));
65 }
67 /* Invalidate the Destination Buffer */
68 if (result == EDMA3_DRV_SOK)
69 {
70 result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt));
71 }
72 #endif /* EDMA3_ENABLE_DCACHE */
75 /* Set B count reload as B count. */
76 BRCnt = bcnt;
78 /* Setting up the SRC/DES Index */
79 srcbidx = (int)acnt;
80 desbidx = (int)acnt;
81 if (syncType == EDMA3_DRV_SYNC_A)
82 {
83 /* A Sync Transfer Mode */
84 srccidx = (int)acnt;
85 descidx = (int)acnt;
86 }
87 else
88 {
89 /* AB Sync Transfer Mode */
90 srccidx = ((int)acnt * (int)bcnt);
91 descidx = ((int)acnt * (int)bcnt);
92 }
95 /* Setup for Channel 1*/
96 tcc = EDMA3_DRV_TCC_ANY;
97 chId = EDMA3_DRV_DMA_CHANNEL_ANY;
99 /* Request any DMA channel and any TCC */
100 if (result == EDMA3_DRV_SOK)
101 {
102 result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc,
103 (EDMA3_RM_EventQueue)0,
104 &callback1, NULL);
105 }
107 if (result == EDMA3_DRV_SOK)
108 {
109 /* Fill the PaRAM Set with transfer specific information */
110 paramSet.srcAddr = (unsigned int)(srcBuff1);
111 paramSet.destAddr = (unsigned int)(dstBuff1);
113 /**
114 * Be Careful !!!
115 * Valid values for SRCBIDX/DSTBIDX are between \9632768 and 32767
116 * Valid values for SRCCIDX/DSTCIDX are between \9632768 and 32767
117 */
118 paramSet.srcBIdx = srcbidx;
119 paramSet.destBIdx = desbidx;
120 paramSet.srcCIdx = srccidx;
121 paramSet.destCIdx = descidx;
123 /**
124 * Be Careful !!!
125 * Valid values for ACNT/BCNT/CCNT are between 0 and 65535.
126 * ACNT/BCNT/CCNT must be greater than or equal to 1.
127 * Maximum number of bytes in an array (ACNT) is 65535 bytes
128 * Maximum number of arrays in a frame (BCNT) is 65535
129 * Maximum number of frames in a block (CCNT) is 65535
130 */
131 paramSet.aCnt = acnt;
132 paramSet.bCnt = bcnt;
133 paramSet.cCnt = ccnt;
135 /* For AB-synchronized transfers, BCNTRLD is not used. */
136 paramSet.bCntReload = BRCnt;
138 paramSet.linkAddr = 0xFFFFu;
140 /* Src & Dest are in INCR modes */
141 paramSet.opt &= 0xFFFFFFFCu;
142 /* Program the TCC */
143 paramSet.opt |= ((tcc << OPT_TCC_SHIFT) & OPT_TCC_MASK);
145 /* Enable Intermediate & Final transfer completion interrupt */
146 paramSet.opt |= (1 << OPT_ITCINTEN_SHIFT);
147 paramSet.opt |= (1 << OPT_TCINTEN_SHIFT);
149 if (syncType == EDMA3_DRV_SYNC_A)
150 {
151 paramSet.opt &= 0xFFFFFFFBu;
152 }
153 else
154 {
155 /* AB Sync Transfer Mode */
156 paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT);
157 }
159 /* Now, write the PaRAM Set. */
160 result = EDMA3_DRV_setPaRAM(hEdma, chId, ¶mSet);
161 }
164 /*
165 * There is another way to program the PaRAM Set using specific APIs
166 * for different PaRAM set entries. It gives user more control and easier
167 * to use interface. User can use any of the methods.
168 * Below is the alternative way to program the PaRAM Set.
169 */
171 /*
172 if (result == EDMA3_DRV_SOK)
173 {
174 result = EDMA3_DRV_setSrcParams (hEdma, chId, (unsigned int)(srcBuff1),
175 EDMA3_DRV_ADDR_MODE_INCR,
176 EDMA3_DRV_W8BIT);
177 }
179 if (result == EDMA3_DRV_SOK)
180 {
181 result = EDMA3_DRV_setDestParams (hEdma, chId, (unsigned int)(dstBuff1),
182 EDMA3_DRV_ADDR_MODE_INCR,
183 EDMA3_DRV_W8BIT);
184 }
186 if (result == EDMA3_DRV_SOK)
187 {
188 result = EDMA3_DRV_setSrcIndex (hEdma, chId, srcbidx, srccidx);
189 }
191 if (result == EDMA3_DRV_SOK)
192 {
193 result = EDMA3_DRV_setDestIndex (hEdma, chId, desbidx, descidx);
194 }
196 if (result == EDMA3_DRV_SOK)
197 {
198 if (syncType == EDMA3_DRV_SYNC_A)
199 {
200 result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
201 BRCnt, EDMA3_DRV_SYNC_A);
202 }
203 else
204 {
205 result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
206 BRCnt, EDMA3_DRV_SYNC_AB);
207 }
208 }
210 if (result == EDMA3_DRV_SOK)
211 {
212 result = EDMA3_DRV_setOptField (hEdma, chId,
213 EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
214 }
216 if (result == EDMA3_DRV_SOK)
217 {
218 result = EDMA3_DRV_setOptField (hEdma, chId,
219 EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
220 }
222 */
225 /*
226 * Since the transfer is going to happen in Manual mode of EDMA3
227 * operation, we have to 'Enable the Transfer' multiple times.
228 * Number of times depends upon the Mode (A/AB Sync)
229 * and the different counts.
230 */
231 if (result == EDMA3_DRV_SOK)
232 {
233 /*Need to activate next param*/
234 if (syncType == EDMA3_DRV_SYNC_A)
235 {
236 numenabled = bcnt * ccnt;
237 }
238 else
239 {
240 /* AB Sync Transfer Mode */
241 numenabled = ccnt;
242 }
244 for (i = 0; i < numenabled; i++)
245 {
246 irqRaised1 = 0;
248 /*
249 * Now enable the transfer as many times as calculated above.
250 */
251 result = EDMA3_DRV_enableTransfer (hEdma, chId,
252 EDMA3_DRV_TRIG_MODE_MANUAL);
253 if (result != EDMA3_DRV_SOK)
254 {
255 printf ("edma3_test: EDMA3_DRV_enableTransfer " \
256 "Failed, error code: %d\r\n", result);
257 break;
258 }
260 /* Wait for the Completion ISR. */
261 while (irqRaised1 == 0u)
262 {
263 Task_sleep (1u);
264 }
266 /* Check the status of the completed transfer */
267 if (irqRaised1 < 0)
268 {
269 /* Some error occured, break from the FOR loop. */
270 printf ("\r\nedma3_test: Event Miss Occured!!!\r\n");
272 /* Clear the error bits first */
273 result = EDMA3_DRV_clearErrorBits (hEdma, chId);
274 break;
275 }
276 }
277 }
280 /* Match the Source and Destination Buffers. */
281 if (EDMA3_DRV_SOK == result)
282 {
283 for (i = 0; i < (acnt*bcnt*ccnt); i++)
284 {
285 if (srcBuff1[i] != dstBuff1[i])
286 {
287 Istestpassed = 0u;
288 printf("edma3_test: Data write-read matching" \
289 "FAILED at i = %d\r\n", i);
290 break;
291 }
292 }
293 if (i == (acnt*bcnt*ccnt))
294 {
295 Istestpassed = 1u;
296 }
299 /* Free the previously allocated channel. */
300 result = EDMA3_DRV_freeChannel (hEdma, chId);
301 if (result != EDMA3_DRV_SOK)
302 {
303 printf("edma3_test: EDMA3_DRV_freeChannel() FAILED, " \
304 "error code: %d\r\n", result);
305 }
306 }
309 if(Istestpassed == 1u)
310 {
311 printf("edma3_test PASSED\r\n");
312 }
313 else
314 {
315 printf("edma3_test FAILED\r\n");
316 result = ((EDMA3_DRV_SOK == result) ?
317 EDMA3_DATA_MISMATCH_ERROR : result);
318 }
321 return result;
322 }