1 /*
2 * dma_test.c
3 *
4 * EDMA3 mem-to-mem data copy test case, using a DMA channel.
5 *
6 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #include "sample.h"
41 extern signed char _srcBuff1[MAX_BUFFER_SIZE];
42 extern signed char _dstBuff1[MAX_BUFFER_SIZE];
44 extern signed char *srcBuff1;
45 extern signed char *dstBuff1;
47 extern void *AppSemHandle1;
50 /**
51 * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel.
52 *
53 *
54 * \param acnt [IN] Number of bytes in an array
55 * \param bcnt [IN] Number of arrays in a frame
56 * \param ccnt [IN] Number of frames in a block
57 * \param syncType [IN] Synchronization type (A/AB Sync)
58 *
59 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
60 */
61 EDMA3_DRV_Result edma3_test(
62 EDMA3_DRV_Handle hEdma,
63 uint32_t acnt,
64 uint32_t bcnt,
65 uint32_t ccnt,
66 EDMA3_DRV_SyncType syncType)
67 {
68 EDMA3_DRV_Result result = EDMA3_DRV_SOK;
69 EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0};
70 uint32_t chId = 0;
71 uint32_t tcc = 0;
72 int i;
73 uint32_t count;
74 uint32_t Istestpassed = 0u;
75 uint32_t numenabled = 0;
76 uint32_t BRCnt = 0;
77 int srcbidx = 0, desbidx = 0;
78 int srccidx = 0, descidx = 0;
81 srcBuff1 = (signed char*) GLOBAL_ADDR(_srcBuff1);
82 dstBuff1 = (signed char*) GLOBAL_ADDR(_dstBuff1);
85 /* Initalize source and destination buffers */
86 for (count = 0u; count < (acnt*bcnt*ccnt); count++)
87 {
88 srcBuff1[count] = (int)count;
89 /**
90 * No need to initialize the destination buffer as it is being invalidated.
91 dstBuff1[count] = initval;
92 */
93 }
96 #ifdef EDMA3_ENABLE_DCACHE
97 /*
98 * Note: These functions are required if the buffer is in DDR.
99 * For other cases, where buffer is NOT in DDR, user
100 * may or may not require the below functions.
101 */
102 /* Flush the Source Buffer */
103 if (result == EDMA3_DRV_SOK)
104 {
105 result = Edma3_CacheFlush((uint32_t)srcBuff1, (acnt*bcnt*ccnt));
106 }
108 /* Invalidate the Destination Buffer */
109 if (result == EDMA3_DRV_SOK)
110 {
111 result = Edma3_CacheInvalidate((uint32_t)dstBuff1, (acnt*bcnt*ccnt));
112 }
113 #endif /* EDMA3_ENABLE_DCACHE */
116 /* Set B count reload as B count. */
117 BRCnt = bcnt;
119 /* Setting up the SRC/DES Index */
120 srcbidx = (int)acnt;
121 desbidx = (int)acnt;
122 if (syncType == EDMA3_DRV_SYNC_A)
123 {
124 /* A Sync Transfer Mode */
125 srccidx = (int)acnt;
126 descidx = (int)acnt;
127 }
128 else
129 {
130 /* AB Sync Transfer Mode */
131 srccidx = ((int)acnt * (int)bcnt);
132 descidx = ((int)acnt * (int)bcnt);
133 }
136 /* Setup for Channel 1*/
137 tcc = EDMA3_DRV_TCC_ANY;
138 chId = EDMA3_DRV_DMA_CHANNEL_ANY;
140 /* Request any DMA channel and any TCC */
141 if (result == EDMA3_DRV_SOK)
142 {
143 result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc,
144 (EDMA3_RM_EventQueue)0,
145 &callback1, NULL);
146 }
148 if (result == EDMA3_DRV_SOK)
149 {
150 /* Fill the PaRAM Set with transfer specific information */
151 paramSet.srcAddr = (uint32_t)(srcBuff1);
152 paramSet.destAddr = (uint32_t)(dstBuff1);
154 /**
155 * Be Careful !!!
156 * Valid values for SRCBIDX/DSTBIDX are between \9632768 and 32767
157 * Valid values for SRCCIDX/DSTCIDX are between \9632768 and 32767
158 */
159 paramSet.srcBIdx = srcbidx;
160 paramSet.destBIdx = desbidx;
161 paramSet.srcCIdx = srccidx;
162 paramSet.destCIdx = descidx;
164 /**
165 * Be Careful !!!
166 * Valid values for ACNT/BCNT/CCNT are between 0 and 65535.
167 * ACNT/BCNT/CCNT must be greater than or equal to 1.
168 * Maximum number of bytes in an array (ACNT) is 65535 bytes
169 * Maximum number of arrays in a frame (BCNT) is 65535
170 * Maximum number of frames in a block (CCNT) is 65535
171 */
172 paramSet.aCnt = acnt;
173 paramSet.bCnt = bcnt;
174 paramSet.cCnt = ccnt;
176 /* For AB-synchronized transfers, BCNTRLD is not used. */
177 paramSet.bCntReload = BRCnt;
179 paramSet.linkAddr = 0xFFFFu;
181 /* Src & Dest are in INCR modes */
182 paramSet.opt &= 0xFFFFFFFCu;
183 /* Program the TCC */
184 paramSet.opt |= ((tcc << OPT_TCC_SHIFT) & OPT_TCC_MASK);
186 /* Enable Intermediate & Final transfer completion interrupt */
187 paramSet.opt |= (1 << OPT_ITCINTEN_SHIFT);
188 paramSet.opt |= (1 << OPT_TCINTEN_SHIFT);
190 if (syncType == EDMA3_DRV_SYNC_A)
191 {
192 paramSet.opt &= 0xFFFFFFFBu;
193 }
194 else
195 {
196 /* AB Sync Transfer Mode */
197 paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT);
198 }
200 /* Now, write the PaRAM Set. */
201 result = EDMA3_DRV_setPaRAM(hEdma, chId, ¶mSet);
202 }
205 /*
206 * There is another way to program the PaRAM Set using specific APIs
207 * for different PaRAM set entries. It gives user more control and easier
208 * to use interface. User can use any of the methods.
209 * Below is the alternative way to program the PaRAM Set.
210 */
212 /*
213 if (result == EDMA3_DRV_SOK)
214 {
215 result = EDMA3_DRV_setSrcParams (hEdma, chId, (uint32_t)(srcBuff1),
216 EDMA3_DRV_ADDR_MODE_INCR,
217 EDMA3_DRV_W8BIT);
218 }
220 if (result == EDMA3_DRV_SOK)
221 {
222 result = EDMA3_DRV_setDestParams (hEdma, chId, (uint32_t)(dstBuff1),
223 EDMA3_DRV_ADDR_MODE_INCR,
224 EDMA3_DRV_W8BIT);
225 }
227 if (result == EDMA3_DRV_SOK)
228 {
229 result = EDMA3_DRV_setSrcIndex (hEdma, chId, srcbidx, srccidx);
230 }
232 if (result == EDMA3_DRV_SOK)
233 {
234 result = EDMA3_DRV_setDestIndex (hEdma, chId, desbidx, descidx);
235 }
237 if (result == EDMA3_DRV_SOK)
238 {
239 if (syncType == EDMA3_DRV_SYNC_A)
240 {
241 result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
242 BRCnt, EDMA3_DRV_SYNC_A);
243 }
244 else
245 {
246 result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
247 BRCnt, EDMA3_DRV_SYNC_AB);
248 }
249 }
251 if (result == EDMA3_DRV_SOK)
252 {
253 result = EDMA3_DRV_setOptField (hEdma, chId,
254 EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
255 }
257 if (result == EDMA3_DRV_SOK)
258 {
259 result = EDMA3_DRV_setOptField (hEdma, chId,
260 EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
261 }
263 */
266 /*
267 * Since the transfer is going to happen in Manual mode of EDMA3
268 * operation, we have to 'Enable the Transfer' multiple times.
269 * Number of times depends upon the Mode (A/AB Sync)
270 * and the different counts.
271 */
272 if (result == EDMA3_DRV_SOK)
273 {
274 /*Need to activate next param*/
275 if (syncType == EDMA3_DRV_SYNC_A)
276 {
277 numenabled = bcnt * ccnt;
278 }
279 else
280 {
281 /* AB Sync Transfer Mode */
282 numenabled = ccnt;
283 }
285 for (i = 0; i < numenabled; i++)
286 {
287 irqRaised1 = 0;
289 /*
290 * Now enable the transfer as many times as calculated above.
291 */
292 result = EDMA3_DRV_enableTransfer (hEdma, chId,
293 EDMA3_DRV_TRIG_MODE_MANUAL);
294 if (result != EDMA3_DRV_SOK)
295 {
296 printf ("edma3_test: EDMA3_DRV_enableTransfer " \
297 "Failed, error code: %d\r\n", (int)result);
298 break;
299 }
300 edma3OsSemTake(AppSemHandle1, EDMA3_OSSEM_NO_TIMEOUT);
301 /* Wait for the Completion ISR. */
302 while (irqRaised1 == 0u)
303 {
304 /* Wait for the Completion ISR. */
305 printf ("waiting for interrupt...\n");
306 }
308 /* Check the status of the completed transfer */
309 if (irqRaised1 < 0)
310 {
311 /* Some error occured, break from the FOR loop. */
312 printf ("\r\nedma3_test: Event Miss Occured!!!\r\n");
314 /* Clear the error bits first */
315 result = EDMA3_DRV_clearErrorBits (hEdma, chId);
316 break;
317 }
318 }
319 }
322 /* Match the Source and Destination Buffers. */
323 if (EDMA3_DRV_SOK == result)
324 {
325 for (i = 0; i < (acnt*bcnt*ccnt); i++)
326 {
327 if (srcBuff1[i] != dstBuff1[i])
328 {
329 Istestpassed = 0u;
330 printf("edma3_test: Data write-read matching" \
331 "FAILED at i = %d\r\n", i);
332 break;
333 }
334 }
335 if (i == (acnt*bcnt*ccnt))
336 {
337 Istestpassed = 1u;
338 }
341 /* Free the previously allocated channel. */
342 result = EDMA3_DRV_freeChannel (hEdma, chId);
343 if (result != EDMA3_DRV_SOK)
344 {
345 printf("edma3_test: EDMA3_DRV_freeChannel() FAILED, " \
346 "error code: %d\r\n", (int)result);
347 }
348 }
351 if(Istestpassed == 1u)
352 {
353 printf("edma3_test PASSED\r\n");
354 }
355 else
356 {
357 printf("edma3_test FAILED\r\n");
358 result = ((EDMA3_DRV_SOK == result) ?
359 EDMA3_DATA_MISMATCH_ERROR : result);
360 }
361 return result;
362 }