63e708af81c4c74c785073068c15f4ddf1fce2ac
1 /*
2 * bios6_edma3_drv_sample.h
3 *
4 * Header file for the Demo application for the EDMA3 Driver.
5 *
6 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #ifndef _SAMPLE_H_
40 #define _SAMPLE_H_
42 #include <stdio.h>
43 #include <xdc/std.h>
44 #include <ti/sysbios/knl/Task.h>
46 /* Include EDMA3 Driver */
47 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
49 #ifdef __cplusplus
50 extern "C" {
51 #endif
53 /* MAX ACOUNT */
54 #define MAX_ACOUNT (64u)
55 /* MAX BCOUNT */
56 #define MAX_BCOUNT (1u)
57 /* MAX CCOUNT */
58 #define MAX_CCOUNT (1u)
59 /**
60 * Buffers (src and dest) are needed for mem-2-mem data transfers.
61 * This define is for the MAXIMUM size and hence the maximum data
62 * which could be transferred using the sample test cases below.
63 */
64 #define MAX_BUFFER_SIZE (MAX_ACOUNT * MAX_BCOUNT * MAX_CCOUNT)
66 #ifndef BUILD_TDA2XX_MPU
67 /* To enable/disable the cache .*/
68 #define EDMA3_ENABLE_DCACHE (1u)
69 #endif
71 /* OPT Field specific defines */
72 #define OPT_SYNCDIM_SHIFT (0x00000002u)
73 #define OPT_TCC_MASK (0x0003F000u)
74 #define OPT_TCC_SHIFT (0x0000000Cu)
75 #define OPT_ITCINTEN_SHIFT (0x00000015u)
76 #define OPT_TCINTEN_SHIFT (0x00000014u)
78 /**
79 * EDMA3 Driver Handle, which is used to call all the Driver APIs.
80 * It gets initialized during EDMA3 Initialization.
81 */
82 extern EDMA3_DRV_Handle hEdma[];
84 extern void callback1 (uint32_t tcc, EDMA3_RM_TccStatus status,
85 void *appData);
87 extern void callback2 (uint32_t tcc, EDMA3_RM_TccStatus status,
88 void *appData);
90 extern signed char* getGlobalAddr(signed char* addr);
91 /* Flag variable to check transfer completion on channel 1 */
92 extern volatile short irqRaised1;
93 /* Flag variable to check transfer completion on channel 2 */
94 extern volatile short irqRaised2;
96 #define MAX_NUM_EDMA_INSTANCES 5
98 /* Define to verify the default RM config.
99 * Additional configuration required. Update the
100 * gblCfgReqdArray[] to reflect the master/slave config.
101 * In the case of multiple instances default configuration
102 * may require more than one cores other than core 0 to be master.
103 * #define EDMA3_DRV_USE_DEF_RM_CFG
104 */
106 #define GLOBAL_ADDR(addr) (getGlobalAddr(addr))
108 /**
109 * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel.
110 *
111 *
112 * \param acnt [IN] Number of bytes in an array
113 * \param bcnt [IN] Number of arrays in a frame
114 * \param ccnt [IN] Number of frames in a block
115 * \param syncType [IN] Synchronization type (A/AB Sync)
116 *
117 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
118 */
119 EDMA3_DRV_Result edma3_test(
120 EDMA3_DRV_Handle hEdma,
121 uint32_t acnt,
122 uint32_t bcnt,
123 uint32_t ccnt,
124 EDMA3_DRV_SyncType syncType);
128 /**
129 * \brief EDMA3 mem-to-mem data copy test case, using two DMA
130 * channels, linked to each other.
131 *
132 * \param acnt [IN] Number of bytes in an array
133 * \param bcnt [IN] Number of arrays in a frame
134 * \param ccnt [IN] Number of frames in a block
135 * \param syncType [IN] Synchronization type (A/AB Sync)
136 *
137 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
138 */
139 EDMA3_DRV_Result edma3_test_with_link(
140 EDMA3_DRV_Handle hEdma,
141 uint32_t acnt,
142 uint32_t bcnt,
143 uint32_t ccnt,
144 EDMA3_DRV_SyncType syncType);
148 /**
149 * \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel.
150 *
151 *
152 * \param acnt [IN] Number of bytes in an array
153 * \param bcnt [IN] Number of arrays in a frame
154 * \param ccnt [IN] Number of frames in a block
155 * \param syncType [IN] Synchronization type (A/AB Sync)
156 *
157 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
158 */
159 EDMA3_DRV_Result qdma_test(
160 EDMA3_DRV_Handle hEdma,
161 uint32_t acnt,
162 uint32_t bcnt,
163 uint32_t ccnt,
164 EDMA3_DRV_SyncType syncType);
168 /**
169 * \brief EDMA3 misc test cases.
170 * This test case will read/write to some CC registers.
171 *
172 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
173 */
174 EDMA3_DRV_Result edma3_misc_test(EDMA3_DRV_Handle hEdma);
177 /**
178 * \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel,
179 * linked to another LINK channel.
180 *
181 * \param acnt [IN] Number of bytes in an array
182 * \param bcnt [IN] Number of arrays in a frame
183 * \param ccnt [IN] Number of frames in a block
184 * \param syncType [IN] Synchronization type (A/AB Sync)
185 *
186 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
187 */
188 EDMA3_DRV_Result qdma_test_with_link(
189 EDMA3_DRV_Handle hEdma,
190 uint32_t acnt,
191 uint32_t bcnt,
192 uint32_t ccnt,
193 EDMA3_DRV_SyncType syncType);
196 /**
197 * \brief EDMA3 mem-to-mem data copy test case, using two DMA channels,
198 * chained to each other.
199 *
200 * \param acnt [IN] Number of bytes in an array
201 * \param bcnt [IN] Number of arrays in a frame
202 * \param ccnt [IN] Number of frames in a block
203 * \param syncType [IN] Synchronization type (A/AB Sync)
204 *
205 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
206 */
207 EDMA3_DRV_Result edma3_test_with_chaining(
208 EDMA3_DRV_Handle hEdma,
209 uint32_t acnt,
210 uint32_t bcnt,
211 uint32_t ccnt,
212 EDMA3_DRV_SyncType syncType);
215 /**
216 * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel.
217 * This test case doesnot rely on the callback mechanism.
218 * Instead, it Polls the IPR register to check the transfer
219 * completion status.
220 *
221 * \param acnt [IN] Number of bytes in an array
222 * \param bcnt [IN] Number of arrays in a frame
223 * \param ccnt [IN] Number of frames in a block
224 * \param syncType [IN] Synchronization type (A/AB Sync)
225 *
226 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
227 */
228 EDMA3_DRV_Result edma3_test_poll_mode(
229 EDMA3_DRV_Handle hEdma,
230 uint32_t acnt,
231 uint32_t bcnt,
232 uint32_t ccnt,
233 EDMA3_DRV_SyncType syncType);
236 /**
237 * \brief EDMA3 ping-pong based data copy test case, using a DMA and
238 * a link channel.
239 *
240 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
241 */
242 EDMA3_DRV_Result edma3_test_ping_pong_mode(EDMA3_DRV_Handle hEdma);
244 #ifdef __cplusplus
245 }
246 #endif /* extern "C" */
248 #endif /* _SAMPLE_H_ */