[keystone-rtos/edma3_lld.git] / examples / edma3_user_space_driver / evmC66AK2E / evmC66AK2ESample.c
1 /*
2 * sample_c66ak2e_cfg.c
3 *
4 * Platform specific EDMA3 hardware related information like number of transfer
5 * controllers, various interrupt ids etc. It is used while interrupts
6 * enabling / disabling. It needs to be ported for different SoCs.
7 *
8 * Copyright (C) 2012-2013 Texas Instruments Incorporated - http://www.ti.com/
9 *
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 #include <ti/sdo/edma3/rm/edma3_rm.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES 5u
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
47 /* Number of DSPs present in the system */
48 #define NUM_DSPS 1u
49 //const unsigned int numDsps = NUM_DSPS;
51 #define CGEM_REG_START (0x01800000)
54 //extern cregister volatile unsigned int DNUM;
55 #define DNUM 0
57 #define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
60 /* Determine the processor id by reading DNUM register. */
61 unsigned short determineProcId()
62 {
63 volatile unsigned int *addr;
64 unsigned int core_no;
66 /* Identify the core number */
67 addr = (unsigned int *)(CGEM_REG_START+0x40000);
68 core_no = ((*addr) & 0x000F0000)>>16;
70 return core_no;
71 }
73 signed char* getGlobalAddr(signed char* addr)
74 {
75 if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
76 {
77 return (addr); /* The address is already a global address */
78 }
80 return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
81 }
82 /** Whether global configuration required for EDMA3 or not.
83 * This configuration should be done only once for the EDMA3 hardware by
84 * any one of the masters (i.e. DSPs).
85 * It can be changed depending on the use-case.
86 */
87 unsigned int gblCfgReqdArray [NUM_DSPS] = {
88 0, /* DSP#0 is Master, will do the global init */
89 };
91 unsigned short isGblConfigRequired(unsigned int dspNum)
92 {
93 return gblCfgReqdArray[dspNum];
94 }
96 /* Semaphore handles */
97 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL,NULL,NULL};
100 /* Variable which will be used internally for referring number of Event Queues. */
101 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u, 2u, 2u};
103 /* Variable which will be used internally for referring number of TCs. */
104 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u, 2u, 2u};
106 /**
107 * Variable which will be used internally for referring transfer completion
108 * interrupt. Completion interrupts for all the shadow regions and all the
109 * EDMA3 controllers are captured since it is a multi-DSP platform.
110 */
111 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
112 {
113 38u, 39u, 40u, 41u,
114 42u, 43u, 44u, 45u,
115 },
116 {
117 8u, 9u, 10u, 11u,
118 12u, 13u, 14u, 15u,
119 },
120 {
121 24u, 25u, 26u, 27u,
122 28u, 29u, 30u, 31u,
123 },
124 {
125 225u, 226u, 227u, 228u,
126 229u, 230u, 231u, 232u,
127 },
128 {
129 212u, 213u, 214u, 215u,
130 216u, 217u, 218u, 219u,
131 },
132 };
134 /**
135 * Variable which will be used internally for referring channel controller's
136 * error interrupt.
137 */
138 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u, 220u, 207u};
140 /**
141 * Variable which will be used internally for referring transfer controllers'
142 * error interrupts.
143 */
144 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = {
145 {
146 34u, 35u, 0u, 0u,
147 0u, 0u, 0u, 0u,
148 },
149 {
150 2u, 3u, 4u, 5u,
151 0u, 0u, 0u, 0u,
152 },
153 {
154 18u, 19u, 20u, 21u,
155 0u, 0u, 0u, 0u,
156 },
157 {
158 222u, 223u, 0u, 0u,
159 0u, 0u, 0u, 0u,
160 },
161 {
162 209u, 210u, 0u, 0u,
163 0u, 0u, 0u, 0u,
164 },
165 };
167 /* Driver Object Initialization Configuration */
168 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
169 {
170 {
171 /* EDMA3 INSTANCE# 0 */
172 /** Total number of DMA Channels supported by the EDMA3 Controller */
173 64u,
174 /** Total number of QDMA Channels supported by the EDMA3 Controller */
175 8u,
176 /** Total number of TCCs supported by the EDMA3 Controller */
177 64u,
178 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
179 512u,
180 /** Total number of Event Queues in the EDMA3 Controller */
181 2u,
182 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
183 2u,
184 /** Number of Regions on this EDMA3 controller */
185 8u,
187 /**
188 * \brief Channel mapping existence
189 * A value of 0 (No channel mapping) implies that there is fixed association
190 * for a channel number to a parameter entry number or, in other words,
191 * PaRAM entry n corresponds to channel n.
192 */
193 1u,
195 /** Existence of memory protection feature */
196 1u,
198 /** Global Register Region of CC Registers */
199 (void *)0x02700000u,
200 /** Transfer Controller (TC) Registers */
201 {
202 (void *)0x02760000u,
203 (void *)0x02768000u,
204 (void *)NULL,
205 (void *)NULL,
206 (void *)NULL,
207 (void *)NULL,
208 (void *)NULL,
209 (void *)NULL
210 },
211 /** Interrupt no. for Transfer Completion */
212 38u,
213 /** Interrupt no. for CC Error */
214 32u,
215 /** Interrupt no. for TCs Error */
216 {
217 34u,
218 35u,
219 0u,
220 0u,
221 0u,
222 0u,
223 0u,
224 0u,
225 },
227 /**
228 * \brief EDMA3 TC priority setting
229 *
230 * User can program the priority of the Event Queues
231 * at a system-wide level. This means that the user can set the
232 * priority of an IO initiated by either of the TCs (Transfer Controllers)
233 * relative to IO initiated by the other bus masters on the
234 * device (ARM, DSP, USB, etc)
235 */
236 {
237 0u,
238 1u,
239 0u,
240 0u,
241 0u,
242 0u,
243 0u,
244 0u
245 },
246 /**
247 * \brief To Configure the Threshold level of number of events
248 * that can be queued up in the Event queues. EDMA3CC error register
249 * (CCERR) will indicate whether or not at any instant of time the
250 * number of events queued up in any of the event queues exceeds
251 * or equals the threshold/watermark value that is set
252 * in the queue watermark threshold register (QWMTHRA).
253 */
254 {
255 16u,
256 16u,
257 0u,
258 0u,
259 0u,
260 0u,
261 0u,
262 0u
263 },
265 /**
266 * \brief To Configure the Default Burst Size (DBS) of TCs.
267 * An optimally-sized command is defined by the transfer controller
268 * default burst size (DBS). Different TCs can have different
269 * DBS values. It is defined in Bytes.
270 */
271 {
272 128u,
273 128u,
274 0u,
275 0u,
276 0u,
277 0u,
278 0u,
279 0u
280 },
282 /**
283 * \brief Mapping from each DMA channel to a Parameter RAM set,
284 * if it exists, otherwise of no use.
285 */
286 {
287 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
288 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
289 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
290 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
291 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
292 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
293 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
294 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
295 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
296 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
297 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
298 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
299 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
300 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
301 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
302 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
303 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
304 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
305 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
306 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
307 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
308 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
309 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
310 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
311 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
312 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
313 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
314 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
315 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
316 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
317 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
318 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
319 },
321 /**
322 * \brief Mapping from each DMA channel to a TCC. This specific
323 * TCC code will be returned when the transfer is completed
324 * on the mapped channel.
325 */
326 {
327 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
328 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
329 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
330 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
331 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
332 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
333 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
334 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
335 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
336 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
337 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
338 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
339 },
341 /**
342 * \brief Mapping of DMA channels to Hardware Events from
343 * various peripherals, which use EDMA for data transfer.
344 * All channels need not be mapped, some can be free also.
345 */
346 {
347 0xFFFFFFFFu,
348 0x00000000u
349 }
350 },
352 {
353 /* EDMA3 INSTANCE# 1 */
354 /** Total number of DMA Channels supported by the EDMA3 Controller */
355 64u,
356 /** Total number of QDMA Channels supported by the EDMA3 Controller */
357 8u,
358 /** Total number of TCCs supported by the EDMA3 Controller */
359 64u,
360 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
361 512u,
362 /** Total number of Event Queues in the EDMA3 Controller */
363 4u,
364 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
365 4u,
366 /** Number of Regions on this EDMA3 controller */
367 8u,
369 /**
370 * \brief Channel mapping existence
371 * A value of 0 (No channel mapping) implies that there is fixed association
372 * for a channel number to a parameter entry number or, in other words,
373 * PaRAM entry n corresponds to channel n.
374 */
375 1u,
377 /** Existence of memory protection feature */
378 1u,
380 /** Global Register Region of CC Registers */
381 (void *)0x02720000u,
382 /** Transfer Controller (TC) Registers */
383 {
384 (void *)0x02770000u,
385 (void *)0x02778000u,
386 (void *)0x02780000u,
387 (void *)0x02788000u,
388 (void *)NULL,
389 (void *)NULL,
390 (void *)NULL,
391 (void *)NULL
392 },
393 /** Interrupt no. for Transfer Completion */
394 8u,
395 /** Interrupt no. for CC Error */
396 0u,
397 /** Interrupt no. for TCs Error */
398 {
399 2u,
400 3u,
401 4u,
402 5u,
403 0u,
404 0u,
405 0u,
406 0u,
407 },
409 /**
410 * \brief EDMA3 TC priority setting
411 *
412 * User can program the priority of the Event Queues
413 * at a system-wide level. This means that the user can set the
414 * priority of an IO initiated by either of the TCs (Transfer Controllers)
415 * relative to IO initiated by the other bus masters on the
416 * device (ARM, DSP, USB, etc)
417 */
418 {
419 0u,
420 1u,
421 2u,
422 3u,
423 0u,
424 0u,
425 0u,
426 0u
427 },
428 /**
429 * \brief To Configure the Threshold level of number of events
430 * that can be queued up in the Event queues. EDMA3CC error register
431 * (CCERR) will indicate whether or not at any instant of time the
432 * number of events queued up in any of the event queues exceeds
433 * or equals the threshold/watermark value that is set
434 * in the queue watermark threshold register (QWMTHRA).
435 */
436 {
437 16u,
438 16u,
439 16u,
440 16u,
441 0u,
442 0u,
443 0u,
444 0u
445 },
447 /**
448 * \brief To Configure the Default Burst Size (DBS) of TCs.
449 * An optimally-sized command is defined by the transfer controller
450 * default burst size (DBS). Different TCs can have different
451 * DBS values. It is defined in Bytes.
452 */
453 {
454 128u,
455 128u,
456 128u,
457 128u,
458 0u,
459 0u,
460 0u,
461 0u
462 },
464 /**
465 * \brief Mapping from each DMA channel to a Parameter RAM set,
466 * if it exists, otherwise of no use.
467 */
468 {
469 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
470 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
471 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
472 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
473 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
474 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
475 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
476 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
477 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
478 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
479 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
480 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
481 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
482 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
483 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
484 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
485 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
486 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
487 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
488 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
489 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
490 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
491 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
492 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
493 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
494 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
495 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
496 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
497 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
498 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
499 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
500 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
501 },
503 /**
504 * \brief Mapping from each DMA channel to a TCC. This specific
505 * TCC code will be returned when the transfer is completed
506 * on the mapped channel.
507 */
508 {
509 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
510 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
511 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
512 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
513 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
514 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
515 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
516 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
517 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
518 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
519 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
520 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
521 },
523 /**
524 * \brief Mapping of DMA channels to Hardware Events from
525 * various peripherals, which use EDMA for data transfer.
526 * All channels need not be mapped, some can be free also.
527 */
528 {
529 0xFFFFFFFFu,
530 0x00000000u
531 }
532 },
534 {
535 /* EDMA3 INSTANCE# 2 */
536 /** Total number of DMA Channels supported by the EDMA3 Controller */
537 64u,
538 /** Total number of QDMA Channels supported by the EDMA3 Controller */
539 8u,
540 /** Total number of TCCs supported by the EDMA3 Controller */
541 64u,
542 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
543 512u,
544 /** Total number of Event Queues in the EDMA3 Controller */
545 4u,
546 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
547 4u,
548 /** Number of Regions on this EDMA3 controller */
549 8u,
551 /**
552 * \brief Channel mapping existence
553 * A value of 0 (No channel mapping) implies that there is fixed association
554 * for a channel number to a parameter entry number or, in other words,
555 * PaRAM entry n corresponds to channel n.
556 */
557 1u,
559 /** Existence of memory protection feature */
560 1u,
562 /** Global Register Region of CC Registers */
563 (void *)0x02740000u,
564 /** Transfer Controller (TC) Registers */
565 {
566 (void *)0x02790000u,
567 (void *)0x02798000u,
568 (void *)0x027A0000u,
569 (void *)0x027A8000u,
570 (void *)NULL,
571 (void *)NULL,
572 (void *)NULL,
573 (void *)NULL
574 },
575 /** Interrupt no. for Transfer Completion */
576 24u,
577 /** Interrupt no. for CC Error */
578 16u,
579 /** Interrupt no. for TCs Error */
580 {
581 18u,
582 19u,
583 20u,
584 21u,
585 0u,
586 0u,
587 0u,
588 0u,
589 },
591 /**
592 * \brief EDMA3 TC priority setting
593 *
594 * User can program the priority of the Event Queues
595 * at a system-wide level. This means that the user can set the
596 * priority of an IO initiated by either of the TCs (Transfer Controllers)
597 * relative to IO initiated by the other bus masters on the
598 * device (ARM, DSP, USB, etc)
599 */
600 {
601 0u,
602 1u,
603 2u,
604 3u,
605 0u,
606 0u,
607 0u,
608 0u
609 },
610 /**
611 * \brief To Configure the Threshold level of number of events
612 * that can be queued up in the Event queues. EDMA3CC error register
613 * (CCERR) will indicate whether or not at any instant of time the
614 * number of events queued up in any of the event queues exceeds
615 * or equals the threshold/watermark value that is set
616 * in the queue watermark threshold register (QWMTHRA).
617 */
618 {
619 16u,
620 16u,
621 16u,
622 16u,
623 0u,
624 0u,
625 0u,
626 0u
627 },
629 /**
630 * \brief To Configure the Default Burst Size (DBS) of TCs.
631 * An optimally-sized command is defined by the transfer controller
632 * default burst size (DBS). Different TCs can have different
633 * DBS values. It is defined in Bytes.
634 */
635 {
636 128u,
637 128u,
638 128u,
639 128u,
640 0u,
641 0u,
642 0u,
643 0u
644 },
646 /**
647 * \brief Mapping from each DMA channel to a Parameter RAM set,
648 * if it exists, otherwise of no use.
649 */
650 {
651 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
652 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
653 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
654 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
655 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
656 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
657 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
658 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
659 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
660 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
661 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
662 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
663 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
664 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
665 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
666 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
667 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
668 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
669 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
670 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
671 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
672 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
673 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
674 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
675 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
676 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
677 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
678 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
679 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
680 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
681 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
682 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
683 },
685 /**
686 * \brief Mapping from each DMA channel to a TCC. This specific
687 * TCC code will be returned when the transfer is completed
688 * on the mapped channel.
689 */
690 {
691 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
692 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
693 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
694 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
695 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
696 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
697 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
698 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
699 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
700 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
701 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
702 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
703 },
705 /**
706 * \brief Mapping of DMA channels to Hardware Events from
707 * various peripherals, which use EDMA for data transfer.
708 * All channels need not be mapped, some can be free also.
709 */
710 {
711 0xFFFFFFFFu,
712 0x00000000u
713 }
714 },
716 {
717 /* EDMA3 INSTANCE# 3 */
718 /** Total number of DMA Channels supported by the EDMA3 Controller */
719 64u,
720 /** Total number of QDMA Channels supported by the EDMA3 Controller */
721 8u,
722 /** Total number of TCCs supported by the EDMA3 Controller */
723 64u,
724 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
725 512u,
726 /** Total number of Event Queues in the EDMA3 Controller */
727 2u,
728 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
729 2u,
730 /** Number of Regions on this EDMA3 controller */
731 8u,
733 /**
734 * \brief Channel mapping existence
735 * A value of 0 (No channel mapping) implies that there is fixed association
736 * for a channel number to a parameter entry number or, in other words,
737 * PaRAM entry n corresponds to channel n.
738 */
739 1u,
741 /** Existence of memory protection feature */
742 1u,
744 /** Global Register Region of CC Registers */
745 (void *)0x02728000u,
746 /** Transfer Controller (TC) Registers */
747 {
748 (void *)0x027B0000u,
749 (void *)0x027B8000u,
750 (void *)NULL,
751 (void *)NULL,
752 (void *)NULL,
753 (void *)NULL,
754 (void *)NULL,
755 (void *)NULL
756 },
757 /** Interrupt no. for Transfer Completion */
758 225u,
759 /** Interrupt no. for CC Error */
760 220u,
761 /** Interrupt no. for TCs Error */
762 {
763 222u,
764 223u,
765 0u,
766 0u,
767 0u,
768 0u,
769 0u,
770 0u,
771 },
773 /**
774 * \brief EDMA3 TC priority setting
775 *
776 * User can program the priority of the Event Queues
777 * at a system-wide level. This means that the user can set the
778 * priority of an IO initiated by either of the TCs (Transfer Controllers)
779 * relative to IO initiated by the other bus masters on the
780 * device (ARM, DSP, USB, etc)
781 */
782 {
783 0u,
784 1u,
785 0u,
786 0u,
787 0u,
788 0u,
789 0u,
790 0u
791 },
792 /**
793 * \brief To Configure the Threshold level of number of events
794 * that can be queued up in the Event queues. EDMA3CC error register
795 * (CCERR) will indicate whether or not at any instant of time the
796 * number of events queued up in any of the event queues exceeds
797 * or equals the threshold/watermark value that is set
798 * in the queue watermark threshold register (QWMTHRA).
799 */
800 {
801 16u,
802 16u,
803 0u,
804 0u,
805 0u,
806 0u,
807 0u,
808 0u
809 },
811 /**
812 * \brief To Configure the Default Burst Size (DBS) of TCs.
813 * An optimally-sized command is defined by the transfer controller
814 * default burst size (DBS). Different TCs can have different
815 * DBS values. It is defined in Bytes.
816 */
817 {
818 128u,
819 128u,
820 0u,
821 0u,
822 0u,
823 0u,
824 0u,
825 0u
826 },
828 /**
829 * \brief Mapping from each DMA channel to a Parameter RAM set,
830 * if it exists, otherwise of no use.
831 */
832 {
833 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
834 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
835 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
836 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
837 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
838 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
839 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
840 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
841 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
842 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
843 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
844 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
845 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
846 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
847 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
848 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
849 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
850 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
851 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
852 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
853 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
854 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
855 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
856 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
857 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
858 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
859 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
860 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
861 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
862 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
863 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
864 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
865 },
867 /**
868 * \brief Mapping from each DMA channel to a TCC. This specific
869 * TCC code will be returned when the transfer is completed
870 * on the mapped channel.
871 */
872 {
873 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
874 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
875 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
876 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
877 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
878 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
879 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
880 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
881 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
882 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
883 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
884 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
885 },
887 /**
888 * \brief Mapping of DMA channels to Hardware Events from
889 * various peripherals, which use EDMA for data transfer.
890 * All channels need not be mapped, some can be free also.
891 */
892 {
893 0xFFFFFFFFu,
894 0x00000000u
895 }
896 },
898 {
899 /* EDMA3 INSTANCE# 4 */
900 /** Total number of DMA Channels supported by the EDMA3 Controller */
901 64u,
902 /** Total number of QDMA Channels supported by the EDMA3 Controller */
903 8u,
904 /** Total number of TCCs supported by the EDMA3 Controller */
905 64u,
906 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
907 512u,
908 /** Total number of Event Queues in the EDMA3 Controller */
909 2u,
910 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
911 2u,
912 /** Number of Regions on this EDMA3 controller */
913 8u,
915 /**
916 * \brief Channel mapping existence
917 * A value of 0 (No channel mapping) implies that there is fixed association
918 * for a channel number to a parameter entry number or, in other words,
919 * PaRAM entry n corresponds to channel n.
920 */
921 1u,
923 /** Existence of memory protection feature */
924 1u,
926 /** Global Register Region of CC Registers */
927 (void *)0x02708000u,
928 /** Transfer Controller (TC) Registers */
929 {
930 (void *)0x027B8400u,
931 (void *)0x027B8800u,
932 (void *)NULL,
933 (void *)NULL,
934 (void *)NULL,
935 (void *)NULL,
936 (void *)NULL,
937 (void *)NULL
938 },
939 /** Interrupt no. for Transfer Completion */
940 212u,
941 /** Interrupt no. for CC Error */
942 207u,
943 /** Interrupt no. for TCs Error */
944 {
945 209u,
946 210u,
947 0u,
948 0u,
949 0u,
950 0u,
951 0u,
952 0u,
953 },
955 /**
956 * \brief EDMA3 TC priority setting
957 *
958 * User can program the priority of the Event Queues
959 * at a system-wide level. This means that the user can set the
960 * priority of an IO initiated by either of the TCs (Transfer Controllers)
961 * relative to IO initiated by the other bus masters on the
962 * device (ARM, DSP, USB, etc)
963 */
964 {
965 0u,
966 1u,
967 0u,
968 0u,
969 0u,
970 0u,
971 0u,
972 0u
973 },
974 /**
975 * \brief To Configure the Threshold level of number of events
976 * that can be queued up in the Event queues. EDMA3CC error register
977 * (CCERR) will indicate whether or not at any instant of time the
978 * number of events queued up in any of the event queues exceeds
979 * or equals the threshold/watermark value that is set
980 * in the queue watermark threshold register (QWMTHRA).
981 */
982 {
983 16u,
984 16u,
985 0u,
986 0u,
987 0u,
988 0u,
989 0u,
990 0u
991 },
993 /**
994 * \brief To Configure the Default Burst Size (DBS) of TCs.
995 * An optimally-sized command is defined by the transfer controller
996 * default burst size (DBS). Different TCs can have different
997 * DBS values. It is defined in Bytes.
998 */
999 {
1000 128u,
1001 128u,
1002 0u,
1003 0u,
1004 0u,
1005 0u,
1006 0u,
1007 0u
1008 },
1010 /**
1011 * \brief Mapping from each DMA channel to a Parameter RAM set,
1012 * if it exists, otherwise of no use.
1013 */
1014 {
1015 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1016 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1017 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1018 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1019 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1020 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1021 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1022 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1023 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1024 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1025 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1026 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1027 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1028 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1029 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1030 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1031 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1032 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1033 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1034 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1035 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1036 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1037 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1038 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1039 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1040 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1041 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1042 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1043 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1044 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1045 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1046 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
1047 },
1049 /**
1050 * \brief Mapping from each DMA channel to a TCC. This specific
1051 * TCC code will be returned when the transfer is completed
1052 * on the mapped channel.
1053 */
1054 {
1055 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
1056 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
1057 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
1058 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
1059 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1060 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1061 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1062 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1063 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1064 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1065 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1066 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
1067 },
1069 /**
1070 * \brief Mapping of DMA channels to Hardware Events from
1071 * various peripherals, which use EDMA for data transfer.
1072 * All channels need not be mapped, some can be free also.
1073 */
1074 {
1075 0xFFFFFFFFu,
1076 0x00000000u
1077 }
1078 },
1079 };
1081 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
1082 {
1083 /* EDMA3 INSTANCE# 0 */
1084 {
1085 /* Resources owned/reserved by region 0 */
1086 {
1087 /* ownPaRAMSets */
1088 /* 31 0 63 32 95 64 127 96 */
1089 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
1090 /* 159 128 191 160 223 192 255 224 */
1091 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1092 /* 287 256 319 288 351 320 383 352 */
1093 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1094 /* 415 384 447 416 479 448 511 480 */
1095 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1097 /* ownDmaChannels */
1098 /* 31 0 63 32 */
1099 {0x000000FFu, 0x00000000u},
1101 /* ownQdmaChannels */
1102 /* 31 0 */
1103 {0x00000001u},
1105 /* ownTccs */
1106 /* 31 0 63 32 */
1107 {0x000000FFu, 0x00000000u},
1109 /* resvdPaRAMSets */
1110 /* 31 0 63 32 95 64 127 96 */
1111 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1112 /* 159 128 191 160 223 192 255 224 */
1113 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1114 /* 287 256 319 288 351 320 383 352 */
1115 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1116 /* 415 384 447 416 479 448 511 480 */
1117 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1119 /* resvdDmaChannels */
1120 /* 31 0 63 32 */
1121 {0x00000000u, 0x00000000u},
1123 /* resvdQdmaChannels */
1124 /* 31 0 */
1125 {0x00000000u},
1127 /* resvdTccs */
1128 /* 31 0 63 32 */
1129 {0x00000000u, 0x00000000u},
1130 },
1132 /* Resources owned/reserved by region 1 */
1133 {
1134 /* ownPaRAMSets */
1135 /* 31 0 63 32 95 64 127 96 */
1136 {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
1137 /* 159 128 191 160 223 192 255 224 */
1138 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1139 /* 287 256 319 288 351 320 383 352 */
1140 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1141 /* 415 384 447 416 479 448 511 480 */
1142 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1144 /* ownDmaChannels */
1145 /* 31 0 63 32 */
1146 {0x0000FF00u, 0x00000000u},
1148 /* ownQdmaChannels */
1149 /* 31 0 */
1150 {0x00000002u},
1152 /* ownTccs */
1153 /* 31 0 63 32 */
1154 {0x0000FF00u, 0x00000000u},
1156 /* resvdPaRAMSets */
1157 /* 31 0 63 32 95 64 127 96 */
1158 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1159 /* 159 128 191 160 223 192 255 224 */
1160 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1161 /* 287 256 319 288 351 320 383 352 */
1162 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1163 /* 415 384 447 416 479 448 511 480 */
1164 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1166 /* resvdDmaChannels */
1167 /* 31 0 63 32 */
1168 {0x00000000u, 0x00000000u},
1170 /* resvdQdmaChannels */
1171 /* 31 0 */
1172 {0x00000000u},
1174 /* resvdTccs */
1175 /* 31 0 63 32 */
1176 {0x00000000u, 0x00000000u},
1177 },
1179 /* Resources owned/reserved by region 2 */
1180 {
1181 /* ownPaRAMSets */
1182 /* 31 0 63 32 95 64 127 96 */
1183 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1184 /* 159 128 191 160 223 192 255 224 */
1185 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
1186 /* 287 256 319 288 351 320 383 352 */
1187 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1188 /* 415 384 447 416 479 448 511 480 */
1189 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1191 /* ownDmaChannels */
1192 /* 31 0 63 32 */
1193 {0x00FF0000u, 0x0000000u},
1195 /* ownQdmaChannels */
1196 /* 31 0 */
1197 {0x00000004u},
1199 /* ownTccs */
1200 /* 31 0 63 32 */
1201 {0x00FF0000u, 0x00000000u},
1203 /* resvdPaRAMSets */
1204 /* 31 0 63 32 95 64 127 96 */
1205 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1206 /* 159 128 191 160 223 192 255 224 */
1207 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1208 /* 287 256 319 288 351 320 383 352 */
1209 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1210 /* 415 384 447 416 479 448 511 480 */
1211 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1213 /* resvdDmaChannels */
1214 /* 31 0 63 32 */
1215 {0x00000000u, 0x00000000u},
1217 /* resvdQdmaChannels */
1218 /* 31 0 */
1219 {0x00000000u},
1221 /* resvdTccs */
1222 /* 31 0 63 32 */
1223 {0x00000000u, 0x00000000u},
1224 },
1226 /* Resources owned/reserved by region 3 */
1227 {
1228 /* ownPaRAMSets */
1229 /* 31 0 63 32 95 64 127 96 */
1230 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1231 /* 159 128 191 160 223 192 255 224 */
1232 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
1233 /* 287 256 319 288 351 320 383 352 */
1234 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1235 /* 415 384 447 416 479 448 511 480 */
1236 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1238 /* ownDmaChannels */
1239 /* 31 0 63 32 */
1240 {0xFF000000u, 0x00000000u},
1242 /* ownQdmaChannels */
1243 /* 31 0 */
1244 {0x00000008u},
1246 /* ownTccs */
1247 /* 31 0 63 32 */
1248 {0xFF000000u, 0x00000000u},
1250 /* resvdPaRAMSets */
1251 /* 31 0 63 32 95 64 127 96 */
1252 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1253 /* 159 128 191 160 223 192 255 224 */
1254 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1255 /* 287 256 319 288 351 320 383 352 */
1256 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1257 /* 415 384 447 416 479 448 511 480 */
1258 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1260 /* resvdDmaChannels */
1261 /* 31 0 63 32 */
1262 {0x00000000u, 0x00000000u},
1264 /* resvdQdmaChannels */
1265 /* 31 0 */
1266 {0x00000000u},
1268 /* resvdTccs */
1269 /* 31 0 63 32 */
1270 {0x00000000u, 0x00000000u},
1271 },
1273 /* Resources owned/reserved by region 4 */
1274 {
1275 /* ownPaRAMSets */
1276 /* 31 0 63 32 95 64 127 96 */
1277 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1278 /* 159 128 191 160 223 192 255 224 */
1279 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1280 /* 287 256 319 288 351 320 383 352 */
1281 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
1282 /* 415 384 447 416 479 448 511 480 */
1283 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1285 /* ownDmaChannels */
1286 /* 31 0 63 32 */
1287 {0x00000000u, 0x000000FFu},
1289 /* ownQdmaChannels */
1290 /* 31 0 */
1291 {0x00000010u},
1293 /* ownTccs */
1294 /* 31 0 63 32 */
1295 {0x00000000u, 0x000000FFu},
1297 /* resvdPaRAMSets */
1298 /* 31 0 63 32 95 64 127 96 */
1299 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1300 /* 159 128 191 160 223 192 255 224 */
1301 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1302 /* 287 256 319 288 351 320 383 352 */
1303 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1304 /* 415 384 447 416 479 448 511 480 */
1305 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1307 /* resvdDmaChannels */
1308 /* 31 0 63 32 */
1309 {0x00000000u, 0x00000000u},
1311 /* resvdQdmaChannels */
1312 /* 31 0 */
1313 {0x00000000u},
1315 /* resvdTccs */
1316 /* 31 0 63 32 */
1317 {0x00000000u, 0x00000000u},
1318 },
1320 /* Resources owned/reserved by region 5 */
1321 {
1322 /* ownPaRAMSets */
1323 /* 31 0 63 32 95 64 127 96 */
1324 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1325 /* 159 128 191 160 223 192 255 224 */
1326 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1327 /* 287 256 319 288 351 320 383 352 */
1328 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
1329 /* 415 384 447 416 479 448 511 480 */
1330 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
1332 /* ownDmaChannels */
1333 /* 31 0 63 32 */
1334 {0x00000000u, 0x0000FF00u},
1336 /* ownQdmaChannels */
1337 /* 31 0 */
1338 {0x00000020u},
1340 /* ownTccs */
1341 /* 31 0 63 32 */
1342 {0x00000000u, 0x0000FF00u},
1344 /* resvdPaRAMSets */
1345 /* 31 0 63 32 95 64 127 96 */
1346 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1347 /* 159 128 191 160 223 192 255 224 */
1348 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1349 /* 287 256 319 288 351 320 383 352 */
1350 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1351 /* 415 384 447 416 479 448 511 480 */
1352 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1354 /* resvdDmaChannels */
1355 /* 31 0 63 32 */
1356 {0x00000000u, 0x00000000u},
1358 /* resvdQdmaChannels */
1359 /* 31 0 */
1360 {0x00000000u},
1362 /* resvdTccs */
1363 /* 31 0 63 32 */
1364 {0x00000000u, 0x00000000u},
1365 },
1367 /* Resources owned/reserved by region 6 */
1368 {
1369 /* ownPaRAMSets */
1370 /* 31 0 63 32 95 64 127 96 */
1371 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1372 /* 159 128 191 160 223 192 255 224 */
1373 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1374 /* 287 256 319 288 351 320 383 352 */
1375 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1376 /* 415 384 447 416 479 448 511 480 */
1377 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
1379 /* ownDmaChannels */
1380 /* 31 0 63 32 */
1381 {0x00000000u, 0x00FF0000u},
1383 /* ownQdmaChannels */
1384 /* 31 0 */
1385 {0x00000040u},
1387 /* ownTccs */
1388 /* 31 0 63 32 */
1389 {0x00000000u, 0x00FF0000u},
1391 /* resvdPaRAMSets */
1392 /* 31 0 63 32 95 64 127 96 */
1393 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1394 /* 159 128 191 160 223 192 255 224 */
1395 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1396 /* 287 256 319 288 351 320 383 352 */
1397 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1398 /* 415 384 447 416 479 448 511 480 */
1399 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1401 /* resvdDmaChannels */
1402 /* 31 0 63 32 */
1403 {0x00000000u, 0x00000000u},
1405 /* resvdQdmaChannels */
1406 /* 31 0 */
1407 {0x00000000u},
1409 /* resvdTccs */
1410 /* 31 0 63 32 */
1411 {0x00000000u, 0x00000000u},
1412 },
1414 /* Resources owned/reserved by region 7 */
1415 {
1416 /* ownPaRAMSets */
1417 /* 31 0 63 32 95 64 127 96 */
1418 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1419 /* 159 128 191 160 223 192 255 224 */
1420 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1421 /* 287 256 319 288 351 320 383 352 */
1422 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1423 /* 415 384 447 416 479 448 511 480 */
1424 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
1426 /* ownDmaChannels */
1427 /* 31 0 63 32 */
1428 {0x00000000u, 0xFF000000u},
1430 /* ownQdmaChannels */
1431 /* 31 0 */
1432 {0x00000080u},
1434 /* ownTccs */
1435 /* 31 0 63 32 */
1436 {0x00000000u, 0xFF000000u},
1438 /* resvdPaRAMSets */
1439 /* 31 0 63 32 95 64 127 96 */
1440 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1441 /* 159 128 191 160 223 192 255 224 */
1442 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1443 /* 287 256 319 288 351 320 383 352 */
1444 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1445 /* 415 384 447 416 479 448 511 480 */
1446 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1448 /* resvdDmaChannels */
1449 /* 31 0 63 32 */
1450 {0x00000000u, 0x00000000u},
1452 /* resvdQdmaChannels */
1453 /* 31 0 */
1454 {0x00000000u},
1456 /* resvdTccs */
1457 /* 31 0 63 32 */
1458 {0x00000000u, 0x00000000u},
1459 },
1460 },
1462 /* EDMA3 INSTANCE# 1 */
1463 {
1464 /* Resources owned/reserved by region 0 */
1465 {
1466 /* ownPaRAMSets */
1467 /* 31 0 63 32 95 64 127 96 */
1468 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
1469 /* 159 128 191 160 223 192 255 224 */
1470 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1471 /* 287 256 319 288 351 320 383 352 */
1472 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1473 /* 415 384 447 416 479 448 511 480 */
1474 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1476 /* ownDmaChannels */
1477 /* 31 0 63 32 */
1478 {0x000000FFu, 0x00000000u},
1480 /* ownQdmaChannels */
1481 /* 31 0 */
1482 {0x00000001u},
1484 /* ownTccs */
1485 /* 31 0 63 32 */
1486 {0x000000FFu, 0x00000000u},
1488 /* resvdPaRAMSets */
1489 /* 31 0 63 32 95 64 127 96 */
1490 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1491 /* 159 128 191 160 223 192 255 224 */
1492 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1493 /* 287 256 319 288 351 320 383 352 */
1494 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1495 /* 415 384 447 416 479 448 511 480 */
1496 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1498 /* resvdDmaChannels */
1499 /* 31 0 63 32 */
1500 {0x00000000u, 0x00000000u},
1502 /* resvdQdmaChannels */
1503 /* 31 0 */
1504 {0x00000000u},
1506 /* resvdTccs */
1507 /* 31 0 63 32 */
1508 {0x00000000u, 0x00000000u},
1509 },
1511 /* Resources owned/reserved by region 1 */
1512 {
1513 /* ownPaRAMSets */
1514 /* 31 0 63 32 95 64 127 96 */
1515 {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
1516 /* 159 128 191 160 223 192 255 224 */
1517 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1518 /* 287 256 319 288 351 320 383 352 */
1519 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1520 /* 415 384 447 416 479 448 511 480 */
1521 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1523 /* ownDmaChannels */
1524 /* 31 0 63 32 */
1525 {0x0000FF00u, 0x00000000u},
1527 /* ownQdmaChannels */
1528 /* 31 0 */
1529 {0x00000002u},
1531 /* ownTccs */
1532 /* 31 0 63 32 */
1533 {0x0000FF00u, 0x00000000u},
1535 /* resvdPaRAMSets */
1536 /* 31 0 63 32 95 64 127 96 */
1537 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1538 /* 159 128 191 160 223 192 255 224 */
1539 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1540 /* 287 256 319 288 351 320 383 352 */
1541 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1542 /* 415 384 447 416 479 448 511 480 */
1543 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1545 /* resvdDmaChannels */
1546 /* 31 0 63 32 */
1547 {0x00000000u, 0x00000000u},
1549 /* resvdQdmaChannels */
1550 /* 31 0 */
1551 {0x00000000u},
1553 /* resvdTccs */
1554 /* 31 0 63 32 */
1555 {0x00000000u, 0x00000000u},
1556 },
1558 /* Resources owned/reserved by region 2 */
1559 {
1560 /* ownPaRAMSets */
1561 /* 31 0 63 32 95 64 127 96 */
1562 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1563 /* 159 128 191 160 223 192 255 224 */
1564 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
1565 /* 287 256 319 288 351 320 383 352 */
1566 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1567 /* 415 384 447 416 479 448 511 480 */
1568 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1570 /* ownDmaChannels */
1571 /* 31 0 63 32 */
1572 {0x00FF0000u, 0x0000000u},
1574 /* ownQdmaChannels */
1575 /* 31 0 */
1576 {0x00000004u},
1578 /* ownTccs */
1579 /* 31 0 63 32 */
1580 {0x00FF0000u, 0x00000000u},
1582 /* resvdPaRAMSets */
1583 /* 31 0 63 32 95 64 127 96 */
1584 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1585 /* 159 128 191 160 223 192 255 224 */
1586 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1587 /* 287 256 319 288 351 320 383 352 */
1588 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1589 /* 415 384 447 416 479 448 511 480 */
1590 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1592 /* resvdDmaChannels */
1593 /* 31 0 63 32 */
1594 {0x00000000u, 0x00000000u},
1596 /* resvdQdmaChannels */
1597 /* 31 0 */
1598 {0x00000000u},
1600 /* resvdTccs */
1601 /* 31 0 63 32 */
1602 {0x00000000u, 0x00000000u},
1603 },
1605 /* Resources owned/reserved by region 3 */
1606 {
1607 /* ownPaRAMSets */
1608 /* 31 0 63 32 95 64 127 96 */
1609 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1610 /* 159 128 191 160 223 192 255 224 */
1611 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
1612 /* 287 256 319 288 351 320 383 352 */
1613 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1614 /* 415 384 447 416 479 448 511 480 */
1615 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1617 /* ownDmaChannels */
1618 /* 31 0 63 32 */
1619 {0xFF000000u, 0x00000000u},
1621 /* ownQdmaChannels */
1622 /* 31 0 */
1623 {0x00000008u},
1625 /* ownTccs */
1626 /* 31 0 63 32 */
1627 {0xFF000000u, 0x00000000u},
1629 /* resvdPaRAMSets */
1630 /* 31 0 63 32 95 64 127 96 */
1631 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1632 /* 159 128 191 160 223 192 255 224 */
1633 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1634 /* 287 256 319 288 351 320 383 352 */
1635 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1636 /* 415 384 447 416 479 448 511 480 */
1637 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1639 /* resvdDmaChannels */
1640 /* 31 0 63 32 */
1641 {0x00000000u, 0x00000000u},
1643 /* resvdQdmaChannels */
1644 /* 31 0 */
1645 {0x00000000u},
1647 /* resvdTccs */
1648 /* 31 0 63 32 */
1649 {0x00000000u, 0x00000000u},
1650 },
1652 /* Resources owned/reserved by region 4 */
1653 {
1654 /* ownPaRAMSets */
1655 /* 31 0 63 32 95 64 127 96 */
1656 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1657 /* 159 128 191 160 223 192 255 224 */
1658 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1659 /* 287 256 319 288 351 320 383 352 */
1660 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
1661 /* 415 384 447 416 479 448 511 480 */
1662 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1664 /* ownDmaChannels */
1665 /* 31 0 63 32 */
1666 {0x00000000u, 0x000000FFu},
1668 /* ownQdmaChannels */
1669 /* 31 0 */
1670 {0x00000010u},
1672 /* ownTccs */
1673 /* 31 0 63 32 */
1674 {0x00000000u, 0x000000FFu},
1676 /* resvdPaRAMSets */
1677 /* 31 0 63 32 95 64 127 96 */
1678 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1679 /* 159 128 191 160 223 192 255 224 */
1680 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1681 /* 287 256 319 288 351 320 383 352 */
1682 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1683 /* 415 384 447 416 479 448 511 480 */
1684 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1686 /* resvdDmaChannels */
1687 /* 31 0 63 32 */
1688 {0x00000000u, 0x00000000u},
1690 /* resvdQdmaChannels */
1691 /* 31 0 */
1692 {0x00000000u},
1694 /* resvdTccs */
1695 /* 31 0 63 32 */
1696 {0x00000000u, 0x00000000u},
1697 },
1699 /* Resources owned/reserved by region 5 */
1700 {
1701 /* ownPaRAMSets */
1702 /* 31 0 63 32 95 64 127 96 */
1703 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1704 /* 159 128 191 160 223 192 255 224 */
1705 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1706 /* 287 256 319 288 351 320 383 352 */
1707 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
1708 /* 415 384 447 416 479 448 511 480 */
1709 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
1711 /* ownDmaChannels */
1712 /* 31 0 63 32 */
1713 {0x00000000u, 0x0000FF00u},
1715 /* ownQdmaChannels */
1716 /* 31 0 */
1717 {0x00000020u},
1719 /* ownTccs */
1720 /* 31 0 63 32 */
1721 {0x00000000u, 0x0000FF00u},
1723 /* resvdPaRAMSets */
1724 /* 31 0 63 32 95 64 127 96 */
1725 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1726 /* 159 128 191 160 223 192 255 224 */
1727 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1728 /* 287 256 319 288 351 320 383 352 */
1729 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1730 /* 415 384 447 416 479 448 511 480 */
1731 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1733 /* resvdDmaChannels */
1734 /* 31 0 63 32 */
1735 {0x00000000u, 0x00000000u},
1737 /* resvdQdmaChannels */
1738 /* 31 0 */
1739 {0x00000000u},
1741 /* resvdTccs */
1742 /* 31 0 63 32 */
1743 {0x00000000u, 0x00000000u},
1744 },
1746 /* Resources owned/reserved by region 6 */
1747 {
1748 /* ownPaRAMSets */
1749 /* 31 0 63 32 95 64 127 96 */
1750 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1751 /* 159 128 191 160 223 192 255 224 */
1752 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1753 /* 287 256 319 288 351 320 383 352 */
1754 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1755 /* 415 384 447 416 479 448 511 480 */
1756 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
1758 /* ownDmaChannels */
1759 /* 31 0 63 32 */
1760 {0x00000000u, 0x00FF0000u},
1762 /* ownQdmaChannels */
1763 /* 31 0 */
1764 {0x00000040u},
1766 /* ownTccs */
1767 /* 31 0 63 32 */
1768 {0x00000000u, 0x00FF0000u},
1770 /* resvdPaRAMSets */
1771 /* 31 0 63 32 95 64 127 96 */
1772 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1773 /* 159 128 191 160 223 192 255 224 */
1774 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1775 /* 287 256 319 288 351 320 383 352 */
1776 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1777 /* 415 384 447 416 479 448 511 480 */
1778 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1780 /* resvdDmaChannels */
1781 /* 31 0 63 32 */
1782 {0x00000000u, 0x00000000u},
1784 /* resvdQdmaChannels */
1785 /* 31 0 */
1786 {0x00000000u},
1788 /* resvdTccs */
1789 /* 31 0 63 32 */
1790 {0x00000000u, 0x00000000u},
1791 },
1793 /* Resources owned/reserved by region 7 */
1794 {
1795 /* ownPaRAMSets */
1796 /* 31 0 63 32 95 64 127 96 */
1797 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1798 /* 159 128 191 160 223 192 255 224 */
1799 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1800 /* 287 256 319 288 351 320 383 352 */
1801 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1802 /* 415 384 447 416 479 448 511 480 */
1803 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
1805 /* ownDmaChannels */
1806 /* 31 0 63 32 */
1807 {0x00000000u, 0xFF000000u},
1809 /* ownQdmaChannels */
1810 /* 31 0 */
1811 {0x00000080u},
1813 /* ownTccs */
1814 /* 31 0 63 32 */
1815 {0x00000000u, 0xFF000000u},
1817 /* resvdPaRAMSets */
1818 /* 31 0 63 32 95 64 127 96 */
1819 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1820 /* 159 128 191 160 223 192 255 224 */
1821 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1822 /* 287 256 319 288 351 320 383 352 */
1823 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1824 /* 415 384 447 416 479 448 511 480 */
1825 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1827 /* resvdDmaChannels */
1828 /* 31 0 63 32 */
1829 {0x00000000u, 0x00000000u},
1831 /* resvdQdmaChannels */
1832 /* 31 0 */
1833 {0x00000000u},
1835 /* resvdTccs */
1836 /* 31 0 63 32 */
1837 {0x00000000u, 0x00000000u},
1838 },
1839 },
1841 /* EDMA3 INSTANCE# 2 */
1842 {
1843 /* Resources owned/reserved by region 0 */
1844 {
1845 /* ownPaRAMSets */
1846 /* 31 0 63 32 95 64 127 96 */
1847 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
1848 /* 159 128 191 160 223 192 255 224 */
1849 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1850 /* 287 256 319 288 351 320 383 352 */
1851 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1852 /* 415 384 447 416 479 448 511 480 */
1853 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1855 /* ownDmaChannels */
1856 /* 31 0 63 32 */
1857 {0x000000FFu, 0x00000000u},
1859 /* ownQdmaChannels */
1860 /* 31 0 */
1861 {0x00000001u},
1863 /* ownTccs */
1864 /* 31 0 63 32 */
1865 {0x000000FFu, 0x00000000u},
1867 /* resvdPaRAMSets */
1868 /* 31 0 63 32 95 64 127 96 */
1869 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1870 /* 159 128 191 160 223 192 255 224 */
1871 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1872 /* 287 256 319 288 351 320 383 352 */
1873 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1874 /* 415 384 447 416 479 448 511 480 */
1875 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1877 /* resvdDmaChannels */
1878 /* 31 0 63 32 */
1879 {0x00000000u, 0x00000000u},
1881 /* resvdQdmaChannels */
1882 /* 31 0 */
1883 {0x00000000u},
1885 /* resvdTccs */
1886 /* 31 0 63 32 */
1887 {0x00000000u, 0x00000000u},
1888 },
1890 /* Resources owned/reserved by region 1 */
1891 {
1892 /* ownPaRAMSets */
1893 /* 31 0 63 32 95 64 127 96 */
1894 {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
1895 /* 159 128 191 160 223 192 255 224 */
1896 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1897 /* 287 256 319 288 351 320 383 352 */
1898 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1899 /* 415 384 447 416 479 448 511 480 */
1900 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1902 /* ownDmaChannels */
1903 /* 31 0 63 32 */
1904 {0x0000FF00u, 0x00000000u},
1906 /* ownQdmaChannels */
1907 /* 31 0 */
1908 {0x00000002u},
1910 /* ownTccs */
1911 /* 31 0 63 32 */
1912 {0x0000FF00u, 0x00000000u},
1914 /* resvdPaRAMSets */
1915 /* 31 0 63 32 95 64 127 96 */
1916 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1917 /* 159 128 191 160 223 192 255 224 */
1918 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1919 /* 287 256 319 288 351 320 383 352 */
1920 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1921 /* 415 384 447 416 479 448 511 480 */
1922 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1924 /* resvdDmaChannels */
1925 /* 31 0 63 32 */
1926 {0x00000000u, 0x00000000u},
1928 /* resvdQdmaChannels */
1929 /* 31 0 */
1930 {0x00000000u},
1932 /* resvdTccs */
1933 /* 31 0 63 32 */
1934 {0x00000000u, 0x00000000u},
1935 },
1937 /* Resources owned/reserved by region 2 */
1938 {
1939 /* ownPaRAMSets */
1940 /* 31 0 63 32 95 64 127 96 */
1941 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1942 /* 159 128 191 160 223 192 255 224 */
1943 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
1944 /* 287 256 319 288 351 320 383 352 */
1945 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1946 /* 415 384 447 416 479 448 511 480 */
1947 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1949 /* ownDmaChannels */
1950 /* 31 0 63 32 */
1951 {0x00FF0000u, 0x0000000u},
1953 /* ownQdmaChannels */
1954 /* 31 0 */
1955 {0x00000004u},
1957 /* ownTccs */
1958 /* 31 0 63 32 */
1959 {0x00FF0000u, 0x00000000u},
1961 /* resvdPaRAMSets */
1962 /* 31 0 63 32 95 64 127 96 */
1963 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1964 /* 159 128 191 160 223 192 255 224 */
1965 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1966 /* 287 256 319 288 351 320 383 352 */
1967 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1968 /* 415 384 447 416 479 448 511 480 */
1969 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1971 /* resvdDmaChannels */
1972 /* 31 0 63 32 */
1973 {0x00000000u, 0x00000000u},
1975 /* resvdQdmaChannels */
1976 /* 31 0 */
1977 {0x00000000u},
1979 /* resvdTccs */
1980 /* 31 0 63 32 */
1981 {0x00000000u, 0x00000000u},
1982 },
1984 /* Resources owned/reserved by region 3 */
1985 {
1986 /* ownPaRAMSets */
1987 /* 31 0 63 32 95 64 127 96 */
1988 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1989 /* 159 128 191 160 223 192 255 224 */
1990 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
1991 /* 287 256 319 288 351 320 383 352 */
1992 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1993 /* 415 384 447 416 479 448 511 480 */
1994 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1996 /* ownDmaChannels */
1997 /* 31 0 63 32 */
1998 {0xFF000000u, 0x00000000u},
2000 /* ownQdmaChannels */
2001 /* 31 0 */
2002 {0x00000008u},
2004 /* ownTccs */
2005 /* 31 0 63 32 */
2006 {0xFF000000u, 0x00000000u},
2008 /* resvdPaRAMSets */
2009 /* 31 0 63 32 95 64 127 96 */
2010 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2011 /* 159 128 191 160 223 192 255 224 */
2012 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2013 /* 287 256 319 288 351 320 383 352 */
2014 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2015 /* 415 384 447 416 479 448 511 480 */
2016 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2018 /* resvdDmaChannels */
2019 /* 31 0 63 32 */
2020 {0x00000000u, 0x00000000u},
2022 /* resvdQdmaChannels */
2023 /* 31 0 */
2024 {0x00000000u},
2026 /* resvdTccs */
2027 /* 31 0 63 32 */
2028 {0x00000000u, 0x00000000u},
2029 },
2031 /* Resources owned/reserved by region 4 */
2032 {
2033 /* ownPaRAMSets */
2034 /* 31 0 63 32 95 64 127 96 */
2035 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2036 /* 159 128 191 160 223 192 255 224 */
2037 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2038 /* 287 256 319 288 351 320 383 352 */
2039 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
2040 /* 415 384 447 416 479 448 511 480 */
2041 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
2043 /* ownDmaChannels */
2044 /* 31 0 63 32 */
2045 {0x00000000u, 0x000000FFu},
2047 /* ownQdmaChannels */
2048 /* 31 0 */
2049 {0x00000010u},
2051 /* ownTccs */
2052 /* 31 0 63 32 */
2053 {0x00000000u, 0x000000FFu},
2055 /* resvdPaRAMSets */
2056 /* 31 0 63 32 95 64 127 96 */
2057 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2058 /* 159 128 191 160 223 192 255 224 */
2059 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2060 /* 287 256 319 288 351 320 383 352 */
2061 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2062 /* 415 384 447 416 479 448 511 480 */
2063 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2065 /* resvdDmaChannels */
2066 /* 31 0 63 32 */
2067 {0x00000000u, 0x00000000u},
2069 /* resvdQdmaChannels */
2070 /* 31 0 */
2071 {0x00000000u},
2073 /* resvdTccs */
2074 /* 31 0 63 32 */
2075 {0x00000000u, 0x00000000u},
2076 },
2078 /* Resources owned/reserved by region 5 */
2079 {
2080 /* ownPaRAMSets */
2081 /* 31 0 63 32 95 64 127 96 */
2082 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2083 /* 159 128 191 160 223 192 255 224 */
2084 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2085 /* 287 256 319 288 351 320 383 352 */
2086 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
2087 /* 415 384 447 416 479 448 511 480 */
2088 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
2090 /* ownDmaChannels */
2091 /* 31 0 63 32 */
2092 {0x00000000u, 0x0000FF00u},
2094 /* ownQdmaChannels */
2095 /* 31 0 */
2096 {0x00000020u},
2098 /* ownTccs */
2099 /* 31 0 63 32 */
2100 {0x00000000u, 0x0000FF00u},
2102 /* resvdPaRAMSets */
2103 /* 31 0 63 32 95 64 127 96 */
2104 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2105 /* 159 128 191 160 223 192 255 224 */
2106 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2107 /* 287 256 319 288 351 320 383 352 */
2108 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2109 /* 415 384 447 416 479 448 511 480 */
2110 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2112 /* resvdDmaChannels */
2113 /* 31 0 63 32 */
2114 {0x00000000u, 0x00000000u},
2116 /* resvdQdmaChannels */
2117 /* 31 0 */
2118 {0x00000000u},
2120 /* resvdTccs */
2121 /* 31 0 63 32 */
2122 {0x00000000u, 0x00000000u},
2123 },
2125 /* Resources owned/reserved by region 6 */
2126 {
2127 /* ownPaRAMSets */
2128 /* 31 0 63 32 95 64 127 96 */
2129 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2130 /* 159 128 191 160 223 192 255 224 */
2131 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2132 /* 287 256 319 288 351 320 383 352 */
2133 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2134 /* 415 384 447 416 479 448 511 480 */
2135 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
2137 /* ownDmaChannels */
2138 /* 31 0 63 32 */
2139 {0x00000000u, 0x00FF0000u},
2141 /* ownQdmaChannels */
2142 /* 31 0 */
2143 {0x00000040u},
2145 /* ownTccs */
2146 /* 31 0 63 32 */
2147 {0x00000000u, 0x00FF0000u},
2149 /* resvdPaRAMSets */
2150 /* 31 0 63 32 95 64 127 96 */
2151 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2152 /* 159 128 191 160 223 192 255 224 */
2153 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2154 /* 287 256 319 288 351 320 383 352 */
2155 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2156 /* 415 384 447 416 479 448 511 480 */
2157 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2159 /* resvdDmaChannels */
2160 /* 31 0 63 32 */
2161 {0x00000000u, 0x00000000u},
2163 /* resvdQdmaChannels */
2164 /* 31 0 */
2165 {0x00000000u},
2167 /* resvdTccs */
2168 /* 31 0 63 32 */
2169 {0x00000000u, 0x00000000u},
2170 },
2172 /* Resources owned/reserved by region 7 */
2173 {
2174 /* ownPaRAMSets */
2175 /* 31 0 63 32 95 64 127 96 */
2176 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2177 /* 159 128 191 160 223 192 255 224 */
2178 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2179 /* 287 256 319 288 351 320 383 352 */
2180 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2181 /* 415 384 447 416 479 448 511 480 */
2182 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
2184 /* ownDmaChannels */
2185 /* 31 0 63 32 */
2186 {0x00000000u, 0xFF000000u},
2188 /* ownQdmaChannels */
2189 /* 31 0 */
2190 {0x00000080u},
2192 /* ownTccs */
2193 /* 31 0 63 32 */
2194 {0x00000000u, 0xFF000000u},
2196 /* resvdPaRAMSets */
2197 /* 31 0 63 32 95 64 127 96 */
2198 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2199 /* 159 128 191 160 223 192 255 224 */
2200 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2201 /* 287 256 319 288 351 320 383 352 */
2202 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2203 /* 415 384 447 416 479 448 511 480 */
2204 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2206 /* resvdDmaChannels */
2207 /* 31 0 63 32 */
2208 {0x00000000u, 0x00000000u},
2210 /* resvdQdmaChannels */
2211 /* 31 0 */
2212 {0x00000000u},
2214 /* resvdTccs */
2215 /* 31 0 63 32 */
2216 {0x00000000u, 0x00000000u},
2217 },
2218 },
2220 /* EDMA3 INSTANCE# 3 */
2221 {
2222 /* Resources owned/reserved by region 0 */
2223 {
2224 /* ownPaRAMSets */
2225 /* 31 0 63 32 95 64 127 96 */
2226 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
2227 /* 159 128 191 160 223 192 255 224 */
2228 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2229 /* 287 256 319 288 351 320 383 352 */
2230 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2231 /* 415 384 447 416 479 448 511 480 */
2232 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
2234 /* ownDmaChannels */
2235 /* 31 0 63 32 */
2236 {0x000000FFu, 0x00000000u},
2238 /* ownQdmaChannels */
2239 /* 31 0 */
2240 {0x00000001u},
2242 /* ownTccs */
2243 /* 31 0 63 32 */
2244 {0x000000FFu, 0x00000000u},
2246 /* resvdPaRAMSets */
2247 /* 31 0 63 32 95 64 127 96 */
2248 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2249 /* 159 128 191 160 223 192 255 224 */
2250 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2251 /* 287 256 319 288 351 320 383 352 */
2252 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2253 /* 415 384 447 416 479 448 511 480 */
2254 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2256 /* resvdDmaChannels */
2257 /* 31 0 63 32 */
2258 {0x00000000u, 0x00000000u},
2260 /* resvdQdmaChannels */
2261 /* 31 0 */
2262 {0x00000000u},
2264 /* resvdTccs */
2265 /* 31 0 63 32 */
2266 {0x00000000u, 0x00000000u},
2267 },
2269 /* Resources owned/reserved by region 1 */
2270 {
2271 /* ownPaRAMSets */
2272 /* 31 0 63 32 95 64 127 96 */
2273 {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
2274 /* 159 128 191 160 223 192 255 224 */
2275 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
2276 /* 287 256 319 288 351 320 383 352 */
2277 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2278 /* 415 384 447 416 479 448 511 480 */
2279 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
2281 /* ownDmaChannels */
2282 /* 31 0 63 32 */
2283 {0x0000FF00u, 0x00000000u},
2285 /* ownQdmaChannels */
2286 /* 31 0 */
2287 {0x00000002u},
2289 /* ownTccs */
2290 /* 31 0 63 32 */
2291 {0x0000FF00u, 0x00000000u},
2293 /* resvdPaRAMSets */
2294 /* 31 0 63 32 95 64 127 96 */
2295 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2296 /* 159 128 191 160 223 192 255 224 */
2297 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2298 /* 287 256 319 288 351 320 383 352 */
2299 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2300 /* 415 384 447 416 479 448 511 480 */
2301 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2303 /* resvdDmaChannels */
2304 /* 31 0 63 32 */
2305 {0x00000000u, 0x00000000u},
2307 /* resvdQdmaChannels */
2308 /* 31 0 */
2309 {0x00000000u},
2311 /* resvdTccs */
2312 /* 31 0 63 32 */
2313 {0x00000000u, 0x00000000u},
2314 },
2316 /* Resources owned/reserved by region 2 */
2317 {
2318 /* ownPaRAMSets */
2319 /* 31 0 63 32 95 64 127 96 */
2320 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2321 /* 159 128 191 160 223 192 255 224 */
2322 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
2323 /* 287 256 319 288 351 320 383 352 */
2324 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2325 /* 415 384 447 416 479 448 511 480 */
2326 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
2328 /* ownDmaChannels */
2329 /* 31 0 63 32 */
2330 {0x00FF0000u, 0x0000000u},
2332 /* ownQdmaChannels */
2333 /* 31 0 */
2334 {0x00000004u},
2336 /* ownTccs */
2337 /* 31 0 63 32 */
2338 {0x00FF0000u, 0x00000000u},
2340 /* resvdPaRAMSets */
2341 /* 31 0 63 32 95 64 127 96 */
2342 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2343 /* 159 128 191 160 223 192 255 224 */
2344 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2345 /* 287 256 319 288 351 320 383 352 */
2346 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2347 /* 415 384 447 416 479 448 511 480 */
2348 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2350 /* resvdDmaChannels */
2351 /* 31 0 63 32 */
2352 {0x00000000u, 0x00000000u},
2354 /* resvdQdmaChannels */
2355 /* 31 0 */
2356 {0x00000000u},
2358 /* resvdTccs */
2359 /* 31 0 63 32 */
2360 {0x00000000u, 0x00000000u},
2361 },
2363 /* Resources owned/reserved by region 3 */
2364 {
2365 /* ownPaRAMSets */
2366 /* 31 0 63 32 95 64 127 96 */
2367 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2368 /* 159 128 191 160 223 192 255 224 */
2369 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
2370 /* 287 256 319 288 351 320 383 352 */
2371 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
2372 /* 415 384 447 416 479 448 511 480 */
2373 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
2375 /* ownDmaChannels */
2376 /* 31 0 63 32 */
2377 {0xFF000000u, 0x00000000u},
2379 /* ownQdmaChannels */
2380 /* 31 0 */
2381 {0x00000008u},
2383 /* ownTccs */
2384 /* 31 0 63 32 */
2385 {0xFF000000u, 0x00000000u},
2387 /* resvdPaRAMSets */
2388 /* 31 0 63 32 95 64 127 96 */
2389 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2390 /* 159 128 191 160 223 192 255 224 */
2391 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2392 /* 287 256 319 288 351 320 383 352 */
2393 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2394 /* 415 384 447 416 479 448 511 480 */
2395 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2397 /* resvdDmaChannels */
2398 /* 31 0 63 32 */
2399 {0x00000000u, 0x00000000u},
2401 /* resvdQdmaChannels */
2402 /* 31 0 */
2403 {0x00000000u},
2405 /* resvdTccs */
2406 /* 31 0 63 32 */
2407 {0x00000000u, 0x00000000u},
2408 },
2410 /* Resources owned/reserved by region 4 */
2411 {
2412 /* ownPaRAMSets */
2413 /* 31 0 63 32 95 64 127 96 */
2414 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2415 /* 159 128 191 160 223 192 255 224 */
2416 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2417 /* 287 256 319 288 351 320 383 352 */
2418 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
2419 /* 415 384 447 416 479 448 511 480 */
2420 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
2422 /* ownDmaChannels */
2423 /* 31 0 63 32 */
2424 {0x00000000u, 0x000000FFu},
2426 /* ownQdmaChannels */
2427 /* 31 0 */
2428 {0x00000010u},
2430 /* ownTccs */
2431 /* 31 0 63 32 */
2432 {0x00000000u, 0x000000FFu},
2434 /* resvdPaRAMSets */
2435 /* 31 0 63 32 95 64 127 96 */
2436 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2437 /* 159 128 191 160 223 192 255 224 */
2438 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2439 /* 287 256 319 288 351 320 383 352 */
2440 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2441 /* 415 384 447 416 479 448 511 480 */
2442 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2444 /* resvdDmaChannels */
2445 /* 31 0 63 32 */
2446 {0x00000000u, 0x00000000u},
2448 /* resvdQdmaChannels */
2449 /* 31 0 */
2450 {0x00000000u},
2452 /* resvdTccs */
2453 /* 31 0 63 32 */
2454 {0x00000000u, 0x00000000u},
2455 },
2457 /* Resources owned/reserved by region 5 */
2458 {
2459 /* ownPaRAMSets */
2460 /* 31 0 63 32 95 64 127 96 */
2461 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2462 /* 159 128 191 160 223 192 255 224 */
2463 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2464 /* 287 256 319 288 351 320 383 352 */
2465 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
2466 /* 415 384 447 416 479 448 511 480 */
2467 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
2469 /* ownDmaChannels */
2470 /* 31 0 63 32 */
2471 {0x00000000u, 0x0000FF00u},
2473 /* ownQdmaChannels */
2474 /* 31 0 */
2475 {0x00000020u},
2477 /* ownTccs */
2478 /* 31 0 63 32 */
2479 {0x00000000u, 0x0000FF00u},
2481 /* resvdPaRAMSets */
2482 /* 31 0 63 32 95 64 127 96 */
2483 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2484 /* 159 128 191 160 223 192 255 224 */
2485 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2486 /* 287 256 319 288 351 320 383 352 */
2487 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2488 /* 415 384 447 416 479 448 511 480 */
2489 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2491 /* resvdDmaChannels */
2492 /* 31 0 63 32 */
2493 {0x00000000u, 0x00000000u},
2495 /* resvdQdmaChannels */
2496 /* 31 0 */
2497 {0x00000000u},
2499 /* resvdTccs */
2500 /* 31 0 63 32 */
2501 {0x00000000u, 0x00000000u},
2502 },
2504 /* Resources owned/reserved by region 6 */
2505 {
2506 /* ownPaRAMSets */
2507 /* 31 0 63 32 95 64 127 96 */
2508 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2509 /* 159 128 191 160 223 192 255 224 */
2510 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2511 /* 287 256 319 288 351 320 383 352 */
2512 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2513 /* 415 384 447 416 479 448 511 480 */
2514 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
2516 /* ownDmaChannels */
2517 /* 31 0 63 32 */
2518 {0x00000000u, 0x00FF0000u},
2520 /* ownQdmaChannels */
2521 /* 31 0 */
2522 {0x00000040u},
2524 /* ownTccs */
2525 /* 31 0 63 32 */
2526 {0x00000000u, 0x00FF0000u},
2528 /* resvdPaRAMSets */
2529 /* 31 0 63 32 95 64 127 96 */
2530 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2531 /* 159 128 191 160 223 192 255 224 */
2532 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2533 /* 287 256 319 288 351 320 383 352 */
2534 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2535 /* 415 384 447 416 479 448 511 480 */
2536 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2538 /* resvdDmaChannels */
2539 /* 31 0 63 32 */
2540 {0x00000000u, 0x00000000u},
2542 /* resvdQdmaChannels */
2543 /* 31 0 */
2544 {0x00000000u},
2546 /* resvdTccs */
2547 /* 31 0 63 32 */
2548 {0x00000000u, 0x00000000u},
2549 },
2551 /* Resources owned/reserved by region 7 */
2552 {
2553 /* ownPaRAMSets */
2554 /* 31 0 63 32 95 64 127 96 */
2555 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2556 /* 159 128 191 160 223 192 255 224 */
2557 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2558 /* 287 256 319 288 351 320 383 352 */
2559 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2560 /* 415 384 447 416 479 448 511 480 */
2561 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
2563 /* ownDmaChannels */
2564 /* 31 0 63 32 */
2565 {0x00000000u, 0xFF000000u},
2567 /* ownQdmaChannels */
2568 /* 31 0 */
2569 {0x00000080u},
2571 /* ownTccs */
2572 /* 31 0 63 32 */
2573 {0x00000000u, 0xFF000000u},
2575 /* resvdPaRAMSets */
2576 /* 31 0 63 32 95 64 127 96 */
2577 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2578 /* 159 128 191 160 223 192 255 224 */
2579 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2580 /* 287 256 319 288 351 320 383 352 */
2581 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2582 /* 415 384 447 416 479 448 511 480 */
2583 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2585 /* resvdDmaChannels */
2586 /* 31 0 63 32 */
2587 {0x00000000u, 0x00000000u},
2589 /* resvdQdmaChannels */
2590 /* 31 0 */
2591 {0x00000000u},
2593 /* resvdTccs */
2594 /* 31 0 63 32 */
2595 {0x00000000u, 0x00000000u},
2596 },
2597 },
2599 /* EDMA3 INSTANCE# 4 */
2600 {
2601 /* Resources owned/reserved by region 0 */
2602 {
2603 /* ownPaRAMSets */
2604 /* 31 0 63 32 95 64 127 96 */
2605 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
2606 /* 159 128 191 160 223 192 255 224 */
2607 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2608 /* 287 256 319 288 351 320 383 352 */
2609 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2610 /* 415 384 447 416 479 448 511 480 */
2611 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
2613 /* ownDmaChannels */
2614 /* 31 0 63 32 */
2615 {0x000000FFu, 0x00000000u},
2617 /* ownQdmaChannels */
2618 /* 31 0 */
2619 {0x00000001u},
2621 /* ownTccs */
2622 /* 31 0 63 32 */
2623 {0x000000FFu, 0x00000000u},
2625 /* resvdPaRAMSets */
2626 /* 31 0 63 32 95 64 127 96 */
2627 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2628 /* 159 128 191 160 223 192 255 224 */
2629 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2630 /* 287 256 319 288 351 320 383 352 */
2631 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2632 /* 415 384 447 416 479 448 511 480 */
2633 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2635 /* resvdDmaChannels */
2636 /* 31 0 63 32 */
2637 {0x00000000u, 0x00000000u},
2639 /* resvdQdmaChannels */
2640 /* 31 0 */
2641 {0x00000000u},
2643 /* resvdTccs */
2644 /* 31 0 63 32 */
2645 {0x00000000u, 0x00000000u},
2646 },
2648 /* Resources owned/reserved by region 1 */
2649 {
2650 /* ownPaRAMSets */
2651 /* 31 0 63 32 95 64 127 96 */
2652 {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
2653 /* 159 128 191 160 223 192 255 224 */
2654 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
2655 /* 287 256 319 288 351 320 383 352 */
2656 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2657 /* 415 384 447 416 479 448 511 480 */
2658 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
2660 /* ownDmaChannels */
2661 /* 31 0 63 32 */
2662 {0x0000FF00u, 0x00000000u},
2664 /* ownQdmaChannels */
2665 /* 31 0 */
2666 {0x00000002u},
2668 /* ownTccs */
2669 /* 31 0 63 32 */
2670 {0x0000FF00u, 0x00000000u},
2672 /* resvdPaRAMSets */
2673 /* 31 0 63 32 95 64 127 96 */
2674 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2675 /* 159 128 191 160 223 192 255 224 */
2676 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2677 /* 287 256 319 288 351 320 383 352 */
2678 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2679 /* 415 384 447 416 479 448 511 480 */
2680 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2682 /* resvdDmaChannels */
2683 /* 31 0 63 32 */
2684 {0x00000000u, 0x00000000u},
2686 /* resvdQdmaChannels */
2687 /* 31 0 */
2688 {0x00000000u},
2690 /* resvdTccs */
2691 /* 31 0 63 32 */
2692 {0x00000000u, 0x00000000u},
2693 },
2695 /* Resources owned/reserved by region 2 */
2696 {
2697 /* ownPaRAMSets */
2698 /* 31 0 63 32 95 64 127 96 */
2699 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2700 /* 159 128 191 160 223 192 255 224 */
2701 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
2702 /* 287 256 319 288 351 320 383 352 */
2703 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2704 /* 415 384 447 416 479 448 511 480 */
2705 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
2707 /* ownDmaChannels */
2708 /* 31 0 63 32 */
2709 {0x00FF0000u, 0x0000000u},
2711 /* ownQdmaChannels */
2712 /* 31 0 */
2713 {0x00000004u},
2715 /* ownTccs */
2716 /* 31 0 63 32 */
2717 {0x00FF0000u, 0x00000000u},
2719 /* resvdPaRAMSets */
2720 /* 31 0 63 32 95 64 127 96 */
2721 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2722 /* 159 128 191 160 223 192 255 224 */
2723 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2724 /* 287 256 319 288 351 320 383 352 */
2725 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2726 /* 415 384 447 416 479 448 511 480 */
2727 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2729 /* resvdDmaChannels */
2730 /* 31 0 63 32 */
2731 {0x00000000u, 0x00000000u},
2733 /* resvdQdmaChannels */
2734 /* 31 0 */
2735 {0x00000000u},
2737 /* resvdTccs */
2738 /* 31 0 63 32 */
2739 {0x00000000u, 0x00000000u},
2740 },
2742 /* Resources owned/reserved by region 3 */
2743 {
2744 /* ownPaRAMSets */
2745 /* 31 0 63 32 95 64 127 96 */
2746 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2747 /* 159 128 191 160 223 192 255 224 */
2748 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
2749 /* 287 256 319 288 351 320 383 352 */
2750 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
2751 /* 415 384 447 416 479 448 511 480 */
2752 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
2754 /* ownDmaChannels */
2755 /* 31 0 63 32 */
2756 {0xFF000000u, 0x00000000u},
2758 /* ownQdmaChannels */
2759 /* 31 0 */
2760 {0x00000008u},
2762 /* ownTccs */
2763 /* 31 0 63 32 */
2764 {0xFF000000u, 0x00000000u},
2766 /* resvdPaRAMSets */
2767 /* 31 0 63 32 95 64 127 96 */
2768 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2769 /* 159 128 191 160 223 192 255 224 */
2770 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2771 /* 287 256 319 288 351 320 383 352 */
2772 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2773 /* 415 384 447 416 479 448 511 480 */
2774 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2776 /* resvdDmaChannels */
2777 /* 31 0 63 32 */
2778 {0x00000000u, 0x00000000u},
2780 /* resvdQdmaChannels */
2781 /* 31 0 */
2782 {0x00000000u},
2784 /* resvdTccs */
2785 /* 31 0 63 32 */
2786 {0x00000000u, 0x00000000u},
2787 },
2789 /* Resources owned/reserved by region 4 */
2790 {
2791 /* ownPaRAMSets */
2792 /* 31 0 63 32 95 64 127 96 */
2793 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2794 /* 159 128 191 160 223 192 255 224 */
2795 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2796 /* 287 256 319 288 351 320 383 352 */
2797 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
2798 /* 415 384 447 416 479 448 511 480 */
2799 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
2801 /* ownDmaChannels */
2802 /* 31 0 63 32 */
2803 {0x00000000u, 0x000000FFu},
2805 /* ownQdmaChannels */
2806 /* 31 0 */
2807 {0x00000010u},
2809 /* ownTccs */
2810 /* 31 0 63 32 */
2811 {0x00000000u, 0x000000FFu},
2813 /* resvdPaRAMSets */
2814 /* 31 0 63 32 95 64 127 96 */
2815 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2816 /* 159 128 191 160 223 192 255 224 */
2817 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2818 /* 287 256 319 288 351 320 383 352 */
2819 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2820 /* 415 384 447 416 479 448 511 480 */
2821 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2823 /* resvdDmaChannels */
2824 /* 31 0 63 32 */
2825 {0x00000000u, 0x00000000u},
2827 /* resvdQdmaChannels */
2828 /* 31 0 */
2829 {0x00000000u},
2831 /* resvdTccs */
2832 /* 31 0 63 32 */
2833 {0x00000000u, 0x00000000u},
2834 },
2836 /* Resources owned/reserved by region 5 */
2837 {
2838 /* ownPaRAMSets */
2839 /* 31 0 63 32 95 64 127 96 */
2840 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2841 /* 159 128 191 160 223 192 255 224 */
2842 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2843 /* 287 256 319 288 351 320 383 352 */
2844 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
2845 /* 415 384 447 416 479 448 511 480 */
2846 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
2848 /* ownDmaChannels */
2849 /* 31 0 63 32 */
2850 {0x00000000u, 0x0000FF00u},
2852 /* ownQdmaChannels */
2853 /* 31 0 */
2854 {0x00000020u},
2856 /* ownTccs */
2857 /* 31 0 63 32 */
2858 {0x00000000u, 0x0000FF00u},
2860 /* resvdPaRAMSets */
2861 /* 31 0 63 32 95 64 127 96 */
2862 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2863 /* 159 128 191 160 223 192 255 224 */
2864 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2865 /* 287 256 319 288 351 320 383 352 */
2866 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2867 /* 415 384 447 416 479 448 511 480 */
2868 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2870 /* resvdDmaChannels */
2871 /* 31 0 63 32 */
2872 {0x00000000u, 0x00000000u},
2874 /* resvdQdmaChannels */
2875 /* 31 0 */
2876 {0x00000000u},
2878 /* resvdTccs */
2879 /* 31 0 63 32 */
2880 {0x00000000u, 0x00000000u},
2881 },
2883 /* Resources owned/reserved by region 6 */
2884 {
2885 /* ownPaRAMSets */
2886 /* 31 0 63 32 95 64 127 96 */
2887 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2888 /* 159 128 191 160 223 192 255 224 */
2889 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2890 /* 287 256 319 288 351 320 383 352 */
2891 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2892 /* 415 384 447 416 479 448 511 480 */
2893 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
2895 /* ownDmaChannels */
2896 /* 31 0 63 32 */
2897 {0x00000000u, 0x00FF0000u},
2899 /* ownQdmaChannels */
2900 /* 31 0 */
2901 {0x00000040u},
2903 /* ownTccs */
2904 /* 31 0 63 32 */
2905 {0x00000000u, 0x00FF0000u},
2907 /* resvdPaRAMSets */
2908 /* 31 0 63 32 95 64 127 96 */
2909 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2910 /* 159 128 191 160 223 192 255 224 */
2911 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2912 /* 287 256 319 288 351 320 383 352 */
2913 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2914 /* 415 384 447 416 479 448 511 480 */
2915 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2917 /* resvdDmaChannels */
2918 /* 31 0 63 32 */
2919 {0x00000000u, 0x00000000u},
2921 /* resvdQdmaChannels */
2922 /* 31 0 */
2923 {0x00000000u},
2925 /* resvdTccs */
2926 /* 31 0 63 32 */
2927 {0x00000000u, 0x00000000u},
2928 },
2930 /* Resources owned/reserved by region 7 */
2931 {
2932 /* ownPaRAMSets */
2933 /* 31 0 63 32 95 64 127 96 */
2934 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2935 /* 159 128 191 160 223 192 255 224 */
2936 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2937 /* 287 256 319 288 351 320 383 352 */
2938 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2939 /* 415 384 447 416 479 448 511 480 */
2940 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
2942 /* ownDmaChannels */
2943 /* 31 0 63 32 */
2944 {0x00000000u, 0xFF000000u},
2946 /* ownQdmaChannels */
2947 /* 31 0 */
2948 {0x00000080u},
2950 /* ownTccs */
2951 /* 31 0 63 32 */
2952 {0x00000000u, 0xFF000000u},
2954 /* resvdPaRAMSets */
2955 /* 31 0 63 32 95 64 127 96 */
2956 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2957 /* 159 128 191 160 223 192 255 224 */
2958 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2959 /* 287 256 319 288 351 320 383 352 */
2960 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2961 /* 415 384 447 416 479 448 511 480 */
2962 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2964 /* resvdDmaChannels */
2965 /* 31 0 63 32 */
2966 {0x00000000u, 0x00000000u},
2968 /* resvdQdmaChannels */
2969 /* 31 0 */
2970 {0x00000000u},
2972 /* resvdTccs */
2973 /* 31 0 63 32 */
2974 {0x00000000u, 0x00000000u},
2975 },
2976 },
2977 };
2979 /* End of File */