Merged from master, added a15 support for k2l, c66ak2e
[keystone-rtos/edma3_lld.git] / examples / edma3_user_space_driver / evmTCI6630K2L / evmTCI6630K2LSample.c
1 /*
2  * sample_tci6630k2l_cfg.c
3  *
4  * Platform specific EDMA3 hardware related information like number of transfer
5  * controllers, various interrupt ids etc. It is used while interrupts
6  * enabling / disabling. It needs to be ported for different SoCs.
7  *
8  * Copyright (C) 2012-2013 Texas Instruments Incorporated - http://www.ti.com/
9  *
10  *
11  *  Redistribution and use in source and binary forms, with or without
12  *  modification, are permitted provided that the following conditions
13  *  are met:
14  *
15  *    Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  *
18  *    Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in the
20  *    documentation and/or other materials provided with the
21  *    distribution.
22  *
23  *    Neither the name of Texas Instruments Incorporated nor the names of
24  *    its contributors may be used to endorse or promote products derived
25  *    from this software without specific prior written permission.
26  *
27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38  *
39 */
41 #include <ti/sdo/edma3/rm/edma3_rm.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES                     3u
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
47 /* Number of DSPs present in the system */
48 #define NUM_DSPS                                        4u
49 //const unsigned int numDsps = NUM_DSPS;
51 #define CGEM_REG_START                  (0x01800000)
54 //extern cregister volatile unsigned int DNUM;
55 #define DNUM 0
57 #define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
60 /* Determine the processor id by reading DNUM register. */
61 unsigned short determineProcId()
62         {
63         volatile unsigned int *addr;
64         unsigned int core_no;
66     /* Identify the core number */
67     addr = (unsigned int *)(CGEM_REG_START+0x40000);
68     core_no = ((*addr) & 0x000F0000)>>16;
70         return core_no;
71         }
73 signed char*  getGlobalAddr(signed char* addr)
74 {
75     if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
76     {
77         return (addr); /* The address is already a global address */
78     }
80     return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
81 }
82 /** Whether global configuration required for EDMA3 or not.
83  * This configuration should be done only once for the EDMA3 hardware by
84  * any one of the masters (i.e. DSPs).
85  * It can be changed depending on the use-case.
86  */
87 unsigned int gblCfgReqdArray [NUM_DSPS] = {
88                                                                         0,      /* DSP#0 is Master, will do the global init */
89                                                                         1,      /* DSP#1 is Slave, will not do the global init  */
90                                                                         1,      /* DSP#2 is Slave, will not do the global init  */
91                                                                         1,      /* DSP#3 is Slave, will not do the global init  */
92                                                                         };
94 unsigned short isGblConfigRequired(unsigned int dspNum)
95         {
96         return gblCfgReqdArray[dspNum];
97         }
99 /* Semaphore handles */
100 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL};
103 /* Variable which will be used internally for referring number of Event Queues. */
104 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
106 /* Variable which will be used internally for referring number of TCs. */
107 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
109 /**
110  * Variable which will be used internally for referring transfer completion
111  * interrupt. Completion interrupts for all the shadow regions and all the
112  * EDMA3 controllers are captured since it is a multi-DSP platform.
113  */
114 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
115                                                                                                         {
116                                                                                                         38u, 39u, 40u, 41u,
117                                                                                                         42u, 43u, 44u, 45u,
118                                                                                                         },
119                                                                                                         {
120                                                                                                         8u, 9u, 10u, 11u,
121                                                                                                         12u, 13u, 14u, 15u,
122                                                                                                         },
123                                                                                                         {
124                                                                                                         24u, 25u, 26u, 27u,
125                                                                                                         28u, 29u, 30u, 31u,
126                                                                                                         },
127                                                                                                 };
129 /**
130  * Variable which will be used internally for referring channel controller's
131  * error interrupt.
132  */
133 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u};
135 /**
136  * Variable which will be used internally for referring transfer controllers'
137  * error interrupts.
138  */
139 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] =    {
140                                                                                                         {
141                                                                                                         34u, 35u, 0u, 0u,
142                                                                                                         0u, 0u, 0u, 0u,
143                                                                                                         },
144                                                                                                         {
145                                                                                                         2u, 3u, 4u, 5u,
146                                                                                                         0u, 0u, 0u, 0u,
147                                                                                                         },
148                                                                                                         {
149                                                                                                         18u, 19u, 20u, 21u,
150                                                                                                         0u, 0u, 0u, 0u,
151                                                                                                         },
152                                                                                                 };
154 /* Driver Object Initialization Configuration */
155 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
156         {
157                 {
158                 /* EDMA3 INSTANCE# 0 */
159                 /** Total number of DMA Channels supported by the EDMA3 Controller */
160                 64u,
161                 /** Total number of QDMA Channels supported by the EDMA3 Controller */
162                 8u,
163                 /** Total number of TCCs supported by the EDMA3 Controller */
164                 64u,
165                 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
166                 512u,
167                 /** Total number of Event Queues in the EDMA3 Controller */
168                 2u,
169                 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
170                 2u,
171                 /** Number of Regions on this EDMA3 controller */
172                 8u,
174                 /**
175                  * \brief Channel mapping existence
176                  * A value of 0 (No channel mapping) implies that there is fixed association
177                  * for a channel number to a parameter entry number or, in other words,
178                  * PaRAM entry n corresponds to channel n.
179                  */
180                 1u,
182                 /** Existence of memory protection feature */
183                 1u,
185                 /** Global Register Region of CC Registers */
186                 (void *)0x02700000u,
187                 /** Transfer Controller (TC) Registers */
188                 {
189                 (void *)0x02760000u,
190                 (void *)0x02768000u,
191                 (void *)NULL,
192                 (void *)NULL,
193                 (void *)NULL,
194                 (void *)NULL,
195                 (void *)NULL,
196                 (void *)NULL
197                 },
198                 /** Interrupt no. for Transfer Completion */
199                 38u,
200                 /** Interrupt no. for CC Error */
201                 32u,
202                 /** Interrupt no. for TCs Error */
203                 {
204                 34u,
205                 35u,
206                 0u,
207                 0u,
208                 0u,
209                 0u,
210                 0u,
211                 0u,
212                 },
214                 /**
215                  * \brief EDMA3 TC priority setting
216                  *
217                  * User can program the priority of the Event Queues
218                  * at a system-wide level.  This means that the user can set the
219                  * priority of an IO initiated by either of the TCs (Transfer Controllers)
220                  * relative to IO initiated by the other bus masters on the
221                  * device (ARM, DSP, USB, etc)
222                  */
223                 {
224                 0u,
225                 1u,
226                 0u,
227                 0u,
228                 0u,
229                 0u,
230                 0u,
231                 0u
232                 },
233                 /**
234                  * \brief To Configure the Threshold level of number of events
235                  * that can be queued up in the Event queues. EDMA3CC error register
236                  * (CCERR) will indicate whether or not at any instant of time the
237                  * number of events queued up in any of the event queues exceeds
238                  * or equals the threshold/watermark value that is set
239                  * in the queue watermark threshold register (QWMTHRA).
240                  */
241                 {
242                 16u,
243                 16u,
244                 0u,
245                 0u,
246                 0u,
247                 0u,
248                 0u,
249                 0u
250                 },
252                 /**
253                  * \brief To Configure the Default Burst Size (DBS) of TCs.
254                  * An optimally-sized command is defined by the transfer controller
255                  * default burst size (DBS). Different TCs can have different
256                  * DBS values. It is defined in Bytes.
257                  */
258                 {
259                 128u,
260                 128u,
261                 0u,
262                 0u,
263                 0u,
264                 0u,
265                 0u,
266                 0u
267                 },
269                 /**
270                  * \brief Mapping from each DMA channel to a Parameter RAM set,
271                  * if it exists, otherwise of no use.
272                  */
273                 {
274                     EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
275         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
276         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
277         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
278         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
279         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
280         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
281         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
282         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
283         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
284         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
285         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
286         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
287         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
288         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
289         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
290         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
291         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
292         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
293         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
294         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
295         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
296         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
297         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
298         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
299         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
300         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
301         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
302         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
303         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
304         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
305         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
306                 },
308                  /**
309                   * \brief Mapping from each DMA channel to a TCC. This specific
310                   * TCC code will be returned when the transfer is completed
311                   * on the mapped channel.
312                   */
313                 {
314                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
315                 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
316                 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
317                 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
318                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
319                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
320                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
321                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
322                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
323                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
324                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
325                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
326                 },
328                 /**
329                  * \brief Mapping of DMA channels to Hardware Events from
330                  * various peripherals, which use EDMA for data transfer.
331                  * All channels need not be mapped, some can be free also.
332                  */
333                 {
334                 0xFFFFFFFFu,
335                 0x00000000u
336                 }
337                 },
339                 {
340                 /* EDMA3 INSTANCE# 1 */
341                 /** Total number of DMA Channels supported by the EDMA3 Controller */
342                 64u,
343                 /** Total number of QDMA Channels supported by the EDMA3 Controller */
344                 8u,
345                 /** Total number of TCCs supported by the EDMA3 Controller */
346                 64u,
347                 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
348                 512u,
349                 /** Total number of Event Queues in the EDMA3 Controller */
350                 4u,
351                 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
352                 4u,
353                 /** Number of Regions on this EDMA3 controller */
354                 8u,
356                 /**
357                  * \brief Channel mapping existence
358                  * A value of 0 (No channel mapping) implies that there is fixed association
359                  * for a channel number to a parameter entry number or, in other words,
360                  * PaRAM entry n corresponds to channel n.
361                  */
362                 1u,
364                 /** Existence of memory protection feature */
365                 1u,
367                 /** Global Register Region of CC Registers */
368                 (void *)0x02720000u,
369                 /** Transfer Controller (TC) Registers */
370                 {
371                 (void *)0x02770000u,
372                 (void *)0x02778000u,
373                 (void *)0x02780000u,
374                 (void *)0x02788000u,
375                 (void *)NULL,
376                 (void *)NULL,
377                 (void *)NULL,
378                 (void *)NULL
379                 },
380                 /** Interrupt no. for Transfer Completion */
381                 8u,
382                 /** Interrupt no. for CC Error */
383                 0u,
384                 /** Interrupt no. for TCs Error */
385                 {
386                 2u,
387                 3u,
388                 4u,
389                 5u,
390                 0u,
391                 0u,
392                 0u,
393                 0u,
394                 },
396                 /**
397                  * \brief EDMA3 TC priority setting
398                  *
399                  * User can program the priority of the Event Queues
400                  * at a system-wide level.  This means that the user can set the
401                  * priority of an IO initiated by either of the TCs (Transfer Controllers)
402                  * relative to IO initiated by the other bus masters on the
403                  * device (ARM, DSP, USB, etc)
404                  */
405                 {
406                 0u,
407                 1u,
408                 2u,
409                 3u,
410                 0u,
411                 0u,
412                 0u,
413                 0u
414                 },
415                 /**
416                  * \brief To Configure the Threshold level of number of events
417                  * that can be queued up in the Event queues. EDMA3CC error register
418                  * (CCERR) will indicate whether or not at any instant of time the
419                  * number of events queued up in any of the event queues exceeds
420                  * or equals the threshold/watermark value that is set
421                  * in the queue watermark threshold register (QWMTHRA).
422                  */
423                 {
424                 16u,
425                 16u,
426                 16u,
427                 16u,
428                 0u,
429                 0u,
430                 0u,
431                 0u
432                 },
434                 /**
435                  * \brief To Configure the Default Burst Size (DBS) of TCs.
436                  * An optimally-sized command is defined by the transfer controller
437                  * default burst size (DBS). Different TCs can have different
438                  * DBS values. It is defined in Bytes.
439                  */
440                 {
441                 128u,
442                 128u,
443                 128u,
444                 128u,
445                 0u,
446                 0u,
447                 0u,
448                 0u
449                 },
451                 /**
452                  * \brief Mapping from each DMA channel to a Parameter RAM set,
453                  * if it exists, otherwise of no use.
454                  */
455                 {
456                     EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
457         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
458         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
459         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
460         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
461         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
462         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
463         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
464         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
465         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
466         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
467         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
468         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
469         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
470         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
471         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
472         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
473         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
474         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
475         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
476         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
477         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
478         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
479         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
480         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
481         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
482         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
483         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
484         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
485         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
486         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
487         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
488                 },
490                  /**
491                   * \brief Mapping from each DMA channel to a TCC. This specific
492                   * TCC code will be returned when the transfer is completed
493                   * on the mapped channel.
494                   */
495                 {
496                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
497                 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
498                 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
499                 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
500                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
501                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
502                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
503                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
504                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
505                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
506                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
507                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
508                 },
510                 /**
511                  * \brief Mapping of DMA channels to Hardware Events from
512                  * various peripherals, which use EDMA for data transfer.
513                  * All channels need not be mapped, some can be free also.
514                  */
515                 {
516                 0xFFFFFFFFu,
517                 0x00000000u
518                 }
519                 },
521                 {
522                 /* EDMA3 INSTANCE# 2 */
523                 /** Total number of DMA Channels supported by the EDMA3 Controller */
524                 64u,
525                 /** Total number of QDMA Channels supported by the EDMA3 Controller */
526                 8u,
527                 /** Total number of TCCs supported by the EDMA3 Controller */
528                 64u,
529                 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
530                 512u,
531                 /** Total number of Event Queues in the EDMA3 Controller */
532                 4u,
533                 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
534                 4u,
535                 /** Number of Regions on this EDMA3 controller */
536                 8u,
538                 /**
539                  * \brief Channel mapping existence
540                  * A value of 0 (No channel mapping) implies that there is fixed association
541                  * for a channel number to a parameter entry number or, in other words,
542                  * PaRAM entry n corresponds to channel n.
543                  */
544                 1u,
546                 /** Existence of memory protection feature */
547                 1u,
549                 /** Global Register Region of CC Registers */
550                 (void *)0x02740000u,
551                 /** Transfer Controller (TC) Registers */
552                 {
553                 (void *)0x02790000u,
554                 (void *)0x02798000u,
555                 (void *)0x027A0000u,
556                 (void *)0x027A8000u,
557                 (void *)NULL,
558                 (void *)NULL,
559                 (void *)NULL,
560                 (void *)NULL
561                 },
562                 /** Interrupt no. for Transfer Completion */
563                 24u,
564                 /** Interrupt no. for CC Error */
565                 16u,
566                 /** Interrupt no. for TCs Error */
567                 {
568                 18u,
569                 19u,
570                 20u,
571                 21u,
572                 0u,
573                 0u,
574                 0u,
575                 0u,
576                 },
578                 /**
579                  * \brief EDMA3 TC priority setting
580                  *
581                  * User can program the priority of the Event Queues
582                  * at a system-wide level.  This means that the user can set the
583                  * priority of an IO initiated by either of the TCs (Transfer Controllers)
584                  * relative to IO initiated by the other bus masters on the
585                  * device (ARM, DSP, USB, etc)
586                  */
587                 {
588                 0u,
589                 1u,
590                 2u,
591                 3u,
592                 0u,
593                 0u,
594                 0u,
595                 0u
596                 },
597                 /**
598                  * \brief To Configure the Threshold level of number of events
599                  * that can be queued up in the Event queues. EDMA3CC error register
600                  * (CCERR) will indicate whether or not at any instant of time the
601                  * number of events queued up in any of the event queues exceeds
602                  * or equals the threshold/watermark value that is set
603                  * in the queue watermark threshold register (QWMTHRA).
604                  */
605                 {
606                 16u,
607                 16u,
608                 16u,
609                 16u,
610                 0u,
611                 0u,
612                 0u,
613                 0u
614                 },
616                 /**
617                  * \brief To Configure the Default Burst Size (DBS) of TCs.
618                  * An optimally-sized command is defined by the transfer controller
619                  * default burst size (DBS). Different TCs can have different
620                  * DBS values. It is defined in Bytes.
621                  */
622                 {
623                 128u,
624                 128u,
625                 128u,
626                 128u,
627                 0u,
628                 0u,
629                 0u,
630                 0u
631                 },
633                 /**
634                  * \brief Mapping from each DMA channel to a Parameter RAM set,
635                  * if it exists, otherwise of no use.
636                  */
637                 {
638         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
639         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
640         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
641         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
642         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
643         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
644         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
645         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
646         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
647         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
648         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
649         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
650         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
651         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
652         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
653         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
654         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
655         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
656         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
657         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
658         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
659         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
660         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
661         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
662         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
663         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
664         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
665         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
666         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
667         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
668         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
669         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
670                 },
672                  /**
673                   * \brief Mapping from each DMA channel to a TCC. This specific
674                   * TCC code will be returned when the transfer is completed
675                   * on the mapped channel.
676                   */
677                 {
678                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
679                 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
680                 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
681                 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
682                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
683                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
684                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
685                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
686                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
687                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
688                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
689                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
690                 },
692                 /**
693                  * \brief Mapping of DMA channels to Hardware Events from
694                  * various peripherals, which use EDMA for data transfer.
695                  * All channels need not be mapped, some can be free also.
696                  */
697                 {
698                 0xFFFFFFFFu,
699                 0x00000000u
700                 }
701                 },
703         };
705 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
706         {
707                 /* EDMA3 INSTANCE# 0 */
708                 {
709                         /* Resources owned/reserved by region 0 */
710                         {
711                                 /* ownPaRAMSets */
712                                 /* 31     0     63    32     95    64     127   96 */
713                                 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
714                                 /* 159  128     191  160     223  192     255  224 */
715                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
716                                 /* 287  256     319  288     351  320     383  352 */
717                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
718                                 /* 415  384     447  416     479  448     511  480 */
719                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
721                                 /* ownDmaChannels */
722                                 /* 31     0     63    32 */
723                                 {0x000000FFu, 0x00000000u},
725                                 /* ownQdmaChannels */
726                                 /* 31     0 */
727                                 {0x00000001u},
729                                 /* ownTccs */
730                                 /* 31     0     63    32 */
731                                 {0x000000FFu, 0x00000000u},
733                                 /* resvdPaRAMSets */
734                                 /* 31     0     63    32     95    64     127   96 */
735                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
736                                 /* 159  128     191  160     223  192     255  224 */
737                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
738                                 /* 287  256     319  288     351  320     383  352 */
739                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
740                                 /* 415  384     447  416     479  448     511  480 */
741                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
743                                 /* resvdDmaChannels */
744                                 /* 31     0     63    32 */
745                                 {0x00000000u, 0x00000000u},
747                                 /* resvdQdmaChannels */
748                                 /* 31     0 */
749                                 {0x00000000u},
751                                 /* resvdTccs */
752                                 /* 31     0     63    32 */
753                                 {0x00000000u, 0x00000000u},
754                         },
756                 /* Resources owned/reserved by region 1 */
757                         {
758                                 /* ownPaRAMSets */
759                                 /* 31     0     63    32     95    64     127   96 */
760                                 {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
761                                 /* 159  128     191  160     223  192     255  224 */
762                                  0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
763                                 /* 287  256     319  288     351  320     383  352 */
764                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
765                                 /* 415  384     447  416     479  448     511  480 */
766                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
768                                 /* ownDmaChannels */
769                                 /* 31     0     63    32 */
770                                 {0x0000FF00u, 0x00000000u},
772                                 /* ownQdmaChannels */
773                                 /* 31     0 */
774                                 {0x00000002u},
776                                 /* ownTccs */
777                                 /* 31     0     63    32 */
778                                 {0x0000FF00u, 0x00000000u},
780                                 /* resvdPaRAMSets */
781                                 /* 31     0     63    32     95    64     127   96 */
782                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
783                                 /* 159  128     191  160     223  192     255  224 */
784                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
785                                 /* 287  256     319  288     351  320     383  352 */
786                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
787                                 /* 415  384     447  416     479  448     511  480 */
788                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
790                                 /* resvdDmaChannels */
791                                 /* 31     0     63    32 */
792                                 {0x00000000u, 0x00000000u},
794                                 /* resvdQdmaChannels */
795                                 /* 31     0 */
796                                 {0x00000000u},
798                                 /* resvdTccs */
799                                 /* 31     0     63    32 */
800                                 {0x00000000u, 0x00000000u},
801                         },
803                 /* Resources owned/reserved by region 2 */
804                         {
805                                 /* ownPaRAMSets */
806                                 /* 31     0     63    32     95    64     127   96 */
807                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
808                                 /* 159  128     191  160     223  192     255  224 */
809                                  0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
810                                 /* 287  256     319  288     351  320     383  352 */
811                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
812                                 /* 415  384     447  416     479  448     511  480 */
813                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
815                                 /* ownDmaChannels */
816                                 /* 31     0     63    32 */
817                                 {0x00FF0000u, 0x0000000u},
819                                 /* ownQdmaChannels */
820                                 /* 31     0 */
821                                 {0x00000004u},
823                                 /* ownTccs */
824                                 /* 31     0     63    32 */
825                                 {0x00FF0000u, 0x00000000u},
827                                 /* resvdPaRAMSets */
828                                 /* 31     0     63    32     95    64     127   96 */
829                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
830                                 /* 159  128     191  160     223  192     255  224 */
831                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
832                                 /* 287  256     319  288     351  320     383  352 */
833                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
834                                 /* 415  384     447  416     479  448     511  480 */
835                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
837                                 /* resvdDmaChannels */
838                                 /* 31     0     63    32 */
839                                 {0x00000000u, 0x00000000u},
841                                 /* resvdQdmaChannels */
842                                 /* 31     0 */
843                                 {0x00000000u},
845                                 /* resvdTccs */
846                                 /* 31     0     63    32 */
847                                 {0x00000000u, 0x00000000u},
848                         },
850                 /* Resources owned/reserved by region 3 */
851                         {
852                                 /* ownPaRAMSets */
853                                 /* 31     0     63    32     95    64     127   96 */
854                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
855                                 /* 159  128     191  160     223  192     255  224 */
856                                  0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
857                                 /* 287  256     319  288     351  320     383  352 */
858                                  0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
859                                 /* 415  384     447  416     479  448     511  480 */
860                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
862                                 /* ownDmaChannels */
863                                 /* 31     0     63    32 */
864                                 {0xFF000000u, 0x00000000u},
866                                 /* ownQdmaChannels */
867                                 /* 31     0 */
868                                 {0x00000008u},
870                                 /* ownTccs */
871                                 /* 31     0     63    32 */
872                                 {0xFF000000u, 0x00000000u},
874                                 /* resvdPaRAMSets */
875                                 /* 31     0     63    32     95    64     127   96 */
876                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
877                                 /* 159  128     191  160     223  192     255  224 */
878                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
879                                 /* 287  256     319  288     351  320     383  352 */
880                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
881                                 /* 415  384     447  416     479  448     511  480 */
882                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
884                                 /* resvdDmaChannels */
885                                 /* 31     0     63    32 */
886                                 {0x00000000u, 0x00000000u},
888                                 /* resvdQdmaChannels */
889                                 /* 31     0 */
890                                 {0x00000000u},
892                                 /* resvdTccs */
893                                 /* 31     0     63    32 */
894                                 {0x00000000u, 0x00000000u},
895                         },
897                 /* Resources owned/reserved by region 4 */
898                         {
899                                 /* ownPaRAMSets */
900                                 /* 31     0     63    32     95    64     127   96 */
901                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
902                                 /* 159  128     191  160     223  192     255  224 */
903                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
904                                 /* 287  256     319  288     351  320     383  352 */
905                                  0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
906                                 /* 415  384     447  416     479  448     511  480 */
907                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
909                                 /* ownDmaChannels */
910                                 /* 31     0     63    32 */
911                                 {0x00000000u, 0x000000FFu},
913                                 /* ownQdmaChannels */
914                                 /* 31     0 */
915                                 {0x00000010u},
917                                 /* ownTccs */
918                                 /* 31     0     63    32 */
919                                 {0x00000000u, 0x000000FFu},
921                                 /* resvdPaRAMSets */
922                                 /* 31     0     63    32     95    64     127   96 */
923                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
924                                 /* 159  128     191  160     223  192     255  224 */
925                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
926                                 /* 287  256     319  288     351  320     383  352 */
927                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
928                                 /* 415  384     447  416     479  448     511  480 */
929                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
931                                 /* resvdDmaChannels */
932                                 /* 31     0     63    32 */
933                                 {0x00000000u, 0x00000000u},
935                                 /* resvdQdmaChannels */
936                                 /* 31     0 */
937                                 {0x00000000u},
939                                 /* resvdTccs */
940                                 /* 31     0     63    32 */
941                                 {0x00000000u, 0x00000000u},
942                         },
944                 /* Resources owned/reserved by region 5 */
945                         {
946                                 /* ownPaRAMSets */
947                                 /* 31     0     63    32     95    64     127   96 */
948                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
949                                 /* 159  128     191  160     223  192     255  224 */
950                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
951                                 /* 287  256     319  288     351  320     383  352 */
952                                  0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
953                                 /* 415  384     447  416     479  448     511  480 */
954                                  0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
956                                 /* ownDmaChannels */
957                                 /* 31     0     63    32 */
958                                 {0x00000000u, 0x0000FF00u},
960                                 /* ownQdmaChannels */
961                                 /* 31     0 */
962                                 {0x00000020u},
964                                 /* ownTccs */
965                                 /* 31     0     63    32 */
966                                 {0x00000000u, 0x0000FF00u},
968                                 /* resvdPaRAMSets */
969                                 /* 31     0     63    32     95    64     127   96 */
970                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
971                                 /* 159  128     191  160     223  192     255  224 */
972                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
973                                 /* 287  256     319  288     351  320     383  352 */
974                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
975                                 /* 415  384     447  416     479  448     511  480 */
976                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
978                                 /* resvdDmaChannels */
979                                 /* 31     0     63    32 */
980                                 {0x00000000u, 0x00000000u},
982                                 /* resvdQdmaChannels */
983                                 /* 31     0 */
984                                 {0x00000000u},
986                                 /* resvdTccs */
987                                 /* 31     0     63    32 */
988                                 {0x00000000u, 0x00000000u},
989                         },
991                 /* Resources owned/reserved by region 6 */
992                         {
993                                 /* ownPaRAMSets */
994                                 /* 31     0     63    32     95    64     127   96 */
995                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
996                                 /* 159  128     191  160     223  192     255  224 */
997                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
998                                 /* 287  256     319  288     351  320     383  352 */
999                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1000                                 /* 415  384     447  416     479  448     511  480 */
1001                                  0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
1003                                 /* ownDmaChannels */
1004                                 /* 31     0     63    32 */
1005                                 {0x00000000u, 0x00FF0000u},
1007                                 /* ownQdmaChannels */
1008                                 /* 31     0 */
1009                                 {0x00000040u},
1011                                 /* ownTccs */
1012                                 /* 31     0     63    32 */
1013                                 {0x00000000u, 0x00FF0000u},
1015                                 /* resvdPaRAMSets */
1016                                 /* 31     0     63    32     95    64     127   96 */
1017                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1018                                 /* 159  128     191  160     223  192     255  224 */
1019                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1020                                 /* 287  256     319  288     351  320     383  352 */
1021                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1022                                 /* 415  384     447  416     479  448     511  480 */
1023                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1025                                 /* resvdDmaChannels */
1026                                 /* 31     0     63    32 */
1027                                 {0x00000000u, 0x00000000u},
1029                                 /* resvdQdmaChannels */
1030                                 /* 31     0 */
1031                                 {0x00000000u},
1033                                 /* resvdTccs */
1034                                 /* 31     0     63    32 */
1035                                 {0x00000000u, 0x00000000u},
1036                         },
1038                 /* Resources owned/reserved by region 7 */
1039                         {
1040                                 /* ownPaRAMSets */
1041                                 /* 31     0     63    32     95    64     127   96 */
1042                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1043                                 /* 159  128     191  160     223  192     255  224 */
1044                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1045                                 /* 287  256     319  288     351  320     383  352 */
1046                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1047                                 /* 415  384     447  416     479  448     511  480 */
1048                                  0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
1050                                 /* ownDmaChannels */
1051                                 /* 31     0     63    32 */
1052                                 {0x00000000u, 0xFF000000u},
1054                                 /* ownQdmaChannels */
1055                                 /* 31     0 */
1056                                 {0x00000080u},
1058                                 /* ownTccs */
1059                                 /* 31     0     63    32 */
1060                                 {0x00000000u, 0xFF000000u},
1062                                 /* resvdPaRAMSets */
1063                                 /* 31     0     63    32     95    64     127   96 */
1064                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1065                                 /* 159  128     191  160     223  192     255  224 */
1066                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1067                                 /* 287  256     319  288     351  320     383  352 */
1068                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1069                                 /* 415  384     447  416     479  448     511  480 */
1070                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1072                                 /* resvdDmaChannels */
1073                                 /* 31     0     63    32 */
1074                                 {0x00000000u, 0x00000000u},
1076                                 /* resvdQdmaChannels */
1077                                 /* 31     0 */
1078                                 {0x00000000u},
1080                                 /* resvdTccs */
1081                                 /* 31     0     63    32 */
1082                                 {0x00000000u, 0x00000000u},
1083                         },
1084                 },
1086                 /* EDMA3 INSTANCE# 1 */
1087                 {
1088                         /* Resources owned/reserved by region 0 */
1089                         {
1090                                 /* ownPaRAMSets */
1091                                 /* 31     0     63    32     95    64     127   96 */
1092                                 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
1093                                 /* 159  128     191  160     223  192     255  224 */
1094                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1095                                 /* 287  256     319  288     351  320     383  352 */
1096                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1097                                 /* 415  384     447  416     479  448     511  480 */
1098                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1100                                 /* ownDmaChannels */
1101                                 /* 31     0     63    32 */
1102                                 {0x000000FFu, 0x00000000u},
1104                                 /* ownQdmaChannels */
1105                                 /* 31     0 */
1106                                 {0x00000001u},
1108                                 /* ownTccs */
1109                                 /* 31     0     63    32 */
1110                                 {0x000000FFu, 0x00000000u},
1112                                 /* resvdPaRAMSets */
1113                                 /* 31     0     63    32     95    64     127   96 */
1114                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1115                                 /* 159  128     191  160     223  192     255  224 */
1116                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1117                                 /* 287  256     319  288     351  320     383  352 */
1118                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1119                                 /* 415  384     447  416     479  448     511  480 */
1120                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1122                                 /* resvdDmaChannels */
1123                                 /* 31     0     63    32 */
1124                                 {0x00000000u, 0x00000000u},
1126                                 /* resvdQdmaChannels */
1127                                 /* 31     0 */
1128                                 {0x00000000u},
1130                                 /* resvdTccs */
1131                                 /* 31     0     63    32 */
1132                                 {0x00000000u, 0x00000000u},
1133                         },
1135                 /* Resources owned/reserved by region 1 */
1136                         {
1137                                 /* ownPaRAMSets */
1138                                 /* 31     0     63    32     95    64     127   96 */
1139                                 {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
1140                                 /* 159  128     191  160     223  192     255  224 */
1141                                  0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1142                                 /* 287  256     319  288     351  320     383  352 */
1143                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1144                                 /* 415  384     447  416     479  448     511  480 */
1145                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1147                                 /* ownDmaChannels */
1148                                 /* 31     0     63    32 */
1149                                 {0x0000FF00u, 0x00000000u},
1151                                 /* ownQdmaChannels */
1152                                 /* 31     0 */
1153                                 {0x00000002u},
1155                                 /* ownTccs */
1156                                 /* 31     0     63    32 */
1157                                 {0x0000FF00u, 0x00000000u},
1159                                 /* resvdPaRAMSets */
1160                                 /* 31     0     63    32     95    64     127   96 */
1161                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1162                                 /* 159  128     191  160     223  192     255  224 */
1163                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1164                                 /* 287  256     319  288     351  320     383  352 */
1165                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1166                                 /* 415  384     447  416     479  448     511  480 */
1167                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1169                                 /* resvdDmaChannels */
1170                                 /* 31     0     63    32 */
1171                                 {0x00000000u, 0x00000000u},
1173                                 /* resvdQdmaChannels */
1174                                 /* 31     0 */
1175                                 {0x00000000u},
1177                                 /* resvdTccs */
1178                                 /* 31     0     63    32 */
1179                                 {0x00000000u, 0x00000000u},
1180                         },
1182                 /* Resources owned/reserved by region 2 */
1183                         {
1184                                 /* ownPaRAMSets */
1185                                 /* 31     0     63    32     95    64     127   96 */
1186                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1187                                 /* 159  128     191  160     223  192     255  224 */
1188                                  0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
1189                                 /* 287  256     319  288     351  320     383  352 */
1190                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1191                                 /* 415  384     447  416     479  448     511  480 */
1192                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1194                                 /* ownDmaChannels */
1195                                 /* 31     0     63    32 */
1196                                 {0x00FF0000u, 0x0000000u},
1198                                 /* ownQdmaChannels */
1199                                 /* 31     0 */
1200                                 {0x00000004u},
1202                                 /* ownTccs */
1203                                 /* 31     0     63    32 */
1204                                 {0x00FF0000u, 0x00000000u},
1206                                 /* resvdPaRAMSets */
1207                                 /* 31     0     63    32     95    64     127   96 */
1208                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1209                                 /* 159  128     191  160     223  192     255  224 */
1210                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1211                                 /* 287  256     319  288     351  320     383  352 */
1212                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1213                                 /* 415  384     447  416     479  448     511  480 */
1214                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1216                                 /* resvdDmaChannels */
1217                                 /* 31     0     63    32 */
1218                                 {0x00000000u, 0x00000000u},
1220                                 /* resvdQdmaChannels */
1221                                 /* 31     0 */
1222                                 {0x00000000u},
1224                                 /* resvdTccs */
1225                                 /* 31     0     63    32 */
1226                                 {0x00000000u, 0x00000000u},
1227                         },
1229                 /* Resources owned/reserved by region 3 */
1230                         {
1231                                 /* ownPaRAMSets */
1232                                 /* 31     0     63    32     95    64     127   96 */
1233                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1234                                 /* 159  128     191  160     223  192     255  224 */
1235                                  0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
1236                                 /* 287  256     319  288     351  320     383  352 */
1237                                  0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1238                                 /* 415  384     447  416     479  448     511  480 */
1239                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1241                                 /* ownDmaChannels */
1242                                 /* 31     0     63    32 */
1243                                 {0xFF000000u, 0x00000000u},
1245                                 /* ownQdmaChannels */
1246                                 /* 31     0 */
1247                                 {0x00000008u},
1249                                 /* ownTccs */
1250                                 /* 31     0     63    32 */
1251                                 {0xFF000000u, 0x00000000u},
1253                                 /* resvdPaRAMSets */
1254                                 /* 31     0     63    32     95    64     127   96 */
1255                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1256                                 /* 159  128     191  160     223  192     255  224 */
1257                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1258                                 /* 287  256     319  288     351  320     383  352 */
1259                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1260                                 /* 415  384     447  416     479  448     511  480 */
1261                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1263                                 /* resvdDmaChannels */
1264                                 /* 31     0     63    32 */
1265                                 {0x00000000u, 0x00000000u},
1267                                 /* resvdQdmaChannels */
1268                                 /* 31     0 */
1269                                 {0x00000000u},
1271                                 /* resvdTccs */
1272                                 /* 31     0     63    32 */
1273                                 {0x00000000u, 0x00000000u},
1274                         },
1276                 /* Resources owned/reserved by region 4 */
1277                         {
1278                                 /* ownPaRAMSets */
1279                                 /* 31     0     63    32     95    64     127   96 */
1280                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1281                                 /* 159  128     191  160     223  192     255  224 */
1282                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1283                                 /* 287  256     319  288     351  320     383  352 */
1284                                  0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
1285                                 /* 415  384     447  416     479  448     511  480 */
1286                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1288                                 /* ownDmaChannels */
1289                                 /* 31     0     63    32 */
1290                                 {0x00000000u, 0x000000FFu},
1292                                 /* ownQdmaChannels */
1293                                 /* 31     0 */
1294                                 {0x00000010u},
1296                                 /* ownTccs */
1297                                 /* 31     0     63    32 */
1298                                 {0x00000000u, 0x000000FFu},
1300                                 /* resvdPaRAMSets */
1301                                 /* 31     0     63    32     95    64     127   96 */
1302                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1303                                 /* 159  128     191  160     223  192     255  224 */
1304                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1305                                 /* 287  256     319  288     351  320     383  352 */
1306                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1307                                 /* 415  384     447  416     479  448     511  480 */
1308                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1310                                 /* resvdDmaChannels */
1311                                 /* 31     0     63    32 */
1312                                 {0x00000000u, 0x00000000u},
1314                                 /* resvdQdmaChannels */
1315                                 /* 31     0 */
1316                                 {0x00000000u},
1318                                 /* resvdTccs */
1319                                 /* 31     0     63    32 */
1320                                 {0x00000000u, 0x00000000u},
1321                         },
1323                 /* Resources owned/reserved by region 5 */
1324                         {
1325                                 /* ownPaRAMSets */
1326                                 /* 31     0     63    32     95    64     127   96 */
1327                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1328                                 /* 159  128     191  160     223  192     255  224 */
1329                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1330                                 /* 287  256     319  288     351  320     383  352 */
1331                                  0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
1332                                 /* 415  384     447  416     479  448     511  480 */
1333                                  0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
1335                                 /* ownDmaChannels */
1336                                 /* 31     0     63    32 */
1337                                 {0x00000000u, 0x0000FF00u},
1339                                 /* ownQdmaChannels */
1340                                 /* 31     0 */
1341                                 {0x00000020u},
1343                                 /* ownTccs */
1344                                 /* 31     0     63    32 */
1345                                 {0x00000000u, 0x0000FF00u},
1347                                 /* resvdPaRAMSets */
1348                                 /* 31     0     63    32     95    64     127   96 */
1349                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1350                                 /* 159  128     191  160     223  192     255  224 */
1351                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1352                                 /* 287  256     319  288     351  320     383  352 */
1353                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1354                                 /* 415  384     447  416     479  448     511  480 */
1355                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1357                                 /* resvdDmaChannels */
1358                                 /* 31     0     63    32 */
1359                                 {0x00000000u, 0x00000000u},
1361                                 /* resvdQdmaChannels */
1362                                 /* 31     0 */
1363                                 {0x00000000u},
1365                                 /* resvdTccs */
1366                                 /* 31     0     63    32 */
1367                                 {0x00000000u, 0x00000000u},
1368                         },
1370                 /* Resources owned/reserved by region 6 */
1371                         {
1372                                 /* ownPaRAMSets */
1373                                 /* 31     0     63    32     95    64     127   96 */
1374                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1375                                 /* 159  128     191  160     223  192     255  224 */
1376                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1377                                 /* 287  256     319  288     351  320     383  352 */
1378                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1379                                 /* 415  384     447  416     479  448     511  480 */
1380                                  0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
1382                                 /* ownDmaChannels */
1383                                 /* 31     0     63    32 */
1384                                 {0x00000000u, 0x00FF0000u},
1386                                 /* ownQdmaChannels */
1387                                 /* 31     0 */
1388                                 {0x00000040u},
1390                                 /* ownTccs */
1391                                 /* 31     0     63    32 */
1392                                 {0x00000000u, 0x00FF0000u},
1394                                 /* resvdPaRAMSets */
1395                                 /* 31     0     63    32     95    64     127   96 */
1396                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1397                                 /* 159  128     191  160     223  192     255  224 */
1398                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1399                                 /* 287  256     319  288     351  320     383  352 */
1400                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1401                                 /* 415  384     447  416     479  448     511  480 */
1402                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1404                                 /* resvdDmaChannels */
1405                                 /* 31     0     63    32 */
1406                                 {0x00000000u, 0x00000000u},
1408                                 /* resvdQdmaChannels */
1409                                 /* 31     0 */
1410                                 {0x00000000u},
1412                                 /* resvdTccs */
1413                                 /* 31     0     63    32 */
1414                                 {0x00000000u, 0x00000000u},
1415                         },
1417                 /* Resources owned/reserved by region 7 */
1418                         {
1419                                 /* ownPaRAMSets */
1420                                 /* 31     0     63    32     95    64     127   96 */
1421                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1422                                 /* 159  128     191  160     223  192     255  224 */
1423                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1424                                 /* 287  256     319  288     351  320     383  352 */
1425                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1426                                 /* 415  384     447  416     479  448     511  480 */
1427                                  0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
1429                                 /* ownDmaChannels */
1430                                 /* 31     0     63    32 */
1431                                 {0x00000000u, 0xFF000000u},
1433                                 /* ownQdmaChannels */
1434                                 /* 31     0 */
1435                                 {0x00000080u},
1437                                 /* ownTccs */
1438                                 /* 31     0     63    32 */
1439                                 {0x00000000u, 0xFF000000u},
1441                                 /* resvdPaRAMSets */
1442                                 /* 31     0     63    32     95    64     127   96 */
1443                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1444                                 /* 159  128     191  160     223  192     255  224 */
1445                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1446                                 /* 287  256     319  288     351  320     383  352 */
1447                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1448                                 /* 415  384     447  416     479  448     511  480 */
1449                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1451                                 /* resvdDmaChannels */
1452                                 /* 31     0     63    32 */
1453                                 {0x00000000u, 0x00000000u},
1455                                 /* resvdQdmaChannels */
1456                                 /* 31     0 */
1457                                 {0x00000000u},
1459                                 /* resvdTccs */
1460                                 /* 31     0     63    32 */
1461                                 {0x00000000u, 0x00000000u},
1462                         },
1463                 },
1465                 /* EDMA3 INSTANCE# 2 */
1466                 {
1467                         /* Resources owned/reserved by region 0 */
1468                         {
1469                                 /* ownPaRAMSets */
1470                                 /* 31     0     63    32     95    64     127   96 */
1471                                 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
1472                                 /* 159  128     191  160     223  192     255  224 */
1473                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1474                                 /* 287  256     319  288     351  320     383  352 */
1475                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1476                                 /* 415  384     447  416     479  448     511  480 */
1477                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1479                                 /* ownDmaChannels */
1480                                 /* 31     0     63    32 */
1481                                 {0x000000FFu, 0x00000000u},
1483                                 /* ownQdmaChannels */
1484                                 /* 31     0 */
1485                                 {0x00000001u},
1487                                 /* ownTccs */
1488                                 /* 31     0     63    32 */
1489                                 {0x000000FFu, 0x00000000u},
1491                                 /* resvdPaRAMSets */
1492                                 /* 31     0     63    32     95    64     127   96 */
1493                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1494                                 /* 159  128     191  160     223  192     255  224 */
1495                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1496                                 /* 287  256     319  288     351  320     383  352 */
1497                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1498                                 /* 415  384     447  416     479  448     511  480 */
1499                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1501                                 /* resvdDmaChannels */
1502                                 /* 31     0     63    32 */
1503                                 {0x00000000u, 0x00000000u},
1505                                 /* resvdQdmaChannels */
1506                                 /* 31     0 */
1507                                 {0x00000000u},
1509                                 /* resvdTccs */
1510                                 /* 31     0     63    32 */
1511                                 {0x00000000u, 0x00000000u},
1512                         },
1514                 /* Resources owned/reserved by region 1 */
1515                         {
1516                                 /* ownPaRAMSets */
1517                                 /* 31     0     63    32     95    64     127   96 */
1518                                 {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
1519                                 /* 159  128     191  160     223  192     255  224 */
1520                                  0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1521                                 /* 287  256     319  288     351  320     383  352 */
1522                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1523                                 /* 415  384     447  416     479  448     511  480 */
1524                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1526                                 /* ownDmaChannels */
1527                                 /* 31     0     63    32 */
1528                                 {0x0000FF00u, 0x00000000u},
1530                                 /* ownQdmaChannels */
1531                                 /* 31     0 */
1532                                 {0x00000002u},
1534                                 /* ownTccs */
1535                                 /* 31     0     63    32 */
1536                                 {0x0000FF00u, 0x00000000u},
1538                                 /* resvdPaRAMSets */
1539                                 /* 31     0     63    32     95    64     127   96 */
1540                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1541                                 /* 159  128     191  160     223  192     255  224 */
1542                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1543                                 /* 287  256     319  288     351  320     383  352 */
1544                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1545                                 /* 415  384     447  416     479  448     511  480 */
1546                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1548                                 /* resvdDmaChannels */
1549                                 /* 31     0     63    32 */
1550                                 {0x00000000u, 0x00000000u},
1552                                 /* resvdQdmaChannels */
1553                                 /* 31     0 */
1554                                 {0x00000000u},
1556                                 /* resvdTccs */
1557                                 /* 31     0     63    32 */
1558                                 {0x00000000u, 0x00000000u},
1559                         },
1561                 /* Resources owned/reserved by region 2 */
1562                         {
1563                                 /* ownPaRAMSets */
1564                                 /* 31     0     63    32     95    64     127   96 */
1565                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1566                                 /* 159  128     191  160     223  192     255  224 */
1567                                  0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
1568                                 /* 287  256     319  288     351  320     383  352 */
1569                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1570                                 /* 415  384     447  416     479  448     511  480 */
1571                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1573                                 /* ownDmaChannels */
1574                                 /* 31     0     63    32 */
1575                                 {0x00FF0000u, 0x0000000u},
1577                                 /* ownQdmaChannels */
1578                                 /* 31     0 */
1579                                 {0x00000004u},
1581                                 /* ownTccs */
1582                                 /* 31     0     63    32 */
1583                                 {0x00FF0000u, 0x00000000u},
1585                                 /* resvdPaRAMSets */
1586                                 /* 31     0     63    32     95    64     127   96 */
1587                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1588                                 /* 159  128     191  160     223  192     255  224 */
1589                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1590                                 /* 287  256     319  288     351  320     383  352 */
1591                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1592                                 /* 415  384     447  416     479  448     511  480 */
1593                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1595                                 /* resvdDmaChannels */
1596                                 /* 31     0     63    32 */
1597                                 {0x00000000u, 0x00000000u},
1599                                 /* resvdQdmaChannels */
1600                                 /* 31     0 */
1601                                 {0x00000000u},
1603                                 /* resvdTccs */
1604                                 /* 31     0     63    32 */
1605                                 {0x00000000u, 0x00000000u},
1606                         },
1608                 /* Resources owned/reserved by region 3 */
1609                         {
1610                                 /* ownPaRAMSets */
1611                                 /* 31     0     63    32     95    64     127   96 */
1612                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1613                                 /* 159  128     191  160     223  192     255  224 */
1614                                  0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
1615                                 /* 287  256     319  288     351  320     383  352 */
1616                                  0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1617                                 /* 415  384     447  416     479  448     511  480 */
1618                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1620                                 /* ownDmaChannels */
1621                                 /* 31     0     63    32 */
1622                                 {0xFF000000u, 0x00000000u},
1624                                 /* ownQdmaChannels */
1625                                 /* 31     0 */
1626                                 {0x00000008u},
1628                                 /* ownTccs */
1629                                 /* 31     0     63    32 */
1630                                 {0xFF000000u, 0x00000000u},
1632                                 /* resvdPaRAMSets */
1633                                 /* 31     0     63    32     95    64     127   96 */
1634                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1635                                 /* 159  128     191  160     223  192     255  224 */
1636                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1637                                 /* 287  256     319  288     351  320     383  352 */
1638                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1639                                 /* 415  384     447  416     479  448     511  480 */
1640                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1642                                 /* resvdDmaChannels */
1643                                 /* 31     0     63    32 */
1644                                 {0x00000000u, 0x00000000u},
1646                                 /* resvdQdmaChannels */
1647                                 /* 31     0 */
1648                                 {0x00000000u},
1650                                 /* resvdTccs */
1651                                 /* 31     0     63    32 */
1652                                 {0x00000000u, 0x00000000u},
1653                         },
1655                 /* Resources owned/reserved by region 4 */
1656                         {
1657                                 /* ownPaRAMSets */
1658                                 /* 31     0     63    32     95    64     127   96 */
1659                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1660                                 /* 159  128     191  160     223  192     255  224 */
1661                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1662                                 /* 287  256     319  288     351  320     383  352 */
1663                                  0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
1664                                 /* 415  384     447  416     479  448     511  480 */
1665                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1667                                 /* ownDmaChannels */
1668                                 /* 31     0     63    32 */
1669                                 {0x00000000u, 0x000000FFu},
1671                                 /* ownQdmaChannels */
1672                                 /* 31     0 */
1673                                 {0x00000010u},
1675                                 /* ownTccs */
1676                                 /* 31     0     63    32 */
1677                                 {0x00000000u, 0x000000FFu},
1679                                 /* resvdPaRAMSets */
1680                                 /* 31     0     63    32     95    64     127   96 */
1681                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1682                                 /* 159  128     191  160     223  192     255  224 */
1683                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1684                                 /* 287  256     319  288     351  320     383  352 */
1685                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1686                                 /* 415  384     447  416     479  448     511  480 */
1687                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1689                                 /* resvdDmaChannels */
1690                                 /* 31     0     63    32 */
1691                                 {0x00000000u, 0x00000000u},
1693                                 /* resvdQdmaChannels */
1694                                 /* 31     0 */
1695                                 {0x00000000u},
1697                                 /* resvdTccs */
1698                                 /* 31     0     63    32 */
1699                                 {0x00000000u, 0x00000000u},
1700                         },
1702                 /* Resources owned/reserved by region 5 */
1703                         {
1704                                 /* ownPaRAMSets */
1705                                 /* 31     0     63    32     95    64     127   96 */
1706                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1707                                 /* 159  128     191  160     223  192     255  224 */
1708                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1709                                 /* 287  256     319  288     351  320     383  352 */
1710                                  0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
1711                                 /* 415  384     447  416     479  448     511  480 */
1712                                  0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
1714                                 /* ownDmaChannels */
1715                                 /* 31     0     63    32 */
1716                                 {0x00000000u, 0x0000FF00u},
1718                                 /* ownQdmaChannels */
1719                                 /* 31     0 */
1720                                 {0x00000020u},
1722                                 /* ownTccs */
1723                                 /* 31     0     63    32 */
1724                                 {0x00000000u, 0x0000FF00u},
1726                                 /* resvdPaRAMSets */
1727                                 /* 31     0     63    32     95    64     127   96 */
1728                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1729                                 /* 159  128     191  160     223  192     255  224 */
1730                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1731                                 /* 287  256     319  288     351  320     383  352 */
1732                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1733                                 /* 415  384     447  416     479  448     511  480 */
1734                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1736                                 /* resvdDmaChannels */
1737                                 /* 31     0     63    32 */
1738                                 {0x00000000u, 0x00000000u},
1740                                 /* resvdQdmaChannels */
1741                                 /* 31     0 */
1742                                 {0x00000000u},
1744                                 /* resvdTccs */
1745                                 /* 31     0     63    32 */
1746                                 {0x00000000u, 0x00000000u},
1747                         },
1749                 /* Resources owned/reserved by region 6 */
1750                         {
1751                                 /* ownPaRAMSets */
1752                                 /* 31     0     63    32     95    64     127   96 */
1753                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1754                                 /* 159  128     191  160     223  192     255  224 */
1755                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1756                                 /* 287  256     319  288     351  320     383  352 */
1757                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1758                                 /* 415  384     447  416     479  448     511  480 */
1759                                  0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
1761                                 /* ownDmaChannels */
1762                                 /* 31     0     63    32 */
1763                                 {0x00000000u, 0x00FF0000u},
1765                                 /* ownQdmaChannels */
1766                                 /* 31     0 */
1767                                 {0x00000040u},
1769                                 /* ownTccs */
1770                                 /* 31     0     63    32 */
1771                                 {0x00000000u, 0x00FF0000u},
1773                                 /* resvdPaRAMSets */
1774                                 /* 31     0     63    32     95    64     127   96 */
1775                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1776                                 /* 159  128     191  160     223  192     255  224 */
1777                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1778                                 /* 287  256     319  288     351  320     383  352 */
1779                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1780                                 /* 415  384     447  416     479  448     511  480 */
1781                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1783                                 /* resvdDmaChannels */
1784                                 /* 31     0     63    32 */
1785                                 {0x00000000u, 0x00000000u},
1787                                 /* resvdQdmaChannels */
1788                                 /* 31     0 */
1789                                 {0x00000000u},
1791                                 /* resvdTccs */
1792                                 /* 31     0     63    32 */
1793                                 {0x00000000u, 0x00000000u},
1794                         },
1796                 /* Resources owned/reserved by region 7 */
1797                         {
1798                                 /* ownPaRAMSets */
1799                                 /* 31     0     63    32     95    64     127   96 */
1800                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1801                                 /* 159  128     191  160     223  192     255  224 */
1802                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1803                                 /* 287  256     319  288     351  320     383  352 */
1804                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1805                                 /* 415  384     447  416     479  448     511  480 */
1806                                  0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
1808                                 /* ownDmaChannels */
1809                                 /* 31     0     63    32 */
1810                                 {0x00000000u, 0xFF000000u},
1812                                 /* ownQdmaChannels */
1813                                 /* 31     0 */
1814                                 {0x00000080u},
1816                                 /* ownTccs */
1817                                 /* 31     0     63    32 */
1818                                 {0x00000000u, 0xFF000000u},
1820                                 /* resvdPaRAMSets */
1821                                 /* 31     0     63    32     95    64     127   96 */
1822                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1823                                 /* 159  128     191  160     223  192     255  224 */
1824                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1825                                 /* 287  256     319  288     351  320     383  352 */
1826                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1827                                 /* 415  384     447  416     479  448     511  480 */
1828                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1830                                 /* resvdDmaChannels */
1831                                 /* 31     0     63    32 */
1832                                 {0x00000000u, 0x00000000u},
1834                                 /* resvdQdmaChannels */
1835                                 /* 31     0 */
1836                                 {0x00000000u},
1838                                 /* resvdTccs */
1839                                 /* 31     0     63    32 */
1840                                 {0x00000000u, 0x00000000u},
1841                         },
1842                 },
1843         };
1845 /* End of File */