Merge pull request #12 in PROCESSOR-SDK/edma3_lld from PRSDK-3125 to rtos-next
[keystone-rtos/edma3_lld.git] / examples / edma3_user_space_driver / evmTCI6638K2K / evmTCI6638K2KSample.c
1 /*
2  * sample_tci6638k2k_cfg.c
3  *
4  * Platform specific EDMA3 hardware related information like number of transfer
5  * controllers, various interrupt ids etc. It is used while interrupts
6  * enabling / disabling. It needs to be ported for different SoCs.
7  *
8  * Copyright (C) 2012-2013 Texas Instruments Incorporated - http://www.ti.com/
9  *
10  *
11  *  Redistribution and use in source and binary forms, with or without
12  *  modification, are permitted provided that the following conditions
13  *  are met:
14  *
15  *    Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  *
18  *    Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in the
20  *    documentation and/or other materials provided with the
21  *    distribution.
22  *
23  *    Neither the name of Texas Instruments Incorporated nor the names of
24  *    its contributors may be used to endorse or promote products derived
25  *    from this software without specific prior written permission.
26  *
27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38  *
39 */
41 #include <ti/sdo/edma3/rm/edma3_rm.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES                     5u
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
47 /* Number of DSPs present in the system */
48 #define NUM_DSPS                                        8u
49 //const unsigned int numDsps = NUM_DSPS;
51 #define CGEM_REG_START                  (0x01800000)
54 //extern cregister volatile unsigned int DNUM;
55 #define DNUM 0
57 #define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
60 /* Determine the processor id by reading DNUM register. */
61 unsigned short determineProcId()
62         {
63         volatile unsigned int *addr;
64         unsigned int core_no;
66     /* Identify the core number */
67     addr = (unsigned int *)(CGEM_REG_START+0x40000);
68     core_no = ((*addr) & 0x000F0000)>>16;
70         return core_no;
71         }
73 signed char*  getGlobalAddr(signed char* addr)
74 {
75     if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
76     {
77         return (addr); /* The address is already a global address */
78     }
80     return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
81 }
82 /** Whether global configuration required for EDMA3 or not.
83  * This configuration should be done only once for the EDMA3 hardware by
84  * any one of the masters (i.e. DSPs).
85  * It can be changed depending on the use-case.
86  */
87 unsigned int gblCfgReqdArray [NUM_DSPS] = {
88                                                                         0,      /* DSP#0 is Master, will do the global init */
89                                                                         1,      /* DSP#1 is Slave, will not do the global init  */
90                                                                         1,      /* DSP#2 is Slave, will not do the global init  */
91                                                                         1,      /* DSP#3 is Slave, will not do the global init  */
92                                                                         1,      /* DSP#4 is Slave, will not do the global init  */
93                                                                         1,      /* DSP#5 is Slave, will not do the global init  */
94                                                                         1,      /* DSP#6 is Slave, will not do the global init  */
95                                                                         1,      /* DSP#7 is Slave, will not do the global init  */
96                                                                         };
98 unsigned short isGblConfigRequired(unsigned int dspNum)
99         {
100         return gblCfgReqdArray[dspNum];
101         }
103 /* Semaphore handles */
104 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL,NULL,NULL};
107 /* Variable which will be used internally for referring number of Event Queues. */
108 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u, 2u, 2u};
110 /* Variable which will be used internally for referring number of TCs. */
111 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u, 2u, 2u};
113 /**
114  * Variable which will be used internally for referring transfer completion
115  * interrupt. Completion interrupts for all the shadow regions and all the
116  * EDMA3 controllers are captured since it is a multi-DSP platform.
117  */
118 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
119                                                                                                         {
120                                                                                                         38u, 39u, 40u, 41u,
121                                                                                                         42u, 43u, 44u, 45u,
122                                                                                                         },
123                                                                                                         {
124                                                                                                         8u, 9u, 10u, 11u,
125                                                                                                         12u, 13u, 14u, 15u,
126                                                                                                         },
127                                                                                                         {
128                                                                                                         24u, 25u, 26u, 27u,
129                                                                                                         28u, 29u, 30u, 31u,
130                                                                                                         },
131                                                                                                         {
132                                                                                                         225u, 226u, 227u, 228u,
133                                                                                                         229u, 230u, 231u, 232u,
134                                                                                                         },
135                                                                                                         {
136                                                                                                         212u, 213u, 214u, 215u,
137                                                                                                         216u, 217u, 218u, 219u,
138                                                                                                         },
139                                                                                                 };
141 /**
142  * Variable which will be used internally for referring channel controller's
143  * error interrupt.
144  */
145 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u, 220u, 207u};
147 /**
148  * Variable which will be used internally for referring transfer controllers'
149  * error interrupts.
150  */
151 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] =    {
152                                                                                                         {
153                                                                                                         34u, 35u, 0u, 0u,
154                                                                                                         0u, 0u, 0u, 0u,
155                                                                                                         },
156                                                                                                         {
157                                                                                                         2u, 3u, 4u, 5u,
158                                                                                                         0u, 0u, 0u, 0u,
159                                                                                                         },
160                                                                                                         {
161                                                                                                         18u, 19u, 20u, 21u,
162                                                                                                         0u, 0u, 0u, 0u,
163                                                                                                         },
164                                                                                                         {
165                                                                                                         222u, 223u, 0u, 0u,
166                                                                                                         0u, 0u, 0u, 0u,
167                                                                                                         },
168                                                                                                         {
169                                                                                                         209u, 210u, 0u, 0u,
170                                                                                                         0u, 0u, 0u, 0u,
171                                                                                                         },
172                                                                                                 };
174 /* Driver Object Initialization Configuration */
175 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
176         {
177                 {
178                 /* EDMA3 INSTANCE# 0 */
179                 /** Total number of DMA Channels supported by the EDMA3 Controller */
180                 64u,
181                 /** Total number of QDMA Channels supported by the EDMA3 Controller */
182                 8u,
183                 /** Total number of TCCs supported by the EDMA3 Controller */
184                 64u,
185                 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
186                 512u,
187                 /** Total number of Event Queues in the EDMA3 Controller */
188                 2u,
189                 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
190                 2u,
191                 /** Number of Regions on this EDMA3 controller */
192                 8u,
194                 /**
195                  * \brief Channel mapping existence
196                  * A value of 0 (No channel mapping) implies that there is fixed association
197                  * for a channel number to a parameter entry number or, in other words,
198                  * PaRAM entry n corresponds to channel n.
199                  */
200                 1u,
202                 /** Existence of memory protection feature */
203                 1u,
205                 /** Global Register Region of CC Registers */
206                 (void *)0x02700000u,
207                 /** Transfer Controller (TC) Registers */
208                 {
209                 (void *)0x02760000u,
210                 (void *)0x02768000u,
211                 (void *)NULL,
212                 (void *)NULL,
213                 (void *)NULL,
214                 (void *)NULL,
215                 (void *)NULL,
216                 (void *)NULL
217                 },
218                 /** Interrupt no. for Transfer Completion */
219                 38u,
220                 /** Interrupt no. for CC Error */
221                 32u,
222                 /** Interrupt no. for TCs Error */
223                 {
224                 34u,
225                 35u,
226                 0u,
227                 0u,
228                 0u,
229                 0u,
230                 0u,
231                 0u,
232                 },
234                 /**
235                  * \brief EDMA3 TC priority setting
236                  *
237                  * User can program the priority of the Event Queues
238                  * at a system-wide level.  This means that the user can set the
239                  * priority of an IO initiated by either of the TCs (Transfer Controllers)
240                  * relative to IO initiated by the other bus masters on the
241                  * device (ARM, DSP, USB, etc)
242                  */
243                 {
244                 0u,
245                 1u,
246                 0u,
247                 0u,
248                 0u,
249                 0u,
250                 0u,
251                 0u
252                 },
253                 /**
254                  * \brief To Configure the Threshold level of number of events
255                  * that can be queued up in the Event queues. EDMA3CC error register
256                  * (CCERR) will indicate whether or not at any instant of time the
257                  * number of events queued up in any of the event queues exceeds
258                  * or equals the threshold/watermark value that is set
259                  * in the queue watermark threshold register (QWMTHRA).
260                  */
261                 {
262                 16u,
263                 16u,
264                 0u,
265                 0u,
266                 0u,
267                 0u,
268                 0u,
269                 0u
270                 },
272                 /**
273                  * \brief To Configure the Default Burst Size (DBS) of TCs.
274                  * An optimally-sized command is defined by the transfer controller
275                  * default burst size (DBS). Different TCs can have different
276                  * DBS values. It is defined in Bytes.
277                  */
278                 {
279                 256u,
280                 256u,
281                 0u,
282                 0u,
283                 0u,
284                 0u,
285                 0u,
286                 0u
287                 },
289                 /**
290                  * \brief Mapping from each DMA channel to a Parameter RAM set,
291                  * if it exists, otherwise of no use.
292                  */
293                 {
294                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
295         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
296         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
297         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
298         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
299         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
300         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
301         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
302         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
303         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
304         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
305         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
306         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
307         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
308         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
309         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
310         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
311         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
312         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
313         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
314         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
315         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
316         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
317         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
318         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
319         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
320         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
321         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
322         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
323         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
324         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
325         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
326                 },
328                  /**
329                   * \brief Mapping from each DMA channel to a TCC. This specific
330                   * TCC code will be returned when the transfer is completed
331                   * on the mapped channel.
332                   */
333                 {
334                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
335                 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
336                 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
337                 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
338                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
339                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
340                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
341                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
342                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
343                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
344                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
345                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
346                 },
348                 /**
349                  * \brief Mapping of DMA channels to Hardware Events from
350                  * various peripherals, which use EDMA for data transfer.
351                  * All channels need not be mapped, some can be free also.
352                  */
353                 {
354                 0xFFFFFFFFu,
355                 0x00000000u
356                 }
357                 },
359                 {
360                 /* EDMA3 INSTANCE# 1 */
361                 /** Total number of DMA Channels supported by the EDMA3 Controller */
362                 64u,
363                 /** Total number of QDMA Channels supported by the EDMA3 Controller */
364                 8u,
365                 /** Total number of TCCs supported by the EDMA3 Controller */
366                 64u,
367                 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
368                 512u,
369                 /** Total number of Event Queues in the EDMA3 Controller */
370                 4u,
371                 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
372                 4u,
373                 /** Number of Regions on this EDMA3 controller */
374                 8u,
376                 /**
377                  * \brief Channel mapping existence
378                  * A value of 0 (No channel mapping) implies that there is fixed association
379                  * for a channel number to a parameter entry number or, in other words,
380                  * PaRAM entry n corresponds to channel n.
381                  */
382                 1u,
384                 /** Existence of memory protection feature */
385                 1u,
387                 /** Global Register Region of CC Registers */
388                 (void *)0x02720000u,
389                 /** Transfer Controller (TC) Registers */
390                 {
391                 (void *)0x02770000u,
392                 (void *)0x02778000u,
393                 (void *)0x02780000u,
394                 (void *)0x02788000u,
395                 (void *)NULL,
396                 (void *)NULL,
397                 (void *)NULL,
398                 (void *)NULL
399                 },
400                 /** Interrupt no. for Transfer Completion */
401                 8u,
402                 /** Interrupt no. for CC Error */
403                 0u,
404                 /** Interrupt no. for TCs Error */
405                 {
406                 2u,
407                 3u,
408                 4u,
409                 5u,
410                 0u,
411                 0u,
412                 0u,
413                 0u,
414                 },
416                 /**
417                  * \brief EDMA3 TC priority setting
418                  *
419                  * User can program the priority of the Event Queues
420                  * at a system-wide level.  This means that the user can set the
421                  * priority of an IO initiated by either of the TCs (Transfer Controllers)
422                  * relative to IO initiated by the other bus masters on the
423                  * device (ARM, DSP, USB, etc)
424                  */
425                 {
426                 0u,
427                 1u,
428                 2u,
429                 3u,
430                 0u,
431                 0u,
432                 0u,
433                 0u
434                 },
435                 /**
436                  * \brief To Configure the Threshold level of number of events
437                  * that can be queued up in the Event queues. EDMA3CC error register
438                  * (CCERR) will indicate whether or not at any instant of time the
439                  * number of events queued up in any of the event queues exceeds
440                  * or equals the threshold/watermark value that is set
441                  * in the queue watermark threshold register (QWMTHRA).
442                  */
443                 {
444                 16u,
445                 16u,
446                 16u,
447                 16u,
448                 0u,
449                 0u,
450                 0u,
451                 0u
452                 },
454                 /**
455                  * \brief To Configure the Default Burst Size (DBS) of TCs.
456                  * An optimally-sized command is defined by the transfer controller
457                  * default burst size (DBS). Different TCs can have different
458                  * DBS values. It is defined in Bytes.
459                  */
460                 {
461                 128u,
462                 128u,
463                 128u,
464                 128u,
465                 0u,
466                 0u,
467                 0u,
468                 0u
469                 },
471                 /**
472                  * \brief Mapping from each DMA channel to a Parameter RAM set,
473                  * if it exists, otherwise of no use.
474                  */
475                 {
476                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
477         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
478         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
479         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
480         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
481         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
482         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
483         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
484         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
485         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
486         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
487         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
488         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
489         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
490         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
491         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
492         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
493         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
494         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
495         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
496         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
497         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
498         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
499         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
500         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
501         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
502         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
503         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
504         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
505         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
506         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
507         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
508                 },
510                  /**
511                   * \brief Mapping from each DMA channel to a TCC. This specific
512                   * TCC code will be returned when the transfer is completed
513                   * on the mapped channel.
514                   */
515                 {
516                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
517                 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
518                 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
519                 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
520                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
521                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
522                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
523                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
524                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
525                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
526                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
527                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
528                 },
530                 /**
531                  * \brief Mapping of DMA channels to Hardware Events from
532                  * various peripherals, which use EDMA for data transfer.
533                  * All channels need not be mapped, some can be free also.
534                  */
535                 {
536                 0xFFFFFFFFu,
537                 0x00000000u
538                 }
539                 },
541                 {
542                 /* EDMA3 INSTANCE# 2 */
543                 /** Total number of DMA Channels supported by the EDMA3 Controller */
544                 64u,
545                 /** Total number of QDMA Channels supported by the EDMA3 Controller */
546                 8u,
547                 /** Total number of TCCs supported by the EDMA3 Controller */
548                 64u,
549                 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
550                 512u,
551                 /** Total number of Event Queues in the EDMA3 Controller */
552                 4u,
553                 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
554                 4u,
555                 /** Number of Regions on this EDMA3 controller */
556                 8u,
558                 /**
559                  * \brief Channel mapping existence
560                  * A value of 0 (No channel mapping) implies that there is fixed association
561                  * for a channel number to a parameter entry number or, in other words,
562                  * PaRAM entry n corresponds to channel n.
563                  */
564                 1u,
566                 /** Existence of memory protection feature */
567                 1u,
569                 /** Global Register Region of CC Registers */
570                 (void *)0x02740000u,
571                 /** Transfer Controller (TC) Registers */
572                 {
573                 (void *)0x02790000u,
574                 (void *)0x02798000u,
575                 (void *)0x027A0000u,
576                 (void *)0x027A8000u,
577                 (void *)NULL,
578                 (void *)NULL,
579                 (void *)NULL,
580                 (void *)NULL
581                 },
582                 /** Interrupt no. for Transfer Completion */
583                 24u,
584                 /** Interrupt no. for CC Error */
585                 16u,
586                 /** Interrupt no. for TCs Error */
587                 {
588                 18u,
589                 19u,
590                 20u,
591                 21u,
592                 0u,
593                 0u,
594                 0u,
595                 0u,
596                 },
598                 /**
599                  * \brief EDMA3 TC priority setting
600                  *
601                  * User can program the priority of the Event Queues
602                  * at a system-wide level.  This means that the user can set the
603                  * priority of an IO initiated by either of the TCs (Transfer Controllers)
604                  * relative to IO initiated by the other bus masters on the
605                  * device (ARM, DSP, USB, etc)
606                  */
607                 {
608                 0u,
609                 1u,
610                 2u,
611                 3u,
612                 0u,
613                 0u,
614                 0u,
615                 0u
616                 },
617                 /**
618                  * \brief To Configure the Threshold level of number of events
619                  * that can be queued up in the Event queues. EDMA3CC error register
620                  * (CCERR) will indicate whether or not at any instant of time the
621                  * number of events queued up in any of the event queues exceeds
622                  * or equals the threshold/watermark value that is set
623                  * in the queue watermark threshold register (QWMTHRA).
624                  */
625                 {
626                 16u,
627                 16u,
628                 16u,
629                 16u,
630                 0u,
631                 0u,
632                 0u,
633                 0u
634                 },
636                 /**
637                  * \brief To Configure the Default Burst Size (DBS) of TCs.
638                  * An optimally-sized command is defined by the transfer controller
639                  * default burst size (DBS). Different TCs can have different
640                  * DBS values. It is defined in Bytes.
641                  */
642                 {
643                 128u,
644                 128u,
645                 128u,
646                 128u,
647                 0u,
648                 0u,
649                 0u,
650                 0u
651                 },
653                 /**
654                  * \brief Mapping from each DMA channel to a Parameter RAM set,
655                  * if it exists, otherwise of no use.
656                  */
657                 {
658         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
659         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
660         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
661         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
662         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
663         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
664         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
665         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
666         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
667         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
668         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
669         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
670         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
671         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
672         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
673         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
674         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
675         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
676         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
677         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
678         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
679         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
680         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
681         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
682         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
683         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
684         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
685         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
686         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
687         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
688         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
689         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
690                 },
692                  /**
693                   * \brief Mapping from each DMA channel to a TCC. This specific
694                   * TCC code will be returned when the transfer is completed
695                   * on the mapped channel.
696                   */
697                 {
698                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
699                 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
700                 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
701                 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
702                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
703                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
704                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
705                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
706                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
707                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
708                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
709                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
710                 },
712                 /**
713                  * \brief Mapping of DMA channels to Hardware Events from
714                  * various peripherals, which use EDMA for data transfer.
715                  * All channels need not be mapped, some can be free also.
716                  */
717                 {
718                 0xFFFFFFFFu,
719                 0x00000000u
720                 }
721                 },
723                 {
724                 /* EDMA3 INSTANCE# 3 */
725                 /** Total number of DMA Channels supported by the EDMA3 Controller */
726                 64u,
727                 /** Total number of QDMA Channels supported by the EDMA3 Controller */
728                 8u,
729                 /** Total number of TCCs supported by the EDMA3 Controller */
730                 64u,
731                 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
732                 512u,
733                 /** Total number of Event Queues in the EDMA3 Controller */
734                 2u,
735                 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
736                 2u,
737                 /** Number of Regions on this EDMA3 controller */
738                 8u,
740                 /**
741                  * \brief Channel mapping existence
742                  * A value of 0 (No channel mapping) implies that there is fixed association
743                  * for a channel number to a parameter entry number or, in other words,
744                  * PaRAM entry n corresponds to channel n.
745                  */
746                 1u,
748                 /** Existence of memory protection feature */
749                 1u,
751                 /** Global Register Region of CC Registers */
752                 (void *)0x02728000u,
753                 /** Transfer Controller (TC) Registers */
754                 {
755                 (void *)0x027B0000u,
756                 (void *)0x027B8000u,
757                 (void *)NULL,
758                 (void *)NULL,
759                 (void *)NULL,
760                 (void *)NULL,
761                 (void *)NULL,
762                 (void *)NULL
763                 },
764                 /** Interrupt no. for Transfer Completion */
765                 225u,
766                 /** Interrupt no. for CC Error */
767                 220u,
768                 /** Interrupt no. for TCs Error */
769                 {
770                 222u,
771                 223u,
772                 0u,
773                 0u,
774                 0u,
775                 0u,
776                 0u,
777                 0u,
778                 },
780                 /**
781                  * \brief EDMA3 TC priority setting
782                  *
783                  * User can program the priority of the Event Queues
784                  * at a system-wide level.  This means that the user can set the
785                  * priority of an IO initiated by either of the TCs (Transfer Controllers)
786                  * relative to IO initiated by the other bus masters on the
787                  * device (ARM, DSP, USB, etc)
788                  */
789                 {
790                 0u,
791                 1u,
792                 0u,
793                 0u,
794                 0u,
795                 0u,
796                 0u,
797                 0u
798                 },
799                 /**
800                  * \brief To Configure the Threshold level of number of events
801                  * that can be queued up in the Event queues. EDMA3CC error register
802                  * (CCERR) will indicate whether or not at any instant of time the
803                  * number of events queued up in any of the event queues exceeds
804                  * or equals the threshold/watermark value that is set
805                  * in the queue watermark threshold register (QWMTHRA).
806                  */
807                 {
808                 16u,
809                 16u,
810                 0u,
811                 0u,
812                 0u,
813                 0u,
814                 0u,
815                 0u
816                 },
818                 /**
819                  * \brief To Configure the Default Burst Size (DBS) of TCs.
820                  * An optimally-sized command is defined by the transfer controller
821                  * default burst size (DBS). Different TCs can have different
822                  * DBS values. It is defined in Bytes.
823                  */
824                 {
825                 128u,
826                 128u,
827                 0u,
828                 0u,
829                 0u,
830                 0u,
831                 0u,
832                 0u
833                 },
835                 /**
836                  * \brief Mapping from each DMA channel to a Parameter RAM set,
837                  * if it exists, otherwise of no use.
838                  */
839                 {
840                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
841         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
842         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
843         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
844         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
845         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
846         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
847         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
848         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
849         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
850         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
851         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
852         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
853         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
854         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
855         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
856         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
857         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
858         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
859         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
860         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
861         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
862         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
863         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
864         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
865         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
866         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
867         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
868         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
869         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
870         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
871         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
872                 },
874                  /**
875                   * \brief Mapping from each DMA channel to a TCC. This specific
876                   * TCC code will be returned when the transfer is completed
877                   * on the mapped channel.
878                   */
879                 {
880                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
881                 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
882                 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
883                 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
884                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
885                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
886                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
887                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
888                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
889                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
890                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
891                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
892                 },
894                 /**
895                  * \brief Mapping of DMA channels to Hardware Events from
896                  * various peripherals, which use EDMA for data transfer.
897                  * All channels need not be mapped, some can be free also.
898                  */
899                 {
900                 0xFFFFFFFFu,
901                 0x00000000u
902                 }
903                 },
905                 {
906                 /* EDMA3 INSTANCE# 4 */
907                 /** Total number of DMA Channels supported by the EDMA3 Controller */
908                 64u,
909                 /** Total number of QDMA Channels supported by the EDMA3 Controller */
910                 8u,
911                 /** Total number of TCCs supported by the EDMA3 Controller */
912                 64u,
913                 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
914                 512u,
915                 /** Total number of Event Queues in the EDMA3 Controller */
916                 2u,
917                 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
918                 2u,
919                 /** Number of Regions on this EDMA3 controller */
920                 8u,
922                 /**
923                  * \brief Channel mapping existence
924                  * A value of 0 (No channel mapping) implies that there is fixed association
925                  * for a channel number to a parameter entry number or, in other words,
926                  * PaRAM entry n corresponds to channel n.
927                  */
928                 1u,
930                 /** Existence of memory protection feature */
931                 1u,
933                 /** Global Register Region of CC Registers */
934                 (void *)0x02708000u,
935                 /** Transfer Controller (TC) Registers */
936                 {
937                 (void *)0x027B8400u,
938                 (void *)0x027B8800u,
939                 (void *)NULL,
940                 (void *)NULL,
941                 (void *)NULL,
942                 (void *)NULL,
943                 (void *)NULL,
944                 (void *)NULL
945                 },
946                 /** Interrupt no. for Transfer Completion */
947                 212u,
948                 /** Interrupt no. for CC Error */
949                 207u,
950                 /** Interrupt no. for TCs Error */
951                 {
952                 209u,
953                 210u,
954                 0u,
955                 0u,
956                 0u,
957                 0u,
958                 0u,
959                 0u,
960                 },
962                 /**
963                  * \brief EDMA3 TC priority setting
964                  *
965                  * User can program the priority of the Event Queues
966                  * at a system-wide level.  This means that the user can set the
967                  * priority of an IO initiated by either of the TCs (Transfer Controllers)
968                  * relative to IO initiated by the other bus masters on the
969                  * device (ARM, DSP, USB, etc)
970                  */
971                 {
972                 0u,
973                 1u,
974                 0u,
975                 0u,
976                 0u,
977                 0u,
978                 0u,
979                 0u
980                 },
981                 /**
982                  * \brief To Configure the Threshold level of number of events
983                  * that can be queued up in the Event queues. EDMA3CC error register
984                  * (CCERR) will indicate whether or not at any instant of time the
985                  * number of events queued up in any of the event queues exceeds
986                  * or equals the threshold/watermark value that is set
987                  * in the queue watermark threshold register (QWMTHRA).
988                  */
989                 {
990                 16u,
991                 16u,
992                 0u,
993                 0u,
994                 0u,
995                 0u,
996                 0u,
997                 0u
998                 },
1000                 /**
1001                  * \brief To Configure the Default Burst Size (DBS) of TCs.
1002                  * An optimally-sized command is defined by the transfer controller
1003                  * default burst size (DBS). Different TCs can have different
1004                  * DBS values. It is defined in Bytes.
1005                  */
1006                 {
1007                 256u,
1008                 256u,
1009                 0u,
1010                 0u,
1011                 0u,
1012                 0u,
1013                 0u,
1014                 0u
1015                 },
1017                 /**
1018                  * \brief Mapping from each DMA channel to a Parameter RAM set,
1019                  * if it exists, otherwise of no use.
1020                  */
1021                 {
1022                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1023         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1024         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1025         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1026         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1027         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1028         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1029         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1030         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1031         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1032         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1033         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1034         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1035         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1036         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1037         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1038         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1039         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1040         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1041         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1042         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1043         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1044         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1045         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1046         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1047         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1048         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1049         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1050         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1051         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1052         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1053         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
1054                 },
1056                  /**
1057                   * \brief Mapping from each DMA channel to a TCC. This specific
1058                   * TCC code will be returned when the transfer is completed
1059                   * on the mapped channel.
1060                   */
1061                 {
1062                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
1063                 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
1064                 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
1065                 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
1066                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1067                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1068                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1069                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1070                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1071                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1072                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1073                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
1074                 },
1076                 /**
1077                  * \brief Mapping of DMA channels to Hardware Events from
1078                  * various peripherals, which use EDMA for data transfer.
1079                  * All channels need not be mapped, some can be free also.
1080                  */
1081                 {
1082                 0xFFFFFFFFu,
1083                 0x00000000u
1084                 }
1085                 },
1086         };
1088 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
1089         {
1090                 /* EDMA3 INSTANCE# 0 */
1091                 {
1092                         /* Resources owned/reserved by region 0 */
1093                         {
1094                                 /* ownPaRAMSets */
1095                                 /* 31     0     63    32     95    64     127   96 */
1096                                 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
1097                                 /* 159  128     191  160     223  192     255  224 */
1098                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1099                                 /* 287  256     319  288     351  320     383  352 */
1100                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1101                                 /* 415  384     447  416     479  448     511  480 */
1102                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1104                                 /* ownDmaChannels */
1105                                 /* 31     0     63    32 */
1106                                 {0x000000FFu, 0x00000000u},
1108                                 /* ownQdmaChannels */
1109                                 /* 31     0 */
1110                                 {0x00000001u},
1112                                 /* ownTccs */
1113                                 /* 31     0     63    32 */
1114                                 {0x000000FFu, 0x00000000u},
1116                                 /* resvdPaRAMSets */
1117                                 /* 31     0     63    32     95    64     127   96 */
1118                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1119                                 /* 159  128     191  160     223  192     255  224 */
1120                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1121                                 /* 287  256     319  288     351  320     383  352 */
1122                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1123                                 /* 415  384     447  416     479  448     511  480 */
1124                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1126                                 /* resvdDmaChannels */
1127                                 /* 31     0     63    32 */
1128                                 {0x00000000u, 0x00000000u},
1130                                 /* resvdQdmaChannels */
1131                                 /* 31     0 */
1132                                 {0x00000000u},
1134                                 /* resvdTccs */
1135                                 /* 31     0     63    32 */
1136                                 {0x00000000u, 0x00000000u},
1137                         },
1139                 /* Resources owned/reserved by region 1 */
1140                         {
1141                                 /* ownPaRAMSets */
1142                                 /* 31     0     63    32     95    64     127   96 */
1143                                 {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
1144                                 /* 159  128     191  160     223  192     255  224 */
1145                                  0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1146                                 /* 287  256     319  288     351  320     383  352 */
1147                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1148                                 /* 415  384     447  416     479  448     511  480 */
1149                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1151                                 /* ownDmaChannels */
1152                                 /* 31     0     63    32 */
1153                                 {0x0000FF00u, 0x00000000u},
1155                                 /* ownQdmaChannels */
1156                                 /* 31     0 */
1157                                 {0x00000002u},
1159                                 /* ownTccs */
1160                                 /* 31     0     63    32 */
1161                                 {0x0000FF00u, 0x00000000u},
1163                                 /* resvdPaRAMSets */
1164                                 /* 31     0     63    32     95    64     127   96 */
1165                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1166                                 /* 159  128     191  160     223  192     255  224 */
1167                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1168                                 /* 287  256     319  288     351  320     383  352 */
1169                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1170                                 /* 415  384     447  416     479  448     511  480 */
1171                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1173                                 /* resvdDmaChannels */
1174                                 /* 31     0     63    32 */
1175                                 {0x00000000u, 0x00000000u},
1177                                 /* resvdQdmaChannels */
1178                                 /* 31     0 */
1179                                 {0x00000000u},
1181                                 /* resvdTccs */
1182                                 /* 31     0     63    32 */
1183                                 {0x00000000u, 0x00000000u},
1184                         },
1186                 /* Resources owned/reserved by region 2 */
1187                         {
1188                                 /* ownPaRAMSets */
1189                                 /* 31     0     63    32     95    64     127   96 */
1190                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1191                                 /* 159  128     191  160     223  192     255  224 */
1192                                  0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
1193                                 /* 287  256     319  288     351  320     383  352 */
1194                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1195                                 /* 415  384     447  416     479  448     511  480 */
1196                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1198                                 /* ownDmaChannels */
1199                                 /* 31     0     63    32 */
1200                                 {0x00FF0000u, 0x0000000u},
1202                                 /* ownQdmaChannels */
1203                                 /* 31     0 */
1204                                 {0x00000004u},
1206                                 /* ownTccs */
1207                                 /* 31     0     63    32 */
1208                                 {0x00FF0000u, 0x00000000u},
1210                                 /* resvdPaRAMSets */
1211                                 /* 31     0     63    32     95    64     127   96 */
1212                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1213                                 /* 159  128     191  160     223  192     255  224 */
1214                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1215                                 /* 287  256     319  288     351  320     383  352 */
1216                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1217                                 /* 415  384     447  416     479  448     511  480 */
1218                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1220                                 /* resvdDmaChannels */
1221                                 /* 31     0     63    32 */
1222                                 {0x00000000u, 0x00000000u},
1224                                 /* resvdQdmaChannels */
1225                                 /* 31     0 */
1226                                 {0x00000000u},
1228                                 /* resvdTccs */
1229                                 /* 31     0     63    32 */
1230                                 {0x00000000u, 0x00000000u},
1231                         },
1233                 /* Resources owned/reserved by region 3 */
1234                         {
1235                                 /* ownPaRAMSets */
1236                                 /* 31     0     63    32     95    64     127   96 */
1237                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1238                                 /* 159  128     191  160     223  192     255  224 */
1239                                  0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
1240                                 /* 287  256     319  288     351  320     383  352 */
1241                                  0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1242                                 /* 415  384     447  416     479  448     511  480 */
1243                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1245                                 /* ownDmaChannels */
1246                                 /* 31     0     63    32 */
1247                                 {0xFF000000u, 0x00000000u},
1249                                 /* ownQdmaChannels */
1250                                 /* 31     0 */
1251                                 {0x00000008u},
1253                                 /* ownTccs */
1254                                 /* 31     0     63    32 */
1255                                 {0xFF000000u, 0x00000000u},
1257                                 /* resvdPaRAMSets */
1258                                 /* 31     0     63    32     95    64     127   96 */
1259                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1260                                 /* 159  128     191  160     223  192     255  224 */
1261                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1262                                 /* 287  256     319  288     351  320     383  352 */
1263                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1264                                 /* 415  384     447  416     479  448     511  480 */
1265                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1267                                 /* resvdDmaChannels */
1268                                 /* 31     0     63    32 */
1269                                 {0x00000000u, 0x00000000u},
1271                                 /* resvdQdmaChannels */
1272                                 /* 31     0 */
1273                                 {0x00000000u},
1275                                 /* resvdTccs */
1276                                 /* 31     0     63    32 */
1277                                 {0x00000000u, 0x00000000u},
1278                         },
1280                 /* Resources owned/reserved by region 4 */
1281                         {
1282                                 /* ownPaRAMSets */
1283                                 /* 31     0     63    32     95    64     127   96 */
1284                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1285                                 /* 159  128     191  160     223  192     255  224 */
1286                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1287                                 /* 287  256     319  288     351  320     383  352 */
1288                                  0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
1289                                 /* 415  384     447  416     479  448     511  480 */
1290                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1292                                 /* ownDmaChannels */
1293                                 /* 31     0     63    32 */
1294                                 {0x00000000u, 0x000000FFu},
1296                                 /* ownQdmaChannels */
1297                                 /* 31     0 */
1298                                 {0x00000010u},
1300                                 /* ownTccs */
1301                                 /* 31     0     63    32 */
1302                                 {0x00000000u, 0x000000FFu},
1304                                 /* resvdPaRAMSets */
1305                                 /* 31     0     63    32     95    64     127   96 */
1306                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1307                                 /* 159  128     191  160     223  192     255  224 */
1308                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1309                                 /* 287  256     319  288     351  320     383  352 */
1310                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1311                                 /* 415  384     447  416     479  448     511  480 */
1312                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1314                                 /* resvdDmaChannels */
1315                                 /* 31     0     63    32 */
1316                                 {0x00000000u, 0x00000000u},
1318                                 /* resvdQdmaChannels */
1319                                 /* 31     0 */
1320                                 {0x00000000u},
1322                                 /* resvdTccs */
1323                                 /* 31     0     63    32 */
1324                                 {0x00000000u, 0x00000000u},
1325                         },
1327                 /* Resources owned/reserved by region 5 */
1328                         {
1329                                 /* ownPaRAMSets */
1330                                 /* 31     0     63    32     95    64     127   96 */
1331                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1332                                 /* 159  128     191  160     223  192     255  224 */
1333                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1334                                 /* 287  256     319  288     351  320     383  352 */
1335                                  0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
1336                                 /* 415  384     447  416     479  448     511  480 */
1337                                  0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
1339                                 /* ownDmaChannels */
1340                                 /* 31     0     63    32 */
1341                                 {0x00000000u, 0x0000FF00u},
1343                                 /* ownQdmaChannels */
1344                                 /* 31     0 */
1345                                 {0x00000020u},
1347                                 /* ownTccs */
1348                                 /* 31     0     63    32 */
1349                                 {0x00000000u, 0x0000FF00u},
1351                                 /* resvdPaRAMSets */
1352                                 /* 31     0     63    32     95    64     127   96 */
1353                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1354                                 /* 159  128     191  160     223  192     255  224 */
1355                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1356                                 /* 287  256     319  288     351  320     383  352 */
1357                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1358                                 /* 415  384     447  416     479  448     511  480 */
1359                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1361                                 /* resvdDmaChannels */
1362                                 /* 31     0     63    32 */
1363                                 {0x00000000u, 0x00000000u},
1365                                 /* resvdQdmaChannels */
1366                                 /* 31     0 */
1367                                 {0x00000000u},
1369                                 /* resvdTccs */
1370                                 /* 31     0     63    32 */
1371                                 {0x00000000u, 0x00000000u},
1372                         },
1374                 /* Resources owned/reserved by region 6 */
1375                         {
1376                                 /* ownPaRAMSets */
1377                                 /* 31     0     63    32     95    64     127   96 */
1378                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1379                                 /* 159  128     191  160     223  192     255  224 */
1380                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1381                                 /* 287  256     319  288     351  320     383  352 */
1382                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1383                                 /* 415  384     447  416     479  448     511  480 */
1384                                  0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
1386                                 /* ownDmaChannels */
1387                                 /* 31     0     63    32 */
1388                                 {0x00000000u, 0x00FF0000u},
1390                                 /* ownQdmaChannels */
1391                                 /* 31     0 */
1392                                 {0x00000040u},
1394                                 /* ownTccs */
1395                                 /* 31     0     63    32 */
1396                                 {0x00000000u, 0x00FF0000u},
1398                                 /* resvdPaRAMSets */
1399                                 /* 31     0     63    32     95    64     127   96 */
1400                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1401                                 /* 159  128     191  160     223  192     255  224 */
1402                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1403                                 /* 287  256     319  288     351  320     383  352 */
1404                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1405                                 /* 415  384     447  416     479  448     511  480 */
1406                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1408                                 /* resvdDmaChannels */
1409                                 /* 31     0     63    32 */
1410                                 {0x00000000u, 0x00000000u},
1412                                 /* resvdQdmaChannels */
1413                                 /* 31     0 */
1414                                 {0x00000000u},
1416                                 /* resvdTccs */
1417                                 /* 31     0     63    32 */
1418                                 {0x00000000u, 0x00000000u},
1419                         },
1421                 /* Resources owned/reserved by region 7 */
1422                         {
1423                                 /* ownPaRAMSets */
1424                                 /* 31     0     63    32     95    64     127   96 */
1425                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1426                                 /* 159  128     191  160     223  192     255  224 */
1427                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1428                                 /* 287  256     319  288     351  320     383  352 */
1429                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1430                                 /* 415  384     447  416     479  448     511  480 */
1431                                  0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
1433                                 /* ownDmaChannels */
1434                                 /* 31     0     63    32 */
1435                                 {0x00000000u, 0xFF000000u},
1437                                 /* ownQdmaChannels */
1438                                 /* 31     0 */
1439                                 {0x00000080u},
1441                                 /* ownTccs */
1442                                 /* 31     0     63    32 */
1443                                 {0x00000000u, 0xFF000000u},
1445                                 /* resvdPaRAMSets */
1446                                 /* 31     0     63    32     95    64     127   96 */
1447                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1448                                 /* 159  128     191  160     223  192     255  224 */
1449                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1450                                 /* 287  256     319  288     351  320     383  352 */
1451                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1452                                 /* 415  384     447  416     479  448     511  480 */
1453                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1455                                 /* resvdDmaChannels */
1456                                 /* 31     0     63    32 */
1457                                 {0x00000000u, 0x00000000u},
1459                                 /* resvdQdmaChannels */
1460                                 /* 31     0 */
1461                                 {0x00000000u},
1463                                 /* resvdTccs */
1464                                 /* 31     0     63    32 */
1465                                 {0x00000000u, 0x00000000u},
1466                         },
1467                 },
1469                 /* EDMA3 INSTANCE# 1 */
1470                 {
1471                         /* Resources owned/reserved by region 0 */
1472                         {
1473                                 /* ownPaRAMSets */
1474                                 /* 31     0     63    32     95    64     127   96 */
1475                                 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
1476                                 /* 159  128     191  160     223  192     255  224 */
1477                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1478                                 /* 287  256     319  288     351  320     383  352 */
1479                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1480                                 /* 415  384     447  416     479  448     511  480 */
1481                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1483                                 /* ownDmaChannels */
1484                                 /* 31     0     63    32 */
1485                                 {0x000000FFu, 0x00000000u},
1487                                 /* ownQdmaChannels */
1488                                 /* 31     0 */
1489                                 {0x00000001u},
1491                                 /* ownTccs */
1492                                 /* 31     0     63    32 */
1493                                 {0x000000FFu, 0x00000000u},
1495                                 /* resvdPaRAMSets */
1496                                 /* 31     0     63    32     95    64     127   96 */
1497                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1498                                 /* 159  128     191  160     223  192     255  224 */
1499                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1500                                 /* 287  256     319  288     351  320     383  352 */
1501                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1502                                 /* 415  384     447  416     479  448     511  480 */
1503                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1505                                 /* resvdDmaChannels */
1506                                 /* 31     0     63    32 */
1507                                 {0x00000000u, 0x00000000u},
1509                                 /* resvdQdmaChannels */
1510                                 /* 31     0 */
1511                                 {0x00000000u},
1513                                 /* resvdTccs */
1514                                 /* 31     0     63    32 */
1515                                 {0x00000000u, 0x00000000u},
1516                         },
1518                 /* Resources owned/reserved by region 1 */
1519                         {
1520                                 /* ownPaRAMSets */
1521                                 /* 31     0     63    32     95    64     127   96 */
1522                                 {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
1523                                 /* 159  128     191  160     223  192     255  224 */
1524                                  0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1525                                 /* 287  256     319  288     351  320     383  352 */
1526                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1527                                 /* 415  384     447  416     479  448     511  480 */
1528                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1530                                 /* ownDmaChannels */
1531                                 /* 31     0     63    32 */
1532                                 {0x0000FF00u, 0x00000000u},
1534                                 /* ownQdmaChannels */
1535                                 /* 31     0 */
1536                                 {0x00000002u},
1538                                 /* ownTccs */
1539                                 /* 31     0     63    32 */
1540                                 {0x0000FF00u, 0x00000000u},
1542                                 /* resvdPaRAMSets */
1543                                 /* 31     0     63    32     95    64     127   96 */
1544                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1545                                 /* 159  128     191  160     223  192     255  224 */
1546                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1547                                 /* 287  256     319  288     351  320     383  352 */
1548                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1549                                 /* 415  384     447  416     479  448     511  480 */
1550                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1552                                 /* resvdDmaChannels */
1553                                 /* 31     0     63    32 */
1554                                 {0x00000000u, 0x00000000u},
1556                                 /* resvdQdmaChannels */
1557                                 /* 31     0 */
1558                                 {0x00000000u},
1560                                 /* resvdTccs */
1561                                 /* 31     0     63    32 */
1562                                 {0x00000000u, 0x00000000u},
1563                         },
1565                 /* Resources owned/reserved by region 2 */
1566                         {
1567                                 /* ownPaRAMSets */
1568                                 /* 31     0     63    32     95    64     127   96 */
1569                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1570                                 /* 159  128     191  160     223  192     255  224 */
1571                                  0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
1572                                 /* 287  256     319  288     351  320     383  352 */
1573                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1574                                 /* 415  384     447  416     479  448     511  480 */
1575                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1577                                 /* ownDmaChannels */
1578                                 /* 31     0     63    32 */
1579                                 {0x00FF0000u, 0x0000000u},
1581                                 /* ownQdmaChannels */
1582                                 /* 31     0 */
1583                                 {0x00000004u},
1585                                 /* ownTccs */
1586                                 /* 31     0     63    32 */
1587                                 {0x00FF0000u, 0x00000000u},
1589                                 /* resvdPaRAMSets */
1590                                 /* 31     0     63    32     95    64     127   96 */
1591                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1592                                 /* 159  128     191  160     223  192     255  224 */
1593                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1594                                 /* 287  256     319  288     351  320     383  352 */
1595                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1596                                 /* 415  384     447  416     479  448     511  480 */
1597                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1599                                 /* resvdDmaChannels */
1600                                 /* 31     0     63    32 */
1601                                 {0x00000000u, 0x00000000u},
1603                                 /* resvdQdmaChannels */
1604                                 /* 31     0 */
1605                                 {0x00000000u},
1607                                 /* resvdTccs */
1608                                 /* 31     0     63    32 */
1609                                 {0x00000000u, 0x00000000u},
1610                         },
1612                 /* Resources owned/reserved by region 3 */
1613                         {
1614                                 /* ownPaRAMSets */
1615                                 /* 31     0     63    32     95    64     127   96 */
1616                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1617                                 /* 159  128     191  160     223  192     255  224 */
1618                                  0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
1619                                 /* 287  256     319  288     351  320     383  352 */
1620                                  0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1621                                 /* 415  384     447  416     479  448     511  480 */
1622                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1624                                 /* ownDmaChannels */
1625                                 /* 31     0     63    32 */
1626                                 {0xFF000000u, 0x00000000u},
1628                                 /* ownQdmaChannels */
1629                                 /* 31     0 */
1630                                 {0x00000008u},
1632                                 /* ownTccs */
1633                                 /* 31     0     63    32 */
1634                                 {0xFF000000u, 0x00000000u},
1636                                 /* resvdPaRAMSets */
1637                                 /* 31     0     63    32     95    64     127   96 */
1638                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1639                                 /* 159  128     191  160     223  192     255  224 */
1640                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1641                                 /* 287  256     319  288     351  320     383  352 */
1642                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1643                                 /* 415  384     447  416     479  448     511  480 */
1644                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1646                                 /* resvdDmaChannels */
1647                                 /* 31     0     63    32 */
1648                                 {0x00000000u, 0x00000000u},
1650                                 /* resvdQdmaChannels */
1651                                 /* 31     0 */
1652                                 {0x00000000u},
1654                                 /* resvdTccs */
1655                                 /* 31     0     63    32 */
1656                                 {0x00000000u, 0x00000000u},
1657                         },
1659                 /* Resources owned/reserved by region 4 */
1660                         {
1661                                 /* ownPaRAMSets */
1662                                 /* 31     0     63    32     95    64     127   96 */
1663                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1664                                 /* 159  128     191  160     223  192     255  224 */
1665                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1666                                 /* 287  256     319  288     351  320     383  352 */
1667                                  0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
1668                                 /* 415  384     447  416     479  448     511  480 */
1669                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1671                                 /* ownDmaChannels */
1672                                 /* 31     0     63    32 */
1673                                 {0x00000000u, 0x000000FFu},
1675                                 /* ownQdmaChannels */
1676                                 /* 31     0 */
1677                                 {0x00000010u},
1679                                 /* ownTccs */
1680                                 /* 31     0     63    32 */
1681                                 {0x00000000u, 0x000000FFu},
1683                                 /* resvdPaRAMSets */
1684                                 /* 31     0     63    32     95    64     127   96 */
1685                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1686                                 /* 159  128     191  160     223  192     255  224 */
1687                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1688                                 /* 287  256     319  288     351  320     383  352 */
1689                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1690                                 /* 415  384     447  416     479  448     511  480 */
1691                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1693                                 /* resvdDmaChannels */
1694                                 /* 31     0     63    32 */
1695                                 {0x00000000u, 0x00000000u},
1697                                 /* resvdQdmaChannels */
1698                                 /* 31     0 */
1699                                 {0x00000000u},
1701                                 /* resvdTccs */
1702                                 /* 31     0     63    32 */
1703                                 {0x00000000u, 0x00000000u},
1704                         },
1706                 /* Resources owned/reserved by region 5 */
1707                         {
1708                                 /* ownPaRAMSets */
1709                                 /* 31     0     63    32     95    64     127   96 */
1710                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1711                                 /* 159  128     191  160     223  192     255  224 */
1712                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1713                                 /* 287  256     319  288     351  320     383  352 */
1714                                  0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
1715                                 /* 415  384     447  416     479  448     511  480 */
1716                                  0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
1718                                 /* ownDmaChannels */
1719                                 /* 31     0     63    32 */
1720                                 {0x00000000u, 0x0000FF00u},
1722                                 /* ownQdmaChannels */
1723                                 /* 31     0 */
1724                                 {0x00000020u},
1726                                 /* ownTccs */
1727                                 /* 31     0     63    32 */
1728                                 {0x00000000u, 0x0000FF00u},
1730                                 /* resvdPaRAMSets */
1731                                 /* 31     0     63    32     95    64     127   96 */
1732                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1733                                 /* 159  128     191  160     223  192     255  224 */
1734                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1735                                 /* 287  256     319  288     351  320     383  352 */
1736                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1737                                 /* 415  384     447  416     479  448     511  480 */
1738                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1740                                 /* resvdDmaChannels */
1741                                 /* 31     0     63    32 */
1742                                 {0x00000000u, 0x00000000u},
1744                                 /* resvdQdmaChannels */
1745                                 /* 31     0 */
1746                                 {0x00000000u},
1748                                 /* resvdTccs */
1749                                 /* 31     0     63    32 */
1750                                 {0x00000000u, 0x00000000u},
1751                         },
1753                 /* Resources owned/reserved by region 6 */
1754                         {
1755                                 /* ownPaRAMSets */
1756                                 /* 31     0     63    32     95    64     127   96 */
1757                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1758                                 /* 159  128     191  160     223  192     255  224 */
1759                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1760                                 /* 287  256     319  288     351  320     383  352 */
1761                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1762                                 /* 415  384     447  416     479  448     511  480 */
1763                                  0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
1765                                 /* ownDmaChannels */
1766                                 /* 31     0     63    32 */
1767                                 {0x00000000u, 0x00FF0000u},
1769                                 /* ownQdmaChannels */
1770                                 /* 31     0 */
1771                                 {0x00000040u},
1773                                 /* ownTccs */
1774                                 /* 31     0     63    32 */
1775                                 {0x00000000u, 0x00FF0000u},
1777                                 /* resvdPaRAMSets */
1778                                 /* 31     0     63    32     95    64     127   96 */
1779                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1780                                 /* 159  128     191  160     223  192     255  224 */
1781                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1782                                 /* 287  256     319  288     351  320     383  352 */
1783                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1784                                 /* 415  384     447  416     479  448     511  480 */
1785                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1787                                 /* resvdDmaChannels */
1788                                 /* 31     0     63    32 */
1789                                 {0x00000000u, 0x00000000u},
1791                                 /* resvdQdmaChannels */
1792                                 /* 31     0 */
1793                                 {0x00000000u},
1795                                 /* resvdTccs */
1796                                 /* 31     0     63    32 */
1797                                 {0x00000000u, 0x00000000u},
1798                         },
1800                 /* Resources owned/reserved by region 7 */
1801                         {
1802                                 /* ownPaRAMSets */
1803                                 /* 31     0     63    32     95    64     127   96 */
1804                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1805                                 /* 159  128     191  160     223  192     255  224 */
1806                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1807                                 /* 287  256     319  288     351  320     383  352 */
1808                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1809                                 /* 415  384     447  416     479  448     511  480 */
1810                                  0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
1812                                 /* ownDmaChannels */
1813                                 /* 31     0     63    32 */
1814                                 {0x00000000u, 0xFF000000u},
1816                                 /* ownQdmaChannels */
1817                                 /* 31     0 */
1818                                 {0x00000080u},
1820                                 /* ownTccs */
1821                                 /* 31     0     63    32 */
1822                                 {0x00000000u, 0xFF000000u},
1824                                 /* resvdPaRAMSets */
1825                                 /* 31     0     63    32     95    64     127   96 */
1826                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1827                                 /* 159  128     191  160     223  192     255  224 */
1828                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1829                                 /* 287  256     319  288     351  320     383  352 */
1830                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1831                                 /* 415  384     447  416     479  448     511  480 */
1832                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1834                                 /* resvdDmaChannels */
1835                                 /* 31     0     63    32 */
1836                                 {0x00000000u, 0x00000000u},
1838                                 /* resvdQdmaChannels */
1839                                 /* 31     0 */
1840                                 {0x00000000u},
1842                                 /* resvdTccs */
1843                                 /* 31     0     63    32 */
1844                                 {0x00000000u, 0x00000000u},
1845                         },
1846                 },
1848                 /* EDMA3 INSTANCE# 2 */
1849                 {
1850                         /* Resources owned/reserved by region 0 */
1851                         {
1852                                 /* ownPaRAMSets */
1853                                 /* 31     0     63    32     95    64     127   96 */
1854                                 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
1855                                 /* 159  128     191  160     223  192     255  224 */
1856                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1857                                 /* 287  256     319  288     351  320     383  352 */
1858                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1859                                 /* 415  384     447  416     479  448     511  480 */
1860                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1862                                 /* ownDmaChannels */
1863                                 /* 31     0     63    32 */
1864                                 {0x000000FFu, 0x00000000u},
1866                                 /* ownQdmaChannels */
1867                                 /* 31     0 */
1868                                 {0x00000001u},
1870                                 /* ownTccs */
1871                                 /* 31     0     63    32 */
1872                                 {0x000000FFu, 0x00000000u},
1874                                 /* resvdPaRAMSets */
1875                                 /* 31     0     63    32     95    64     127   96 */
1876                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1877                                 /* 159  128     191  160     223  192     255  224 */
1878                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1879                                 /* 287  256     319  288     351  320     383  352 */
1880                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1881                                 /* 415  384     447  416     479  448     511  480 */
1882                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1884                                 /* resvdDmaChannels */
1885                                 /* 31     0     63    32 */
1886                                 {0x00000000u, 0x00000000u},
1888                                 /* resvdQdmaChannels */
1889                                 /* 31     0 */
1890                                 {0x00000000u},
1892                                 /* resvdTccs */
1893                                 /* 31     0     63    32 */
1894                                 {0x00000000u, 0x00000000u},
1895                         },
1897                 /* Resources owned/reserved by region 1 */
1898                         {
1899                                 /* ownPaRAMSets */
1900                                 /* 31     0     63    32     95    64     127   96 */
1901                                 {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
1902                                 /* 159  128     191  160     223  192     255  224 */
1903                                  0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1904                                 /* 287  256     319  288     351  320     383  352 */
1905                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1906                                 /* 415  384     447  416     479  448     511  480 */
1907                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1909                                 /* ownDmaChannels */
1910                                 /* 31     0     63    32 */
1911                                 {0x0000FF00u, 0x00000000u},
1913                                 /* ownQdmaChannels */
1914                                 /* 31     0 */
1915                                 {0x00000002u},
1917                                 /* ownTccs */
1918                                 /* 31     0     63    32 */
1919                                 {0x0000FF00u, 0x00000000u},
1921                                 /* resvdPaRAMSets */
1922                                 /* 31     0     63    32     95    64     127   96 */
1923                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1924                                 /* 159  128     191  160     223  192     255  224 */
1925                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1926                                 /* 287  256     319  288     351  320     383  352 */
1927                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1928                                 /* 415  384     447  416     479  448     511  480 */
1929                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1931                                 /* resvdDmaChannels */
1932                                 /* 31     0     63    32 */
1933                                 {0x00000000u, 0x00000000u},
1935                                 /* resvdQdmaChannels */
1936                                 /* 31     0 */
1937                                 {0x00000000u},
1939                                 /* resvdTccs */
1940                                 /* 31     0     63    32 */
1941                                 {0x00000000u, 0x00000000u},
1942                         },
1944                 /* Resources owned/reserved by region 2 */
1945                         {
1946                                 /* ownPaRAMSets */
1947                                 /* 31     0     63    32     95    64     127   96 */
1948                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1949                                 /* 159  128     191  160     223  192     255  224 */
1950                                  0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
1951                                 /* 287  256     319  288     351  320     383  352 */
1952                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1953                                 /* 415  384     447  416     479  448     511  480 */
1954                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1956                                 /* ownDmaChannels */
1957                                 /* 31     0     63    32 */
1958                                 {0x00FF0000u, 0x0000000u},
1960                                 /* ownQdmaChannels */
1961                                 /* 31     0 */
1962                                 {0x00000004u},
1964                                 /* ownTccs */
1965                                 /* 31     0     63    32 */
1966                                 {0x00FF0000u, 0x00000000u},
1968                                 /* resvdPaRAMSets */
1969                                 /* 31     0     63    32     95    64     127   96 */
1970                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1971                                 /* 159  128     191  160     223  192     255  224 */
1972                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1973                                 /* 287  256     319  288     351  320     383  352 */
1974                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1975                                 /* 415  384     447  416     479  448     511  480 */
1976                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1978                                 /* resvdDmaChannels */
1979                                 /* 31     0     63    32 */
1980                                 {0x00000000u, 0x00000000u},
1982                                 /* resvdQdmaChannels */
1983                                 /* 31     0 */
1984                                 {0x00000000u},
1986                                 /* resvdTccs */
1987                                 /* 31     0     63    32 */
1988                                 {0x00000000u, 0x00000000u},
1989                         },
1991                 /* Resources owned/reserved by region 3 */
1992                         {
1993                                 /* ownPaRAMSets */
1994                                 /* 31     0     63    32     95    64     127   96 */
1995                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1996                                 /* 159  128     191  160     223  192     255  224 */
1997                                  0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
1998                                 /* 287  256     319  288     351  320     383  352 */
1999                                  0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
2000                                 /* 415  384     447  416     479  448     511  480 */
2001                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
2003                                 /* ownDmaChannels */
2004                                 /* 31     0     63    32 */
2005                                 {0xFF000000u, 0x00000000u},
2007                                 /* ownQdmaChannels */
2008                                 /* 31     0 */
2009                                 {0x00000008u},
2011                                 /* ownTccs */
2012                                 /* 31     0     63    32 */
2013                                 {0xFF000000u, 0x00000000u},
2015                                 /* resvdPaRAMSets */
2016                                 /* 31     0     63    32     95    64     127   96 */
2017                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2018                                 /* 159  128     191  160     223  192     255  224 */
2019                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2020                                 /* 287  256     319  288     351  320     383  352 */
2021                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2022                                 /* 415  384     447  416     479  448     511  480 */
2023                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2025                                 /* resvdDmaChannels */
2026                                 /* 31     0     63    32 */
2027                                 {0x00000000u, 0x00000000u},
2029                                 /* resvdQdmaChannels */
2030                                 /* 31     0 */
2031                                 {0x00000000u},
2033                                 /* resvdTccs */
2034                                 /* 31     0     63    32 */
2035                                 {0x00000000u, 0x00000000u},
2036                         },
2038                 /* Resources owned/reserved by region 4 */
2039                         {
2040                                 /* ownPaRAMSets */
2041                                 /* 31     0     63    32     95    64     127   96 */
2042                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2043                                 /* 159  128     191  160     223  192     255  224 */
2044                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2045                                 /* 287  256     319  288     351  320     383  352 */
2046                                  0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
2047                                 /* 415  384     447  416     479  448     511  480 */
2048                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
2050                                 /* ownDmaChannels */
2051                                 /* 31     0     63    32 */
2052                                 {0x00000000u, 0x000000FFu},
2054                                 /* ownQdmaChannels */
2055                                 /* 31     0 */
2056                                 {0x00000010u},
2058                                 /* ownTccs */
2059                                 /* 31     0     63    32 */
2060                                 {0x00000000u, 0x000000FFu},
2062                                 /* resvdPaRAMSets */
2063                                 /* 31     0     63    32     95    64     127   96 */
2064                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2065                                 /* 159  128     191  160     223  192     255  224 */
2066                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2067                                 /* 287  256     319  288     351  320     383  352 */
2068                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2069                                 /* 415  384     447  416     479  448     511  480 */
2070                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2072                                 /* resvdDmaChannels */
2073                                 /* 31     0     63    32 */
2074                                 {0x00000000u, 0x00000000u},
2076                                 /* resvdQdmaChannels */
2077                                 /* 31     0 */
2078                                 {0x00000000u},
2080                                 /* resvdTccs */
2081                                 /* 31     0     63    32 */
2082                                 {0x00000000u, 0x00000000u},
2083                         },
2085                 /* Resources owned/reserved by region 5 */
2086                         {
2087                                 /* ownPaRAMSets */
2088                                 /* 31     0     63    32     95    64     127   96 */
2089                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2090                                 /* 159  128     191  160     223  192     255  224 */
2091                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2092                                 /* 287  256     319  288     351  320     383  352 */
2093                                  0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
2094                                 /* 415  384     447  416     479  448     511  480 */
2095                                  0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
2097                                 /* ownDmaChannels */
2098                                 /* 31     0     63    32 */
2099                                 {0x00000000u, 0x0000FF00u},
2101                                 /* ownQdmaChannels */
2102                                 /* 31     0 */
2103                                 {0x00000020u},
2105                                 /* ownTccs */
2106                                 /* 31     0     63    32 */
2107                                 {0x00000000u, 0x0000FF00u},
2109                                 /* resvdPaRAMSets */
2110                                 /* 31     0     63    32     95    64     127   96 */
2111                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2112                                 /* 159  128     191  160     223  192     255  224 */
2113                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2114                                 /* 287  256     319  288     351  320     383  352 */
2115                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2116                                 /* 415  384     447  416     479  448     511  480 */
2117                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2119                                 /* resvdDmaChannels */
2120                                 /* 31     0     63    32 */
2121                                 {0x00000000u, 0x00000000u},
2123                                 /* resvdQdmaChannels */
2124                                 /* 31     0 */
2125                                 {0x00000000u},
2127                                 /* resvdTccs */
2128                                 /* 31     0     63    32 */
2129                                 {0x00000000u, 0x00000000u},
2130                         },
2132                 /* Resources owned/reserved by region 6 */
2133                         {
2134                                 /* ownPaRAMSets */
2135                                 /* 31     0     63    32     95    64     127   96 */
2136                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2137                                 /* 159  128     191  160     223  192     255  224 */
2138                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2139                                 /* 287  256     319  288     351  320     383  352 */
2140                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2141                                 /* 415  384     447  416     479  448     511  480 */
2142                                  0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
2144                                 /* ownDmaChannels */
2145                                 /* 31     0     63    32 */
2146                                 {0x00000000u, 0x00FF0000u},
2148                                 /* ownQdmaChannels */
2149                                 /* 31     0 */
2150                                 {0x00000040u},
2152                                 /* ownTccs */
2153                                 /* 31     0     63    32 */
2154                                 {0x00000000u, 0x00FF0000u},
2156                                 /* resvdPaRAMSets */
2157                                 /* 31     0     63    32     95    64     127   96 */
2158                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2159                                 /* 159  128     191  160     223  192     255  224 */
2160                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2161                                 /* 287  256     319  288     351  320     383  352 */
2162                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2163                                 /* 415  384     447  416     479  448     511  480 */
2164                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2166                                 /* resvdDmaChannels */
2167                                 /* 31     0     63    32 */
2168                                 {0x00000000u, 0x00000000u},
2170                                 /* resvdQdmaChannels */
2171                                 /* 31     0 */
2172                                 {0x00000000u},
2174                                 /* resvdTccs */
2175                                 /* 31     0     63    32 */
2176                                 {0x00000000u, 0x00000000u},
2177                         },
2179                 /* Resources owned/reserved by region 7 */
2180                         {
2181                                 /* ownPaRAMSets */
2182                                 /* 31     0     63    32     95    64     127   96 */
2183                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2184                                 /* 159  128     191  160     223  192     255  224 */
2185                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2186                                 /* 287  256     319  288     351  320     383  352 */
2187                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2188                                 /* 415  384     447  416     479  448     511  480 */
2189                                  0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
2191                                 /* ownDmaChannels */
2192                                 /* 31     0     63    32 */
2193                                 {0x00000000u, 0xFF000000u},
2195                                 /* ownQdmaChannels */
2196                                 /* 31     0 */
2197                                 {0x00000080u},
2199                                 /* ownTccs */
2200                                 /* 31     0     63    32 */
2201                                 {0x00000000u, 0xFF000000u},
2203                                 /* resvdPaRAMSets */
2204                                 /* 31     0     63    32     95    64     127   96 */
2205                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2206                                 /* 159  128     191  160     223  192     255  224 */
2207                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2208                                 /* 287  256     319  288     351  320     383  352 */
2209                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2210                                 /* 415  384     447  416     479  448     511  480 */
2211                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2213                                 /* resvdDmaChannels */
2214                                 /* 31     0     63    32 */
2215                                 {0x00000000u, 0x00000000u},
2217                                 /* resvdQdmaChannels */
2218                                 /* 31     0 */
2219                                 {0x00000000u},
2221                                 /* resvdTccs */
2222                                 /* 31     0     63    32 */
2223                                 {0x00000000u, 0x00000000u},
2224                         },
2225                 },
2227                 /* EDMA3 INSTANCE# 3 */
2228                 {
2229                         /* Resources owned/reserved by region 0 */
2230                         {
2231                                 /* ownPaRAMSets */
2232                                 /* 31     0     63    32     95    64     127   96 */
2233                                 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
2234                                 /* 159  128     191  160     223  192     255  224 */
2235                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2236                                 /* 287  256     319  288     351  320     383  352 */
2237                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2238                                 /* 415  384     447  416     479  448     511  480 */
2239                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
2241                                 /* ownDmaChannels */
2242                                 /* 31     0     63    32 */
2243                                 {0x000000FFu, 0x00000000u},
2245                                 /* ownQdmaChannels */
2246                                 /* 31     0 */
2247                                 {0x00000001u},
2249                                 /* ownTccs */
2250                                 /* 31     0     63    32 */
2251                                 {0x000000FFu, 0x00000000u},
2253                                 /* resvdPaRAMSets */
2254                                 /* 31     0     63    32     95    64     127   96 */
2255                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
2256                                 /* 159  128     191  160     223  192     255  224 */
2257                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2258                                 /* 287  256     319  288     351  320     383  352 */
2259                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
2260                                 /* 415  384     447  416     479  448     511  480 */
2261                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
2263                                 /* resvdDmaChannels */
2264                                 /* 31     0     63    32 */
2265                                 {0x00000000u, 0x00000000u},
2267                      &nbs