packages/ti/sdo/edma3/drv/docs/html/edma3_8h.html

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  25 <h1>edma3.h File Reference</h1>EDMA3 Driver Internal header file.
  26 <a href="#_details">More...</a>
  27 <p>
  28 <code>#include &lt;<a class="el" href="edma3__drv_8h_source.html">ti/sdo/edma3/drv/edma3_drv.h</a>&gt;</code><br>
  29 <code>#include &lt;ti/sdo/edma3/rm/src/edma3_rl_cc.h&gt;</code><br>
  30
  31 <p>
  32 <a href="edma3_8h_source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
  33 <tr><td></td></tr>
  34 <tr><td colspan="2"><br><h2>Data Structures</h2></td></tr>
  35 <tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__Object.html">EDMA3_DRV_Object</a></td></tr>
  36
  37 <tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EDMA3 Driver Object (HW Specific) Maintenance structure.  <a href="structEDMA3__DRV__Object.html#_details">More...</a><br></td></tr>
  38 <tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__Instance.html">EDMA3_DRV_Instance</a></td></tr>
  39
  40 <tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EDMA3 Driver Instance Configuration Structure.  <a href="structEDMA3__DRV__Instance.html#_details">More...</a><br></td></tr>
  41 <tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__ChBoundResources.html">EDMA3_DRV_ChBoundResources</a></td></tr>
  42
  43 <tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EDMA3 Channel-Bound resources.  <a href="structEDMA3__DRV__ChBoundResources.html#_details">More...</a><br></td></tr>
  44 <tr><td colspan="2"><br><h2>Defines</h2></td></tr>
  45 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g8f8eb3bcb034cb9b8894e13446cb1cbc">EDMA3_DRV_OPT_SAM_CLR_MASK</a>&nbsp;&nbsp;&nbsp;(~EDMA3_CCRL_OPT_SAM_MASK)</td></tr>
  46
  47 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#gfac07539fb70302972cda2e399b55d2d">EDMA3_DRV_OPT_SAM_SET_MASK</a>(mode)&nbsp;&nbsp;&nbsp;(((EDMA3_CCRL_OPT_SAM_MASK &gt;&gt; EDMA3_CCRL_OPT_SAM_SHIFT) &amp; (mode)) &lt;&lt; EDMA3_CCRL_OPT_SAM_SHIFT)</td></tr>
  48
  49 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g7124c266cca1721d0c581a0987db710c">EDMA3_DRV_OPT_DAM_CLR_MASK</a>&nbsp;&nbsp;&nbsp;(~EDMA3_CCRL_OPT_DAM_MASK)</td></tr>
  50
  51 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g830dd86288eb7689c9d0b1d9efffd8dc">EDMA3_DRV_OPT_DAM_SET_MASK</a>(mode)&nbsp;&nbsp;&nbsp;(((EDMA3_CCRL_OPT_DAM_MASK &gt;&gt; EDMA3_CCRL_OPT_DAM_SHIFT) &amp; (mode)) &lt;&lt; EDMA3_CCRL_OPT_DAM_SHIFT)</td></tr>
  52
  53 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g94a55c484f8b28d1330b2f7439fc3bb5">EDMA3_DRV_OPT_SYNCDIM_CLR_MASK</a>&nbsp;&nbsp;&nbsp;(~EDMA3_CCRL_OPT_SYNCDIM_MASK)</td></tr>
  54
  55 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#gadeb814822eb88413ad0b477daaf5618">EDMA3_DRV_OPT_SYNCDIM_SET_MASK</a>(synctype)&nbsp;&nbsp;&nbsp;(((EDMA3_CCRL_OPT_SYNCDIM_MASK &gt;&gt; EDMA3_CCRL_OPT_SYNCDIM_SHIFT) &amp; (synctype)) &lt;&lt; EDMA3_CCRL_OPT_SYNCDIM_SHIFT)</td></tr>
  56
  57 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#gf98e3b1c0a6f706c7912e0553869c0d8">EDMA3_DRV_OPT_STATIC_CLR_MASK</a>&nbsp;&nbsp;&nbsp;(~EDMA3_CCRL_OPT_STATIC_MASK)</td></tr>
  58
  59 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#gc8f0463136b315d05eeb92f368d8fa4b">EDMA3_DRV_OPT_STATIC_SET_MASK</a>(en)&nbsp;&nbsp;&nbsp;(((EDMA3_CCRL_OPT_STATIC_MASK &gt;&gt; EDMA3_CCRL_OPT_STATIC_SHIFT) &amp; (en)) &lt;&lt; EDMA3_CCRL_OPT_STATIC_SHIFT)</td></tr>
  60
  61 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#ge27f77f2edda76ba51366aeb272d4e60">EDMA3_DRV_OPT_FWID_CLR_MASK</a>&nbsp;&nbsp;&nbsp;(~EDMA3_CCRL_OPT_FWID_MASK)</td></tr>
  62
  63 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g4792ca2a3e861f72de9cda47620fecdd">EDMA3_DRV_OPT_FWID_SET_MASK</a>(width)&nbsp;&nbsp;&nbsp;(((EDMA3_CCRL_OPT_FWID_MASK &gt;&gt; EDMA3_CCRL_OPT_FWID_SHIFT) &amp; (width)) &lt;&lt; EDMA3_CCRL_OPT_FWID_SHIFT)</td></tr>
  64
  65 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g1217ef163c2dd075395a2df88cb360c4">EDMA3_DRV_OPT_TCCMODE_CLR_MASK</a>&nbsp;&nbsp;&nbsp;(~EDMA3_CCRL_OPT_TCCMODE_MASK)</td></tr>
  66
  67 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g699cfa20a6cef0ef068bb7a153728bdd">EDMA3_DRV_OPT_TCCMODE_SET_MASK</a>(early)&nbsp;&nbsp;&nbsp;(((EDMA3_CCRL_OPT_TCCMODE_MASK &gt;&gt; EDMA3_CCRL_OPT_TCCMODE_SHIFT) &amp; (early)) &lt;&lt; EDMA3_CCRL_OPT_TCCMODE_SHIFT)</td></tr>
  68
  69 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#gc1f0ef888662367807c19f2b90e768da">EDMA3_DRV_OPT_TCC_CLR_MASK</a>&nbsp;&nbsp;&nbsp;(~EDMA3_CCRL_OPT_TCC_MASK)</td></tr>
  70
  71 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g3a66ad0a56b1cffc77a24f317fc9c187">EDMA3_DRV_OPT_TCC_SET_MASK</a>(tcc)&nbsp;&nbsp;&nbsp;(((EDMA3_CCRL_OPT_TCC_MASK &gt;&gt; EDMA3_CCRL_OPT_TCC_SHIFT) &amp; (tcc)) &lt;&lt; EDMA3_CCRL_OPT_TCC_SHIFT)</td></tr>
  72
  73 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g79ff6a50b02e1274982bdbf2cbcbde45">EDMA3_DRV_OPT_TCINTEN_CLR_MASK</a>&nbsp;&nbsp;&nbsp;(~EDMA3_CCRL_OPT_TCINTEN_MASK)</td></tr>
  74
  75 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#gb28ac1ef05e45d68493889185c089d8b">EDMA3_DRV_OPT_TCINTEN_SET_MASK</a>(tcinten)&nbsp;&nbsp;&nbsp;(((EDMA3_CCRL_OPT_TCINTEN_MASK &gt;&gt; EDMA3_CCRL_OPT_TCINTEN_SHIFT) &amp; (tcinten)) &lt;&lt; EDMA3_CCRL_OPT_TCINTEN_SHIFT)</td></tr>
  76
  77 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#gd6691f3ab6360542be3608f1f0d30f94">EDMA3_DRV_OPT_ITCINTEN_CLR_MASK</a>&nbsp;&nbsp;&nbsp;(~EDMA3_CCRL_OPT_ITCINTEN_MASK)</td></tr>
  78
  79 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#ga09f19c778bd3f79d818f9ddfcfa4527">EDMA3_DRV_OPT_ITCINTEN_SET_MASK</a>(itcinten)&nbsp;&nbsp;&nbsp;(((EDMA3_CCRL_OPT_ITCINTEN_MASK &gt;&gt; EDMA3_CCRL_OPT_ITCINTEN_SHIFT) &amp; (itcinten)) &lt;&lt; EDMA3_CCRL_OPT_ITCINTEN_SHIFT)</td></tr>
  80
  81 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#gf65c01f6b6d98350641cfd7d44c9fe29">EDMA3_DRV_OPT_TCCHEN_CLR_MASK</a>&nbsp;&nbsp;&nbsp;(~EDMA3_CCRL_OPT_TCCHEN_MASK)</td></tr>
  82
  83 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#gb6bf27d49bee8718d6bcadc7db5846f2">EDMA3_DRV_OPT_TCCHEN_SET_MASK</a>(tcchen)&nbsp;&nbsp;&nbsp;(((EDMA3_CCRL_OPT_TCCHEN_MASK &gt;&gt; EDMA3_CCRL_OPT_TCCHEN_SHIFT) &amp; (tcchen)) &lt;&lt; EDMA3_CCRL_OPT_TCCHEN_SHIFT)</td></tr>
  84
  85 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g03c733b9efc0cacad5d723df42965417">EDMA3_DRV_OPT_ITCCHEN_CLR_MASK</a>&nbsp;&nbsp;&nbsp;(~EDMA3_CCRL_OPT_ITCCHEN_MASK)</td></tr>
  86
  87 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g392b347ff043e8c01f09fcd26afdb5ae">EDMA3_DRV_OPT_ITCCHEN_SET_MASK</a>(itcchen)&nbsp;&nbsp;&nbsp;(((EDMA3_CCRL_OPT_ITCCHEN_MASK &gt;&gt; EDMA3_CCRL_OPT_ITCCHEN_SHIFT) &amp; (itcchen)) &lt;&lt; EDMA3_CCRL_OPT_ITCCHEN_SHIFT)</td></tr>
  88
  89 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g37e90d4750a3507557edbcf1abea72f1">EDMA3_DRV_OPT_SAM_GET_MASK</a>(mode)&nbsp;&nbsp;&nbsp;((mode)&amp;1u)</td></tr>
  90
  91 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#ge57f580330feda1404eae500aa188027">EDMA3_DRV_OPT_DAM_GET_MASK</a>(mode)&nbsp;&nbsp;&nbsp;(((mode)&amp;(1u&lt;&lt;1u))&gt;&gt;1u)</td></tr>
  92
  93 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g850dbfb8d30c7c88946f16c3e72ddc6f">EDMA3_DRV_OPT_SYNCDIM_GET_MASK</a>(synctype)&nbsp;&nbsp;&nbsp;(((synctype)&amp;(1u&lt;&lt;2u))&gt;&gt;2u)</td></tr>
  94
  95 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#ge6fb4041cb351778896d9e5f36cc93ec">EDMA3_DRV_OPT_STATIC_GET_MASK</a>(en)&nbsp;&nbsp;&nbsp;(((en)&amp;(1u&lt;&lt;3u))&gt;&gt;3u)</td></tr>
  96
  97 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#geb1a9f25696e29ded8385098c2d0b5dd">EDMA3_DRV_OPT_FWID_GET_MASK</a>(width)&nbsp;&nbsp;&nbsp;(((width)&amp;(0x7u&lt;&lt;8u))&gt;&gt;8u)</td></tr>
  98
  99 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g10ff431c1470c80b671630325aa1daf3">EDMA3_DRV_OPT_TCCMODE_GET_MASK</a>(early)&nbsp;&nbsp;&nbsp;(((early)&amp;(1u&lt;&lt;11u))&gt;&gt;11u)</td></tr>
 100
 101 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g8bff94ce4e06d6ceff4d1a349d156772">EDMA3_DRV_OPT_TCC_GET_MASK</a>(tcc)&nbsp;&nbsp;&nbsp;(((tcc)&amp;(0x3fu&lt;&lt;12u))&gt;&gt;12u)</td></tr>
 102
 103 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g89003543d2cac8863f5ccc499b49544f">EDMA3_DRV_OPT_TCINTEN_GET_MASK</a>(tcinten)&nbsp;&nbsp;&nbsp;(((tcinten)&amp;(1u&lt;&lt;20u))&gt;&gt;20u)</td></tr>
 104
 105 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g233e949db2fdfdbd9fbf59087ed55cc3">EDMA3_DRV_OPT_ITCINTEN_GET_MASK</a>(itcinten)&nbsp;&nbsp;&nbsp;(((itcinten)&amp;(1u&lt;&lt;21u))&gt;&gt;21u)</td></tr>
 106
 107 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g4035b86365bd33f8fefa580727dee8b6">EDMA3_DRV_OPT_TCCHEN_GET_MASK</a>(tcchen)&nbsp;&nbsp;&nbsp;(((tcchen)&amp;(1u&lt;&lt;22u))&gt;&gt;22u)</td></tr>
 108
 109 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g72c380703011132ce0d9ac3785fbeb3c">EDMA3_DRV_OPT_ITCCHEN_GET_MASK</a>(itcchen)&nbsp;&nbsp;&nbsp;(((itcchen)&amp;(1u&lt;&lt;23u))&gt;&gt;23u)</td></tr>
 110
 111 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g409f66cdeb5f189a8d687a1fb06b628b">EDMA3_DRV_DMAQNUM_CLR_MASK</a>(chNum)&nbsp;&nbsp;&nbsp;(~(0x7u&lt;&lt;(((chNum)%8u)*4u)))</td></tr>
 112
 113 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g9565d8cf85587d078e6461d70c37a076">EDMA3_DRV_DMAQNUM_SET_MASK</a>(chNum, queNum)&nbsp;&nbsp;&nbsp;((0x7u &amp; (queNum)) &lt;&lt; (((chNum)%8u)*4u))</td></tr>
 114
 115 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#gaad5f60f99c4eb458e673eeaeae3b010">EDMA3_DRV_QDMAQNUM_CLR_MASK</a>(chNum)&nbsp;&nbsp;&nbsp;(~(0x7u&lt;&lt;((chNum)*4u)))</td></tr>
 116
 117 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g1019bc830c16ce5e5557e9ffa77c1849">EDMA3_DRV_QDMAQNUM_SET_MASK</a>(chNum, queNum)&nbsp;&nbsp;&nbsp;((0x7u &amp; (queNum)) &lt;&lt; ((chNum)*4u))</td></tr>
 118
 119 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#gca673583173065e21138c48dbb9178c2">EDMA3_DRV_QCH_TRWORD_CLR_MASK</a>&nbsp;&nbsp;&nbsp;(~EDMA3_CCRL_QCHMAP_TRWORD_MASK)</td></tr>
 120
 121 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g2e860c4dd4f300b8e525459265badf00">EDMA3_DRV_QCH_TRWORD_SET_MASK</a>(paRAMId)&nbsp;&nbsp;&nbsp;(((EDMA3_CCRL_QCHMAP_TRWORD_MASK &gt;&gt; EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) &amp; (paRAMId)) &lt;&lt; EDMA3_CCRL_QCHMAP_TRWORD_SHIFT)</td></tr>
 122
 123 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g327c61c1c3bd1a8626422740afe1ba87">EDMA3_DRV_ACNT_MAX_VAL</a>&nbsp;&nbsp;&nbsp;(0xFFFFu)</td></tr>
 124
 125 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#gcddc884a7f04818a5414f50d47f6557a">EDMA3_DRV_BCNT_MAX_VAL</a>&nbsp;&nbsp;&nbsp;(0xFFFFu)</td></tr>
 126
 127 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g7a7b3a05a0df24ca4c6a9eecb67eb3a0">EDMA3_DRV_CCNT_MAX_VAL</a>&nbsp;&nbsp;&nbsp;(0xFFFFu)</td></tr>
 128
 129 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g6b632c36ba341b121084b4cace4ab08a">EDMA3_DRV_BCNTRELD_MAX_VAL</a>&nbsp;&nbsp;&nbsp;(0xFFFFu)</td></tr>
 130
 131 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#ga303a99313f06c4cc5847808e77a62f7">EDMA3_DRV_SRCBIDX_MAX_VAL</a>&nbsp;&nbsp;&nbsp;(0x7FFF)</td></tr>
 132
 133 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g2d7dcd81496ec940fdb4f12f4097cc58">EDMA3_DRV_SRCBIDX_MIN_VAL</a>&nbsp;&nbsp;&nbsp;(-32768)</td></tr>
 134
 135 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#gdee65d5b901dc0f1389b5893671ceaec">EDMA3_DRV_SRCCIDX_MAX_VAL</a>&nbsp;&nbsp;&nbsp;(0x7FFF)</td></tr>
 136
 137 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g0ba07ebff0ad43098a897c82a4e3a770">EDMA3_DRV_SRCCIDX_MIN_VAL</a>&nbsp;&nbsp;&nbsp;(-32768)</td></tr>
 138
 139 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g61db4ad0efd771e5a6529d5317eb6868">EDMA3_DRV_DSTBIDX_MAX_VAL</a>&nbsp;&nbsp;&nbsp;(0x7FFF)</td></tr>
 140
 141 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g69be49afebad0d5f51a7c22e63e997da">EDMA3_DRV_DSTBIDX_MIN_VAL</a>&nbsp;&nbsp;&nbsp;(-32768)</td></tr>
 142
 143 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#gce9c681ea369ac518637d0230779b81d">EDMA3_DRV_DSTCIDX_MAX_VAL</a>&nbsp;&nbsp;&nbsp;(0x7FFF)</td></tr>
 144
 145 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#ge82b7e659498b89776bb911ef2be57ff">EDMA3_DRV_DSTCIDX_MIN_VAL</a>&nbsp;&nbsp;&nbsp;(-32768)</td></tr>
 146
 147 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g6df53975e4e70e768939803cbf70731c">EDMA3_DRV_QPRIORITY_MAX_VAL</a>&nbsp;&nbsp;&nbsp;(7u)</td></tr>
 148
 149 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g5447af2e6fe703656d1d8970907be8d0">EDMA3_DRV_QPRIORITY_MIN_VAL</a>&nbsp;&nbsp;&nbsp;(0u)</td></tr>
 150
 151 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvIntBoundVals.html#g693594a030677f7a98982fa5e984eb24">EDMA3_DRV_DMA_CH_MAX_VAL</a>&nbsp;&nbsp;&nbsp;(EDMA3_MAX_DMA_CH - 1u)</td></tr>
 152
 153 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvIntBoundVals.html#gd11d223c31c4a866579d24824651c32e">EDMA3_DRV_LINK_CH_MIN_VAL</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_DMA_CH_MAX_VAL + 1u)</td></tr>
 154
 155 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvIntBoundVals.html#g80def5ca49ced66788a60a5c4aaf86df">EDMA3_DRV_LINK_CH_MAX_VAL</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_LINK_CH_MIN_VAL + EDMA3_MAX_PARAM_SETS - 1u)</td></tr>
 156
 157 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvIntBoundVals.html#gb774d59e32745cfb92efad6c95c1a03a">EDMA3_DRV_QDMA_CH_MIN_VAL</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_LINK_CH_MAX_VAL + 1u)</td></tr>
 158
 159 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvIntBoundVals.html#g7387c6c088b73459e5e687a906872d40">EDMA3_DRV_QDMA_CH_MAX_VAL</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CH_MIN_VAL + EDMA3_MAX_QDMA_CH - 1u)</td></tr>
 160
 161 <tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvIntBoundVals.html#g284b41342f06d48c42dfeff6e5fb99d4">EDMA3_DRV_LOG_CH_MAX_VAL</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CH_MAX_VAL)</td></tr>
 162
 163 <tr><td colspan="2"><br><h2>Enumerations</h2></td></tr>
 164 <tr><td class="memItemLeft" nowrap align="right" valign="top">enum &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvIntObjMaint.html#g3ffbc9f29815ad0c419628ffd48773e2">EDMA3_DRV_ObjState</a> { <br>
 165 &nbsp;&nbsp;<a class="el" href="group__Edma3DrvIntObjMaint.html#gg3ffbc9f29815ad0c419628ffd48773e2c63bb19f6bb9201ede0ab01fee8cc2c8">EDMA3_DRV_DELETED</a> =  0,
 166 <br>
 167 &nbsp;&nbsp;<a class="el" href="group__Edma3DrvIntObjMaint.html#gg3ffbc9f29815ad0c419628ffd48773e2156b61cc903b7f968f4fa3c6879279a1">EDMA3_DRV_CREATED</a> =  1,
 168 <br>
 169 &nbsp;&nbsp;<a class="el" href="group__Edma3DrvIntObjMaint.html#gg3ffbc9f29815ad0c419628ffd48773e2c6942f4b9d254339a0a9c7a9b681e000">EDMA3_DRV_OPENED</a> =  2,
 170 <br>
 171 &nbsp;&nbsp;<a class="el" href="group__Edma3DrvIntObjMaint.html#gg3ffbc9f29815ad0c419628ffd48773e263c09aac2aa49bb0d853a27a07e64906">EDMA3_DRV_CLOSED</a> =  3
 172 <br>
 173  }</td></tr>
 174
 175 <tr><td class="memItemLeft" nowrap align="right" valign="top">enum &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvInt.html#g109b96a7254584040923bf5c1218114b">EDMA3_DRV_ChannelType</a> { <br>
 176 &nbsp;&nbsp;<a class="el" href="group__Edma3DrvInt.html#gg109b96a7254584040923bf5c1218114b9ecdf7e60c4b3c2f0b79e9e312515967">EDMA3_DRV_CHANNEL_TYPE_NONE</a>,
 177 <br>
 178 &nbsp;&nbsp;<a class="el" href="group__Edma3DrvInt.html#gg109b96a7254584040923bf5c1218114b6dc7145a399d00eb24cfb274f7818aac">EDMA3_DRV_CHANNEL_TYPE_DMA</a> =  1,
 179 <br>
 180 &nbsp;&nbsp;<a class="el" href="group__Edma3DrvInt.html#gg109b96a7254584040923bf5c1218114b02501491279cad3d6f1a835d34f014ad">EDMA3_DRV_CHANNEL_TYPE_QDMA</a> =  2,
 181 <br>
 182 &nbsp;&nbsp;<a class="el" href="group__Edma3DrvInt.html#gg109b96a7254584040923bf5c1218114bf7114acddb9776d14b223f9e87a29736">EDMA3_DRV_CHANNEL_TYPE_LINK</a> =  3
 183 <br>
 184  }</td></tr>
 185
 186 <tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EDMA3 Channel Type.  <a href="group__Edma3DrvInt.html#g109b96a7254584040923bf5c1218114b">More...</a><br></td></tr>
 187 </table>
 188 <hr><h2>Detailed Description</h2>
 189 EDMA3 Driver Internal header file.
 190 <p>
 191 This file contains implementation specific details used by the EDMA3 Driver internally.<p>
 192 (C) Copyright 2006, Texas Instruments, Inc </div>
 193 <hr size="1"><address style="text-align: right;"><small>Generated on Wed Jun 3 22:19:11 2009 for EDMA3 Driver by&nbsp;
 194 <a href="http://www.doxygen.org/index.html">
 195 <img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.5.9 </small></address>
 196 </body>
 197 </html>