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21 <h1>EDMA3 Driver Advanced APIs<br/>
22 <small>
23 [<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n.html">EDMA3 Driver APIs</a>]</small>
24 </h1><table border="0" cellpadding="0" cellspacing="0">
25 <tr><td colspan="2"><h2>Data Structures</h2></td></tr>
26 <tr><td class="memItemLeft" align="right" valign="top">struct </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a></td></tr>
27 <tr><td class="mdescLeft"> </td><td class="mdescRight">Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. <a href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html#_details">More...</a><br/></td></tr>
28 <tr><td colspan="2"><h2>Typedefs</h2></td></tr>
29 <tr><td class="memItemLeft" align="right" valign="top">typedef EDMA3_DRV_Result(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gae7867a62f61919df85b323ce981163e4">EDMA3_DRV_mapXbarEvtToChan</a> )(unsigned int eventNum, unsigned int *chanNum, const <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a> *edmaGblXbarConfig)</td></tr>
30 <tr><td class="mdescLeft"> </td><td class="mdescRight">Associates cross bar mapped event to channel. <a href="#gae7867a62f61919df85b323ce981163e4"></a><br/></td></tr>
31 <tr><td class="memItemLeft" align="right" valign="top">typedef EDMA3_DRV_Result(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga02168cc5612b65b34812ce52df7154a3">EDMA3_DRV_xbarConfigScr</a> )(unsigned int eventNum, unsigned int chanNum)</td></tr>
32 <tr><td class="mdescLeft"> </td><td class="mdescRight">Writes to the cross bar mapped event to channel to system configuration register. <a href="#ga02168cc5612b65b34812ce52df7154a3"></a><br/></td></tr>
33 <tr><td colspan="2"><h2>Functions</h2></td></tr>
34 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaa8561ee446bd1b9d0c5c4b106c9f40a9">EDMA3_DRV_linkChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2)</td></tr>
35 <tr><td class="mdescLeft"> </td><td class="mdescRight">Link two logical channels. <a href="#gaa8561ee446bd1b9d0c5c4b106c9f40a9"></a><br/></td></tr>
36 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaca6ef38f26d8e043352fa8963b7f090a">EDMA3_DRV_unlinkChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh)</td></tr>
37 <tr><td class="mdescLeft"> </td><td class="mdescRight">Unlink the channel from the earlier linked logical channel. <a href="#gaca6ef38f26d8e043352fa8963b7f090a"></a><br/></td></tr>
38 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gab8e524124e4aaa158fcaf494798def5e">EDMA3_DRV_chainChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2, const <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html">EDMA3_DRV_ChainOptions</a> *chainOptions)</td></tr>
39 <tr><td class="mdescLeft"> </td><td class="mdescRight">Chain the two specified channels. <a href="#gab8e524124e4aaa158fcaf494798def5e"></a><br/></td></tr>
40 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gad6424fda12e9b6cccae47ccb22207bcf">EDMA3_DRV_unchainChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh)</td></tr>
41 <tr><td class="mdescLeft"> </td><td class="mdescRight">Unchain the two channels. <a href="#gad6424fda12e9b6cccae47ccb22207bcf"></a><br/></td></tr>
42 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga669ea0f2097604af17b9213a28985191">EDMA3_DRV_setQdmaTrigWord</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_RM_QdmaTrigWord trigWord)</td></tr>
43 <tr><td class="mdescLeft"> </td><td class="mdescRight">Assign a Trigger Word to the specified QDMA channel. <a href="#ga669ea0f2097604af17b9213a28985191"></a><br/></td></tr>
44 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga77841fc83e3876a3014963404cfc08ba">EDMA3_DRV_setPaRAM</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, const <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html">EDMA3_DRV_PaRAMRegs</a> *newPaRAM)</td></tr>
45 <tr><td class="mdescLeft"> </td><td class="mdescRight">Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link). <a href="#ga77841fc83e3876a3014963404cfc08ba"></a><br/></td></tr>
46 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga437d851ec0eb6c05bb118886ee5c17f2">EDMA3_DRV_getPaRAM</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html">EDMA3_DRV_PaRAMRegs</a> *currPaRAM)</td></tr>
47 <tr><td class="mdescLeft"> </td><td class="mdescRight">Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link). <a href="#ga437d851ec0eb6c05bb118886ee5c17f2"></a><br/></td></tr>
48 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga83bcb5bc4e319fd6e78466ab5df5c0ac">EDMA3_DRV_setPaRAMEntry</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga82b01ec2292a13ad48a5bfcc724dfac6">EDMA3_DRV_PaRAMEntry</a> paRAMEntry, unsigned int newPaRAMEntryVal)</td></tr>
49 <tr><td class="mdescLeft"> </td><td class="mdescRight">Set a particular PaRAM set entry of the specified PaRAM set. <a href="#ga83bcb5bc4e319fd6e78466ab5df5c0ac"></a><br/></td></tr>
50 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga443b63758caa5383ef0f9f66b29fb5e8">EDMA3_DRV_getPaRAMEntry</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga82b01ec2292a13ad48a5bfcc724dfac6">EDMA3_DRV_PaRAMEntry</a> paRAMEntry, unsigned int *paRAMEntryVal)</td></tr>
51 <tr><td class="mdescLeft"> </td><td class="mdescRight">Get a particular PaRAM set entry of the specified PaRAM set. <a href="#ga443b63758caa5383ef0f9f66b29fb5e8"></a><br/></td></tr>
52 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga41151895e480b66bf320ec662506f078">EDMA3_DRV_setPaRAMField</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga3e31ba1b02dcbace3044c11c83ef5466">EDMA3_DRV_PaRAMField</a> paRAMField, unsigned int newPaRAMFieldVal)</td></tr>
53 <tr><td class="mdescLeft"> </td><td class="mdescRight">Set a particular PaRAM set field of the specified PaRAM set. <a href="#ga41151895e480b66bf320ec662506f078"></a><br/></td></tr>
54 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga1254ca24861fd4b580010f118f093b51">EDMA3_DRV_getPaRAMField</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga3e31ba1b02dcbace3044c11c83ef5466">EDMA3_DRV_PaRAMField</a> paRAMField, unsigned int *currPaRAMFieldVal)</td></tr>
55 <tr><td class="mdescLeft"> </td><td class="mdescRight">Get a particular PaRAM set field of the specified PaRAM set. <a href="#ga1254ca24861fd4b580010f118f093b51"></a><br/></td></tr>
56 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga6a6c40cddb7bb7bc74635e104757e225">EDMA3_DRV_setEvtQPriority</a> (EDMA3_DRV_Handle hEdma, const <a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html">EDMA3_DRV_EvtQuePriority</a> *evtQPriObj)</td></tr>
57 <tr><td class="mdescLeft"> </td><td class="mdescRight">Sets EDMA TC priority. <a href="#ga6a6c40cddb7bb7bc74635e104757e225"></a><br/></td></tr>
58 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga4419ae8ba6468ec35090e2717a28f958">EDMA3_DRV_mapChToEvtQ</a> (EDMA3_DRV_Handle hEdma, unsigned int channelId, EDMA3_RM_EventQueue eventQ)</td></tr>
59 <tr><td class="mdescLeft"> </td><td class="mdescRight">Associate Channel to Event Queue. <a href="#ga4419ae8ba6468ec35090e2717a28f958"></a><br/></td></tr>
60 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gab2058b44b471c44d001035e1a38fd06d">EDMA3_DRV_getMapChToEvtQ</a> (EDMA3_DRV_Handle hEdma, unsigned int channelId, unsigned int *mappedEvtQ)</td></tr>
61 <tr><td class="mdescLeft"> </td><td class="mdescRight">Get the Event Queue mapped to the specified DMA/QDMA channel. <a href="#gab2058b44b471c44d001035e1a38fd06d"></a><br/></td></tr>
62 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga2574c3da30322981b763e54dd1ea7fb2">EDMA3_DRV_setCCRegister</a> (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int newRegValue)</td></tr>
63 <tr><td class="mdescLeft"> </td><td class="mdescRight">Set the Channel Controller (CC) Register value. <a href="#ga2574c3da30322981b763e54dd1ea7fb2"></a><br/></td></tr>
64 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga297f964f8fa3df44683e1bdedd56d928">EDMA3_DRV_getCCRegister</a> (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int *regValue)</td></tr>
65 <tr><td class="mdescLeft"> </td><td class="mdescRight">Get the Channel Controller (CC) Register value. <a href="#ga297f964f8fa3df44683e1bdedd56d928"></a><br/></td></tr>
66 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaa73fe4d0c29760be55306a8fc1f35161">EDMA3_DRV_waitAndClearTcc</a> (EDMA3_DRV_Handle hEdma, unsigned int tccNo)</td></tr>
67 <tr><td class="mdescLeft"> </td><td class="mdescRight">Wait for a transfer completion interrupt to occur and clear it. <a href="#gaa73fe4d0c29760be55306a8fc1f35161"></a><br/></td></tr>
68 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga3c098a85435e55a8eff2561cbcd79a77">EDMA3_DRV_checkAndClearTcc</a> (EDMA3_DRV_Handle hEdma, unsigned int tccNo, unsigned short *tccStatus)</td></tr>
69 <tr><td class="mdescLeft"> </td><td class="mdescRight">Returns the status of a previously initiated transfer. <a href="#ga3c098a85435e55a8eff2561cbcd79a77"></a><br/></td></tr>
70 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gafeb7b2a17615b14bdac9b11af69e5142">EDMA3_DRV_getPaRAMPhyAddr</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *paramPhyAddr)</td></tr>
71 <tr><td class="mdescLeft"> </td><td class="mdescRight">Get the PaRAM Set Physical Address associated with a logical channel. <a href="#gafeb7b2a17615b14bdac9b11af69e5142"></a><br/></td></tr>
72 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga379162d6a5076160d4ed2e01ca8dcac6">EDMA3_DRV_Ioctl</a> (EDMA3_DRV_Handle hEdma, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8577940463f7ca5a8977b2fb65fae19a">EDMA3_DRV_IoctlCmd</a> cmd, void *cmdArg, void *param)</td></tr>
73 <tr><td class="mdescLeft"> </td><td class="mdescRight">EDMA3 Driver IOCTL. <a href="#ga379162d6a5076160d4ed2e01ca8dcac6"></a><br/></td></tr>
74 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Handle </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga866c17eaf78a3e0ddc83a397b91fe850">EDMA3_DRV_getInstHandle</a> (unsigned int phyCtrllerInstId, EDMA3_RM_RegionId regionId, EDMA3_DRV_Result *errorCode)</td></tr>
75 <tr><td class="mdescLeft"> </td><td class="mdescRight">Return the previously opened EDMA3 Driver Instance handle. <a href="#ga866c17eaf78a3e0ddc83a397b91fe850"></a><br/></td></tr>
76 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga43031c6c66af92677c388c156b50480b">EDMA3_DRV_registerTccCb</a> (EDMA3_DRV_Handle hEdma, const unsigned int channelId, EDMA3_RM_TccCallback tccCb, void *cbData)</td></tr>
77 <tr><td class="mdescLeft"> </td><td class="mdescRight">Registers a transfer completion handler for a specific DMA/QDMA channel. <a href="#ga43031c6c66af92677c388c156b50480b"></a><br/></td></tr>
78 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaa4ab2ce058e4e40a812b8a20970d4088">EDMA3_DRV_unregisterTccCb</a> (EDMA3_DRV_Handle hEdma, const unsigned int channelId)</td></tr>
79 <tr><td class="mdescLeft"> </td><td class="mdescRight">Un-register the previously registered callback function against a DMA/QDMA channel. <a href="#gaa4ab2ce058e4e40a812b8a20970d4088"></a><br/></td></tr>
80 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga276f4ecd7f1e59f09ad065b633643ae4">EDMA3_DRV_setTcErrorInt</a> (unsigned int phyCtrllerInstId, unsigned int tcId, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga2b3b55b1d7c987a7873d8b0b085173b2">EDMA3_DRV_Tc_Err</a> tcErr)</td></tr>
81 <tr><td class="mdescLeft"> </td><td class="mdescRight">Enable/disable specific EDMA3 Transfer Controller Interrupts. <a href="#ga276f4ecd7f1e59f09ad065b633643ae4"></a><br/></td></tr>
82 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga85bad51ec992ce36ed7f28842b7d8219">EDMA3_DRV_getChannelStatus</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *lchStatus)</td></tr>
83 <tr><td class="mdescLeft"> </td><td class="mdescRight">Get the current status of the DMA/QDMA channel. <a href="#ga85bad51ec992ce36ed7f28842b7d8219"></a><br/></td></tr>
84 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaba9535a00375255494df382382b834de">EDMA3_DRV_mapTccLinkCh</a> (EDMA3_DRV_Handle hEdma, unsigned int linkCh, unsigned int tcc)</td></tr>
85 <tr><td class="mdescLeft"> </td><td class="mdescRight">Associates a link channel and a TCC. <a href="#gaba9535a00375255494df382382b834de"></a><br/></td></tr>
86 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga1ff9d2ede0fb29c7194f15ba58ad8e0f">EDMA3_DRV_initXbarEventMap</a> (EDMA3_DRV_Handle hEdma, const <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a> *edmaGblXbarConfig, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gae7867a62f61919df85b323ce981163e4">EDMA3_DRV_mapXbarEvtToChan</a> mapXbarEvtFunc, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga02168cc5612b65b34812ce52df7154a3">EDMA3_DRV_xbarConfigScr</a> configXbarScr)</td></tr>
87 <tr><td class="mdescLeft"> </td><td class="mdescRight">Initialize the cross bar mapped event to channel function. <a href="#ga1ff9d2ede0fb29c7194f15ba58ad8e0f"></a><br/></td></tr>
88 </table>
89 <hr/><h2>Typedef Documentation</h2>
90 <a class="anchor" id="gae7867a62f61919df85b323ce981163e4"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_mapXbarEvtToChan" ref="gae7867a62f61919df85b323ce981163e4" args=")(unsigned int eventNum, unsigned int *chanNum, const EDMA3_DRV_GblXbarToChanConfigParams *edmaGblXbarConfig)" -->
91 <div class="memitem">
92 <div class="memproto">
93 <table class="memname">
94 <tr>
95 <td class="memname">typedef EDMA3_DRV_Result(* <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gae7867a62f61919df85b323ce981163e4">EDMA3_DRV_mapXbarEvtToChan</a>)(unsigned int eventNum, unsigned int *chanNum, const <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a> *edmaGblXbarConfig)</td>
96 </tr>
97 </table>
98 </div>
99 <div class="memdoc">
101 <p>Associates cross bar mapped event to channel. </p>
102 <p>This function have to be defined in the configuration file. This function will be called only if the channel requested for is beyond the maximum number of channels. This function should read from the global cross bar mapped configuration data structure and return the mapped channel number to this event.</p>
103 <dl><dt><b>Parameters:</b></dt><dd>
104 <table border="0" cellspacing="2" cellpadding="0">
105 <tr><td valign="top"></td><td valign="top"><em>eventNum</em> </td><td>[IN] Event number </td></tr>
106 <tr><td valign="top"></td><td valign="top"><em>chanNum</em> </td><td>[IN/OUT]Return the channel number to which the request event is mapped to. </td></tr>
107 <tr><td valign="top"></td><td valign="top"><em>edmaGblXbarConfig</em> </td><td>[IN] This is the configuration data structure for mapping the events to the channel</td></tr>
108 </table>
109 </dd>
110 </dl>
111 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
112 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique event values. It is non-re-entrant for same event values. </dd></dl>
114 </div>
115 </div>
116 <a class="anchor" id="ga02168cc5612b65b34812ce52df7154a3"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_xbarConfigScr" ref="ga02168cc5612b65b34812ce52df7154a3" args=")(unsigned int eventNum, unsigned int chanNum)" -->
117 <div class="memitem">
118 <div class="memproto">
119 <table class="memname">
120 <tr>
121 <td class="memname">typedef EDMA3_DRV_Result(* <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga02168cc5612b65b34812ce52df7154a3">EDMA3_DRV_xbarConfigScr</a>)(unsigned int eventNum, unsigned int chanNum)</td>
122 </tr>
123 </table>
124 </div>
125 <div class="memdoc">
127 <p>Writes to the cross bar mapped event to channel to system configuration register. </p>
128 <p>This function have to be defined in the configuration file. This function will be called only if the event number requested for is beyond the maximum number of channels and if any channel is allocated to this event. This function should read the cross bar mapped event number and write the allocated channel number in Control Config Event Mux registers.</p>
129 <dl><dt><b>Parameters:</b></dt><dd>
130 <table border="0" cellspacing="2" cellpadding="0">
131 <tr><td valign="top"></td><td valign="top"><em>eventNum</em> </td><td>[IN] Event number </td></tr>
132 <tr><td valign="top"></td><td valign="top"><em>chanNum</em> </td><td>[IN/OUT]Return the channel number to which the request event is mapped to.</td></tr>
133 </table>
134 </dd>
135 </dl>
136 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
137 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique event values. It is non-re-entrant for same event values. </dd></dl>
139 </div>
140 </div>
141 <hr/><h2>Function Documentation</h2>
142 <a class="anchor" id="gaa8561ee446bd1b9d0c5c4b106c9f40a9"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_linkChannel" ref="gaa8561ee446bd1b9d0c5c4b106c9f40a9" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2)" -->
143 <div class="memitem">
144 <div class="memproto">
145 <table class="memname">
146 <tr>
147 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_linkChannel </td>
148 <td>(</td>
149 <td class="paramtype">EDMA3_DRV_Handle </td>
150 <td class="paramname"> <em>hEdma</em>, </td>
151 </tr>
152 <tr>
153 <td class="paramkey"></td>
154 <td></td>
155 <td class="paramtype">unsigned int </td>
156 <td class="paramname"> <em>lCh1</em>, </td>
157 </tr>
158 <tr>
159 <td class="paramkey"></td>
160 <td></td>
161 <td class="paramtype">unsigned int </td>
162 <td class="paramname"> <em>lCh2</em></td><td> </td>
163 </tr>
164 <tr>
165 <td></td>
166 <td>)</td>
167 <td></td><td></td><td></td>
168 </tr>
169 </table>
170 </div>
171 <div class="memdoc">
173 <p>Link two logical channels. </p>
174 <p>This API is used to link two previously allocated logical (DMA/QDMA/Link) channels.</p>
175 <p>It sets the Link field of the PaRAM set associated with first logical channel (lCh1) to point it to the PaRAM set associated with second logical channel (lCh2).</p>
176 <p>It also sets the TCC field of PaRAM set of second logical channel to the same as that of the first logical channel, only if the TCC field doesnot contain a valid TCC code. In case the second logical channel has its own TCC, the TCC field remains unchanged.</p>
177 <dl><dt><b>Parameters:</b></dt><dd>
178 <table border="0" cellspacing="2" cellpadding="0">
179 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
180 <tr><td valign="top"></td><td valign="top"><em>lCh1</em> </td><td>[IN] Logical Channel to which particular channel will be linked. </td></tr>
181 <tr><td valign="top"></td><td valign="top"><em>lCh2</em> </td><td>[IN] Logical Channel which needs to be linked to the first channel. After the transfer based on the PaRAM set of lCh1 is over, the PaRAM set of lCh2 will be copied to the PaRAM set of lCh1 and transfer will resume. For DMA channels, another sync event is required to initiate the transfer on the Link channel.</td></tr>
182 </table>
183 </dd>
184 </dl>
185 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
186 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh1 & lCh2 values. It is non-re-entrant for same lCh1 & lCh2 values. </dd></dl>
188 </div>
189 </div>
190 <a class="anchor" id="gaca6ef38f26d8e043352fa8963b7f090a"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_unlinkChannel" ref="gaca6ef38f26d8e043352fa8963b7f090a" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh)" -->
191 <div class="memitem">
192 <div class="memproto">
193 <table class="memname">
194 <tr>
195 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_unlinkChannel </td>
196 <td>(</td>
197 <td class="paramtype">EDMA3_DRV_Handle </td>
198 <td class="paramname"> <em>hEdma</em>, </td>
199 </tr>
200 <tr>
201 <td class="paramkey"></td>
202 <td></td>
203 <td class="paramtype">unsigned int </td>
204 <td class="paramname"> <em>lCh</em></td><td> </td>
205 </tr>
206 <tr>
207 <td></td>
208 <td>)</td>
209 <td></td><td></td><td></td>
210 </tr>
211 </table>
212 </div>
213 <div class="memdoc">
215 <p>Unlink the channel from the earlier linked logical channel. </p>
216 <p>This function breaks the link between the specified channel and the earlier linked logical channel by clearing the Link Address field.</p>
217 <dl><dt><b>Parameters:</b></dt><dd>
218 <table border="0" cellspacing="2" cellpadding="0">
219 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
220 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] Channel for which linking has to be removed</td></tr>
221 </table>
222 </dd>
223 </dl>
224 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
225 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
227 </div>
228 </div>
229 <a class="anchor" id="gab8e524124e4aaa158fcaf494798def5e"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_chainChannel" ref="gab8e524124e4aaa158fcaf494798def5e" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2, const EDMA3_DRV_ChainOptions *chainOptions)" -->
230 <div class="memitem">
231 <div class="memproto">
232 <table class="memname">
233 <tr>
234 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_chainChannel </td>
235 <td>(</td>
236 <td class="paramtype">EDMA3_DRV_Handle </td>
237 <td class="paramname"> <em>hEdma</em>, </td>
238 </tr>
239 <tr>
240 <td class="paramkey"></td>
241 <td></td>
242 <td class="paramtype">unsigned int </td>
243 <td class="paramname"> <em>lCh1</em>, </td>
244 </tr>
245 <tr>
246 <td class="paramkey"></td>
247 <td></td>
248 <td class="paramtype">unsigned int </td>
249 <td class="paramname"> <em>lCh2</em>, </td>
250 </tr>
251 <tr>
252 <td class="paramkey"></td>
253 <td></td>
254 <td class="paramtype">const <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html">EDMA3_DRV_ChainOptions</a> * </td>
255 <td class="paramname"> <em>chainOptions</em></td><td> </td>
256 </tr>
257 <tr>
258 <td></td>
259 <td>)</td>
260 <td></td><td></td><td></td>
261 </tr>
262 </table>
263 </div>
264 <div class="memdoc">
266 <p>Chain the two specified channels. </p>
267 <p>This API is used to chain a DMA channel to a previously allocated DMA/QDMA channel.</p>
268 <p>Chaining is different from Linking. The EDMA3 link feature reloads the current channel parameter set with the linked parameter set. The EDMA3 chaining feature does not modify or update any channel parameter set; it provides a synchronization event (or trigger) to the chained DMA channel, as soon as the transfer (final or intermediate) completes on the main DMA/QDMA channel.</p>
269 <dl><dt><b>Parameters:</b></dt><dd>
270 <table border="0" cellspacing="2" cellpadding="0">
271 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance.</td></tr>
272 <tr><td valign="top"></td><td valign="top"><em>lCh1</em> </td><td>[IN] DMA/QDMA channel to which a particular DMA channel will be chained. </td></tr>
273 <tr><td valign="top"></td><td valign="top"><em>lCh2</em> </td><td>[IN] DMA channel which needs to be chained to the first DMA/QDMA channel. </td></tr>
274 <tr><td valign="top"></td><td valign="top"><em>chainOptions</em> </td><td>[IN] Options such as intermediate interrupts are required or not, intermediate/final chaining is enabled or not etc.</td></tr>
275 </table>
276 </dd>
277 </dl>
278 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
279 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh1 & lCh2 values. It is non-re-entrant for same lCh1 & lCh2 values. </dd></dl>
281 </div>
282 </div>
283 <a class="anchor" id="gad6424fda12e9b6cccae47ccb22207bcf"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_unchainChannel" ref="gad6424fda12e9b6cccae47ccb22207bcf" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh)" -->
284 <div class="memitem">
285 <div class="memproto">
286 <table class="memname">
287 <tr>
288 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_unchainChannel </td>
289 <td>(</td>
290 <td class="paramtype">EDMA3_DRV_Handle </td>
291 <td class="paramname"> <em>hEdma</em>, </td>
292 </tr>
293 <tr>
294 <td class="paramkey"></td>
295 <td></td>
296 <td class="paramtype">unsigned int </td>
297 <td class="paramname"> <em>lCh</em></td><td> </td>
298 </tr>
299 <tr>
300 <td></td>
301 <td>)</td>
302 <td></td><td></td><td></td>
303 </tr>
304 </table>
305 </div>
306 <div class="memdoc">
308 <p>Unchain the two channels. </p>
309 <dl><dt><b>Parameters:</b></dt><dd>
310 <table border="0" cellspacing="2" cellpadding="0">
311 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
312 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] Channel whose chaining with the other channel has to be removed.</td></tr>
313 </table>
314 </dd>
315 </dl>
316 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
317 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
319 </div>
320 </div>
321 <a class="anchor" id="ga669ea0f2097604af17b9213a28985191"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setQdmaTrigWord" ref="ga669ea0f2097604af17b9213a28985191" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_RM_QdmaTrigWord trigWord)" -->
322 <div class="memitem">
323 <div class="memproto">
324 <table class="memname">
325 <tr>
326 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord </td>
327 <td>(</td>
328 <td class="paramtype">EDMA3_DRV_Handle </td>
329 <td class="paramname"> <em>hEdma</em>, </td>
330 </tr>
331 <tr>
332 <td class="paramkey"></td>
333 <td></td>
334 <td class="paramtype">unsigned int </td>
335 <td class="paramname"> <em>lCh</em>, </td>
336 </tr>
337 <tr>
338 <td class="paramkey"></td>
339 <td></td>
340 <td class="paramtype">EDMA3_RM_QdmaTrigWord </td>
341 <td class="paramname"> <em>trigWord</em></td><td> </td>
342 </tr>
343 <tr>
344 <td></td>
345 <td>)</td>
346 <td></td><td></td><td></td>
347 </tr>
348 </table>
349 </div>
350 <div class="memdoc">
352 <p>Assign a Trigger Word to the specified QDMA channel. </p>
353 <p>This API sets the Trigger word for the specific QDMA channel in the QCHMAP Register. Default QDMA trigger word is CCNT.</p>
354 <dl><dt><b>Parameters:</b></dt><dd>
355 <table border="0" cellspacing="2" cellpadding="0">
356 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Instance object </td></tr>
357 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] QDMA Channel which needs to be assigned the Trigger Word </td></tr>
358 <tr><td valign="top"></td><td valign="top"><em>trigWord</em> </td><td>[IN] The Trigger Word for the QDMA channel. Trigger Word is the word in the PaRAM Register Set which, when written to by CPU, will start the QDMA transfer automatically.</td></tr>
359 </table>
360 </dd>
361 </dl>
362 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
363 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
365 </div>
366 </div>
367 <a class="anchor" id="ga77841fc83e3876a3014963404cfc08ba"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setPaRAM" ref="ga77841fc83e3876a3014963404cfc08ba" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, const EDMA3_DRV_PaRAMRegs *newPaRAM)" -->
368 <div class="memitem">
369 <div class="memproto">
370 <table class="memname">
371 <tr>
372 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setPaRAM </td>
373 <td>(</td>
374 <td class="paramtype">EDMA3_DRV_Handle </td>
375 <td class="paramname"> <em>hEdma</em>, </td>
376 </tr>
377 <tr>
378 <td class="paramkey"></td>
379 <td></td>
380 <td class="paramtype">unsigned int </td>
381 <td class="paramname"> <em>lCh</em>, </td>
382 </tr>
383 <tr>
384 <td class="paramkey"></td>
385 <td></td>
386 <td class="paramtype">const <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html">EDMA3_DRV_PaRAMRegs</a> * </td>
387 <td class="paramname"> <em>newPaRAM</em></td><td> </td>
388 </tr>
389 <tr>
390 <td></td>
391 <td>)</td>
392 <td></td><td></td><td></td>
393 </tr>
394 </table>
395 </div>
396 <div class="memdoc">
398 <p>Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link). </p>
399 <p>This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set associated with the logical channel. OPT field of the PaRAM Set is written first and the CCNT field is written last.</p>
400 <p>Caution: It should be used carefully when programming the QDMA channels whose trigger words are not CCNT field.</p>
401 <dl><dt><b>Parameters:</b></dt><dd>
402 <table border="0" cellspacing="2" cellpadding="0">
403 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Instance object </td></tr>
404 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] Logical Channel for which new PaRAM set is specified </td></tr>
405 <tr><td valign="top"></td><td valign="top"><em>newPaRAM</em> </td><td>[IN] Parameter RAM set to be copied onto existing PaRAM</td></tr>
406 </table>
407 </dd>
408 </dl>
409 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
410 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
412 </div>
413 </div>
414 <a class="anchor" id="ga437d851ec0eb6c05bb118886ee5c17f2"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAM" ref="ga437d851ec0eb6c05bb118886ee5c17f2" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMRegs *currPaRAM)" -->
415 <div class="memitem">
416 <div class="memproto">
417 <table class="memname">
418 <tr>
419 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getPaRAM </td>
420 <td>(</td>
421 <td class="paramtype">EDMA3_DRV_Handle </td>
422 <td class="paramname"> <em>hEdma</em>, </td>
423 </tr>
424 <tr>
425 <td class="paramkey"></td>
426 <td></td>
427 <td class="paramtype">unsigned int </td>
428 <td class="paramname"> <em>lCh</em>, </td>
429 </tr>
430 <tr>
431 <td class="paramkey"></td>
432 <td></td>
433 <td class="paramtype"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html">EDMA3_DRV_PaRAMRegs</a> * </td>
434 <td class="paramname"> <em>currPaRAM</em></td><td> </td>
435 </tr>
436 <tr>
437 <td></td>
438 <td>)</td>
439 <td></td><td></td><td></td>
440 </tr>
441 </table>
442 </div>
443 <div class="memdoc">
445 <p>Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link). </p>
446 <dl><dt><b>Parameters:</b></dt><dd>
447 <table border="0" cellspacing="2" cellpadding="0">
448 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Instance object </td></tr>
449 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] Logical Channel whose PaRAM set is requested </td></tr>
450 <tr><td valign="top"></td><td valign="top"><em>currPaRAM</em> </td><td>[IN/OUT] User gets the existing PaRAM here</td></tr>
451 </table>
452 </dd>
453 </dl>
454 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
455 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
457 </div>
458 </div>
459 <a class="anchor" id="ga83bcb5bc4e319fd6e78466ab5df5c0ac"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setPaRAMEntry" ref="ga83bcb5bc4e319fd6e78466ab5df5c0ac" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int newPaRAMEntryVal)" -->
460 <div class="memitem">
461 <div class="memproto">
462 <table class="memname">
463 <tr>
464 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry </td>
465 <td>(</td>
466 <td class="paramtype">EDMA3_DRV_Handle </td>
467 <td class="paramname"> <em>hEdma</em>, </td>
468 </tr>
469 <tr>
470 <td class="paramkey"></td>
471 <td></td>
472 <td class="paramtype">unsigned int </td>
473 <td class="paramname"> <em>lCh</em>, </td>
474 </tr>
475 <tr>
476 <td class="paramkey"></td>
477 <td></td>
478 <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga82b01ec2292a13ad48a5bfcc724dfac6">EDMA3_DRV_PaRAMEntry</a> </td>
479 <td class="paramname"> <em>paRAMEntry</em>, </td>
480 </tr>
481 <tr>
482 <td class="paramkey"></td>
483 <td></td>
484 <td class="paramtype">unsigned int </td>
485 <td class="paramname"> <em>newPaRAMEntryVal</em></td><td> </td>
486 </tr>
487 <tr>
488 <td></td>
489 <td>)</td>
490 <td></td><td></td><td></td>
491 </tr>
492 </table>
493 </div>
494 <div class="memdoc">
496 <p>Set a particular PaRAM set entry of the specified PaRAM set. </p>
497 <dl><dt><b>Parameters:</b></dt><dd>
498 <table border="0" cellspacing="2" cellpadding="0">
499 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
500 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] Logical Channel bound to the Parameter RAM set whose specified field needs to be set </td></tr>
501 <tr><td valign="top"></td><td valign="top"><em>paRAMEntry</em> </td><td>[IN] Specify the PaRAM set entry which needs to be set </td></tr>
502 <tr><td valign="top"></td><td valign="top"><em>newPaRAMEntryVal</em> </td><td>[IN] The new field setting</td></tr>
503 </table>
504 </dd>
505 </dl>
506 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
507 <dl class="note"><dt><b>Note:</b></dt><dd>This API should be used while setting the PaRAM set entry for QDMA channels. If EDMA3_DRV_setPaRAMField () used, it will trigger the QDMA channel before complete PaRAM set entry is written. For DMA channels, no such constraint is there.</dd></dl>
508 <p>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </p>
510 </div>
511 </div>
512 <a class="anchor" id="ga443b63758caa5383ef0f9f66b29fb5e8"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAMEntry" ref="ga443b63758caa5383ef0f9f66b29fb5e8" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int *paRAMEntryVal)" -->
513 <div class="memitem">
514 <div class="memproto">
515 <table class="memname">
516 <tr>
517 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry </td>
518 <td>(</td>
519 <td class="paramtype">EDMA3_DRV_Handle </td>
520 <td class="paramname"> <em>hEdma</em>, </td>
521 </tr>
522 <tr>
523 <td class="paramkey"></td>
524 <td></td>
525 <td class="paramtype">unsigned int </td>
526 <td class="paramname"> <em>lCh</em>, </td>
527 </tr>
528 <tr>
529 <td class="paramkey"></td>
530 <td></td>
531 <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga82b01ec2292a13ad48a5bfcc724dfac6">EDMA3_DRV_PaRAMEntry</a> </td>
532 <td class="paramname"> <em>paRAMEntry</em>, </td>
533 </tr>
534 <tr>
535 <td class="paramkey"></td>
536 <td></td>
537 <td class="paramtype">unsigned int * </td>
538 <td class="paramname"> <em>paRAMEntryVal</em></td><td> </td>
539 </tr>
540 <tr>
541 <td></td>
542 <td>)</td>
543 <td></td><td></td><td></td>
544 </tr>
545 </table>
546 </div>
547 <div class="memdoc">
549 <p>Get a particular PaRAM set entry of the specified PaRAM set. </p>
550 <dl><dt><b>Parameters:</b></dt><dd>
551 <table border="0" cellspacing="2" cellpadding="0">
552 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
553 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] Logical Channel bound to the Parameter RAM set whose specified field value is needed </td></tr>
554 <tr><td valign="top"></td><td valign="top"><em>paRAMEntry</em> </td><td>[IN] Specify the PaRAM set entry which needs to be obtained </td></tr>
555 <tr><td valign="top"></td><td valign="top"><em>paRAMEntryVal</em> </td><td>[IN/OUT] The value of the field is returned here</td></tr>
556 </table>
557 </dd>
558 </dl>
559 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
560 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
562 </div>
563 </div>
564 <a class="anchor" id="ga41151895e480b66bf320ec662506f078"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setPaRAMField" ref="ga41151895e480b66bf320ec662506f078" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int newPaRAMFieldVal)" -->
565 <div class="memitem">
566 <div class="memproto">
567 <table class="memname">
568 <tr>
569 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setPaRAMField </td>
570 <td>(</td>
571 <td class="paramtype">EDMA3_DRV_Handle </td>
572 <td class="paramname"> <em>hEdma</em>, </td>
573 </tr>
574 <tr>
575 <td class="paramkey"></td>
576 <td></td>
577 <td class="paramtype">unsigned int </td>
578 <td class="paramname"> <em>lCh</em>, </td>
579 </tr>
580 <tr>
581 <td class="paramkey"></td>
582 <td></td>
583 <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga3e31ba1b02dcbace3044c11c83ef5466">EDMA3_DRV_PaRAMField</a> </td>
584 <td class="paramname"> <em>paRAMField</em>, </td>
585 </tr>
586 <tr>
587 <td class="paramkey"></td>
588 <td></td>
589 <td class="paramtype">unsigned int </td>
590 <td class="paramname"> <em>newPaRAMFieldVal</em></td><td> </td>
591 </tr>
592 <tr>
593 <td></td>
594 <td>)</td>
595 <td></td><td></td><td></td>
596 </tr>
597 </table>
598 </div>
599 <div class="memdoc">
601 <p>Set a particular PaRAM set field of the specified PaRAM set. </p>
602 <dl><dt><b>Parameters:</b></dt><dd>
603 <table border="0" cellspacing="2" cellpadding="0">
604 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
605 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] Logical Channel bound to the PaRAM set whose specified field needs to be set </td></tr>
606 <tr><td valign="top"></td><td valign="top"><em>paRAMField</em> </td><td>[IN] Specify the PaRAM set field which needs to be set </td></tr>
607 <tr><td valign="top"></td><td valign="top"><em>newPaRAMFieldVal</em> </td><td>[IN] The new field setting</td></tr>
608 </table>
609 </dd>
610 </dl>
611 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
612 <dl class="note"><dt><b>Note:</b></dt><dd>This API CANNOT be used while setting the PaRAM set field for QDMA channels. It can trigger the QDMA channel before complete PaRAM set ENTRY (4-bytes field) is written (for eg, as soon one sets the ACNT field for QDMA channel, transfer is started, before one modifies the BCNT field). For DMA channels, no such constraint is there.</dd></dl>
613 <p>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </p>
615 </div>
616 </div>
617 <a class="anchor" id="ga1254ca24861fd4b580010f118f093b51"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAMField" ref="ga1254ca24861fd4b580010f118f093b51" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int *currPaRAMFieldVal)" -->
618 <div class="memitem">
619 <div class="memproto">
620 <table class="memname">
621 <tr>
622 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getPaRAMField </td>
623 <td>(</td>
624 <td class="paramtype">EDMA3_DRV_Handle </td>
625 <td class="paramname"> <em>hEdma</em>, </td>
626 </tr>
627 <tr>
628 <td class="paramkey"></td>
629 <td></td>
630 <td class="paramtype">unsigned int </td>
631 <td class="paramname"> <em>lCh</em>, </td>
632 </tr>
633 <tr>
634 <td class="paramkey"></td>
635 <td></td>
636 <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga3e31ba1b02dcbace3044c11c83ef5466">EDMA3_DRV_PaRAMField</a> </td>
637 <td class="paramname"> <em>paRAMField</em>, </td>
638 </tr>
639 <tr>
640 <td class="paramkey"></td>
641 <td></td>
642 <td class="paramtype">unsigned int * </td>
643 <td class="paramname"> <em>currPaRAMFieldVal</em></td><td> </td>
644 </tr>
645 <tr>
646 <td></td>
647 <td>)</td>
648 <td></td><td></td><td></td>
649 </tr>
650 </table>
651 </div>
652 <div class="memdoc">
654 <p>Get a particular PaRAM set field of the specified PaRAM set. </p>
655 <dl><dt><b>Parameters:</b></dt><dd>
656 <table border="0" cellspacing="2" cellpadding="0">
657 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
658 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] Logical Channel bound to the PaRAM set whose specified field value is needed </td></tr>
659 <tr><td valign="top"></td><td valign="top"><em>paRAMField</em> </td><td>[IN] Specify the PaRAM set field which needs to be obtained </td></tr>
660 <tr><td valign="top"></td><td valign="top"><em>currPaRAMFieldVal</em> </td><td>[IN/OUT] The value of the field is returned here</td></tr>
661 </table>
662 </dd>
663 </dl>
664 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
665 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
667 </div>
668 </div>
669 <a class="anchor" id="ga6a6c40cddb7bb7bc74635e104757e225"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setEvtQPriority" ref="ga6a6c40cddb7bb7bc74635e104757e225" args="(EDMA3_DRV_Handle hEdma, const EDMA3_DRV_EvtQuePriority *evtQPriObj)" -->
670 <div class="memitem">
671 <div class="memproto">
672 <table class="memname">
673 <tr>
674 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority </td>
675 <td>(</td>
676 <td class="paramtype">EDMA3_DRV_Handle </td>
677 <td class="paramname"> <em>hEdma</em>, </td>
678 </tr>
679 <tr>
680 <td class="paramkey"></td>
681 <td></td>
682 <td class="paramtype">const <a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html">EDMA3_DRV_EvtQuePriority</a> * </td>
683 <td class="paramname"> <em>evtQPriObj</em></td><td> </td>
684 </tr>
685 <tr>
686 <td></td>
687 <td>)</td>
688 <td></td><td></td><td></td>
689 </tr>
690 </table>
691 </div>
692 <div class="memdoc">
694 <p>Sets EDMA TC priority. </p>
695 <p>User can program the priority of the Event Queues at a system-wide level. This means that the user can set the priority of an IO initiated by either of the TCs (Transfer Ctrllers) relative to IO initiated by the other bus masters on the device (ARM, DSP, USB, etc)</p>
696 <dl><dt><b>Parameters:</b></dt><dd>
697 <table border="0" cellspacing="2" cellpadding="0">
698 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
699 <tr><td valign="top"></td><td valign="top"><em>evtQPriObj</em> </td><td>[IN] Priority of the Event Queues</td></tr>
700 </table>
701 </dd>
702 </dl>
703 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
704 <dl class="note"><dt><b>Note:</b></dt><dd>This function disables the global interrupts while modifying the global CC Registers, to make it re-entrant. </dd></dl>
706 </div>
707 </div>
708 <a class="anchor" id="ga4419ae8ba6468ec35090e2717a28f958"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_mapChToEvtQ" ref="ga4419ae8ba6468ec35090e2717a28f958" args="(EDMA3_DRV_Handle hEdma, unsigned int channelId, EDMA3_RM_EventQueue eventQ)" -->
709 <div class="memitem">
710 <div class="memproto">
711 <table class="memname">
712 <tr>
713 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ </td>
714 <td>(</td>
715 <td class="paramtype">EDMA3_DRV_Handle </td>
716 <td class="paramname"> <em>hEdma</em>, </td>
717 </tr>
718 <tr>
719 <td class="paramkey"></td>
720 <td></td>
721 <td class="paramtype">unsigned int </td>
722 <td class="paramname"> <em>channelId</em>, </td>
723 </tr>
724 <tr>
725 <td class="paramkey"></td>
726 <td></td>
727 <td class="paramtype">EDMA3_RM_EventQueue </td>
728 <td class="paramname"> <em>eventQ</em></td><td> </td>
729 </tr>
730 <tr>
731 <td></td>
732 <td>)</td>
733 <td></td><td></td><td></td>
734 </tr>
735 </table>
736 </div>
737 <div class="memdoc">
739 <p>Associate Channel to Event Queue. </p>
740 <dl><dt><b>Parameters:</b></dt><dd>
741 <table border="0" cellspacing="2" cellpadding="0">
742 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
743 <tr><td valign="top"></td><td valign="top"><em>channelId</em> </td><td>[IN] Logical Channel to which the Event Queue is to be mapped </td></tr>
744 <tr><td valign="top"></td><td valign="top"><em>eventQ</em> </td><td>[IN] The Event Queue which is to be mapped to the DMA channel</td></tr>
745 </table>
746 </dd>
747 </dl>
748 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
749 <dl class="note"><dt><b>Note:</b></dt><dd>There should not be any data transfer going on while setting the mapping. Results could be unpredictable.</dd></dl>
750 <p>This function disables the global interrupts while modifying the global CC Registers, to make it re-entrant. </p>
752 </div>
753 </div>
754 <a class="anchor" id="gab2058b44b471c44d001035e1a38fd06d"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getMapChToEvtQ" ref="gab2058b44b471c44d001035e1a38fd06d" args="(EDMA3_DRV_Handle hEdma, unsigned int channelId, unsigned int *mappedEvtQ)" -->
755 <div class="memitem">
756 <div class="memproto">
757 <table class="memname">
758 <tr>
759 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ </td>
760 <td>(</td>
761 <td class="paramtype">EDMA3_DRV_Handle </td>
762 <td class="paramname"> <em>hEdma</em>, </td>
763 </tr>
764 <tr>
765 <td class="paramkey"></td>
766 <td></td>
767 <td class="paramtype">unsigned int </td>
768 <td class="paramname"> <em>channelId</em>, </td>
769 </tr>
770 <tr>
771 <td class="paramkey"></td>
772 <td></td>
773 <td class="paramtype">unsigned int * </td>
774 <td class="paramname"> <em>mappedEvtQ</em></td><td> </td>
775 </tr>
776 <tr>
777 <td></td>
778 <td>)</td>
779 <td></td><td></td><td></td>
780 </tr>
781 </table>
782 </div>
783 <div class="memdoc">
785 <p>Get the Event Queue mapped to the specified DMA/QDMA channel. </p>
786 <dl><dt><b>Parameters:</b></dt><dd>
787 <table border="0" cellspacing="2" cellpadding="0">
788 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
789 <tr><td valign="top"></td><td valign="top"><em>channelId</em> </td><td>[IN] Logical Channel whose associated Event Queue is needed </td></tr>
790 <tr><td valign="top"></td><td valign="top"><em>mappedEvtQ</em> </td><td>[IN/OUT] The Event Queue which is mapped to the DMA/QDMA channel</td></tr>
791 </table>
792 </dd>
793 </dl>
794 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
795 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
797 </div>
798 </div>
799 <a class="anchor" id="ga2574c3da30322981b763e54dd1ea7fb2"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setCCRegister" ref="ga2574c3da30322981b763e54dd1ea7fb2" args="(EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int newRegValue)" -->
800 <div class="memitem">
801 <div class="memproto">
802 <table class="memname">
803 <tr>
804 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setCCRegister </td>
805 <td>(</td>
806 <td class="paramtype">EDMA3_DRV_Handle </td>
807 <td class="paramname"> <em>hEdma</em>, </td>
808 </tr>
809 <tr>
810 <td class="paramkey"></td>
811 <td></td>
812 <td class="paramtype">unsigned int </td>
813 <td class="paramname"> <em>regOffset</em>, </td>
814 </tr>
815 <tr>
816 <td class="paramkey"></td>
817 <td></td>
818 <td class="paramtype">unsigned int </td>
819 <td class="paramname"> <em>newRegValue</em></td><td> </td>
820 </tr>
821 <tr>
822 <td></td>
823 <td>)</td>
824 <td></td><td></td><td></td>
825 </tr>
826 </table>
827 </div>
828 <div class="memdoc">
830 <p>Set the Channel Controller (CC) Register value. </p>
831 <dl><dt><b>Parameters:</b></dt><dd>
832 <table border="0" cellspacing="2" cellpadding="0">
833 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
834 <tr><td valign="top"></td><td valign="top"><em>regOffset</em> </td><td>[IN] CC Register offset whose value needs to be set </td></tr>
835 <tr><td valign="top"></td><td valign="top"><em>newRegValue</em> </td><td>[IN] New CC Register Value</td></tr>
836 </table>
837 </dd>
838 </dl>
839 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
840 <dl class="note"><dt><b>Note:</b></dt><dd>This function is non re-entrant for users using the same EDMA handle i.e. working on the same shadow region. Before modifying a register, it tries to acquire a semaphore (Driver instance specific), to protect simultaneous modification of the same register by two different users. After the successful change, it releases the semaphore. For users working on different shadow regions, thus different EDMA handles, this function is re-entrant. </dd></dl>
842 </div>
843 </div>
844 <a class="anchor" id="ga297f964f8fa3df44683e1bdedd56d928"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getCCRegister" ref="ga297f964f8fa3df44683e1bdedd56d928" args="(EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int *regValue)" -->
845 <div class="memitem">
846 <div class="memproto">
847 <table class="memname">
848 <tr>
849 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getCCRegister </td>
850 <td>(</td>
851 <td class="paramtype">EDMA3_DRV_Handle </td>
852 <td class="paramname"> <em>hEdma</em>, </td>
853 </tr>
854 <tr>
855 <td class="paramkey"></td>
856 <td></td>
857 <td class="paramtype">unsigned int </td>
858 <td class="paramname"> <em>regOffset</em>, </td>
859 </tr>
860 <tr>
861 <td class="paramkey"></td>
862 <td></td>
863 <td class="paramtype">unsigned int * </td>
864 <td class="paramname"> <em>regValue</em></td><td> </td>
865 </tr>
866 <tr>
867 <td></td>
868 <td>)</td>
869 <td></td><td></td><td></td>
870 </tr>
871 </table>
872 </div>
873 <div class="memdoc">
875 <p>Get the Channel Controller (CC) Register value. </p>
876 <dl><dt><b>Parameters:</b></dt><dd>
877 <table border="0" cellspacing="2" cellpadding="0">
878 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
879 <tr><td valign="top"></td><td valign="top"><em>regOffset</em> </td><td>[IN] CC Register offset whose value is needed </td></tr>
880 <tr><td valign="top"></td><td valign="top"><em>regValue</em> </td><td>[IN/OUT] CC Register Value</td></tr>
881 </table>
882 </dd>
883 </dl>
884 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
885 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
887 </div>
888 </div>
889 <a class="anchor" id="gaa73fe4d0c29760be55306a8fc1f35161"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_waitAndClearTcc" ref="gaa73fe4d0c29760be55306a8fc1f35161" args="(EDMA3_DRV_Handle hEdma, unsigned int tccNo)" -->
890 <div class="memitem">
891 <div class="memproto">
892 <table class="memname">
893 <tr>
894 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc </td>
895 <td>(</td>
896 <td class="paramtype">EDMA3_DRV_Handle </td>
897 <td class="paramname"> <em>hEdma</em>, </td>
898 </tr>
899 <tr>
900 <td class="paramkey"></td>
901 <td></td>
902 <td class="paramtype">unsigned int </td>
903 <td class="paramname"> <em>tccNo</em></td><td> </td>
904 </tr>
905 <tr>
906 <td></td>
907 <td>)</td>
908 <td></td><td></td><td></td>
909 </tr>
910 </table>
911 </div>
912 <div class="memdoc">
914 <p>Wait for a transfer completion interrupt to occur and clear it. </p>
915 <p>This is a blocking function that returns when the IPR/IPRH bit corresponding to the tccNo specified, is SET. It clears the corresponding bit while returning also.</p>
916 <p>This function waits for the specific bit indefinitely in a tight loop, with out any delay in between. USE IT CAUTIOUSLY.</p>
917 <dl><dt><b>Parameters:</b></dt><dd>
918 <table border="0" cellspacing="2" cellpadding="0">
919 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
920 <tr><td valign="top"></td><td valign="top"><em>tccNo</em> </td><td>[IN] TCC, specific to which the function waits on a IPR/IPRH bit.</td></tr>
921 </table>
922 </dd>
923 </dl>
924 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
925 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for different tccNo. </dd></dl>
927 </div>
928 </div>
929 <a class="anchor" id="ga3c098a85435e55a8eff2561cbcd79a77"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_checkAndClearTcc" ref="ga3c098a85435e55a8eff2561cbcd79a77" args="(EDMA3_DRV_Handle hEdma, unsigned int tccNo, unsigned short *tccStatus)" -->
930 <div class="memitem">
931 <div class="memproto">
932 <table class="memname">
933 <tr>
934 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc </td>
935 <td>(</td>
936 <td class="paramtype">EDMA3_DRV_Handle </td>
937 <td class="paramname"> <em>hEdma</em>, </td>
938 </tr>
939 <tr>
940 <td class="paramkey"></td>
941 <td></td>
942 <td class="paramtype">unsigned int </td>
943 <td class="paramname"> <em>tccNo</em>, </td>
944 </tr>
945 <tr>
946 <td class="paramkey"></td>
947 <td></td>
948 <td class="paramtype">unsigned short * </td>
949 <td class="paramname"> <em>tccStatus</em></td><td> </td>
950 </tr>
951 <tr>
952 <td></td>
953 <td>)</td>
954 <td></td><td></td><td></td>
955 </tr>
956 </table>
957 </div>
958 <div class="memdoc">
960 <p>Returns the status of a previously initiated transfer. </p>
961 <p>This is a non-blocking function that returns the status of a previously initiated transfer, based on the IPR/IPRH bit. This bit corresponds to the tccNo specified by the user. It clears the corresponding bit, if SET, while returning also.</p>
962 <dl><dt><b>Parameters:</b></dt><dd>
963 <table border="0" cellspacing="2" cellpadding="0">
964 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
965 <tr><td valign="top"></td><td valign="top"><em>tccNo</em> </td><td>[IN] TCC, specific to which the function checks the status of the IPR/IPRH bit. </td></tr>
966 <tr><td valign="top"></td><td valign="top"><em>tccStatus</em> </td><td>[IN/OUT] Status of the transfer is returned here. Returns "TRUE" if the transfer has completed (IPR/IPRH bit SET), "FALSE" if the transfer has not completed successfully (IPR/IPRH bit NOT SET).</td></tr>
967 </table>
968 </dd>
969 </dl>
970 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
971 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for different tccNo. </dd></dl>
973 </div>
974 </div>
975 <a class="anchor" id="gafeb7b2a17615b14bdac9b11af69e5142"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAMPhyAddr" ref="gafeb7b2a17615b14bdac9b11af69e5142" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *paramPhyAddr)" -->
976 <div class="memitem">
977 <div class="memproto">
978 <table class="memname">
979 <tr>
980 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr </td>
981 <td>(</td>
982 <td class="paramtype">EDMA3_DRV_Handle </td>
983 <td class="paramname"> <em>hEdma</em>, </td>
984 </tr>
985 <tr>
986 <td class="paramkey"></td>
987 <td></td>
988 <td class="paramtype">unsigned int </td>
989 <td class="paramname"> <em>lCh</em>, </td>
990 </tr>
991 <tr>
992 <td class="paramkey"></td>
993 <td></td>
994 <td class="paramtype">unsigned int * </td>
995 <td class="paramname"> <em>paramPhyAddr</em></td><td> </td>
996 </tr>
997 <tr>
998 <td></td>
999 <td>)</td>
1000 <td></td><td></td><td></td>
1001 </tr>
1002 </table>
1003 </div>
1004 <div class="memdoc">
1006 <p>Get the PaRAM Set Physical Address associated with a logical channel. </p>
1007 <p>This function returns the PaRAM Set Phy Address (unsigned 32 bits). The returned address could be used by the advanced users to program the PaRAM Set directly without using any APIs.</p>
1008 <p>Least significant 16 bits of this address could be used to program the LINK field in the PaRAM Set. Users which program the LINK field directly SHOULD use this API to get the associated PaRAM Set address with the LINK channel.</p>
1009 <dl><dt><b>Parameters:</b></dt><dd>
1010 <table border="0" cellspacing="2" cellpadding="0">
1011 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
1012 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] Logical Channel for which the PaRAM set physical address is required </td></tr>
1013 <tr><td valign="top"></td><td valign="top"><em>paramPhyAddr</em> </td><td>[IN/OUT] PaRAM Set physical address is returned here.</td></tr>
1014 </table>
1015 </dd>
1016 </dl>
1017 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
1018 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
1020 </div>
1021 </div>
1022 <a class="anchor" id="ga379162d6a5076160d4ed2e01ca8dcac6"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_Ioctl" ref="ga379162d6a5076160d4ed2e01ca8dcac6" args="(EDMA3_DRV_Handle hEdma, EDMA3_DRV_IoctlCmd cmd, void *cmdArg, void *param)" -->
1023 <div class="memitem">
1024 <div class="memproto">
1025 <table class="memname">
1026 <tr>
1027 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_Ioctl </td>
1028 <td>(</td>
1029 <td class="paramtype">EDMA3_DRV_Handle </td>
1030 <td class="paramname"> <em>hEdma</em>, </td>
1031 </tr>
1032 <tr>
1033 <td class="paramkey"></td>
1034 <td></td>
1035 <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8577940463f7ca5a8977b2fb65fae19a">EDMA3_DRV_IoctlCmd</a> </td>
1036 <td class="paramname"> <em>cmd</em>, </td>
1037 </tr>
1038 <tr>
1039 <td class="paramkey"></td>
1040 <td></td>
1041 <td class="paramtype">void * </td>
1042 <td class="paramname"> <em>cmdArg</em>, </td>
1043 </tr>
1044 <tr>
1045 <td class="paramkey"></td>
1046 <td></td>
1047 <td class="paramtype">void * </td>
1048 <td class="paramname"> <em>param</em></td><td> </td>
1049 </tr>
1050 <tr>
1051 <td></td>
1052 <td>)</td>
1053 <td></td><td></td><td></td>
1054 </tr>
1055 </table>
1056 </div>
1057 <div class="memdoc">
1059 <p>EDMA3 Driver IOCTL. </p>
1060 <p>This function provides IOCTL functionality for EDMA3 Driver.</p>
1061 <dl><dt><b>Parameters:</b></dt><dd>
1062 <table border="0" cellspacing="2" cellpadding="0">
1063 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
1064 <tr><td valign="top"></td><td valign="top"><em>cmd</em> </td><td>[IN] IOCTL command to be performed </td></tr>
1065 <tr><td valign="top"></td><td valign="top"><em>cmdArg</em> </td><td>[IN/OUT] IOCTL command argument (if any) </td></tr>
1066 <tr><td valign="top"></td><td valign="top"><em>param</em> </td><td>[IN/OUT] Device/Cmd specific argument</td></tr>
1067 </table>
1068 </dd>
1069 </dl>
1070 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
1071 <dl class="note"><dt><b>Note:</b></dt><dd>For 'EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION', this function is re-entrant. For 'EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION', this function is re-entrant for different EDMA3 Driver Instances (handles). </dd></dl>
1073 </div>
1074 </div>
1075 <a class="anchor" id="ga866c17eaf78a3e0ddc83a397b91fe850"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getInstHandle" ref="ga866c17eaf78a3e0ddc83a397b91fe850" args="(unsigned int phyCtrllerInstId, EDMA3_RM_RegionId regionId, EDMA3_DRV_Result *errorCode)" -->
1076 <div class="memitem">
1077 <div class="memproto">
1078 <table class="memname">
1079 <tr>
1080 <td class="memname">EDMA3_DRV_Handle EDMA3_DRV_getInstHandle </td>
1081 <td>(</td>
1082 <td class="paramtype">unsigned int </td>
1083 <td class="paramname"> <em>phyCtrllerInstId</em>, </td>
1084 </tr>
1085 <tr>
1086 <td class="paramkey"></td>
1087 <td></td>
1088 <td class="paramtype">EDMA3_RM_RegionId </td>
1089 <td class="paramname"> <em>regionId</em>, </td>
1090 </tr>
1091 <tr>
1092 <td class="paramkey"></td>
1093 <td></td>
1094 <td class="paramtype">EDMA3_DRV_Result * </td>
1095 <td class="paramname"> <em>errorCode</em></td><td> </td>
1096 </tr>
1097 <tr>
1098 <td></td>
1099 <td>)</td>
1100 <td></td><td></td><td></td>
1101 </tr>
1102 </table>
1103 </div>
1104 <div class="memdoc">
1106 <p>Return the previously opened EDMA3 Driver Instance handle. </p>
1107 <p>This API is used to return the previously opened EDMA3 Driver's Instance Handle (region specific), which could be used to call other EDMA3 Driver APIs. Since EDMA3 Driver does not allow multiple instances, for a single shadow region, this API is provided. This API is meant for users who DO NOT want to / could not open a new Driver Instance and hence re-use the existing Driver Instance to allocate EDMA3 resources and use various other EDMA3 Driver APIs.</p>
1108 <p>In case the Driver Instance is not yet opened, NULL is returned as the function return value whereas EDMA3_DRV_E_INST_NOT_OPENED is returned in the errorCode.</p>
1109 <dl><dt><b>Parameters:</b></dt><dd>
1110 <table border="0" cellspacing="2" cellpadding="0">
1111 <tr><td valign="top"></td><td valign="top"><em>phyCtrllerInstId</em> </td><td>[IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0). </td></tr>
1112 <tr><td valign="top"></td><td valign="top"><em>regionId</em> </td><td>[IN] Shadow Region id for which the previously opened driver's instance handle is required. </td></tr>
1113 <tr><td valign="top"></td><td valign="top"><em>errorCode</em> </td><td>[OUT] Error code while returning Driver Instance Handle.</td></tr>
1114 </table>
1115 </dd>
1116 </dl>
1117 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_Handle : If successful, this API will return the driver's instance handle.</dd></dl>
1118 <dl class="note"><dt><b>Note:</b></dt><dd>1) This API returns the previously opened EDMA3 Driver's Instance handle. The instance, if exists, could have been opened by some other user (most probably) or may be by the same user calling this API. If it was opened by some other user, then that user can very well close this instance anytime, without even knowing that the same instance handle is being used by other users as well. In that case, the handle becomes INVALID and user has to open a valid driver instance for his/her use.</dd></dl>
1119 <p>2) This function is re-entrant. </p>
1121 </div>
1122 </div>
1123 <a class="anchor" id="ga43031c6c66af92677c388c156b50480b"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_registerTccCb" ref="ga43031c6c66af92677c388c156b50480b" args="(EDMA3_DRV_Handle hEdma, const unsigned int channelId, EDMA3_RM_TccCallback tccCb, void *cbData)" -->
1124 <div class="memitem">
1125 <div class="memproto">
1126 <table class="memname">
1127 <tr>
1128 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_registerTccCb </td>
1129 <td>(</td>
1130 <td class="paramtype">EDMA3_DRV_Handle </td>
1131 <td class="paramname"> <em>hEdma</em>, </td>
1132 </tr>
1133 <tr>
1134 <td class="paramkey"></td>
1135 <td></td>
1136 <td class="paramtype">const unsigned int </td>
1137 <td class="paramname"> <em>channelId</em>, </td>
1138 </tr>
1139 <tr>
1140 <td class="paramkey"></td>
1141 <td></td>
1142 <td class="paramtype">EDMA3_RM_TccCallback </td>
1143 <td class="paramname"> <em>tccCb</em>, </td>
1144 </tr>
1145 <tr>
1146 <td class="paramkey"></td>
1147 <td></td>
1148 <td class="paramtype">void * </td>
1149 <td class="paramname"> <em>cbData</em></td><td> </td>
1150 </tr>
1151 <tr>
1152 <td></td>
1153 <td>)</td>
1154 <td></td><td></td><td></td>
1155 </tr>
1156 </table>
1157 </div>
1158 <div class="memdoc">
1160 <p>Registers a transfer completion handler for a specific DMA/QDMA channel. </p>
1161 <p>This function registers a non-NULL callback function for a specific DMA or QDMA channel and enables the completion interrupt for the TCC associated with the underlying channel in the IER/IERH register. It also sets the DRAE/DRAEH register for the TCC associated with the specified DMA/QDMA channel. If user enables the transfer completion interrupts (intermediate or final) in the OPT field of the associated PaRAM Set, the registered callback function will be called by the EDMA3 Resource Manager.</p>
1162 <p>If a call-back function is already registered for the channel, the API fails with the error code EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED.</p>
1163 <dl><dt><b>Parameters:</b></dt><dd>
1164 <table border="0" cellspacing="2" cellpadding="0">
1165 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
1166 <tr><td valign="top"></td><td valign="top"><em>channelId</em> </td><td>[IN] DMA/QDMA channel for which the callback function needs to be registered. </td></tr>
1167 <tr><td valign="top"></td><td valign="top"><em>tccCb</em> </td><td>[IN] The callback function to be registered. </td></tr>
1168 <tr><td valign="top"></td><td valign="top"><em>cbData</em> </td><td>[IN] Callback data to be passed while calling the callback function.</td></tr>
1169 </table>
1170 </dd>
1171 </dl>
1172 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
1173 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique channelId values. It is non- re-entrant for same channelId value. </dd></dl>
1175 </div>
1176 </div>
1177 <a class="anchor" id="gaa4ab2ce058e4e40a812b8a20970d4088"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_unregisterTccCb" ref="gaa4ab2ce058e4e40a812b8a20970d4088" args="(EDMA3_DRV_Handle hEdma, const unsigned int channelId)" -->
1178 <div class="memitem">
1179 <div class="memproto">
1180 <table class="memname">
1181 <tr>
1182 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_unregisterTccCb </td>
1183 <td>(</td>
1184 <td class="paramtype">EDMA3_DRV_Handle </td>
1185 <td class="paramname"> <em>hEdma</em>, </td>
1186 </tr>
1187 <tr>
1188 <td class="paramkey"></td>
1189 <td></td>
1190 <td class="paramtype">const unsigned int </td>
1191 <td class="paramname"> <em>channelId</em></td><td> </td>
1192 </tr>
1193 <tr>
1194 <td></td>
1195 <td>)</td>
1196 <td></td><td></td><td></td>
1197 </tr>
1198 </table>
1199 </div>
1200 <div class="memdoc">
1202 <p>Un-register the previously registered callback function against a DMA/QDMA channel. </p>
1203 <p>This function un-registers the previously registered callback function for the DMA/QDMA channel by removing any stored callback function. Moreover, it clears the: Interrupt Enable Register (IER/IERH) by writing to the IECR/IECRH register, for the TCC associated with that particular channel, DRA/DRAEH register for the TCC associated with the specified DMA/QDMA channel</p>
1204 <dl><dt><b>Parameters:</b></dt><dd>
1205 <table border="0" cellspacing="2" cellpadding="0">
1206 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
1207 <tr><td valign="top"></td><td valign="top"><em>channelId</em> </td><td>[IN] DMA/QDMA channel for which the callback function needs to be un-registered.</td></tr>
1208 </table>
1209 </dd>
1210 </dl>
1211 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
1212 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique channelId. It is non-re-entrant for same channelId. </dd></dl>
1214 </div>
1215 </div>
1216 <a class="anchor" id="ga276f4ecd7f1e59f09ad065b633643ae4"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setTcErrorInt" ref="ga276f4ecd7f1e59f09ad065b633643ae4" args="(unsigned int phyCtrllerInstId, unsigned int tcId, EDMA3_DRV_Tc_Err tcErr)" -->
1217 <div class="memitem">
1218 <div class="memproto">
1219 <table class="memname">
1220 <tr>
1221 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setTcErrorInt </td>
1222 <td>(</td>
1223 <td class="paramtype">unsigned int </td>
1224 <td class="paramname"> <em>phyCtrllerInstId</em>, </td>
1225 </tr>
1226 <tr>
1227 <td class="paramkey"></td>
1228 <td></td>
1229 <td class="paramtype">unsigned int </td>
1230 <td class="paramname"> <em>tcId</em>, </td>
1231 </tr>
1232 <tr>
1233 <td class="paramkey"></td>
1234 <td></td>
1235 <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga2b3b55b1d7c987a7873d8b0b085173b2">EDMA3_DRV_Tc_Err</a> </td>
1236 <td class="paramname"> <em>tcErr</em></td><td> </td>
1237 </tr>
1238 <tr>
1239 <td></td>
1240 <td>)</td>
1241 <td></td><td></td><td></td>
1242 </tr>
1243 </table>
1244 </div>
1245 <div class="memdoc">
1247 <p>Enable/disable specific EDMA3 Transfer Controller Interrupts. </p>
1248 <p>This function allows one to enable/disable specific EDMA3 Transfer Controller Interrupts. Since these interrupts don't get enabled by default, this API can be used to achieve the same.</p>
1249 <dl><dt><b>Parameters:</b></dt><dd>
1250 <table border="0" cellspacing="2" cellpadding="0">
1251 <tr><td valign="top"></td><td valign="top"><em>phyCtrllerInstId</em> </td><td>[IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0). </td></tr>
1252 <tr><td valign="top"></td><td valign="top"><em>tcId</em> </td><td>[IN] Transfer Controller Id. It starts from 0 for each EDMA3 hardware and can go upto (TCs available on EDMA3 Hardware - 1). </td></tr>
1253 <tr><td valign="top"></td><td valign="top"><em>tcErr</em> </td><td>[IN] TC Error Interrupts which need to be enabled/disabled.</td></tr>
1254 </table>
1255 </dd>
1256 </dl>
1257 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error code</dd></dl>
1258 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique combination of EDMA3 hw and TC. It is non-re-entrant for same combination. </dd></dl>
1260 </div>
1261 </div>
1262 <a class="anchor" id="ga85bad51ec992ce36ed7f28842b7d8219"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getChannelStatus" ref="ga85bad51ec992ce36ed7f28842b7d8219" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *lchStatus)" -->
1263 <div class="memitem">
1264 <div class="memproto">
1265 <table class="memname">
1266 <tr>
1267 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getChannelStatus </td>
1268 <td>(</td>
1269 <td class="paramtype">EDMA3_DRV_Handle </td>
1270 <td class="paramname"> <em>hEdma</em>, </td>
1271 </tr>
1272 <tr>
1273 <td class="paramkey"></td>
1274 <td></td>
1275 <td class="paramtype">unsigned int </td>
1276 <td class="paramname"> <em>lCh</em>, </td>
1277 </tr>
1278 <tr>
1279 <td class="paramkey"></td>
1280 <td></td>
1281 <td class="paramtype">unsigned int * </td>
1282 <td class="paramname"> <em>lchStatus</em></td><td> </td>
1283 </tr>
1284 <tr>
1285 <td></td>
1286 <td>)</td>
1287 <td></td><td></td><td></td>
1288 </tr>
1289 </table>
1290 </div>
1291 <div class="memdoc">
1293 <p>Get the current status of the DMA/QDMA channel. </p>
1294 <p>This function returns the current status of the specific DMA/QDMA channel. For a DMA channel, it checks whether an event is pending in ER, transfer completion interrupt is pending in IPR and event miss error interrupt is pending in EMR or not. For a QDMA channel, it checks whether a transfer completion interrupt is pending in IPR and event miss error interrupt is pending in QEMR or not.</p>
1295 <dl><dt><b>Parameters:</b></dt><dd>
1296 <table border="0" cellspacing="2" cellpadding="0">
1297 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
1298 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] DMA/QDMA channel for which the current status is required. </td></tr>
1299 <tr><td valign="top"></td><td valign="top"><em>lchStatus</em> </td><td>[IN/OUT]Status of the channel. Defines mentioned above are used (and may be combined) to return the actual status.</td></tr>
1300 </table>
1301 </dd>
1302 </dl>
1303 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
1304 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
1306 </div>
1307 </div>
1308 <a class="anchor" id="gaba9535a00375255494df382382b834de"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_mapTccLinkCh" ref="gaba9535a00375255494df382382b834de" args="(EDMA3_DRV_Handle hEdma, unsigned int linkCh, unsigned int tcc)" -->
1309 <div class="memitem">
1310 <div class="memproto">
1311 <table class="memname">
1312 <tr>
1313 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_mapTccLinkCh </td>
1314 <td>(</td>
1315 <td class="paramtype">EDMA3_DRV_Handle </td>
1316 <td class="paramname"> <em>hEdma</em>, </td>
1317 </tr>
1318 <tr>
1319 <td class="paramkey"></td>
1320 <td></td>
1321 <td class="paramtype">unsigned int </td>
1322 <td class="paramname"> <em>linkCh</em>, </td>
1323 </tr>
1324 <tr>
1325 <td class="paramkey"></td>
1326 <td></td>
1327 <td class="paramtype">unsigned int </td>
1328 <td class="paramname"> <em>tcc</em></td><td> </td>
1329 </tr>
1330 <tr>
1331 <td></td>
1332 <td>)</td>
1333 <td></td><td></td><td></td>
1334 </tr>
1335 </table>
1336 </div>
1337 <div class="memdoc">
1339 <p>Associates a link channel and a TCC. </p>
1340 <p>This API is used to map a TCC to a LINK channel. It should be used with LINK channels ONLY else it will fail. It will copy the TCC code in the OPT field of the param set associated with the link channel.</p>
1341 <dl><dt><b>Parameters:</b></dt><dd>
1342 <table border="0" cellspacing="2" cellpadding="0">
1343 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
1344 <tr><td valign="top"></td><td valign="top"><em>linkCh</em> </td><td>[IN] Link Channel to which a particular TCC needs to be mapped. </td></tr>
1345 <tr><td valign="top"></td><td valign="top"><em>tcc</em> </td><td>[IN] TCC which needs to be mapped.</td></tr>
1346 </table>
1347 </dd>
1348 </dl>
1349 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
1350 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique linkCh values. It is non-re-entrant for same linkCh values. </dd></dl>
1352 </div>
1353 </div>
1354 <a class="anchor" id="ga1ff9d2ede0fb29c7194f15ba58ad8e0f"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_initXbarEventMap" ref="ga1ff9d2ede0fb29c7194f15ba58ad8e0f" args="(EDMA3_DRV_Handle hEdma, const EDMA3_DRV_GblXbarToChanConfigParams *edmaGblXbarConfig, EDMA3_DRV_mapXbarEvtToChan mapXbarEvtFunc, EDMA3_DRV_xbarConfigScr configXbarScr)" -->
1355 <div class="memitem">
1356 <div class="memproto">
1357 <table class="memname">
1358 <tr>
1359 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_initXbarEventMap </td>
1360 <td>(</td>
1361 <td class="paramtype">EDMA3_DRV_Handle </td>
1362 <td class="paramname"> <em>hEdma</em>, </td>
1363 </tr>
1364 <tr>
1365 <td class="paramkey"></td>
1366 <td></td>
1367 <td class="paramtype">const <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a> * </td>
1368 <td class="paramname"> <em>edmaGblXbarConfig</em>, </td>
1369 </tr>
1370 <tr>
1371 <td class="paramkey"></td>
1372 <td></td>
1373 <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gae7867a62f61919df85b323ce981163e4">EDMA3_DRV_mapXbarEvtToChan</a> </td>
1374 <td class="paramname"> <em>mapXbarEvtFunc</em>, </td>
1375 </tr>
1376 <tr>
1377 <td class="paramkey"></td>
1378 <td></td>
1379 <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga02168cc5612b65b34812ce52df7154a3">EDMA3_DRV_xbarConfigScr</a> </td>
1380 <td class="paramname"> <em>configXbarScr</em></td><td> </td>
1381 </tr>
1382 <tr>
1383 <td></td>
1384 <td>)</td>
1385 <td></td><td></td><td></td>
1386 </tr>
1387 </table>
1388 </div>
1389 <div class="memdoc">
1391 <p>Initialize the cross bar mapped event to channel function. </p>
1392 <p>This API provides interface to associate the cross bar mapped event to edma channel in the driver. This function will called by the application during initilization. User could pass the application specific configuration structure during init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available. </p>
1393 <dl><dt><b>Parameters:</b></dt><dd>
1394 <table border="0" cellspacing="2" cellpadding="0">
1395 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
1396 <tr><td valign="top"></td><td valign="top"><em>edmaGblXbarConfig</em> </td><td>[IN] This is the configuration data structure for mapping the events to the channel </td></tr>
1397 <tr><td valign="top"></td><td valign="top"><em>mapXbarEvtFunc</em> </td><td>[IN] This is the user defined function for mapping the cross bar event to channel.</td></tr>
1398 </table>
1399 </dd>
1400 </dl>
1401 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
1402 <dl class="note"><dt><b>Note:</b></dt><dd>This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data structures, to make it re-entrant. </dd></dl>
1404 </div>
1405 </div>
1406 </div>
1407 <hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:38 2011 for EDMA3 Driver by
1408 <a href="http://www.doxygen.org/index.html">
1409 <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
1410 </body>
1411 </html>