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21 <h1>EDMA3 Driver Basic APIs<br/>
22 <small>
23 [<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n.html">EDMA3 Driver APIs</a>]</small>
24 </h1><table border="0" cellpadding="0" cellspacing="0">
25 <tr><td colspan="2"><h2>Functions</h2></td></tr>
26 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga301122cb5f7cca50ae824611bd816f8e">EDMA3_DRV_requestChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int *pLCh, unsigned int *pTcc, EDMA3_RM_EventQueue evtQueue, EDMA3_RM_TccCallback tccCb, void *cbData)</td></tr>
27 <tr><td class="mdescLeft"> </td><td class="mdescRight">Request a DMA/QDMA/Link channel. <a href="#ga301122cb5f7cca50ae824611bd816f8e"></a><br/></td></tr>
28 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga0589ed9b15b42ecefc4a6ccd8e1758fc">EDMA3_DRV_freeChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int channelId)</td></tr>
29 <tr><td class="mdescLeft"> </td><td class="mdescRight">Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings. <a href="#ga0589ed9b15b42ecefc4a6ccd8e1758fc"></a><br/></td></tr>
30 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga35daa16c899b38d5af19d7d2d22777a5">EDMA3_DRV_clearErrorBits</a> (EDMA3_DRV_Handle hEdma, unsigned int channelId)</td></tr>
31 <tr><td class="mdescLeft"> </td><td class="mdescRight">Disables the DMA Channel by clearing the Event Enable Register and clears Error Register & Secondary Event Register for a specific DMA channel. <a href="#ga35daa16c899b38d5af19d7d2d22777a5"></a><br/></td></tr>
32 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga095f1fea5377f30e65e6135414ad6e77">EDMA3_DRV_setOptField</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gaa0c576e8e46ac8db85c05bf73c01a5f9">EDMA3_DRV_OptField</a> optField, unsigned int newOptFieldVal)</td></tr>
33 <tr><td class="mdescLeft"> </td><td class="mdescRight">Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. <a href="#ga095f1fea5377f30e65e6135414ad6e77"></a><br/></td></tr>
34 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gad6bc4ec80662493860491f6374af7695">EDMA3_DRV_getOptField</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gaa0c576e8e46ac8db85c05bf73c01a5f9">EDMA3_DRV_OptField</a> optField, unsigned int *optFieldVal)</td></tr>
35 <tr><td class="mdescLeft"> </td><td class="mdescRight">Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. <a href="#gad6bc4ec80662493860491f6374af7695"></a><br/></td></tr>
36 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga95f7e74ccb30f273b42b0cc08664ba55">EDMA3_DRV_setSrcParams</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int srcAddr, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga5896f43e878f4e9c47b449fccdec3af9">EDMA3_DRV_AddrMode</a> addrMode, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8c37673293432ed46f9e26f04f5681dc">EDMA3_DRV_FifoWidth</a> fifoWidth)</td></tr>
37 <tr><td class="mdescLeft"> </td><td class="mdescRight">DMA source parameters setup. <a href="#ga95f7e74ccb30f273b42b0cc08664ba55"></a><br/></td></tr>
38 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gab4be03dc87dc50975c5ea870944dcee4">EDMA3_DRV_setDestParams</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int destAddr, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga5896f43e878f4e9c47b449fccdec3af9">EDMA3_DRV_AddrMode</a> addrMode, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8c37673293432ed46f9e26f04f5681dc">EDMA3_DRV_FifoWidth</a> fifoWidth)</td></tr>
39 <tr><td class="mdescLeft"> </td><td class="mdescRight">DMA Destination parameters setup. <a href="#gab4be03dc87dc50975c5ea870944dcee4"></a><br/></td></tr>
40 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga212d4abb6f644084b3a29b856c0ef0ac">EDMA3_DRV_setSrcIndex</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, int srcBIdx, int srcCIdx)</td></tr>
41 <tr><td class="mdescLeft"> </td><td class="mdescRight">DMA source index setup. <a href="#ga212d4abb6f644084b3a29b856c0ef0ac"></a><br/></td></tr>
42 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga4e7ec3c58f498bdbac7a507e0cba6221">EDMA3_DRV_setDestIndex</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, int destBIdx, int destCIdx)</td></tr>
43 <tr><td class="mdescLeft"> </td><td class="mdescRight">DMA destination index setup. <a href="#ga4e7ec3c58f498bdbac7a507e0cba6221"></a><br/></td></tr>
44 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga8e54f2e2e016bc557ed3374eb46d62ee">EDMA3_DRV_setTransferParams</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsigned int cCnt, unsigned int bCntReload, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga1cc0705e142298a424a312034bd3b2c2">EDMA3_DRV_SyncType</a> syncType)</td></tr>
45 <tr><td class="mdescLeft"> </td><td class="mdescRight">DMA transfer parameters setup. <a href="#ga8e54f2e2e016bc557ed3374eb46d62ee"></a><br/></td></tr>
46 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga5c80afa7645f1e492951c0419c21dbe6">EDMA3_DRV_enableTransfer</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> trigMode)</td></tr>
47 <tr><td class="mdescLeft"> </td><td class="mdescRight">Start EDMA transfer on the specified channel. <a href="#ga5c80afa7645f1e492951c0419c21dbe6"></a><br/></td></tr>
48 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gadb56f2a6d896c03a77f14c8fdf57a397">EDMA3_DRV_disableTransfer</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> trigMode)</td></tr>
49 <tr><td class="mdescLeft"> </td><td class="mdescRight">Disable DMA transfer on the specified channel. <a href="#gadb56f2a6d896c03a77f14c8fdf57a397"></a><br/></td></tr>
50 <tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga11070a2e9fb80e16fe96e8ad210e0b59">EDMA3_DRV_disableLogicalChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> trigMode)</td></tr>
51 <tr><td class="mdescLeft"> </td><td class="mdescRight">Disable the event driven DMA channel or QDMA channel. <a href="#ga11070a2e9fb80e16fe96e8ad210e0b59"></a><br/></td></tr>
52 </table>
53 <hr/><h2>Function Documentation</h2>
54 <a class="anchor" id="ga301122cb5f7cca50ae824611bd816f8e"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_requestChannel" ref="ga301122cb5f7cca50ae824611bd816f8e" args="(EDMA3_DRV_Handle hEdma, unsigned int *pLCh, unsigned int *pTcc, EDMA3_RM_EventQueue evtQueue, EDMA3_RM_TccCallback tccCb, void *cbData)" -->
55 <div class="memitem">
56 <div class="memproto">
57 <table class="memname">
58 <tr>
59 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_requestChannel </td>
60 <td>(</td>
61 <td class="paramtype">EDMA3_DRV_Handle </td>
62 <td class="paramname"> <em>hEdma</em>, </td>
63 </tr>
64 <tr>
65 <td class="paramkey"></td>
66 <td></td>
67 <td class="paramtype">unsigned int * </td>
68 <td class="paramname"> <em>pLCh</em>, </td>
69 </tr>
70 <tr>
71 <td class="paramkey"></td>
72 <td></td>
73 <td class="paramtype">unsigned int * </td>
74 <td class="paramname"> <em>pTcc</em>, </td>
75 </tr>
76 <tr>
77 <td class="paramkey"></td>
78 <td></td>
79 <td class="paramtype">EDMA3_RM_EventQueue </td>
80 <td class="paramname"> <em>evtQueue</em>, </td>
81 </tr>
82 <tr>
83 <td class="paramkey"></td>
84 <td></td>
85 <td class="paramtype">EDMA3_RM_TccCallback </td>
86 <td class="paramname"> <em>tccCb</em>, </td>
87 </tr>
88 <tr>
89 <td class="paramkey"></td>
90 <td></td>
91 <td class="paramtype">void * </td>
92 <td class="paramname"> <em>cbData</em></td><td> </td>
93 </tr>
94 <tr>
95 <td></td>
96 <td>)</td>
97 <td></td><td></td><td></td>
98 </tr>
99 </table>
100 </div>
101 <div class="memdoc">
103 <p>Request a DMA/QDMA/Link channel. </p>
104 <p>Each channel (DMA/QDMA/Link) must be requested before initiating a DMA transfer on that channel.</p>
105 <p>This API is used to allocate a logical channel (DMA/QDMA/Link) along with the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are also allocated along with the requested channel. User can also specify a specific TCC which needs to be allocated with the DMA/QDMA channel or else can request any available TCC.</p>
106 <p>For Link channels, ONLY a PaRAM Set is allocated and the allocated PaRAM Set number is returned as the logical channel no. A TCC code can also be specified while making the request. This TCC code will be copied to the LINK field of the allocated PaRAM Set and will be associated with the Link channel.</p>
107 <p>User can request a specific logical channel - DMA, QDMA and Link, by passing the channel id in 'pLCh'. Note that the channel id is the same as the actual resource id in case of DMA channels and Link channels. For DMA channels, channel id lies between 0 and (max dma channels - 1). For Link channels, channel id lies between (max dma channels) and (max param sets - 1). To allocate specific QDMA channels, user SHOULD use the defines EDMA3_DRV_QDMA_CHANNEL_X mentioned above.</p>
108 <p>User can also request ANY available logical channel by specifying the below mentioned values in '*pLCh': a) EDMA3_DRV_DMA_CHANNEL_ANY: For DMA channels b) EDMA3_DRV_QDMA_CHANNEL_ANY: For QDMA channels, and c) EDMA3_DRV_LINK_CHANNEL: For Link channels. Normally user should use this value to request link channels (PaRAM Sets used for linking purpose only), unless he wants to use some specific link channels (PaRAM Sets) which is also allowed. d) EDMA3_DRV_LINK_CHANNEL_WITH_TCC: For Link channels. User should use this value to request link channels with TCC code.</p>
109 <p>This API internally uses EDMA3_RM_allocResource () to allocate the desired resources (DMA/QDMA channel, PaRAM Set and TCC).</p>
110 <p>This API also registers a specific callback function, in case the same is provided, against the allocated TCC. To do this, this API calls EDMA3_RM_registerTccCb(), which is a part of the Resource Manager. Please note that the interrupts are enabled for the specific TCC only if callback function is provided. In the absence of this, the API assumes that the requested logical channel is going to be used in Poll mode environment.</p>
111 <p>For DMA/QDMA channels, after allocating all the EDMA3 resources, this API sets the TCC field of the OPT PaRAM Word with the allocated TCC. It also sets the event queue for the channel allocated. The event queue needs to be specified by the user.</p>
112 <p>For DMA channel, it also sets the DCHMAP register, if required.</p>
113 <p>For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and enables the QDMA channel by writing to the QEESR register.</p>
114 <dl><dt><b>Parameters:</b></dt><dd>
115 <table border="0" cellspacing="2" cellpadding="0">
116 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the previously opened Driver Instance. </td></tr>
117 <tr><td valign="top"></td><td valign="top"><em>pLCh</em> </td><td>[IN/OUT] Requested logical channel id. Examples:</p>
118 <ul>
119 <li>EDMA3_DRV_HW_CHANNEL_EVENT_0</li>
120 <li>To request a DMA Master Channel mapped to EDMA Event 0.</li>
121 </ul>
122 </td></tr>
123 </table>
124 </dd>
125 </dl>
126 <ul>
127 <li>EDMA3_DRV_DMA_CHANNEL_ANY</li>
128 <li>For requesting any DMA Master channel with no event mapping.</li>
129 </ul>
130 <ul>
131 <li>EDMA3_DRV_QDMA_CHANNEL_ANY</li>
132 <li>For requesting any QDMA Master channel</li>
133 </ul>
134 <ul>
135 <li>EDMA3_DRV_QDMA_CHANNEL_0</li>
136 <li>For requesting the QDMA Channel 0.</li>
137 </ul>
138 <ul>
139 <li>EDMA3_DRV_LINK_CHANNEL</li>
140 <li>For requesting a DMA Slave Channel,</li>
141 <li>to be linked to some other Master</li>
142 <li>channel.</li>
143 </ul>
144 <ul>
145 <li>EDMA3_DRV_LINK_CHANNEL_WITH_TCC</li>
146 <li>For requesting a DMA Slave Channel,</li>
147 <li>to be linked to some other Master</li>
148 <li>channel, with a TCC associated with it.</li>
149 </ul>
150 <p>In case user passes a specific channel Id, pLCh value is left unchanged. In case user requests ANY available resource, the allocated channel id is returned in pLCh.</p>
151 <dl class="note"><dt><b>Note:</b></dt><dd>To request a PaRAM Set for the purpose of linking to another channel, call the function with</dd></dl>
152 <p>*pLCh = EDMA3_DRV_LINK_CHANNEL or EDMA3_DRV_LINK_CHANNEL_WITH_TCC</p>
153 <p>This function will update *pLCh with the allocated Link channel handle.</p>
154 <dl><dt><b>Parameters:</b></dt><dd>
155 <table border="0" cellspacing="2" cellpadding="0">
156 <tr><td valign="top"></td><td valign="top"><em>pTcc</em> </td><td>[IN/OUT] The channel number on which the completion/error interrupt is generated. Not used if user requested for a Link channel. Examples:</p>
157 <ul>
158 <li>EDMA3_DRV_HW_CHANNEL_EVENT_0</li>
159 <li>To request TCC associated with</li>
160 <li>DMA Master Channel mapped to EDMA</li>
161 <li>event 0.</li>
162 </ul>
163 </td></tr>
164 </table>
165 </dd>
166 </dl>
167 <ul>
168 <li>EDMA3_DRV_TCC_ANY</li>
169 <li>For requesting any TCC with no</li>
170 <li>channel mapping. In case user passes a specific TCC value, pTcc value is left unchanged. In case user requests ANY available TCC, the allocated one is returned in pTcc</li>
171 </ul>
172 <dl><dt><b>Parameters:</b></dt><dd>
173 <table border="0" cellspacing="2" cellpadding="0">
174 <tr><td valign="top"></td><td valign="top"><em>evtQueue</em> </td><td>[IN] Event Queue Number to which the channel will be mapped (valid only for the Master Channel (DMA/QDMA) request)</td></tr>
175 <tr><td valign="top"></td><td valign="top"><em>tccCb</em> </td><td>[IN] TCC callback - caters to channel- specific events like "Event Miss Error" or "Transfer Complete"</td></tr>
176 <tr><td valign="top"></td><td valign="top"><em>cbData</em> </td><td>[IN] Data which will be passed directly to the tccCb callback function</td></tr>
177 </table>
178 </dd>
179 </dl>
180 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error code</dd></dl>
181 <dl class="note"><dt><b>Note:</b></dt><dd>This function internally uses EDMA3 Resource Manager, which acquires a RM Instance specific semaphore to prevent simultaneous access to the global pool of resources. It also disables the global interrupts while modifying the global CC registers. It is re-entrant, but SHOULD NOT be called from the user callback function (ISR context). </dd></dl>
183 </div>
184 </div>
185 <a class="anchor" id="ga0589ed9b15b42ecefc4a6ccd8e1758fc"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_freeChannel" ref="ga0589ed9b15b42ecefc4a6ccd8e1758fc" args="(EDMA3_DRV_Handle hEdma, unsigned int channelId)" -->
186 <div class="memitem">
187 <div class="memproto">
188 <table class="memname">
189 <tr>
190 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_freeChannel </td>
191 <td>(</td>
192 <td class="paramtype">EDMA3_DRV_Handle </td>
193 <td class="paramname"> <em>hEdma</em>, </td>
194 </tr>
195 <tr>
196 <td class="paramkey"></td>
197 <td></td>
198 <td class="paramtype">unsigned int </td>
199 <td class="paramname"> <em>channelId</em></td><td> </td>
200 </tr>
201 <tr>
202 <td></td>
203 <td>)</td>
204 <td></td><td></td><td></td>
205 </tr>
206 </table>
207 </div>
208 <div class="memdoc">
210 <p>Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings. </p>
211 <p>This API internally uses EDMA3_RM_freeResource () to free the desired resources.</p>
212 <p>For Link channels, this API only frees the associated PaRAM Set.</p>
213 <p>For DMA/QDMA channels, it does the following operations: a) Disable any ongoing transfer on the channel, b) Unregister the TCC Callback function and disable the interrupts, c) Remove the channel to Event Queue mapping, d) For DMA channels, clear the DCHMAP register, if available e) For QDMA channels, clear the QCHMAP register, f) Frees the DMA/QDMA channel in the end.</p>
214 <dl><dt><b>Parameters:</b></dt><dd>
215 <table border="0" cellspacing="2" cellpadding="0">
216 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
217 <tr><td valign="top"></td><td valign="top"><em>channelId</em> </td><td>[IN] Logical Channel number to be freed.</td></tr>
218 </table>
219 </dd>
220 </dl>
221 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error code</dd></dl>
222 <dl class="note"><dt><b>Note:</b></dt><dd>This function disables the global interrupts while modifying the global CC registers and while modifying global data structures, to prevent simultaneous access to the global pool of resources. It internally calls EDMA3_RM_freeResource () for resource de-allocation. It is re-entrant. </dd></dl>
224 </div>
225 </div>
226 <a class="anchor" id="ga35daa16c899b38d5af19d7d2d22777a5"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_clearErrorBits" ref="ga35daa16c899b38d5af19d7d2d22777a5" args="(EDMA3_DRV_Handle hEdma, unsigned int channelId)" -->
227 <div class="memitem">
228 <div class="memproto">
229 <table class="memname">
230 <tr>
231 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_clearErrorBits </td>
232 <td>(</td>
233 <td class="paramtype">EDMA3_DRV_Handle </td>
234 <td class="paramname"> <em>hEdma</em>, </td>
235 </tr>
236 <tr>
237 <td class="paramkey"></td>
238 <td></td>
239 <td class="paramtype">unsigned int </td>
240 <td class="paramname"> <em>channelId</em></td><td> </td>
241 </tr>
242 <tr>
243 <td></td>
244 <td>)</td>
245 <td></td><td></td><td></td>
246 </tr>
247 </table>
248 </div>
249 <div class="memdoc">
251 <p>Disables the DMA Channel by clearing the Event Enable Register and clears Error Register & Secondary Event Register for a specific DMA channel. </p>
252 <p>This API clears the Event Enable register, Event Miss register and Secondary Event register for a specific DMA channel. It also clears the CC Error register.</p>
253 <dl><dt><b>Parameters:</b></dt><dd>
254 <table border="0" cellspacing="2" cellpadding="0">
255 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
256 <tr><td valign="top"></td><td valign="top"><em>channelId</em> </td><td>[IN] DMA Channel needs to be cleaned.</td></tr>
257 </table>
258 </dd>
259 </dl>
260 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error code</dd></dl>
261 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique channelId values. It is non- re-entrant for same channelId value. </dd></dl>
263 </div>
264 </div>
265 <a class="anchor" id="ga095f1fea5377f30e65e6135414ad6e77"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setOptField" ref="ga095f1fea5377f30e65e6135414ad6e77" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int newOptFieldVal)" -->
266 <div class="memitem">
267 <div class="memproto">
268 <table class="memname">
269 <tr>
270 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setOptField </td>
271 <td>(</td>
272 <td class="paramtype">EDMA3_DRV_Handle </td>
273 <td class="paramname"> <em>hEdma</em>, </td>
274 </tr>
275 <tr>
276 <td class="paramkey"></td>
277 <td></td>
278 <td class="paramtype">unsigned int </td>
279 <td class="paramname"> <em>lCh</em>, </td>
280 </tr>
281 <tr>
282 <td class="paramkey"></td>
283 <td></td>
284 <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gaa0c576e8e46ac8db85c05bf73c01a5f9">EDMA3_DRV_OptField</a> </td>
285 <td class="paramname"> <em>optField</em>, </td>
286 </tr>
287 <tr>
288 <td class="paramkey"></td>
289 <td></td>
290 <td class="paramtype">unsigned int </td>
291 <td class="paramname"> <em>newOptFieldVal</em></td><td> </td>
292 </tr>
293 <tr>
294 <td></td>
295 <td>)</td>
296 <td></td><td></td><td></td>
297 </tr>
298 </table>
299 </div>
300 <div class="memdoc">
302 <p>Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. </p>
303 <p>This API can be used to set various optional parameters for an EDMA3 transfer. Like enable/disable completion interrupts, enable/disable chaining, setting the transfer mode (A/AB Sync), setting the FIFO width etc.</p>
304 <dl><dt><b>Parameters:</b></dt><dd>
305 <table border="0" cellspacing="2" cellpadding="0">
306 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
307 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] Logical Channel, bound to which PaRAM set OPT field needs to be set. </td></tr>
308 <tr><td valign="top"></td><td valign="top"><em>optField</em> </td><td>[IN] The particular field of OPT Word that needs setting </td></tr>
309 <tr><td valign="top"></td><td valign="top"><em>newOptFieldVal</em> </td><td>[IN] The new OPT field value</td></tr>
310 </table>
311 </dd>
312 </dl>
313 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
314 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
316 </div>
317 </div>
318 <a class="anchor" id="gad6bc4ec80662493860491f6374af7695"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getOptField" ref="gad6bc4ec80662493860491f6374af7695" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int *optFieldVal)" -->
319 <div class="memitem">
320 <div class="memproto">
321 <table class="memname">
322 <tr>
323 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getOptField </td>
324 <td>(</td>
325 <td class="paramtype">EDMA3_DRV_Handle </td>
326 <td class="paramname"> <em>hEdma</em>, </td>
327 </tr>
328 <tr>
329 <td class="paramkey"></td>
330 <td></td>
331 <td class="paramtype">unsigned int </td>
332 <td class="paramname"> <em>lCh</em>, </td>
333 </tr>
334 <tr>
335 <td class="paramkey"></td>
336 <td></td>
337 <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gaa0c576e8e46ac8db85c05bf73c01a5f9">EDMA3_DRV_OptField</a> </td>
338 <td class="paramname"> <em>optField</em>, </td>
339 </tr>
340 <tr>
341 <td class="paramkey"></td>
342 <td></td>
343 <td class="paramtype">unsigned int * </td>
344 <td class="paramname"> <em>optFieldVal</em></td><td> </td>
345 </tr>
346 <tr>
347 <td></td>
348 <td>)</td>
349 <td></td><td></td><td></td>
350 </tr>
351 </table>
352 </div>
353 <div class="memdoc">
355 <p>Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. </p>
356 <p>This API can be used to read various optional parameters for an EDMA3 transfer. Like enable/disable completion interrupts, enable/disable chaining, setting the transfer mode (A/AB Sync), setting the FIFO width etc.</p>
357 <dl><dt><b>Parameters:</b></dt><dd>
358 <table border="0" cellspacing="2" cellpadding="0">
359 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
360 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] Logical Channel, bound to which PaRAM set OPT field is required. </td></tr>
361 <tr><td valign="top"></td><td valign="top"><em>optField</em> </td><td>[IN] The particular field of OPT Word that is needed </td></tr>
362 <tr><td valign="top"></td><td valign="top"><em>optFieldVal</em> </td><td>[IN/OUT] Value of the OPT field</td></tr>
363 </table>
364 </dd>
365 </dl>
366 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
367 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
369 </div>
370 </div>
371 <a class="anchor" id="ga95f7e74ccb30f273b42b0cc08664ba55"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setSrcParams" ref="ga95f7e74ccb30f273b42b0cc08664ba55" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int srcAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)" -->
372 <div class="memitem">
373 <div class="memproto">
374 <table class="memname">
375 <tr>
376 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setSrcParams </td>
377 <td>(</td>
378 <td class="paramtype">EDMA3_DRV_Handle </td>
379 <td class="paramname"> <em>hEdma</em>, </td>
380 </tr>
381 <tr>
382 <td class="paramkey"></td>
383 <td></td>
384 <td class="paramtype">unsigned int </td>
385 <td class="paramname"> <em>lCh</em>, </td>
386 </tr>
387 <tr>
388 <td class="paramkey"></td>
389 <td></td>
390 <td class="paramtype">unsigned int </td>
391 <td class="paramname"> <em>srcAddr</em>, </td>
392 </tr>
393 <tr>
394 <td class="paramkey"></td>
395 <td></td>
396 <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga5896f43e878f4e9c47b449fccdec3af9">EDMA3_DRV_AddrMode</a> </td>
397 <td class="paramname"> <em>addrMode</em>, </td>
398 </tr>
399 <tr>
400 <td class="paramkey"></td>
401 <td></td>
402 <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8c37673293432ed46f9e26f04f5681dc">EDMA3_DRV_FifoWidth</a> </td>
403 <td class="paramname"> <em>fifoWidth</em></td><td> </td>
404 </tr>
405 <tr>
406 <td></td>
407 <td>)</td>
408 <td></td><td></td><td></td>
409 </tr>
410 </table>
411 </div>
412 <div class="memdoc">
414 <p>DMA source parameters setup. </p>
415 <p>It is used to program the source address, source side addressing mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.</p>
416 <p>In FIFO Addressing mode, memory location must be 32 bytes aligned.</p>
417 <dl><dt><b>Parameters:</b></dt><dd>
418 <table border="0" cellspacing="2" cellpadding="0">
419 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
420 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] Logical Channel for which the source parameters are to be configured </td></tr>
421 <tr><td valign="top"></td><td valign="top"><em>srcAddr</em> </td><td>[IN] Source address </td></tr>
422 <tr><td valign="top"></td><td valign="top"><em>addrMode</em> </td><td>[IN] Address mode [FIFO or Increment] </td></tr>
423 <tr><td valign="top"></td><td valign="top"><em>fifoWidth</em> </td><td>[IN] Width of FIFO (Valid only if addrMode is FIFO)</p>
424 <ol type="1">
425 <li>0 - 8 bit</li>
426 <li>1 - 16 bit</li>
427 <li>2 - 32 bit</li>
428 <li>3 - 64 bit</li>
429 <li>4 - 128 bit</li>
430 <li>5 - 256 bit</li>
431 </ol>
432 </td></tr>
433 </table>
434 </dd>
435 </dl>
436 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
437 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
439 </div>
440 </div>
441 <a class="anchor" id="gab4be03dc87dc50975c5ea870944dcee4"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setDestParams" ref="gab4be03dc87dc50975c5ea870944dcee4" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int destAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)" -->
442 <div class="memitem">
443 <div class="memproto">
444 <table class="memname">
445 <tr>
446 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setDestParams </td>
447 <td>(</td>
448 <td class="paramtype">EDMA3_DRV_Handle </td>
449 <td class="paramname"> <em>hEdma</em>, </td>
450 </tr>
451 <tr>
452 <td class="paramkey"></td>
453 <td></td>
454 <td class="paramtype">unsigned int </td>
455 <td class="paramname"> <em>lCh</em>, </td>
456 </tr>
457 <tr>
458 <td class="paramkey"></td>
459 <td></td>
460 <td class="paramtype">unsigned int </td>
461 <td class="paramname"> <em>destAddr</em>, </td>
462 </tr>
463 <tr>
464 <td class="paramkey"></td>
465 <td></td>
466 <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga5896f43e878f4e9c47b449fccdec3af9">EDMA3_DRV_AddrMode</a> </td>
467 <td class="paramname"> <em>addrMode</em>, </td>
468 </tr>
469 <tr>
470 <td class="paramkey"></td>
471 <td></td>
472 <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8c37673293432ed46f9e26f04f5681dc">EDMA3_DRV_FifoWidth</a> </td>
473 <td class="paramname"> <em>fifoWidth</em></td><td> </td>
474 </tr>
475 <tr>
476 <td></td>
477 <td>)</td>
478 <td></td><td></td><td></td>
479 </tr>
480 </table>
481 </div>
482 <div class="memdoc">
484 <p>DMA Destination parameters setup. </p>
485 <p>It is used to program the destination address, destination side addressing mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.</p>
486 <p>In FIFO Addressing mode, memory location must be 32 bytes aligned.</p>
487 <dl><dt><b>Parameters:</b></dt><dd>
488 <table border="0" cellspacing="2" cellpadding="0">
489 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
490 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] Logical Channel for which the destination parameters are to be configured </td></tr>
491 <tr><td valign="top"></td><td valign="top"><em>destAddr</em> </td><td>[IN] Destination address </td></tr>
492 <tr><td valign="top"></td><td valign="top"><em>addrMode</em> </td><td>[IN] Address mode [FIFO or Increment] </td></tr>
493 <tr><td valign="top"></td><td valign="top"><em>fifoWidth</em> </td><td>[IN] Width of FIFO (Valid only if addrMode is FIFO)</p>
494 <ol type="1">
495 <li>0 - 8 bit</li>
496 <li>1 - 16 bit</li>
497 <li>2 - 32 bit</li>
498 <li>3 - 64 bit</li>
499 <li>4 - 128 bit</li>
500 <li>5 - 256 bit</li>
501 </ol>
502 </td></tr>
503 </table>
504 </dd>
505 </dl>
506 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
507 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
509 </div>
510 </div>
511 <a class="anchor" id="ga212d4abb6f644084b3a29b856c0ef0ac"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setSrcIndex" ref="ga212d4abb6f644084b3a29b856c0ef0ac" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, int srcBIdx, int srcCIdx)" -->
512 <div class="memitem">
513 <div class="memproto">
514 <table class="memname">
515 <tr>
516 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setSrcIndex </td>
517 <td>(</td>
518 <td class="paramtype">EDMA3_DRV_Handle </td>
519 <td class="paramname"> <em>hEdma</em>, </td>
520 </tr>
521 <tr>
522 <td class="paramkey"></td>
523 <td></td>
524 <td class="paramtype">unsigned int </td>
525 <td class="paramname"> <em>lCh</em>, </td>
526 </tr>
527 <tr>
528 <td class="paramkey"></td>
529 <td></td>
530 <td class="paramtype">int </td>
531 <td class="paramname"> <em>srcBIdx</em>, </td>
532 </tr>
533 <tr>
534 <td class="paramkey"></td>
535 <td></td>
536 <td class="paramtype">int </td>
537 <td class="paramname"> <em>srcCIdx</em></td><td> </td>
538 </tr>
539 <tr>
540 <td></td>
541 <td>)</td>
542 <td></td><td></td><td></td>
543 </tr>
544 </table>
545 </div>
546 <div class="memdoc">
548 <p>DMA source index setup. </p>
549 <p>It is used to program the source B index and source C index.</p>
550 <p>SRCBIDX is a 16-bit signed value (2s complement) used for source address modification between each array in the 2nd dimension. Valid values for SRCBIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-synchronized and AB-synchronized transfers.</p>
551 <p>SRCCIDX is a 16-bit signed value (2s complement) used for source address modification in the 3rd dimension. Valid values for SRCCIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when SRCCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame, while the current array in an AB-synchronized transfer is the first array in the frame.</p>
552 <dl><dt><b>Parameters:</b></dt><dd>
553 <table border="0" cellspacing="2" cellpadding="0">
554 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
555 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] Logical Channel for which source indices are to be configured </td></tr>
556 <tr><td valign="top"></td><td valign="top"><em>srcBIdx</em> </td><td>[IN] Source B index </td></tr>
557 <tr><td valign="top"></td><td valign="top"><em>srcCIdx</em> </td><td>[IN] Source C index</td></tr>
558 </table>
559 </dd>
560 </dl>
561 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
562 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
564 </div>
565 </div>
566 <a class="anchor" id="ga4e7ec3c58f498bdbac7a507e0cba6221"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setDestIndex" ref="ga4e7ec3c58f498bdbac7a507e0cba6221" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, int destBIdx, int destCIdx)" -->
567 <div class="memitem">
568 <div class="memproto">
569 <table class="memname">
570 <tr>
571 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setDestIndex </td>
572 <td>(</td>
573 <td class="paramtype">EDMA3_DRV_Handle </td>
574 <td class="paramname"> <em>hEdma</em>, </td>
575 </tr>
576 <tr>
577 <td class="paramkey"></td>
578 <td></td>
579 <td class="paramtype">unsigned int </td>
580 <td class="paramname"> <em>lCh</em>, </td>
581 </tr>
582 <tr>
583 <td class="paramkey"></td>
584 <td></td>
585 <td class="paramtype">int </td>
586 <td class="paramname"> <em>destBIdx</em>, </td>
587 </tr>
588 <tr>
589 <td class="paramkey"></td>
590 <td></td>
591 <td class="paramtype">int </td>
592 <td class="paramname"> <em>destCIdx</em></td><td> </td>
593 </tr>
594 <tr>
595 <td></td>
596 <td>)</td>
597 <td></td><td></td><td></td>
598 </tr>
599 </table>
600 </div>
601 <div class="memdoc">
603 <p>DMA destination index setup. </p>
604 <p>It is used to program the destination B index and destination C index.</p>
605 <p>DSTBIDX is a 16-bit signed value (2s complement) used for destination address modification between each array in the 2nd dimension. Valid values for DSTBIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-synchronized and AB-synchronized transfers.</p>
606 <p>DSTCIDX is a 16-bit signed value (2s complement) used for destination address modification in the 3rd dimension. Valid values are between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array TR in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when DSTCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame, while the current array in a AB-synchronized transfer is the first array in the frame</p>
607 <dl><dt><b>Parameters:</b></dt><dd>
608 <table border="0" cellspacing="2" cellpadding="0">
609 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
610 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] Logical Channel for which dest indices are to be configured </td></tr>
611 <tr><td valign="top"></td><td valign="top"><em>destBIdx</em> </td><td>[IN] Destination B index </td></tr>
612 <tr><td valign="top"></td><td valign="top"><em>destCIdx</em> </td><td>[IN] Destination C index</td></tr>
613 </table>
614 </dd>
615 </dl>
616 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
617 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
619 </div>
620 </div>
621 <a class="anchor" id="ga8e54f2e2e016bc557ed3374eb46d62ee"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setTransferParams" ref="ga8e54f2e2e016bc557ed3374eb46d62ee" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsigned int cCnt, unsigned int bCntReload, EDMA3_DRV_SyncType syncType)" -->
622 <div class="memitem">
623 <div class="memproto">
624 <table class="memname">
625 <tr>
626 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setTransferParams </td>
627 <td>(</td>
628 <td class="paramtype">EDMA3_DRV_Handle </td>
629 <td class="paramname"> <em>hEdma</em>, </td>
630 </tr>
631 <tr>
632 <td class="paramkey"></td>
633 <td></td>
634 <td class="paramtype">unsigned int </td>
635 <td class="paramname"> <em>lCh</em>, </td>
636 </tr>
637 <tr>
638 <td class="paramkey"></td>
639 <td></td>
640 <td class="paramtype">unsigned int </td>
641 <td class="paramname"> <em>aCnt</em>, </td>
642 </tr>
643 <tr>
644 <td class="paramkey"></td>
645 <td></td>
646 <td class="paramtype">unsigned int </td>
647 <td class="paramname"> <em>bCnt</em>, </td>
648 </tr>
649 <tr>
650 <td class="paramkey"></td>
651 <td></td>
652 <td class="paramtype">unsigned int </td>
653 <td class="paramname"> <em>cCnt</em>, </td>
654 </tr>
655 <tr>
656 <td class="paramkey"></td>
657 <td></td>
658 <td class="paramtype">unsigned int </td>
659 <td class="paramname"> <em>bCntReload</em>, </td>
660 </tr>
661 <tr>
662 <td class="paramkey"></td>
663 <td></td>
664 <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga1cc0705e142298a424a312034bd3b2c2">EDMA3_DRV_SyncType</a> </td>
665 <td class="paramname"> <em>syncType</em></td><td> </td>
666 </tr>
667 <tr>
668 <td></td>
669 <td>)</td>
670 <td></td><td></td><td></td>
671 </tr>
672 </table>
673 </div>
674 <div class="memdoc">
676 <p>DMA transfer parameters setup. </p>
677 <p>It is used to specify the various counts (ACNT, BCNT and CCNT), B count reload and the synchronization type</p>
678 <p>ACNT represents the number of bytes within the 1st dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K - 1 bytes). ACNT must be greater than or equal to 1 for a TR to be submitted to EDMA3 Transfer Controller. An ACNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT.</p>
679 <p>BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT are between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K - 1 arrays). A BCNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT.</p>
680 <p>CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT are between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K - 1 frames). A CCNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT. A CCNT value of 0 is considered either a null or dummy transfer.</p>
681 <p>BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-synchronized transfers. In this case, the EDMA3CC decrements the BCNT value by 1 on each TR submission. When BCNT (conceptually) reaches 0, the EDMA3CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the EDMA3TC decrements BCNT appropriately. For AB-synchronized transfers, BCNTRLD is not used.</p>
682 <dl><dt><b>Parameters:</b></dt><dd>
683 <table border="0" cellspacing="2" cellpadding="0">
684 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
685 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] Logical Channel for which transfer parameters are to be configured </td></tr>
686 <tr><td valign="top"></td><td valign="top"><em>aCnt</em> </td><td>[IN] Count for 1st Dimension. </td></tr>
687 <tr><td valign="top"></td><td valign="top"><em>bCnt</em> </td><td>[IN] Count for 2nd Dimension. </td></tr>
688 <tr><td valign="top"></td><td valign="top"><em>cCnt</em> </td><td>[IN] Count for 3rd Dimension. </td></tr>
689 <tr><td valign="top"></td><td valign="top"><em>bCntReload</em> </td><td>[IN] Reload value for bCnt. </td></tr>
690 <tr><td valign="top"></td><td valign="top"><em>syncType</em> </td><td>[IN] Transfer synchronization dimension 0: A-synchronized. Each event triggers the transfer of a single array of ACNT bytes. 1: AB-synchronized. Each event triggers the transfer of BCNT arrays of ACNT bytes.</td></tr>
691 </table>
692 </dd>
693 </dl>
694 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
695 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
697 </div>
698 </div>
699 <a class="anchor" id="ga5c80afa7645f1e492951c0419c21dbe6"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_enableTransfer" ref="ga5c80afa7645f1e492951c0419c21dbe6" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)" -->
700 <div class="memitem">
701 <div class="memproto">
702 <table class="memname">
703 <tr>
704 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_enableTransfer </td>
705 <td>(</td>
706 <td class="paramtype">EDMA3_DRV_Handle </td>
707 <td class="paramname"> <em>hEdma</em>, </td>
708 </tr>
709 <tr>
710 <td class="paramkey"></td>
711 <td></td>
712 <td class="paramtype">unsigned int </td>
713 <td class="paramname"> <em>lCh</em>, </td>
714 </tr>
715 <tr>
716 <td class="paramkey"></td>
717 <td></td>
718 <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> </td>
719 <td class="paramname"> <em>trigMode</em></td><td> </td>
720 </tr>
721 <tr>
722 <td></td>
723 <td>)</td>
724 <td></td><td></td><td></td>
725 </tr>
726 </table>
727 </div>
728 <div class="memdoc">
730 <p>Start EDMA transfer on the specified channel. </p>
731 <p>There are multiple ways to trigger an EDMA3 transfer. The triggering mode option allows choosing from the available triggering modes: Event, Manual or QDMA.</p>
732 <p>In event triggered, a peripheral or an externally generated event triggers the transfer. This API clears the Secondary Event Register and Event Miss Register and then enables the DMA channel by writing to the EESR.</p>
733 <p>In manual triggered mode, CPU manually triggers a transfer by writing a 1 in the Event Set Register (ESR/ESRH). This API writes to the ESR/ESRH to start the transfer.</p>
734 <p>In QDMA triggered mode, a QDMA transfer is triggered when a CPU (or other EDMA3 programmer) writes to the trigger word of the QDMA channel PaRAM set (auto-triggered) or when the EDMA3CC performs a link update on a PaRAM set that has been mapped to a QDMA channel (link triggered). This API enables the QDMA channel by writing to the QEESR register.</p>
735 <dl><dt><b>Parameters:</b></dt><dd>
736 <table border="0" cellspacing="2" cellpadding="0">
737 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
738 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] Channel on which transfer has to be started </td></tr>
739 <tr><td valign="top"></td><td valign="top"><em>trigMode</em> </td><td>[IN] Mode of triggering start of transfer (Manual, QDMA or Event)</td></tr>
740 </table>
741 </dd>
742 </dl>
743 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
744 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
746 </div>
747 </div>
748 <a class="anchor" id="gadb56f2a6d896c03a77f14c8fdf57a397"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_disableTransfer" ref="gadb56f2a6d896c03a77f14c8fdf57a397" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)" -->
749 <div class="memitem">
750 <div class="memproto">
751 <table class="memname">
752 <tr>
753 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_disableTransfer </td>
754 <td>(</td>
755 <td class="paramtype">EDMA3_DRV_Handle </td>
756 <td class="paramname"> <em>hEdma</em>, </td>
757 </tr>
758 <tr>
759 <td class="paramkey"></td>
760 <td></td>
761 <td class="paramtype">unsigned int </td>
762 <td class="paramname"> <em>lCh</em>, </td>
763 </tr>
764 <tr>
765 <td class="paramkey"></td>
766 <td></td>
767 <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> </td>
768 <td class="paramname"> <em>trigMode</em></td><td> </td>
769 </tr>
770 <tr>
771 <td></td>
772 <td>)</td>
773 <td></td><td></td><td></td>
774 </tr>
775 </table>
776 </div>
777 <div class="memdoc">
779 <p>Disable DMA transfer on the specified channel. </p>
780 <p>There are multiple ways by which an EDMA3 transfer could be triggered. The triggering mode option allows choosing from the available triggering modes: Event, Manual or QDMA.</p>
781 <p>To disable a channel which was previously triggered in manual mode, this API clears the Secondary Event Register and Event Miss Register, if set, for the specific DMA channel.</p>
782 <p>To disable a channel which was previously triggered in QDMA mode, this API clears the QDMA Event Enable Register, for the specific QDMA channel.</p>
783 <p>To disable a channel which was previously triggered in event mode, this API clears the Event Enable Register. It also clears Event Register, Secondary Event Register and Event Miss Register, if set, for the specific DMA channel.</p>
784 <dl><dt><b>Parameters:</b></dt><dd>
785 <table border="0" cellspacing="2" cellpadding="0">
786 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
787 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] Channel on which transfer has to be stopped </td></tr>
788 <tr><td valign="top"></td><td valign="top"><em>trigMode</em> </td><td>[IN] Mode of triggering start of transfer</td></tr>
789 </table>
790 </dd>
791 </dl>
792 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
793 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
795 </div>
796 </div>
797 <a class="anchor" id="ga11070a2e9fb80e16fe96e8ad210e0b59"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_disableLogicalChannel" ref="ga11070a2e9fb80e16fe96e8ad210e0b59" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)" -->
798 <div class="memitem">
799 <div class="memproto">
800 <table class="memname">
801 <tr>
802 <td class="memname">EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel </td>
803 <td>(</td>
804 <td class="paramtype">EDMA3_DRV_Handle </td>
805 <td class="paramname"> <em>hEdma</em>, </td>
806 </tr>
807 <tr>
808 <td class="paramkey"></td>
809 <td></td>
810 <td class="paramtype">unsigned int </td>
811 <td class="paramname"> <em>lCh</em>, </td>
812 </tr>
813 <tr>
814 <td class="paramkey"></td>
815 <td></td>
816 <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> </td>
817 <td class="paramname"> <em>trigMode</em></td><td> </td>
818 </tr>
819 <tr>
820 <td></td>
821 <td>)</td>
822 <td></td><td></td><td></td>
823 </tr>
824 </table>
825 </div>
826 <div class="memdoc">
828 <p>Disable the event driven DMA channel or QDMA channel. </p>
829 <p>This API disables the DMA channel (which was previously triggered in event mode) by clearing the Event Enable Register; it disables the QDMA channel by clearing the QDMA Event Enable Register.</p>
830 <p>This API should NOT be used for DMA channels which are not mapped to any hardware events and are used for memory-to-memory copy based transfers. In case of that, this API returns error.</p>
831 <dl><dt><b>Parameters:</b></dt><dd>
832 <table border="0" cellspacing="2" cellpadding="0">
833 <tr><td valign="top"></td><td valign="top"><em>hEdma</em> </td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
834 <tr><td valign="top"></td><td valign="top"><em>lCh</em> </td><td>[IN] DMA/QDMA Channel which needs to be disabled </td></tr>
835 <tr><td valign="top"></td><td valign="top"><em>trigMode</em> </td><td>[IN] Mode of triggering start of transfer</td></tr>
836 </table>
837 </dd>
838 </dl>
839 <dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
840 <dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
842 </div>
843 </div>
844 </div>
845 <hr size="1"/><address style="text-align: right;"><small>Generated on Tue Dec 1 15:12:09 2009 for EDMA3 Driver by
846 <a href="http://www.doxygen.org/index.html">
847 <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
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