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21 <h1>EDMA3 Driver Defines<br/>
22 <small>
23 [<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l.html">EDMA3 Driver Symbols</a>]</small>
24 </h1><table border="0" cellpadding="0" cellspacing="0">
25 <tr><td colspan="2"><h2>Defines</h2></td></tr>
26 <tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5931139feb03ef40cfeb2a45764913dc"></a><!-- doxytag: member="EDMA3_LLD_DRV_SYMBOL_DEFINE::EDMA3_LLD_DRV_VERSION_ID" ref="ga5931139feb03ef40cfeb2a45764913dc" args="" -->
27 #define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga5931139feb03ef40cfeb2a45764913dc">EDMA3_LLD_DRV_VERSION_ID</a> (0x020B0002)</td></tr>
28 <tr><td class="mdescLeft"> </td><td class="mdescRight">This is the EDMA3 LLD Version. Versions numbers are encoded in the following format: 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD). <br/></td></tr>
29 <tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabe61e2f36bdaa29751022b88df96af7c"></a><!-- doxytag: member="EDMA3_LLD_DRV_SYMBOL_DEFINE::EDMA3_LLD_DRV_VERSION_STR" ref="gabe61e2f36bdaa29751022b88df96af7c" args="" -->
30 #define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gabe61e2f36bdaa29751022b88df96af7c">EDMA3_LLD_DRV_VERSION_STR</a> "EDMA3 LLD Revision: 02.11.00.02"</td></tr>
31 <tr><td class="mdescLeft"> </td><td class="mdescRight">This is the version string which describes the EDMA3 LLD along with the date and build information. <br/></td></tr>
32 <tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1c61cf487147fe68e224d1c123a8b9a0"></a><!-- doxytag: member="EDMA3_LLD_DRV_SYMBOL_DEFINE::EDMA3_DRV_E_BASE" ref="ga1c61cf487147fe68e224d1c123a8b9a0" args="" -->
33 #define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga1c61cf487147fe68e224d1c123a8b9a0">EDMA3_DRV_E_BASE</a> (-128)</td></tr>
34 <tr><td class="mdescLeft"> </td><td class="mdescRight">EDMA3 Driver Error Codes Base define. <br/></td></tr>
35 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga2108add0c34a15aae6431e3770ab42dd">EDMA3_DRV_E_OBJ_NOT_DELETED</a> (EDMA3_DRV_E_BASE)</td></tr>
36 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga571264a50142765bf93790095a628262">EDMA3_DRV_E_OBJ_NOT_CLOSED</a> (EDMA3_DRV_E_BASE-1)</td></tr>
37 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gaaa89161057219a701a298204ac3cd827">EDMA3_DRV_E_OBJ_NOT_OPENED</a> (EDMA3_DRV_E_BASE-2)</td></tr>
38 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga7e5b89ad3e356f24adf2ce48a550d96c">EDMA3_DRV_E_RM_CLOSE_FAIL</a> (EDMA3_DRV_E_BASE-3)</td></tr>
39 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga962a29d0b4af2e62ecf27bab146ad1c5">EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL</a> (EDMA3_DRV_E_BASE-4)</td></tr>
40 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga2d8b8e068288390cb892d66f8634e4e9">EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL</a> (EDMA3_DRV_E_BASE-5)</td></tr>
41 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga6dca1e3db587cd849bec8d25cc7949c3">EDMA3_DRV_E_PARAM_SET_UNAVAIL</a> (EDMA3_DRV_E_BASE-6)</td></tr>
42 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gaa2d5c5345b0d44d9d3f066168f25cc0a">EDMA3_DRV_E_TCC_UNAVAIL</a> (EDMA3_DRV_E_BASE-7)</td></tr>
43 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga3a23afbe20784bfbb37df06110d6df47">EDMA3_DRV_E_TCC_REGISTER_FAIL</a> (EDMA3_DRV_E_BASE-8)</td></tr>
44 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga64926c19c48a9ff8467aa202c466708d">EDMA3_DRV_E_CH_PARAM_BIND_FAIL</a> (EDMA3_DRV_E_BASE-9)</td></tr>
45 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga6b09cbce9ece5d6b43a0921a8e1cb475">EDMA3_DRV_E_ADDRESS_NOT_ALIGNED</a> (EDMA3_DRV_E_BASE-10)</td></tr>
46 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga6a52829f2849eae65a02e52fbefc65f4">EDMA3_DRV_E_INVALID_PARAM</a> (EDMA3_DRV_E_BASE-11)</td></tr>
47 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gad8e918ccf5e108e48762ce6d07abc3bd">EDMA3_DRV_E_INVALID_STATE</a> (EDMA3_DRV_E_BASE-12)</td></tr>
48 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga0592531d6026c0f66b68b8df995ce42a">EDMA3_DRV_E_INST_ALREADY_EXISTS</a> (EDMA3_DRV_E_BASE-13)</td></tr>
49 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga5efab7f94c820d6b7f15d9e974629fde">EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED</a> (EDMA3_DRV_E_BASE-14)</td></tr>
50 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga71414464e3ad2e83a022c11d61b5160d">EDMA3_DRV_E_SEMAPHORE</a> (EDMA3_DRV_E_BASE-15)</td></tr>
51 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga8bb0d23bee588175080a0e5ee8bb037c">EDMA3_DRV_E_INST_NOT_OPENED</a> (EDMA3_DRV_E_BASE-16)</td></tr>
52 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga492616b5ce939ae81e6dcabd4cf5a405">EDMA3_DRV_CH_NO_PARAM_MAP</a> EDMA3_RM_CH_NO_PARAM_MAP</td></tr>
53 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga404a225fe0e3f78170bac637568b89fe">EDMA3_DRV_CH_NO_TCC_MAP</a> EDMA3_RM_CH_NO_TCC_MAP</td></tr>
54 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga3f215945183f3d9fc88453c259fa4b7e">EDMA3_DRV_DMA_CHANNEL_ANY</a> 1002u</td></tr>
55 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga48cab1397b2fff89e09b9b1e21b499bd">EDMA3_DRV_QDMA_CHANNEL_ANY</a> 1003u</td></tr>
56 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga72dbba10987168632d1994a98e3b497b">EDMA3_DRV_TCC_ANY</a> 1004u</td></tr>
57 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gac0d22d1bdbb6ee2bd6aa269429486375">EDMA3_DRV_LINK_CHANNEL</a> 1005u</td></tr>
58 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gaf8efda8c9a32c28976c682d6480c976f">EDMA3_DRV_LINK_CHANNEL_WITH_TCC</a> 1006u</td></tr>
59 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gaed8a176b1257cdc385c940a1a9a84107">EDMA3_DRV_QDMA_CHANNEL_0</a> (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)</td></tr>
60 <tr><td class="mdescLeft"> </td><td class="mdescRight">QDMA Channel defines. <a href="#gaed8a176b1257cdc385c940a1a9a84107"></a><br/></td></tr>
61 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga926b824823dfc5263108ee41eb6110d0">EDMA3_DRV_QDMA_CHANNEL_1</a> (EDMA3_DRV_QDMA_CHANNEL_0+1u)</td></tr>
62 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga41b662ac932dfcddef137609a2bd3ad4">EDMA3_DRV_QDMA_CHANNEL_2</a> (EDMA3_DRV_QDMA_CHANNEL_0+2u)</td></tr>
63 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gae97e0af735749d8ab8985dbd738eb578">EDMA3_DRV_QDMA_CHANNEL_3</a> (EDMA3_DRV_QDMA_CHANNEL_0+3u)</td></tr>
64 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga1c11bab1b40c683b59c4801962cc6046">EDMA3_DRV_QDMA_CHANNEL_4</a> (EDMA3_DRV_QDMA_CHANNEL_0+4u)</td></tr>
65 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga7d6c63e3a6da083430afd94578f4bd84">EDMA3_DRV_QDMA_CHANNEL_5</a> (EDMA3_DRV_QDMA_CHANNEL_0+5u)</td></tr>
66 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gac52b4731852ac8dac2f824fe0bdd153c">EDMA3_DRV_QDMA_CHANNEL_6</a> (EDMA3_DRV_QDMA_CHANNEL_0+6u)</td></tr>
67 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gafc951e66232fc729344802c3abf6218b">EDMA3_DRV_QDMA_CHANNEL_7</a> (EDMA3_DRV_QDMA_CHANNEL_0+7u)</td></tr>
68 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga2ca0c95ae69ae4cc71cc8137287a8fd1">EDMA3_DRV_CHANNEL_CLEAN</a> 0x0000u</td></tr>
69 <tr><td class="mdescLeft"> </td><td class="mdescRight">Channel status defines These defines suggest the current state of the DMA / QDMA channel. They are used while returning the channel status from <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga0241fe8f5788e4b4b217d650a383cf39" title="Get the current status of the DMA/QDMA channel.">EDMA3_DRV_getChannelStatus()</a>. <a href="#ga2ca0c95ae69ae4cc71cc8137287a8fd1"></a><br/></td></tr>
70 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga4b4982df7c3844ea394c9bb743fdf558">EDMA3_DRV_CHANNEL_EVENT_PENDING</a> 0x0001u</td></tr>
71 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga80c785afc213172fda74b14c59946480">EDMA3_DRV_CHANNEL_XFER_COMPLETE</a> 0x0002u</td></tr>
72 <tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gab4cc61240f1e9a3f69c602c0ede9553b">EDMA3_DRV_CHANNEL_ERR</a> 0x0004u</td></tr>
73 </table>
74 <hr/><h2>Define Documentation</h2>
75 <a class="anchor" id="ga2108add0c34a15aae6431e3770ab42dd"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_OBJ_NOT_DELETED" ref="ga2108add0c34a15aae6431e3770ab42dd" args="" -->
76 <div class="memitem">
77 <div class="memproto">
78 <table class="memname">
79 <tr>
80 <td class="memname">#define EDMA3_DRV_E_OBJ_NOT_DELETED (EDMA3_DRV_E_BASE)</td>
81 </tr>
82 </table>
83 </div>
84 <div class="memdoc">
85 <p>EDMA3 Driver Object Not Deleted yet. So it cannot be created. </p>
87 </div>
88 </div>
89 <a class="anchor" id="ga571264a50142765bf93790095a628262"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_OBJ_NOT_CLOSED" ref="ga571264a50142765bf93790095a628262" args="" -->
90 <div class="memitem">
91 <div class="memproto">
92 <table class="memname">
93 <tr>
94 <td class="memname">#define EDMA3_DRV_E_OBJ_NOT_CLOSED (EDMA3_DRV_E_BASE-1)</td>
95 </tr>
96 </table>
97 </div>
98 <div class="memdoc">
99 <p>EDMA3 Driver Object Not Closed yet. So it cannot be deleted. </p>
101 </div>
102 </div>
103 <a class="anchor" id="gaaa89161057219a701a298204ac3cd827"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_OBJ_NOT_OPENED" ref="gaaa89161057219a701a298204ac3cd827" args="" -->
104 <div class="memitem">
105 <div class="memproto">
106 <table class="memname">
107 <tr>
108 <td class="memname">#define EDMA3_DRV_E_OBJ_NOT_OPENED (EDMA3_DRV_E_BASE-2)</td>
109 </tr>
110 </table>
111 </div>
112 <div class="memdoc">
113 <p>EDMA3 Driver Object Not Opened yet So it cannot be closed. </p>
115 </div>
116 </div>
117 <a class="anchor" id="ga7e5b89ad3e356f24adf2ce48a550d96c"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_RM_CLOSE_FAIL" ref="ga7e5b89ad3e356f24adf2ce48a550d96c" args="" -->
118 <div class="memitem">
119 <div class="memproto">
120 <table class="memname">
121 <tr>
122 <td class="memname">#define EDMA3_DRV_E_RM_CLOSE_FAIL (EDMA3_DRV_E_BASE-3)</td>
123 </tr>
124 </table>
125 </div>
126 <div class="memdoc">
127 <p>While closing EDMA3 Driver, Resource Manager Close Failed. </p>
129 </div>
130 </div>
131 <a class="anchor" id="ga962a29d0b4af2e62ecf27bab146ad1c5"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL" ref="ga962a29d0b4af2e62ecf27bab146ad1c5" args="" -->
132 <div class="memitem">
133 <div class="memproto">
134 <table class="memname">
135 <tr>
136 <td class="memname">#define EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-4)</td>
137 </tr>
138 </table>
139 </div>
140 <div class="memdoc">
141 <p>The requested DMA Channel not available </p>
143 </div>
144 </div>
145 <a class="anchor" id="ga2d8b8e068288390cb892d66f8634e4e9"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL" ref="ga2d8b8e068288390cb892d66f8634e4e9" args="" -->
146 <div class="memitem">
147 <div class="memproto">
148 <table class="memname">
149 <tr>
150 <td class="memname">#define EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-5)</td>
151 </tr>
152 </table>
153 </div>
154 <div class="memdoc">
155 <p>The requested QDMA Channel not available </p>
157 </div>
158 </div>
159 <a class="anchor" id="ga6dca1e3db587cd849bec8d25cc7949c3"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_PARAM_SET_UNAVAIL" ref="ga6dca1e3db587cd849bec8d25cc7949c3" args="" -->
160 <div class="memitem">
161 <div class="memproto">
162 <table class="memname">
163 <tr>
164 <td class="memname">#define EDMA3_DRV_E_PARAM_SET_UNAVAIL (EDMA3_DRV_E_BASE-6)</td>
165 </tr>
166 </table>
167 </div>
168 <div class="memdoc">
169 <p>The requested PaRAM Set not available </p>
171 </div>
172 </div>
173 <a class="anchor" id="gaa2d5c5345b0d44d9d3f066168f25cc0a"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_TCC_UNAVAIL" ref="gaa2d5c5345b0d44d9d3f066168f25cc0a" args="" -->
174 <div class="memitem">
175 <div class="memproto">
176 <table class="memname">
177 <tr>
178 <td class="memname">#define EDMA3_DRV_E_TCC_UNAVAIL (EDMA3_DRV_E_BASE-7)</td>
179 </tr>
180 </table>
181 </div>
182 <div class="memdoc">
183 <p>The requested TCC not available </p>
185 </div>
186 </div>
187 <a class="anchor" id="ga3a23afbe20784bfbb37df06110d6df47"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_TCC_REGISTER_FAIL" ref="ga3a23afbe20784bfbb37df06110d6df47" args="" -->
188 <div class="memitem">
189 <div class="memproto">
190 <table class="memname">
191 <tr>
192 <td class="memname">#define EDMA3_DRV_E_TCC_REGISTER_FAIL (EDMA3_DRV_E_BASE-8)</td>
193 </tr>
194 </table>
195 </div>
196 <div class="memdoc">
197 <p>The registration of TCC failed </p>
199 </div>
200 </div>
201 <a class="anchor" id="ga64926c19c48a9ff8467aa202c466708d"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_CH_PARAM_BIND_FAIL" ref="ga64926c19c48a9ff8467aa202c466708d" args="" -->
202 <div class="memitem">
203 <div class="memproto">
204 <table class="memname">
205 <tr>
206 <td class="memname">#define EDMA3_DRV_E_CH_PARAM_BIND_FAIL (EDMA3_DRV_E_BASE-9)</td>
207 </tr>
208 </table>
209 </div>
210 <div class="memdoc">
211 <p>The binding of Channel and PaRAM Set failed </p>
213 </div>
214 </div>
215 <a class="anchor" id="ga6b09cbce9ece5d6b43a0921a8e1cb475"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_ADDRESS_NOT_ALIGNED" ref="ga6b09cbce9ece5d6b43a0921a8e1cb475" args="" -->
216 <div class="memitem">
217 <div class="memproto">
218 <table class="memname">
219 <tr>
220 <td class="memname">#define EDMA3_DRV_E_ADDRESS_NOT_ALIGNED (EDMA3_DRV_E_BASE-10)</td>
221 </tr>
222 </table>
223 </div>
224 <div class="memdoc">
225 <p>The address of the memory location passed as argument is not properly aligned. It should be 32 bytes aligned. </p>
227 </div>
228 </div>
229 <a class="anchor" id="ga6a52829f2849eae65a02e52fbefc65f4"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_INVALID_PARAM" ref="ga6a52829f2849eae65a02e52fbefc65f4" args="" -->
230 <div class="memitem">
231 <div class="memproto">
232 <table class="memname">
233 <tr>
234 <td class="memname">#define EDMA3_DRV_E_INVALID_PARAM (EDMA3_DRV_E_BASE-11)</td>
235 </tr>
236 </table>
237 </div>
238 <div class="memdoc">
239 <p>Invalid Parameter passed to API </p>
241 </div>
242 </div>
243 <a class="anchor" id="gad8e918ccf5e108e48762ce6d07abc3bd"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_INVALID_STATE" ref="gad8e918ccf5e108e48762ce6d07abc3bd" args="" -->
244 <div class="memitem">
245 <div class="memproto">
246 <table class="memname">
247 <tr>
248 <td class="memname">#define EDMA3_DRV_E_INVALID_STATE (EDMA3_DRV_E_BASE-12)</td>
249 </tr>
250 </table>
251 </div>
252 <div class="memdoc">
253 <p>Invalid State of EDMA3 HW Obj </p>
255 </div>
256 </div>
257 <a class="anchor" id="ga0592531d6026c0f66b68b8df995ce42a"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_INST_ALREADY_EXISTS" ref="ga0592531d6026c0f66b68b8df995ce42a" args="" -->
258 <div class="memitem">
259 <div class="memproto">
260 <table class="memname">
261 <tr>
262 <td class="memname">#define EDMA3_DRV_E_INST_ALREADY_EXISTS (EDMA3_DRV_E_BASE-13)</td>
263 </tr>
264 </table>
265 </div>
266 <div class="memdoc">
267 <p>EDMA3 Driver instance already exists for the specified region </p>
269 </div>
270 </div>
271 <a class="anchor" id="ga5efab7f94c820d6b7f15d9e974629fde"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED" ref="ga5efab7f94c820d6b7f15d9e974629fde" args="" -->
272 <div class="memitem">
273 <div class="memproto">
274 <table class="memname">
275 <tr>
276 <td class="memname">#define EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED (EDMA3_DRV_E_BASE-14)</td>
277 </tr>
278 </table>
279 </div>
280 <div class="memdoc">
281 <p>FIFO width not supported by the requested TC </p>
283 </div>
284 </div>
285 <a class="anchor" id="ga71414464e3ad2e83a022c11d61b5160d"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_SEMAPHORE" ref="ga71414464e3ad2e83a022c11d61b5160d" args="" -->
286 <div class="memitem">
287 <div class="memproto">
288 <table class="memname">
289 <tr>
290 <td class="memname">#define EDMA3_DRV_E_SEMAPHORE (EDMA3_DRV_E_BASE-15)</td>
291 </tr>
292 </table>
293 </div>
294 <div class="memdoc">
295 <p>Semaphore related error </p>
297 </div>
298 </div>
299 <a class="anchor" id="ga8bb0d23bee588175080a0e5ee8bb037c"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_INST_NOT_OPENED" ref="ga8bb0d23bee588175080a0e5ee8bb037c" args="" -->
300 <div class="memitem">
301 <div class="memproto">
302 <table class="memname">
303 <tr>
304 <td class="memname">#define EDMA3_DRV_E_INST_NOT_OPENED (EDMA3_DRV_E_BASE-16)</td>
305 </tr>
306 </table>
307 </div>
308 <div class="memdoc">
309 <p>EDMA3 Driver Instance does not exist, it is not opened yet </p>
311 </div>
312 </div>
313 <a class="anchor" id="ga492616b5ce939ae81e6dcabd4cf5a405"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_CH_NO_PARAM_MAP" ref="ga492616b5ce939ae81e6dcabd4cf5a405" args="" -->
314 <div class="memitem">
315 <div class="memproto">
316 <table class="memname">
317 <tr>
318 <td class="memname">#define EDMA3_DRV_CH_NO_PARAM_MAP EDMA3_RM_CH_NO_PARAM_MAP</td>
319 </tr>
320 </table>
321 </div>
322 <div class="memdoc">
323 <p>This define is used to specify that a DMA channel is NOT tied to any PaRAM Set and hence any available PaRAM Set could be used for that DMA channel. It could be used in dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH], in global configuration structure EDMA3_RM_GblConfigParams.</p>
324 <p>This value should mandatorily be used to mark DMA channels with no initial mapping to specific PaRAM Sets. </p>
326 </div>
327 </div>
328 <a class="anchor" id="ga404a225fe0e3f78170bac637568b89fe"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_CH_NO_TCC_MAP" ref="ga404a225fe0e3f78170bac637568b89fe" args="" -->
329 <div class="memitem">
330 <div class="memproto">
331 <table class="memname">
332 <tr>
333 <td class="memname">#define EDMA3_DRV_CH_NO_TCC_MAP EDMA3_RM_CH_NO_TCC_MAP</td>
334 </tr>
335 </table>
336 </div>
337 <div class="memdoc">
338 <p>This define is used to specify that the DMA/QDMA channel is not tied to any TCC and hence any available TCC could be used for that DMA/QDMA channel. It could be used in dmaChannelTccMap [EDMA3_MAX_DMA_CH], in global configuration structure EDMA3_RM_GblConfigParams.</p>
339 <p>This value should mandatorily be used to mark DMA channels with no initial mapping to specific TCCs. </p>
341 </div>
342 </div>
343 <a class="anchor" id="ga3f215945183f3d9fc88453c259fa4b7e"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_DMA_CHANNEL_ANY" ref="ga3f215945183f3d9fc88453c259fa4b7e" args="" -->
344 <div class="memitem">
345 <div class="memproto">
346 <table class="memname">
347 <tr>
348 <td class="memname">#define EDMA3_DRV_DMA_CHANNEL_ANY 1002u</td>
349 </tr>
350 </table>
351 </div>
352 <div class="memdoc">
353 <p>Used to specify any available DMA Channel while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaf972552f53ce9efe4db7bfe6db275c06" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>. DMA channel from the pool of (owned && non_reserved && available_right_now) DMA channels will be chosen and returned. </p>
355 </div>
356 </div>
357 <a class="anchor" id="ga48cab1397b2fff89e09b9b1e21b499bd"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_ANY" ref="ga48cab1397b2fff89e09b9b1e21b499bd" args="" -->
358 <div class="memitem">
359 <div class="memproto">
360 <table class="memname">
361 <tr>
362 <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_ANY 1003u</td>
363 </tr>
364 </table>
365 </div>
366 <div class="memdoc">
367 <p>Used to specify any available QDMA Channel while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaf972552f53ce9efe4db7bfe6db275c06" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>. QDMA channel from the pool of (owned && non_reserved && available_right_now) QDMA channels will be chosen and returned. </p>
369 </div>
370 </div>
371 <a class="anchor" id="ga72dbba10987168632d1994a98e3b497b"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_TCC_ANY" ref="ga72dbba10987168632d1994a98e3b497b" args="" -->
372 <div class="memitem">
373 <div class="memproto">
374 <table class="memname">
375 <tr>
376 <td class="memname">#define EDMA3_DRV_TCC_ANY 1004u</td>
377 </tr>
378 </table>
379 </div>
380 <div class="memdoc">
381 <p>Used to specify any available TCC while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaf972552f53ce9efe4db7bfe6db275c06" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>, for both DMA and QDMA channels. TCC from the pool of (owned && non_reserved && available_right_now) TCCs will be chosen and returned. </p>
383 </div>
384 </div>
385 <a class="anchor" id="gac0d22d1bdbb6ee2bd6aa269429486375"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_LINK_CHANNEL" ref="gac0d22d1bdbb6ee2bd6aa269429486375" args="" -->
386 <div class="memitem">
387 <div class="memproto">
388 <table class="memname">
389 <tr>
390 <td class="memname">#define EDMA3_DRV_LINK_CHANNEL 1005u</td>
391 </tr>
392 </table>
393 </div>
394 <div class="memdoc">
395 <p>Used to specify any available PaRAM Set while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaf972552f53ce9efe4db7bfe6db275c06" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>, for Link channels. PaRAM Set from the pool of (owned && non_reserved && available_right_now) PaRAM Sets will be chosen and returned. </p>
397 </div>
398 </div>
399 <a class="anchor" id="gaf8efda8c9a32c28976c682d6480c976f"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_LINK_CHANNEL_WITH_TCC" ref="gaf8efda8c9a32c28976c682d6480c976f" args="" -->
400 <div class="memitem">
401 <div class="memproto">
402 <table class="memname">
403 <tr>
404 <td class="memname">#define EDMA3_DRV_LINK_CHANNEL_WITH_TCC 1006u</td>
405 </tr>
406 </table>
407 </div>
408 <div class="memdoc">
409 <p>Used to specify any available PaRAM Set while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaf972552f53ce9efe4db7bfe6db275c06" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>, for Link channels. TCC code should also be specified and it will be used to populate the LINK field of the PaRAM Set. Without TCC code, the call will fail. PaRAM Set from the pool of (owned && non_reserved && available_right_now) PaRAM Sets will be chosen and returned. </p>
411 </div>
412 </div>
413 <a class="anchor" id="gaed8a176b1257cdc385c940a1a9a84107"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_0" ref="gaed8a176b1257cdc385c940a1a9a84107" args="" -->
414 <div class="memitem">
415 <div class="memproto">
416 <table class="memname">
417 <tr>
418 <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_0 (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)</td>
419 </tr>
420 </table>
421 </div>
422 <div class="memdoc">
424 <p>QDMA Channel defines. </p>
425 <p>They should be used while requesting a specific QDMA channel in API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaf972552f53ce9efe4db7bfe6db275c06" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a> as the argument (*pLch). Please note that these defines should ONLY be used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaf972552f53ce9efe4db7bfe6db275c06" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a> and not in any other API to perform further operations. They are only provided to allow user allocate specific QDMA channels. QDMA Channel 0 </p>
427 </div>
428 </div>
429 <a class="anchor" id="ga926b824823dfc5263108ee41eb6110d0"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_1" ref="ga926b824823dfc5263108ee41eb6110d0" args="" -->
430 <div class="memitem">
431 <div class="memproto">
432 <table class="memname">
433 <tr>
434 <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_1 (EDMA3_DRV_QDMA_CHANNEL_0+1u)</td>
435 </tr>
436 </table>
437 </div>
438 <div class="memdoc">
439 <p>QDMA Channel 1 </p>
441 </div>
442 </div>
443 <a class="anchor" id="ga41b662ac932dfcddef137609a2bd3ad4"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_2" ref="ga41b662ac932dfcddef137609a2bd3ad4" args="" -->
444 <div class="memitem">
445 <div class="memproto">
446 <table class="memname">
447 <tr>
448 <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_2 (EDMA3_DRV_QDMA_CHANNEL_0+2u)</td>
449 </tr>
450 </table>
451 </div>
452 <div class="memdoc">
453 <p>QDMA Channel 2 </p>
455 </div>
456 </div>
457 <a class="anchor" id="gae97e0af735749d8ab8985dbd738eb578"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_3" ref="gae97e0af735749d8ab8985dbd738eb578" args="" -->
458 <div class="memitem">
459 <div class="memproto">
460 <table class="memname">
461 <tr>
462 <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_3 (EDMA3_DRV_QDMA_CHANNEL_0+3u)</td>
463 </tr>
464 </table>
465 </div>
466 <div class="memdoc">
467 <p>QDMA Channel 3 </p>
469 </div>
470 </div>
471 <a class="anchor" id="ga1c11bab1b40c683b59c4801962cc6046"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_4" ref="ga1c11bab1b40c683b59c4801962cc6046" args="" -->
472 <div class="memitem">
473 <div class="memproto">
474 <table class="memname">
475 <tr>
476 <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_4 (EDMA3_DRV_QDMA_CHANNEL_0+4u)</td>
477 </tr>
478 </table>
479 </div>
480 <div class="memdoc">
481 <p>QDMA Channel 4 </p>
483 </div>
484 </div>
485 <a class="anchor" id="ga7d6c63e3a6da083430afd94578f4bd84"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_5" ref="ga7d6c63e3a6da083430afd94578f4bd84" args="" -->
486 <div class="memitem">
487 <div class="memproto">
488 <table class="memname">
489 <tr>
490 <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_5 (EDMA3_DRV_QDMA_CHANNEL_0+5u)</td>
491 </tr>
492 </table>
493 </div>
494 <div class="memdoc">
495 <p>QDMA Channel 5 </p>
497 </div>
498 </div>
499 <a class="anchor" id="gac52b4731852ac8dac2f824fe0bdd153c"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_6" ref="gac52b4731852ac8dac2f824fe0bdd153c" args="" -->
500 <div class="memitem">
501 <div class="memproto">
502 <table class="memname">
503 <tr>
504 <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_6 (EDMA3_DRV_QDMA_CHANNEL_0+6u)</td>
505 </tr>
506 </table>
507 </div>
508 <div class="memdoc">
509 <p>QDMA Channel 6 </p>
511 </div>
512 </div>
513 <a class="anchor" id="gafc951e66232fc729344802c3abf6218b"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_7" ref="gafc951e66232fc729344802c3abf6218b" args="" -->
514 <div class="memitem">
515 <div class="memproto">
516 <table class="memname">
517 <tr>
518 <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_7 (EDMA3_DRV_QDMA_CHANNEL_0+7u)</td>
519 </tr>
520 </table>
521 </div>
522 <div class="memdoc">
523 <p>QDMA Channel 7 </p>
525 </div>
526 </div>
527 <a class="anchor" id="ga2ca0c95ae69ae4cc71cc8137287a8fd1"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_CHANNEL_CLEAN" ref="ga2ca0c95ae69ae4cc71cc8137287a8fd1" args="" -->
528 <div class="memitem">
529 <div class="memproto">
530 <table class="memname">
531 <tr>
532 <td class="memname">#define EDMA3_DRV_CHANNEL_CLEAN 0x0000u</td>
533 </tr>
534 </table>
535 </div>
536 <div class="memdoc">
538 <p>Channel status defines These defines suggest the current state of the DMA / QDMA channel. They are used while returning the channel status from <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga0241fe8f5788e4b4b217d650a383cf39" title="Get the current status of the DMA/QDMA channel.">EDMA3_DRV_getChannelStatus()</a>. </p>
539 <p>Channel is clean; no pending event, completion interrupt and event miss interrupt </p>
541 </div>
542 </div>
543 <a class="anchor" id="ga4b4982df7c3844ea394c9bb743fdf558"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_CHANNEL_EVENT_PENDING" ref="ga4b4982df7c3844ea394c9bb743fdf558" args="" -->
544 <div class="memitem">
545 <div class="memproto">
546 <table class="memname">
547 <tr>
548 <td class="memname">#define EDMA3_DRV_CHANNEL_EVENT_PENDING 0x0001u</td>
549 </tr>
550 </table>
551 </div>
552 <div class="memdoc">
553 <p>Pending event is detected on the DMA channel </p>
555 </div>
556 </div>
557 <a class="anchor" id="ga80c785afc213172fda74b14c59946480"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_CHANNEL_XFER_COMPLETE" ref="ga80c785afc213172fda74b14c59946480" args="" -->
558 <div class="memitem">
559 <div class="memproto">
560 <table class="memname">
561 <tr>
562 <td class="memname">#define EDMA3_DRV_CHANNEL_XFER_COMPLETE 0x0002u</td>
563 </tr>
564 </table>
565 </div>
566 <div class="memdoc">
567 <p>Transfer completion interrupt is detected on the DMA/QDMA channel </p>
569 </div>
570 </div>
571 <a class="anchor" id="gab4cc61240f1e9a3f69c602c0ede9553b"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_CHANNEL_ERR" ref="gab4cc61240f1e9a3f69c602c0ede9553b" args="" -->
572 <div class="memitem">
573 <div class="memproto">
574 <table class="memname">
575 <tr>
576 <td class="memname">#define EDMA3_DRV_CHANNEL_ERR 0x0004u</td>
577 </tr>
578 </table>
579 </div>
580 <div class="memdoc">
581 <p>Event miss error interrupt is detected on the DMA/QDMA channel </p>
583 </div>
584 </div>
585 </div>
586 <hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:00 2011 for EDMA3 Driver by
587 <a href="http://www.doxygen.org/index.html">
588 <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
589 </body>
590 </html>