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21 <h1>EDMA3 Driver Enums<br/>
22 <small>
23 [<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l.html">EDMA3 Driver Symbols</a>]</small>
24 </h1><table border="0" cellpadding="0" cellspacing="0">
25 <tr><td colspan="2"><h2>Enumerations</h2></td></tr>
26 <tr><td class="memItemLeft" align="right" valign="top">enum </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8e20d4ba59240144067e70bb8beb7879">EDMA3_DRV_HW_CHANNEL_EVENT</a> { <br/>
27 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a37748ea68c4fbf181415d15e4548a9d5">EDMA3_DRV_HW_CHANNEL_EVENT_0</a> = 0,
28 <br/>
29 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a34192b4602da79a32906e449e86ddea9">EDMA3_DRV_HW_CHANNEL_EVENT_1</a>,
30 <br/>
31 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879ac36395e3506bd6fc8daf06ea945c4f1b">EDMA3_DRV_HW_CHANNEL_EVENT_2</a>,
32 <br/>
33 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879ad26ddd5a62ff5a8c079eff713ed24a6c">EDMA3_DRV_HW_CHANNEL_EVENT_3</a>,
34 <br/>
35 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879ab8d954a5708596eb302bbe617e16883e">EDMA3_DRV_HW_CHANNEL_EVENT_4</a>,
36 <br/>
37 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a2ca5cca9c6e9c39d36c71feb28729a4c">EDMA3_DRV_HW_CHANNEL_EVENT_5</a>,
38 <br/>
39 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879afed5d83771dff787abfa671c489c5bc1">EDMA3_DRV_HW_CHANNEL_EVENT_6</a>,
40 <br/>
41 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879aad3f865ffab348c3bcfd75339801fc33">EDMA3_DRV_HW_CHANNEL_EVENT_7</a>,
42 <br/>
43 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a3725a5901d7680739b36b5ffd3e5128b">EDMA3_DRV_HW_CHANNEL_EVENT_8</a>,
44 <br/>
45 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a842a774c34014c24c7ad9e4a8aa2aa72">EDMA3_DRV_HW_CHANNEL_EVENT_9</a>,
46 <br/>
47 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a2d99e6b419712a65dcd7a920b36a866e">EDMA3_DRV_HW_CHANNEL_EVENT_10</a>,
48 <br/>
49 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879ab956cf256d1818a5909f0399d85612f4">EDMA3_DRV_HW_CHANNEL_EVENT_11</a>,
50 <br/>
51 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a05b4c74778694509a7759e4cd124bc23">EDMA3_DRV_HW_CHANNEL_EVENT_12</a>,
52 <br/>
53 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a7d86b7fe7d7c3f0077a2c8a445f16943">EDMA3_DRV_HW_CHANNEL_EVENT_13</a>,
54 <br/>
55 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a44782731229ca9470e1f46ed93bf6954">EDMA3_DRV_HW_CHANNEL_EVENT_14</a>,
56 <br/>
57 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a6a773568b775bff069188481b2b1dc75">EDMA3_DRV_HW_CHANNEL_EVENT_15</a>,
58 <br/>
59 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879aa7c914b81cad4f66cd91ec5e89240a9d">EDMA3_DRV_HW_CHANNEL_EVENT_16</a>,
60 <br/>
61 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a6dedf754dfe2a6eb21a9c4b2a8342099">EDMA3_DRV_HW_CHANNEL_EVENT_17</a>,
62 <br/>
63 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a7c0d3ec834f566bf8b3ce427038baf60">EDMA3_DRV_HW_CHANNEL_EVENT_18</a>,
64 <br/>
65 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a71d5ec033e254c3a355a8c876304296f">EDMA3_DRV_HW_CHANNEL_EVENT_19</a>,
66 <br/>
67 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879ac9fd5d6ea19828bba5af7052223d532d">EDMA3_DRV_HW_CHANNEL_EVENT_20</a>,
68 <br/>
69 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a4945278d24520fa8fe0dbf543582bdb4">EDMA3_DRV_HW_CHANNEL_EVENT_21</a>,
70 <br/>
71 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a5222e130853fdbb6ce243bd8f8e516a6">EDMA3_DRV_HW_CHANNEL_EVENT_22</a>,
72 <br/>
73 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a3ace2470d524a24e37a8e87fe5f4546e">EDMA3_DRV_HW_CHANNEL_EVENT_23</a>,
74 <br/>
75 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879ab8dbc9b117c7c16203ffe9268ac8943e">EDMA3_DRV_HW_CHANNEL_EVENT_24</a>,
76 <br/>
77 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a96ff3814c0936e06525dae25737b8e8c">EDMA3_DRV_HW_CHANNEL_EVENT_25</a>,
78 <br/>
79 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a524cc629d15967c9e21547a1053af654">EDMA3_DRV_HW_CHANNEL_EVENT_26</a>,
80 <br/>
81 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a9138ddea8bb08222af544e7a1d884ebf">EDMA3_DRV_HW_CHANNEL_EVENT_27</a>,
82 <br/>
83 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879ae916849b035d8101e163ffb18a45f3b1">EDMA3_DRV_HW_CHANNEL_EVENT_28</a>,
84 <br/>
85 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a97c9fd86fb3de0ff7963cdeb6ae0adb8">EDMA3_DRV_HW_CHANNEL_EVENT_29</a>,
86 <br/>
87 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879ab1bcf6eaa841f660d14fee3e96fd86ed">EDMA3_DRV_HW_CHANNEL_EVENT_30</a>,
88 <br/>
89 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a23b6ccf182d6c2cf4572d84190021c51">EDMA3_DRV_HW_CHANNEL_EVENT_31</a>,
90 <br/>
91 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879adbc4408571a19ec5ec731c2675aeeece">EDMA3_DRV_HW_CHANNEL_EVENT_32</a>,
92 <br/>
93 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a4a54cb99692eb23ecb672ac221a70615">EDMA3_DRV_HW_CHANNEL_EVENT_33</a>,
94 <br/>
95 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a0d03823cb59ab55fd030d1d9603d19af">EDMA3_DRV_HW_CHANNEL_EVENT_34</a>,
96 <br/>
97 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879afda0f229cb06304229edf3900a522b88">EDMA3_DRV_HW_CHANNEL_EVENT_35</a>,
98 <br/>
99 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879aec1b8659d6056dc1a469ff839cb45e8d">EDMA3_DRV_HW_CHANNEL_EVENT_36</a>,
100 <br/>
101 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879aaefcfee3c1dd42b400f4c5d746842068">EDMA3_DRV_HW_CHANNEL_EVENT_37</a>,
102 <br/>
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104 <br/>
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106 <br/>
107 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a01ffb1c47ac459f570347f418da7d8b9">EDMA3_DRV_HW_CHANNEL_EVENT_40</a>,
108 <br/>
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110 <br/>
111 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879aac157667fee035df11975decb8a0fdae">EDMA3_DRV_HW_CHANNEL_EVENT_42</a>,
112 <br/>
113 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879aa048e7a75547802ed7929cef4466fec0">EDMA3_DRV_HW_CHANNEL_EVENT_43</a>,
114 <br/>
115 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a70b36fb01559fd3374607d8a574ded25">EDMA3_DRV_HW_CHANNEL_EVENT_44</a>,
116 <br/>
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118 <br/>
119 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879aa229f0efb4bd21aa34211237b240c524">EDMA3_DRV_HW_CHANNEL_EVENT_46</a>,
120 <br/>
121 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a05fc551f36ded0686a571b6631879a90">EDMA3_DRV_HW_CHANNEL_EVENT_47</a>,
122 <br/>
123 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a295b1b324c9d77d4d971073c52e2e40e">EDMA3_DRV_HW_CHANNEL_EVENT_48</a>,
124 <br/>
125 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a9073a64c7ba4caf6ef0359d82adf24d8">EDMA3_DRV_HW_CHANNEL_EVENT_49</a>,
126 <br/>
127 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a6af730dab1edf67d74b5104fda134950">EDMA3_DRV_HW_CHANNEL_EVENT_50</a>,
128 <br/>
129 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879abd179dd58d8512110a5452b5bdcdbcc1">EDMA3_DRV_HW_CHANNEL_EVENT_51</a>,
130 <br/>
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132 <br/>
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134 <br/>
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136 <br/>
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138 <br/>
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142 <br/>
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144 <br/>
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146 <br/>
147 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879ae6411d5de6e88e2dc7c41e8e5f7859e3">EDMA3_DRV_HW_CHANNEL_EVENT_60</a>,
148 <br/>
149 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879a786abf418a32147a6df87dac6943576c">EDMA3_DRV_HW_CHANNEL_EVENT_61</a>,
150 <br/>
151 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879acf2aaad445adea762c1f1541038b2d9d">EDMA3_DRV_HW_CHANNEL_EVENT_62</a>,
152 <br/>
153 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8e20d4ba59240144067e70bb8beb7879af3f3eacae6b1b26111f7988ca3b3e9e8">EDMA3_DRV_HW_CHANNEL_EVENT_63</a>
154 <br/>
155 }</td></tr>
156 <tr><td class="mdescLeft"> </td><td class="mdescRight"><p>DMA Channels assigned to different Hardware Events. </p>
157 <a href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8e20d4ba59240144067e70bb8beb7879">More...</a><br/></td></tr>
158 <tr><td class="memItemLeft" align="right" valign="top">enum </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gaa0c576e8e46ac8db85c05bf73c01a5f9">EDMA3_DRV_OptField</a> { <br/>
159 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ggaa0c576e8e46ac8db85c05bf73c01a5f9a693924fb6d1e68b84bc3189c7bdc4a43">EDMA3_DRV_OPT_FIELD_SAM</a> = 0,
160 <br/>
161 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ggaa0c576e8e46ac8db85c05bf73c01a5f9a0c59c9664e56dee41effaa7f73bac59e">EDMA3_DRV_OPT_FIELD_DAM</a> = 1,
162 <br/>
163 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ggaa0c576e8e46ac8db85c05bf73c01a5f9a4f41648673db6dbe534b91d742647c14">EDMA3_DRV_OPT_FIELD_SYNCDIM</a> = 2,
164 <br/>
165 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ggaa0c576e8e46ac8db85c05bf73c01a5f9a577a829a8eda4500296701051fa3b62e">EDMA3_DRV_OPT_FIELD_STATIC</a> = 3,
166 <br/>
167 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ggaa0c576e8e46ac8db85c05bf73c01a5f9a8b6903281c09308c0a2caf154fa818c8">EDMA3_DRV_OPT_FIELD_FWID</a> = 4,
168 <br/>
169 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ggaa0c576e8e46ac8db85c05bf73c01a5f9ae4519d3ceac24626c65179ab59fb4920">EDMA3_DRV_OPT_FIELD_TCCMODE</a> = 5,
170 <br/>
171 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ggaa0c576e8e46ac8db85c05bf73c01a5f9af8cd20cde06093138d915f2154daf7f4">EDMA3_DRV_OPT_FIELD_TCC</a> = 6,
172 <br/>
173 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ggaa0c576e8e46ac8db85c05bf73c01a5f9a422f20ac0c5217d2bad4ffe20627bae5">EDMA3_DRV_OPT_FIELD_TCINTEN</a> = 7,
174 <br/>
175 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ggaa0c576e8e46ac8db85c05bf73c01a5f9a6feb2084abf4287d809d27a725e29130">EDMA3_DRV_OPT_FIELD_ITCINTEN</a> = 8,
176 <br/>
177 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ggaa0c576e8e46ac8db85c05bf73c01a5f9ac5ab9f8dea50cb16fbdc30a707fce88f">EDMA3_DRV_OPT_FIELD_TCCHEN</a> = 9,
178 <br/>
179 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ggaa0c576e8e46ac8db85c05bf73c01a5f9a65bb7252badcb593139f4f3747ec96ce">EDMA3_DRV_OPT_FIELD_ITCCHEN</a> = 10
180 <br/>
181 }</td></tr>
182 <tr><td class="mdescLeft"> </td><td class="mdescRight"><p>OPT Field Offset. </p>
183 <a href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gaa0c576e8e46ac8db85c05bf73c01a5f9">More...</a><br/></td></tr>
184 <tr><td class="memItemLeft" align="right" valign="top">enum </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga5896f43e878f4e9c47b449fccdec3af9">EDMA3_DRV_AddrMode</a> { <br/>
185 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga5896f43e878f4e9c47b449fccdec3af9ad51ef7530b1165c92ee355d69339ed38">EDMA3_DRV_ADDR_MODE_INCR</a> = 0,
186 <br/>
187 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga5896f43e878f4e9c47b449fccdec3af9a0efc564b242e308363be650fc96ffc67">EDMA3_DRV_ADDR_MODE_FIFO</a> = 1
188 <br/>
189 }</td></tr>
190 <tr><td class="mdescLeft"> </td><td class="mdescRight"><p>EDMA Addressing modes. </p>
191 <a href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga5896f43e878f4e9c47b449fccdec3af9">More...</a><br/></td></tr>
192 <tr><td class="memItemLeft" align="right" valign="top">enum </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga1cc0705e142298a424a312034bd3b2c2">EDMA3_DRV_SyncType</a> { <br/>
193 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga1cc0705e142298a424a312034bd3b2c2a9466936ba82ec52a8177b725de56db3a">EDMA3_DRV_SYNC_A</a> = 0,
194 <br/>
195 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga1cc0705e142298a424a312034bd3b2c2a2f29eabc70ef33ba7f9a93d0d0c1215b">EDMA3_DRV_SYNC_AB</a> = 1
196 <br/>
197 }</td></tr>
198 <tr><td class="mdescLeft"> </td><td class="mdescRight"><p>EDMA Transfer Synchronization type. </p>
199 <a href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga1cc0705e142298a424a312034bd3b2c2">More...</a><br/></td></tr>
200 <tr><td class="memItemLeft" align="right" valign="top">enum </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga99452326904fbebfaaca597d7be30c80">EDMA3_DRV_StaticMode</a> { <br/>
201 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga99452326904fbebfaaca597d7be30c80a428dccaa64904312a71645116a1ce544">EDMA3_DRV_STATIC_DIS</a> = 0,
202 <br/>
203 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga99452326904fbebfaaca597d7be30c80af9845bfc4f20e338a4c463c6aead3a1f">EDMA3_DRV_STATIC_EN</a> = 1
204 <br/>
205 }</td></tr>
206 <tr><td class="mdescLeft"> </td><td class="mdescRight"><p>True/False: PaRAM set is Static or not. A Static PaRAM set is updated or linked after TR is submitted. </p>
207 <a href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga99452326904fbebfaaca597d7be30c80">More...</a><br/></td></tr>
208 <tr><td class="memItemLeft" align="right" valign="top">enum </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8c37673293432ed46f9e26f04f5681dc">EDMA3_DRV_FifoWidth</a> { <br/>
209 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8c37673293432ed46f9e26f04f5681dcad157735d8521fee719f2ca986777da0b">EDMA3_DRV_W8BIT</a> = 0,
210 <br/>
211 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8c37673293432ed46f9e26f04f5681dca4c7d71dbae74a8fcbfa175ec12372bf8">EDMA3_DRV_W16BIT</a> = 1,
212 <br/>
213 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8c37673293432ed46f9e26f04f5681dcad1eaf7a2e98ccf591f6bba89160857d8">EDMA3_DRV_W32BIT</a> = 2,
214 <br/>
215 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8c37673293432ed46f9e26f04f5681dcaa5b92871ecada67f067ad5d76d2ae887">EDMA3_DRV_W64BIT</a> = 3,
216 <br/>
217 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8c37673293432ed46f9e26f04f5681dca6182f4ed18ba89d22c6be0f8ea91f392">EDMA3_DRV_W128BIT</a> = 4,
218 <br/>
219 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8c37673293432ed46f9e26f04f5681dca28cdc27a7907130b42d56be0ef4368dc">EDMA3_DRV_W256BIT</a> = 5
220 <br/>
221 }</td></tr>
222 <tr><td class="mdescLeft"> </td><td class="mdescRight"><p>EDMA3 FIFO width. </p>
223 <a href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8c37673293432ed46f9e26f04f5681dc">More...</a><br/></td></tr>
224 <tr><td class="memItemLeft" align="right" valign="top">enum </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga17890a22b88466fbd0a14258aa1d0e9c">EDMA3_DRV_TccMode</a> { <br/>
225 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga17890a22b88466fbd0a14258aa1d0e9ca686d71e31f3fe47f64e41a47c2212882">EDMA3_DRV_TCCMODE_NORMAL</a> = 0,
226 <br/>
227 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga17890a22b88466fbd0a14258aa1d0e9ca8d6a8086b0f466c688ad3ae3adef070b">EDMA3_DRV_TCCMODE_EARLY</a> = 1
228 <br/>
229 }</td></tr>
230 <tr><td class="mdescLeft"> </td><td class="mdescRight"><p>Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation. </p>
231 <a href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga17890a22b88466fbd0a14258aa1d0e9c">More...</a><br/></td></tr>
232 <tr><td class="memItemLeft" align="right" valign="top">enum </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga17af0bbf00a59ea1ac3352098fe44a89">EDMA3_DRV_TcintEn</a> { <br/>
233 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga17af0bbf00a59ea1ac3352098fe44a89a73ea2b6eec1b241028ca166be468c84b">EDMA3_DRV_TCINTEN_DIS</a> = 0,
234 <br/>
235 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga17af0bbf00a59ea1ac3352098fe44a89addd5cb442f49c6d3309e88a10ce15be3">EDMA3_DRV_TCINTEN_EN</a> = 1
236 <br/>
237 }</td></tr>
238 <tr><td class="mdescLeft"> </td><td class="mdescRight"><p>Transfer complete interrupt enable. </p>
239 <a href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga17af0bbf00a59ea1ac3352098fe44a89">More...</a><br/></td></tr>
240 <tr><td class="memItemLeft" align="right" valign="top">enum </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga58a32aad3b685509b9f74f63ec2b9d94">EDMA3_DRV_ItcintEn</a> { <br/>
241 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga58a32aad3b685509b9f74f63ec2b9d94a943e78d910f2085bd416b590fbad0dbe">EDMA3_DRV_ITCINTEN_DIS</a> = 0,
242 <br/>
243 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga58a32aad3b685509b9f74f63ec2b9d94a71e67e98224a3ee95e61f70e62a4f834">EDMA3_DRV_ITCINTEN_EN</a> = 1
244 <br/>
245 }</td></tr>
246 <tr><td class="mdescLeft"> </td><td class="mdescRight"><p>Intermediate Transfer complete interrupt enable. </p>
247 <a href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga58a32aad3b685509b9f74f63ec2b9d94">More...</a><br/></td></tr>
248 <tr><td class="memItemLeft" align="right" valign="top">enum </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9904b897549665b3cfacce106fa47d54">EDMA3_DRV_TcchEn</a> { <br/>
249 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga9904b897549665b3cfacce106fa47d54a6c1914663e61e8904dc24d03535d0daf">EDMA3_DRV_TCCHEN_DIS</a> = 0,
250 <br/>
251 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga9904b897549665b3cfacce106fa47d54a40b66d814cdf1a555d445d8dee4aeedb">EDMA3_DRV_TCCHEN_EN</a> = 1
252 <br/>
253 }</td></tr>
254 <tr><td class="mdescLeft"> </td><td class="mdescRight"><p>Transfer complete chaining enable. </p>
255 <a href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9904b897549665b3cfacce106fa47d54">More...</a><br/></td></tr>
256 <tr><td class="memItemLeft" align="right" valign="top">enum </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gaf310b7fc131330276a0757054987c4d4">EDMA3_DRV_ItcchEn</a> { <br/>
257 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ggaf310b7fc131330276a0757054987c4d4af4b23933674163b5cbda9c89e27c280a">EDMA3_DRV_ITCCHEN_DIS</a> = 0,
258 <br/>
259 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ggaf310b7fc131330276a0757054987c4d4acef8781cbeac3dadce5de47c603566e9">EDMA3_DRV_ITCCHEN_EN</a> = 1
260 <br/>
261 }</td></tr>
262 <tr><td class="mdescLeft"> </td><td class="mdescRight"><p>Intermediate Transfer complete chaining enable. </p>
263 <a href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gaf310b7fc131330276a0757054987c4d4">More...</a><br/></td></tr>
264 <tr><td class="memItemLeft" align="right" valign="top">enum </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> { <br/>
265 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga9a3d4fdcf4d2d089d4defebe3ef3880ea1ec2aa1fb8ed48534aa4190622792ea6">EDMA3_DRV_TRIG_MODE_MANUAL</a> = 0,
266 <br/>
267 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga9a3d4fdcf4d2d089d4defebe3ef3880ea7cbf536d24f7cb45fcaadc46ebf229ad">EDMA3_DRV_TRIG_MODE_QDMA</a> = 1,
268 <br/>
269 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga9a3d4fdcf4d2d089d4defebe3ef3880ea34671e10c511d857963484c4712d322d">EDMA3_DRV_TRIG_MODE_EVENT</a> = 2,
270 <br/>
271 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga9a3d4fdcf4d2d089d4defebe3ef3880ea45338caea71cdf45250e863c5fe4ed8d">EDMA3_DRV_TRIG_MODE_NONE</a> = 3
272 <br/>
273 }</td></tr>
274 <tr><td class="mdescLeft"> </td><td class="mdescRight"><p>EDMA Trigger Mode Selection. </p>
275 <a href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">More...</a><br/></td></tr>
276 <tr><td class="memItemLeft" align="right" valign="top">enum </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga82b01ec2292a13ad48a5bfcc724dfac6">EDMA3_DRV_PaRAMEntry</a> { <br/>
277 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga82b01ec2292a13ad48a5bfcc724dfac6a5cb3c2eda075435c8f48ef685a28971b">EDMA3_DRV_PARAM_ENTRY_OPT</a> = 0,
278 <br/>
279 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga82b01ec2292a13ad48a5bfcc724dfac6a08d5dcf368b15427e1b63023be97c699">EDMA3_DRV_PARAM_ENTRY_SRC</a> = 1,
280 <br/>
281 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga82b01ec2292a13ad48a5bfcc724dfac6a80beff4474df6d7a8d217d86bd0faac9">EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT</a> = 2,
282 <br/>
283 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga82b01ec2292a13ad48a5bfcc724dfac6a74640bb1fe574606fb7a0266e32c43fb">EDMA3_DRV_PARAM_ENTRY_DST</a> = 3,
284 <br/>
285 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga82b01ec2292a13ad48a5bfcc724dfac6ad644f9995a90ea8a52c8c25a84550c64">EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX</a> = 4,
286 <br/>
287 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga82b01ec2292a13ad48a5bfcc724dfac6a360b634a41639c9f7ce60f402d346393">EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD</a> = 5,
288 <br/>
289 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga82b01ec2292a13ad48a5bfcc724dfac6a03c6fd4b46aec54aee8f21ba515ff35b">EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX</a> = 6,
290 <br/>
291 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga82b01ec2292a13ad48a5bfcc724dfac6ae4ef2bad3f40788bfd46f198e646d3be">EDMA3_DRV_PARAM_ENTRY_CCNT</a> = 7
292 <br/>
293 }</td></tr>
294 <tr><td class="mdescLeft"> </td><td class="mdescRight"><p>PaRAM Set Entry type. </p>
295 <a href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga82b01ec2292a13ad48a5bfcc724dfac6">More...</a><br/></td></tr>
296 <tr><td class="memItemLeft" align="right" valign="top">enum </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga3e31ba1b02dcbace3044c11c83ef5466">EDMA3_DRV_PaRAMField</a> { <br/>
297 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga3e31ba1b02dcbace3044c11c83ef5466a4e5f6bbfb68c8a5981b321ea2c96400f">EDMA3_DRV_PARAM_FIELD_OPT</a> = 0,
298 <br/>
299 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga3e31ba1b02dcbace3044c11c83ef5466ace688d06479875eed547e49c7c53a7dd">EDMA3_DRV_PARAM_FIELD_SRCADDR</a> = 1,
300 <br/>
301 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga3e31ba1b02dcbace3044c11c83ef5466a331bd6b991f25211c9e330dca0df0f9c">EDMA3_DRV_PARAM_FIELD_ACNT</a> = 2,
302 <br/>
303 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga3e31ba1b02dcbace3044c11c83ef5466a6b1fa5f67bb599bcb53511d709f4b0b4">EDMA3_DRV_PARAM_FIELD_BCNT</a> = 3,
304 <br/>
305 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga3e31ba1b02dcbace3044c11c83ef5466aac116996738f643163f45ae1472aa84b">EDMA3_DRV_PARAM_FIELD_DESTADDR</a> = 4,
306 <br/>
307 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga3e31ba1b02dcbace3044c11c83ef5466a60a6dbf01d64675758281d3ac8d30791">EDMA3_DRV_PARAM_FIELD_SRCBIDX</a> = 5,
308 <br/>
309 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga3e31ba1b02dcbace3044c11c83ef5466ae1e0807fd4f93c272585e417136ece9d">EDMA3_DRV_PARAM_FIELD_DESTBIDX</a> = 6,
310 <br/>
311 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga3e31ba1b02dcbace3044c11c83ef5466a99f25744315b46aa4de1e11011f9d334">EDMA3_DRV_PARAM_FIELD_LINKADDR</a> = 7,
312 <br/>
313 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga3e31ba1b02dcbace3044c11c83ef5466a10933409050bda13b4650123a9fed111">EDMA3_DRV_PARAM_FIELD_BCNTRELOAD</a> = 8,
314 <br/>
315 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga3e31ba1b02dcbace3044c11c83ef5466a01814312c8c7dd46d18c3d315fad737f">EDMA3_DRV_PARAM_FIELD_SRCCIDX</a> = 9,
316 <br/>
317 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga3e31ba1b02dcbace3044c11c83ef5466a4be8857b84549ceb9ae2f533f8db3923">EDMA3_DRV_PARAM_FIELD_DESTCIDX</a> = 10,
318 <br/>
319 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga3e31ba1b02dcbace3044c11c83ef5466affd4ae69a7feb876b6b4aa40d5099017">EDMA3_DRV_PARAM_FIELD_CCNT</a> = 11
320 <br/>
321 }</td></tr>
322 <tr><td class="mdescLeft"> </td><td class="mdescRight"><p>PaRAM Set Field type. </p>
323 <a href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga3e31ba1b02dcbace3044c11c83ef5466">More...</a><br/></td></tr>
324 <tr><td class="memItemLeft" align="right" valign="top">enum </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8577940463f7ca5a8977b2fb65fae19a">EDMA3_DRV_IoctlCmd</a> { , <br/>
325 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8577940463f7ca5a8977b2fb65fae19aac79f621f036d0e97746c5776ccc18a2e">EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION</a>,
326 <br/>
327 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga8577940463f7ca5a8977b2fb65fae19aa9ef62634a561e221c136e62de9694f48">EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION</a>
328 <br/>
329 }</td></tr>
330 <tr><td class="mdescLeft"> </td><td class="mdescRight"><p>EDMA3 Driver IOCTL commands. </p>
331 <a href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8577940463f7ca5a8977b2fb65fae19a">More...</a><br/></td></tr>
332 <tr><td class="memItemLeft" align="right" valign="top">enum </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga2b3b55b1d7c987a7873d8b0b085173b2">EDMA3_DRV_Tc_Err</a> { <br/>
333 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga2b3b55b1d7c987a7873d8b0b085173b2a110f0b3a441d3cc8eddde87e1ef22de9">EDMA3_DRV_TC_ERR_BUSERR_DIS</a> = 0,
334 <br/>
335 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga2b3b55b1d7c987a7873d8b0b085173b2a92df5a4324184dfa6b910a5f326fe87e">EDMA3_DRV_TC_ERR_BUSERR_EN</a>,
336 <br/>
337 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga2b3b55b1d7c987a7873d8b0b085173b2a087691858a676ef6db124941660ff976">EDMA3_DRV_TC_ERR_TRERR_DIS</a>,
338 <br/>
339 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga2b3b55b1d7c987a7873d8b0b085173b2a570e19187612848c18a510d1fa1ea5cc">EDMA3_DRV_TC_ERR_TRERR_EN</a>,
340 <br/>
341 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga2b3b55b1d7c987a7873d8b0b085173b2ac9c1819e715355de30b5905863fdf0a0">EDMA3_DRV_TC_ERR_MMRAERR_DIS</a>,
342 <br/>
343 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga2b3b55b1d7c987a7873d8b0b085173b2af883f7b1ce601de018e3644535f72446">EDMA3_DRV_TC_ERR_MMRAERR_EN</a>,
344 <br/>
345 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga2b3b55b1d7c987a7873d8b0b085173b2ae24b256e04df975d45269caf2325dcd7">EDMA3_DRV_TC_ERR_DIS</a>,
346 <br/>
347 <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gga2b3b55b1d7c987a7873d8b0b085173b2acc54d0adc6465d49a94d6571cc704093">EDMA3_DRV_TC_ERR_EN</a>
348 <br/>
349 }</td></tr>
350 <tr><td class="mdescLeft"> </td><td class="mdescRight"><p>TC Error Enablers. </p>
351 <a href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga2b3b55b1d7c987a7873d8b0b085173b2">More...</a><br/></td></tr>
352 </table>
353 <hr/><h2>Enumeration Type Documentation</h2>
354 <a class="anchor" id="ga8e20d4ba59240144067e70bb8beb7879"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_HW_CHANNEL_EVENT" ref="ga8e20d4ba59240144067e70bb8beb7879" args="" -->
355 <div class="memitem">
356 <div class="memproto">
357 <table class="memname">
358 <tr>
359 <td class="memname">enum <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8e20d4ba59240144067e70bb8beb7879">EDMA3_DRV_HW_CHANNEL_EVENT</a></td>
360 </tr>
361 </table>
362 </div>
363 <div class="memdoc">
365 <p>DMA Channels assigned to different Hardware Events. </p>
366 <p>They should be used while requesting a specific DMA channel. One possible usage is to maintain a SoC specific file, which will contain the mapping of these hardware events to the respective peripherals for better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets changed, only that SoC specific file needs to be changed. for eg, the sample SoC specific file "soc.h" can have these defines:</p>
367 <p>define EDMA3_DRV_HW_CHANNEL_MCBSP_TX EDMA3_DRV_HW_CHANNEL_EVENT_2 define EDMA3_DRV_HW_CHANNEL_MCBSP_RX EDMA3_DRV_HW_CHANNEL_EVENT_3</p>
368 <p>These defines will be used by the MCBSP driver. The same event EDMA3_DRV_HW_CHANNEL_EVENT_2/3 could be mapped to some other peripheral also. </p>
369 <dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
370 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a37748ea68c4fbf181415d15e4548a9d5"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_0" ref="gga8e20d4ba59240144067e70bb8beb7879a37748ea68c4fbf181415d15e4548a9d5" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_0</em> </td><td>
371 <p>Channel assigned to EDMA3 Event 0 </p>
372 </td></tr>
373 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a34192b4602da79a32906e449e86ddea9"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_1" ref="gga8e20d4ba59240144067e70bb8beb7879a34192b4602da79a32906e449e86ddea9" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_1</em> </td><td>
374 <p>Channel assigned to EDMA3 Event 1 </p>
375 </td></tr>
376 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879ac36395e3506bd6fc8daf06ea945c4f1b"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_2" ref="gga8e20d4ba59240144067e70bb8beb7879ac36395e3506bd6fc8daf06ea945c4f1b" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_2</em> </td><td>
377 <p>Channel assigned to EDMA3 Event 2 </p>
378 </td></tr>
379 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879ad26ddd5a62ff5a8c079eff713ed24a6c"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_3" ref="gga8e20d4ba59240144067e70bb8beb7879ad26ddd5a62ff5a8c079eff713ed24a6c" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_3</em> </td><td>
380 <p>Channel assigned to EDMA3 Event 3 </p>
381 </td></tr>
382 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879ab8d954a5708596eb302bbe617e16883e"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_4" ref="gga8e20d4ba59240144067e70bb8beb7879ab8d954a5708596eb302bbe617e16883e" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_4</em> </td><td>
383 <p>Channel assigned to EDMA3 Event 4 </p>
384 </td></tr>
385 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a2ca5cca9c6e9c39d36c71feb28729a4c"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_5" ref="gga8e20d4ba59240144067e70bb8beb7879a2ca5cca9c6e9c39d36c71feb28729a4c" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_5</em> </td><td>
386 <p>Channel assigned to EDMA3 Event 5 </p>
387 </td></tr>
388 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879afed5d83771dff787abfa671c489c5bc1"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_6" ref="gga8e20d4ba59240144067e70bb8beb7879afed5d83771dff787abfa671c489c5bc1" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_6</em> </td><td>
389 <p>Channel assigned to EDMA3 Event 6 </p>
390 </td></tr>
391 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879aad3f865ffab348c3bcfd75339801fc33"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_7" ref="gga8e20d4ba59240144067e70bb8beb7879aad3f865ffab348c3bcfd75339801fc33" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_7</em> </td><td>
392 <p>Channel assigned to EDMA3 Event 7 </p>
393 </td></tr>
394 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a3725a5901d7680739b36b5ffd3e5128b"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_8" ref="gga8e20d4ba59240144067e70bb8beb7879a3725a5901d7680739b36b5ffd3e5128b" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_8</em> </td><td>
395 <p>Channel assigned to EDMA3 Event 8 </p>
396 </td></tr>
397 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a842a774c34014c24c7ad9e4a8aa2aa72"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_9" ref="gga8e20d4ba59240144067e70bb8beb7879a842a774c34014c24c7ad9e4a8aa2aa72" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_9</em> </td><td>
398 <p>Channel assigned to EDMA3 Event 9 </p>
399 </td></tr>
400 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a2d99e6b419712a65dcd7a920b36a866e"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_10" ref="gga8e20d4ba59240144067e70bb8beb7879a2d99e6b419712a65dcd7a920b36a866e" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_10</em> </td><td>
401 <p>Channel assigned to EDMA3 Event 10 </p>
402 </td></tr>
403 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879ab956cf256d1818a5909f0399d85612f4"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_11" ref="gga8e20d4ba59240144067e70bb8beb7879ab956cf256d1818a5909f0399d85612f4" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_11</em> </td><td>
404 <p>Channel assigned to EDMA3 Event 11 </p>
405 </td></tr>
406 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a05b4c74778694509a7759e4cd124bc23"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_12" ref="gga8e20d4ba59240144067e70bb8beb7879a05b4c74778694509a7759e4cd124bc23" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_12</em> </td><td>
407 <p>Channel assigned to EDMA3 Event 12 </p>
408 </td></tr>
409 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a7d86b7fe7d7c3f0077a2c8a445f16943"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_13" ref="gga8e20d4ba59240144067e70bb8beb7879a7d86b7fe7d7c3f0077a2c8a445f16943" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_13</em> </td><td>
410 <p>Channel assigned to EDMA3 Event 13 </p>
411 </td></tr>
412 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a44782731229ca9470e1f46ed93bf6954"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_14" ref="gga8e20d4ba59240144067e70bb8beb7879a44782731229ca9470e1f46ed93bf6954" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_14</em> </td><td>
413 <p>Channel assigned to EDMA3 Event 14 </p>
414 </td></tr>
415 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a6a773568b775bff069188481b2b1dc75"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_15" ref="gga8e20d4ba59240144067e70bb8beb7879a6a773568b775bff069188481b2b1dc75" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_15</em> </td><td>
416 <p>Channel assigned to EDMA3 Event 15 </p>
417 </td></tr>
418 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879aa7c914b81cad4f66cd91ec5e89240a9d"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_16" ref="gga8e20d4ba59240144067e70bb8beb7879aa7c914b81cad4f66cd91ec5e89240a9d" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_16</em> </td><td>
419 <p>Channel assigned to EDMA3 Event 16 </p>
420 </td></tr>
421 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a6dedf754dfe2a6eb21a9c4b2a8342099"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_17" ref="gga8e20d4ba59240144067e70bb8beb7879a6dedf754dfe2a6eb21a9c4b2a8342099" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_17</em> </td><td>
422 <p>Channel assigned to EDMA3 Event 17 </p>
423 </td></tr>
424 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a7c0d3ec834f566bf8b3ce427038baf60"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_18" ref="gga8e20d4ba59240144067e70bb8beb7879a7c0d3ec834f566bf8b3ce427038baf60" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_18</em> </td><td>
425 <p>Channel assigned to EDMA3 Event 18 </p>
426 </td></tr>
427 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a71d5ec033e254c3a355a8c876304296f"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_19" ref="gga8e20d4ba59240144067e70bb8beb7879a71d5ec033e254c3a355a8c876304296f" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_19</em> </td><td>
428 <p>Channel assigned to EDMA3 Event 19 </p>
429 </td></tr>
430 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879ac9fd5d6ea19828bba5af7052223d532d"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_20" ref="gga8e20d4ba59240144067e70bb8beb7879ac9fd5d6ea19828bba5af7052223d532d" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_20</em> </td><td>
431 <p>Channel assigned to EDMA3 Event 20 </p>
432 </td></tr>
433 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a4945278d24520fa8fe0dbf543582bdb4"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_21" ref="gga8e20d4ba59240144067e70bb8beb7879a4945278d24520fa8fe0dbf543582bdb4" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_21</em> </td><td>
434 <p>Channel assigned to EDMA3 Event 21 </p>
435 </td></tr>
436 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a5222e130853fdbb6ce243bd8f8e516a6"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_22" ref="gga8e20d4ba59240144067e70bb8beb7879a5222e130853fdbb6ce243bd8f8e516a6" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_22</em> </td><td>
437 <p>Channel assigned to EDMA3 Event 22 </p>
438 </td></tr>
439 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a3ace2470d524a24e37a8e87fe5f4546e"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_23" ref="gga8e20d4ba59240144067e70bb8beb7879a3ace2470d524a24e37a8e87fe5f4546e" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_23</em> </td><td>
440 <p>Channel assigned to EDMA3 Event 23 </p>
441 </td></tr>
442 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879ab8dbc9b117c7c16203ffe9268ac8943e"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_24" ref="gga8e20d4ba59240144067e70bb8beb7879ab8dbc9b117c7c16203ffe9268ac8943e" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_24</em> </td><td>
443 <p>Channel assigned to EDMA3 Event 24 </p>
444 </td></tr>
445 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a96ff3814c0936e06525dae25737b8e8c"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_25" ref="gga8e20d4ba59240144067e70bb8beb7879a96ff3814c0936e06525dae25737b8e8c" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_25</em> </td><td>
446 <p>Channel assigned to EDMA3 Event 25 </p>
447 </td></tr>
448 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a524cc629d15967c9e21547a1053af654"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_26" ref="gga8e20d4ba59240144067e70bb8beb7879a524cc629d15967c9e21547a1053af654" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_26</em> </td><td>
449 <p>Channel assigned to EDMA3 Event 26 </p>
450 </td></tr>
451 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a9138ddea8bb08222af544e7a1d884ebf"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_27" ref="gga8e20d4ba59240144067e70bb8beb7879a9138ddea8bb08222af544e7a1d884ebf" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_27</em> </td><td>
452 <p>Channel assigned to EDMA3 Event 27 </p>
453 </td></tr>
454 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879ae916849b035d8101e163ffb18a45f3b1"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_28" ref="gga8e20d4ba59240144067e70bb8beb7879ae916849b035d8101e163ffb18a45f3b1" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_28</em> </td><td>
455 <p>Channel assigned to EDMA3 Event 28 </p>
456 </td></tr>
457 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a97c9fd86fb3de0ff7963cdeb6ae0adb8"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_29" ref="gga8e20d4ba59240144067e70bb8beb7879a97c9fd86fb3de0ff7963cdeb6ae0adb8" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_29</em> </td><td>
458 <p>Channel assigned to EDMA3 Event 29 </p>
459 </td></tr>
460 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879ab1bcf6eaa841f660d14fee3e96fd86ed"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_30" ref="gga8e20d4ba59240144067e70bb8beb7879ab1bcf6eaa841f660d14fee3e96fd86ed" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_30</em> </td><td>
461 <p>Channel assigned to EDMA3 Event 30 </p>
462 </td></tr>
463 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a23b6ccf182d6c2cf4572d84190021c51"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_31" ref="gga8e20d4ba59240144067e70bb8beb7879a23b6ccf182d6c2cf4572d84190021c51" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_31</em> </td><td>
464 <p>Channel assigned to EDMA3 Event 31 </p>
465 </td></tr>
466 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879adbc4408571a19ec5ec731c2675aeeece"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_32" ref="gga8e20d4ba59240144067e70bb8beb7879adbc4408571a19ec5ec731c2675aeeece" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_32</em> </td><td>
467 <p>Channel assigned to EDMA3 Event 32 </p>
468 </td></tr>
469 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a4a54cb99692eb23ecb672ac221a70615"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_33" ref="gga8e20d4ba59240144067e70bb8beb7879a4a54cb99692eb23ecb672ac221a70615" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_33</em> </td><td>
470 <p>Channel assigned to EDMA3 Event 33 </p>
471 </td></tr>
472 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a0d03823cb59ab55fd030d1d9603d19af"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_34" ref="gga8e20d4ba59240144067e70bb8beb7879a0d03823cb59ab55fd030d1d9603d19af" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_34</em> </td><td>
473 <p>Channel assigned to EDMA3 Event 34 </p>
474 </td></tr>
475 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879afda0f229cb06304229edf3900a522b88"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_35" ref="gga8e20d4ba59240144067e70bb8beb7879afda0f229cb06304229edf3900a522b88" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_35</em> </td><td>
476 <p>Channel assigned to EDMA3 Event 35 </p>
477 </td></tr>
478 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879aec1b8659d6056dc1a469ff839cb45e8d"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_36" ref="gga8e20d4ba59240144067e70bb8beb7879aec1b8659d6056dc1a469ff839cb45e8d" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_36</em> </td><td>
479 <p>Channel assigned to EDMA3 Event 36 </p>
480 </td></tr>
481 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879aaefcfee3c1dd42b400f4c5d746842068"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_37" ref="gga8e20d4ba59240144067e70bb8beb7879aaefcfee3c1dd42b400f4c5d746842068" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_37</em> </td><td>
482 <p>Channel assigned to EDMA3 Event 37 </p>
483 </td></tr>
484 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a0f175e73d48663fd438dac124870e8db"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_38" ref="gga8e20d4ba59240144067e70bb8beb7879a0f175e73d48663fd438dac124870e8db" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_38</em> </td><td>
485 <p>Channel assigned to EDMA3 Event 38 </p>
486 </td></tr>
487 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879ab3f7ae332e42e4e0c6cd626cb79f3fb7"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_39" ref="gga8e20d4ba59240144067e70bb8beb7879ab3f7ae332e42e4e0c6cd626cb79f3fb7" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_39</em> </td><td>
488 <p>Channel assigned to EDMA3 Event 39 </p>
489 </td></tr>
490 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a01ffb1c47ac459f570347f418da7d8b9"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_40" ref="gga8e20d4ba59240144067e70bb8beb7879a01ffb1c47ac459f570347f418da7d8b9" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_40</em> </td><td>
491 <p>Channel assigned to EDMA3 Event 40 </p>
492 </td></tr>
493 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a1a5aa3f4c27488ec11c8e3b3bc2dd027"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_41" ref="gga8e20d4ba59240144067e70bb8beb7879a1a5aa3f4c27488ec11c8e3b3bc2dd027" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_41</em> </td><td>
494 <p>Channel assigned to EDMA3 Event 41 </p>
495 </td></tr>
496 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879aac157667fee035df11975decb8a0fdae"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_42" ref="gga8e20d4ba59240144067e70bb8beb7879aac157667fee035df11975decb8a0fdae" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_42</em> </td><td>
497 <p>Channel assigned to EDMA3 Event 42 </p>
498 </td></tr>
499 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879aa048e7a75547802ed7929cef4466fec0"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_43" ref="gga8e20d4ba59240144067e70bb8beb7879aa048e7a75547802ed7929cef4466fec0" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_43</em> </td><td>
500 <p>Channel assigned to EDMA3 Event 43 </p>
501 </td></tr>
502 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a70b36fb01559fd3374607d8a574ded25"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_44" ref="gga8e20d4ba59240144067e70bb8beb7879a70b36fb01559fd3374607d8a574ded25" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_44</em> </td><td>
503 <p>Channel assigned to EDMA3 Event 44 </p>
504 </td></tr>
505 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a7a654d02cf59e7102f0738071bdca213"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_45" ref="gga8e20d4ba59240144067e70bb8beb7879a7a654d02cf59e7102f0738071bdca213" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_45</em> </td><td>
506 <p>Channel assigned to EDMA3 Event 45 </p>
507 </td></tr>
508 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879aa229f0efb4bd21aa34211237b240c524"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_46" ref="gga8e20d4ba59240144067e70bb8beb7879aa229f0efb4bd21aa34211237b240c524" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_46</em> </td><td>
509 <p>Channel assigned to EDMA3 Event 46 </p>
510 </td></tr>
511 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a05fc551f36ded0686a571b6631879a90"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_47" ref="gga8e20d4ba59240144067e70bb8beb7879a05fc551f36ded0686a571b6631879a90" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_47</em> </td><td>
512 <p>Channel assigned to EDMA3 Event 47 </p>
513 </td></tr>
514 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a295b1b324c9d77d4d971073c52e2e40e"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_48" ref="gga8e20d4ba59240144067e70bb8beb7879a295b1b324c9d77d4d971073c52e2e40e" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_48</em> </td><td>
515 <p>Channel assigned to EDMA3 Event 48 </p>
516 </td></tr>
517 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a9073a64c7ba4caf6ef0359d82adf24d8"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_49" ref="gga8e20d4ba59240144067e70bb8beb7879a9073a64c7ba4caf6ef0359d82adf24d8" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_49</em> </td><td>
518 <p>Channel assigned to EDMA3 Event 49 </p>
519 </td></tr>
520 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a6af730dab1edf67d74b5104fda134950"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_50" ref="gga8e20d4ba59240144067e70bb8beb7879a6af730dab1edf67d74b5104fda134950" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_50</em> </td><td>
521 <p>Channel assigned to EDMA3 Event 50 </p>
522 </td></tr>
523 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879abd179dd58d8512110a5452b5bdcdbcc1"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_51" ref="gga8e20d4ba59240144067e70bb8beb7879abd179dd58d8512110a5452b5bdcdbcc1" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_51</em> </td><td>
524 <p>Channel assigned to EDMA3 Event 51 </p>
525 </td></tr>
526 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a51b4adfa16b35ade08028839796a1481"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_52" ref="gga8e20d4ba59240144067e70bb8beb7879a51b4adfa16b35ade08028839796a1481" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_52</em> </td><td>
527 <p>Channel assigned to EDMA3 Event 52 </p>
528 </td></tr>
529 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879ae527c710b10d5b4f3f6d7b5968acaec4"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_53" ref="gga8e20d4ba59240144067e70bb8beb7879ae527c710b10d5b4f3f6d7b5968acaec4" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_53</em> </td><td>
530 <p>Channel assigned to EDMA3 Event 53 </p>
531 </td></tr>
532 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a19505cbe43eabceb5988d8cd388b4789"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_54" ref="gga8e20d4ba59240144067e70bb8beb7879a19505cbe43eabceb5988d8cd388b4789" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_54</em> </td><td>
533 <p>Channel assigned to EDMA3 Event 54 </p>
534 </td></tr>
535 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879aa565cbfa49e3f0c1fb2db2db71a454ce"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_55" ref="gga8e20d4ba59240144067e70bb8beb7879aa565cbfa49e3f0c1fb2db2db71a454ce" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_55</em> </td><td>
536 <p>Channel assigned to EDMA3 Event 55 </p>
537 </td></tr>
538 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879ac3c80729cb5bb6f55ebe0366ddc7b54a"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_56" ref="gga8e20d4ba59240144067e70bb8beb7879ac3c80729cb5bb6f55ebe0366ddc7b54a" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_56</em> </td><td>
539 <p>Channel assigned to EDMA3 Event 56 </p>
540 </td></tr>
541 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a910e620e5654fd23c6cfcef61332bed9"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_57" ref="gga8e20d4ba59240144067e70bb8beb7879a910e620e5654fd23c6cfcef61332bed9" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_57</em> </td><td>
542 <p>Channel assigned to EDMA3 Event 57 </p>
543 </td></tr>
544 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879aa5be0518bc15f08ca41a4c9cdea357a0"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_58" ref="gga8e20d4ba59240144067e70bb8beb7879aa5be0518bc15f08ca41a4c9cdea357a0" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_58</em> </td><td>
545 <p>Channel assigned to EDMA3 Event 58 </p>
546 </td></tr>
547 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a42081e20d0bd84418cdebeb3d3c3a74e"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_59" ref="gga8e20d4ba59240144067e70bb8beb7879a42081e20d0bd84418cdebeb3d3c3a74e" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_59</em> </td><td>
548 <p>Channel assigned to EDMA3 Event 59 </p>
549 </td></tr>
550 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879ae6411d5de6e88e2dc7c41e8e5f7859e3"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_60" ref="gga8e20d4ba59240144067e70bb8beb7879ae6411d5de6e88e2dc7c41e8e5f7859e3" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_60</em> </td><td>
551 <p>Channel assigned to EDMA3 Event 60 </p>
552 </td></tr>
553 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879a786abf418a32147a6df87dac6943576c"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_61" ref="gga8e20d4ba59240144067e70bb8beb7879a786abf418a32147a6df87dac6943576c" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_61</em> </td><td>
554 <p>Channel assigned to EDMA3 Event 61 </p>
555 </td></tr>
556 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879acf2aaad445adea762c1f1541038b2d9d"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_62" ref="gga8e20d4ba59240144067e70bb8beb7879acf2aaad445adea762c1f1541038b2d9d" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_62</em> </td><td>
557 <p>Channel assigned to EDMA3 Event 62 </p>
558 </td></tr>
559 <tr><td valign="top"><em><a class="anchor" id="gga8e20d4ba59240144067e70bb8beb7879af3f3eacae6b1b26111f7988ca3b3e9e8"></a><!-- doxytag: member="EDMA3_DRV_HW_CHANNEL_EVENT_63" ref="gga8e20d4ba59240144067e70bb8beb7879af3f3eacae6b1b26111f7988ca3b3e9e8" args="" -->EDMA3_DRV_HW_CHANNEL_EVENT_63</em> </td><td>
560 <p>Channel assigned to EDMA3 Event 63 </p>
561 </td></tr>
562 </table>
563 </dd>
564 </dl>
566 </div>
567 </div>
568 <a class="anchor" id="gaa0c576e8e46ac8db85c05bf73c01a5f9"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_OptField" ref="gaa0c576e8e46ac8db85c05bf73c01a5f9" args="" -->
569 <div class="memitem">
570 <div class="memproto">
571 <table class="memname">
572 <tr>
573 <td class="memname">enum <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gaa0c576e8e46ac8db85c05bf73c01a5f9">EDMA3_DRV_OptField</a></td>
574 </tr>
575 </table>
576 </div>
577 <div class="memdoc">
579 <p>OPT Field Offset. </p>
580 <p>Use this enum to set or get any of the Fields within an OPT of a Parameter RAM set. </p>
581 <dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
582 <tr><td valign="top"><em><a class="anchor" id="ggaa0c576e8e46ac8db85c05bf73c01a5f9a693924fb6d1e68b84bc3189c7bdc4a43"></a><!-- doxytag: member="EDMA3_DRV_OPT_FIELD_SAM" ref="ggaa0c576e8e46ac8db85c05bf73c01a5f9a693924fb6d1e68b84bc3189c7bdc4a43" args="" -->EDMA3_DRV_OPT_FIELD_SAM</em> </td><td>
583 <p>Source addressing mode (INCR / FIFO) (Bit 0) </p>
584 </td></tr>
585 <tr><td valign="top"><em><a class="anchor" id="ggaa0c576e8e46ac8db85c05bf73c01a5f9a0c59c9664e56dee41effaa7f73bac59e"></a><!-- doxytag: member="EDMA3_DRV_OPT_FIELD_DAM" ref="ggaa0c576e8e46ac8db85c05bf73c01a5f9a0c59c9664e56dee41effaa7f73bac59e" args="" -->EDMA3_DRV_OPT_FIELD_DAM</em> </td><td>
586 <p>Destination addressing mode (INCR / FIFO) (Bit 1) </p>
587 </td></tr>
588 <tr><td valign="top"><em><a class="anchor" id="ggaa0c576e8e46ac8db85c05bf73c01a5f9a4f41648673db6dbe534b91d742647c14"></a><!-- doxytag: member="EDMA3_DRV_OPT_FIELD_SYNCDIM" ref="ggaa0c576e8e46ac8db85c05bf73c01a5f9a4f41648673db6dbe534b91d742647c14" args="" -->EDMA3_DRV_OPT_FIELD_SYNCDIM</em> </td><td>
589 <p>Transfer synchronization dimension (A-synchronized / AB-synchronized) (Bit 2) </p>
590 </td></tr>
591 <tr><td valign="top"><em><a class="anchor" id="ggaa0c576e8e46ac8db85c05bf73c01a5f9a577a829a8eda4500296701051fa3b62e"></a><!-- doxytag: member="EDMA3_DRV_OPT_FIELD_STATIC" ref="ggaa0c576e8e46ac8db85c05bf73c01a5f9a577a829a8eda4500296701051fa3b62e" args="" -->EDMA3_DRV_OPT_FIELD_STATIC</em> </td><td>
592 <p>The STATIC field PaRAM set is static/non-static? (Bit 3) </p>
593 </td></tr>
594 <tr><td valign="top"><em><a class="anchor" id="ggaa0c576e8e46ac8db85c05bf73c01a5f9a8b6903281c09308c0a2caf154fa818c8"></a><!-- doxytag: member="EDMA3_DRV_OPT_FIELD_FWID" ref="ggaa0c576e8e46ac8db85c05bf73c01a5f9a8b6903281c09308c0a2caf154fa818c8" args="" -->EDMA3_DRV_OPT_FIELD_FWID</em> </td><td>
595 <p>FIFO Width. Applies if either SAM or DAM is set to FIFO mode. (Bitfield 8-10) </p>
596 </td></tr>
597 <tr><td valign="top"><em><a class="anchor" id="ggaa0c576e8e46ac8db85c05bf73c01a5f9ae4519d3ceac24626c65179ab59fb4920"></a><!-- doxytag: member="EDMA3_DRV_OPT_FIELD_TCCMODE" ref="ggaa0c576e8e46ac8db85c05bf73c01a5f9ae4519d3ceac24626c65179ab59fb4920" args="" -->EDMA3_DRV_OPT_FIELD_TCCMODE</em> </td><td>
598 <p>Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation. (Bit 11) </p>
599 </td></tr>
600 <tr><td valign="top"><em><a class="anchor" id="ggaa0c576e8e46ac8db85c05bf73c01a5f9af8cd20cde06093138d915f2154daf7f4"></a><!-- doxytag: member="EDMA3_DRV_OPT_FIELD_TCC" ref="ggaa0c576e8e46ac8db85c05bf73c01a5f9af8cd20cde06093138d915f2154daf7f4" args="" -->EDMA3_DRV_OPT_FIELD_TCC</em> </td><td>
601 <p>Transfer Complete Code (TCC). This 6-bit code is used to set the relevant bit in chaining enable register (CER[TCC]/CERH[TCC]) for chaining or in interrupt pending register (IPR[TCC]/IPRH[TCC]) for interrupts. (Bitfield 12-17) </p>
602 </td></tr>
603 <tr><td valign="top"><em><a class="anchor" id="ggaa0c576e8e46ac8db85c05bf73c01a5f9a422f20ac0c5217d2bad4ffe20627bae5"></a><!-- doxytag: member="EDMA3_DRV_OPT_FIELD_TCINTEN" ref="ggaa0c576e8e46ac8db85c05bf73c01a5f9a422f20ac0c5217d2bad4ffe20627bae5" args="" -->EDMA3_DRV_OPT_FIELD_TCINTEN</em> </td><td>
604 <p>Transfer complete interrupt enable/disable. (Bit 20) </p>
605 </td></tr>
606 <tr><td valign="top"><em><a class="anchor" id="ggaa0c576e8e46ac8db85c05bf73c01a5f9a6feb2084abf4287d809d27a725e29130"></a><!-- doxytag: member="EDMA3_DRV_OPT_FIELD_ITCINTEN" ref="ggaa0c576e8e46ac8db85c05bf73c01a5f9a6feb2084abf4287d809d27a725e29130" args="" -->EDMA3_DRV_OPT_FIELD_ITCINTEN</em> </td><td>
607 <p>Intermediate transfer complete interrupt enable/disable. (Bit 21) </p>
608 </td></tr>
609 <tr><td valign="top"><em><a class="anchor" id="ggaa0c576e8e46ac8db85c05bf73c01a5f9ac5ab9f8dea50cb16fbdc30a707fce88f"></a><!-- doxytag: member="EDMA3_DRV_OPT_FIELD_TCCHEN" ref="ggaa0c576e8e46ac8db85c05bf73c01a5f9ac5ab9f8dea50cb16fbdc30a707fce88f" args="" -->EDMA3_DRV_OPT_FIELD_TCCHEN</em> </td><td>
610 <p>Transfer complete chaining enable/disable (Bit 22) </p>
611 </td></tr>
612 <tr><td valign="top"><em><a class="anchor" id="ggaa0c576e8e46ac8db85c05bf73c01a5f9a65bb7252badcb593139f4f3747ec96ce"></a><!-- doxytag: member="EDMA3_DRV_OPT_FIELD_ITCCHEN" ref="ggaa0c576e8e46ac8db85c05bf73c01a5f9a65bb7252badcb593139f4f3747ec96ce" args="" -->EDMA3_DRV_OPT_FIELD_ITCCHEN</em> </td><td>
613 <p>Intermediate transfer completion chaining enable/disable (Bit 23) </p>
614 </td></tr>
615 </table>
616 </dd>
617 </dl>
619 </div>
620 </div>
621 <a class="anchor" id="ga5896f43e878f4e9c47b449fccdec3af9"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_AddrMode" ref="ga5896f43e878f4e9c47b449fccdec3af9" args="" -->
622 <div class="memitem">
623 <div class="memproto">
624 <table class="memname">
625 <tr>
626 <td class="memname">enum <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga5896f43e878f4e9c47b449fccdec3af9">EDMA3_DRV_AddrMode</a></td>
627 </tr>
628 </table>
629 </div>
630 <div class="memdoc">
632 <p>EDMA Addressing modes. </p>
633 <p>The EDMA3 TC supports two addressing modes</p>
634 <ol type="1">
635 <li>Increment transfer</li>
636 <li>FIFO transfer</li>
637 </ol>
638 <p>The SAM (Source Addressing Mode) and the DAM (Destination Addressing Mode) can be independently set to either of the two via the OPT register. </p>
639 <dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
640 <tr><td valign="top"><em><a class="anchor" id="gga5896f43e878f4e9c47b449fccdec3af9ad51ef7530b1165c92ee355d69339ed38"></a><!-- doxytag: member="EDMA3_DRV_ADDR_MODE_INCR" ref="gga5896f43e878f4e9c47b449fccdec3af9ad51ef7530b1165c92ee355d69339ed38" args="" -->EDMA3_DRV_ADDR_MODE_INCR</em> </td><td>
641 <p>Increment (INCR) mode. Source addressing within an array increments. Source is not a FIFO. </p>
642 </td></tr>
643 <tr><td valign="top"><em><a class="anchor" id="gga5896f43e878f4e9c47b449fccdec3af9a0efc564b242e308363be650fc96ffc67"></a><!-- doxytag: member="EDMA3_DRV_ADDR_MODE_FIFO" ref="gga5896f43e878f4e9c47b449fccdec3af9a0efc564b242e308363be650fc96ffc67" args="" -->EDMA3_DRV_ADDR_MODE_FIFO</em> </td><td>
644 <p>FIFO mode. Source addressing within an array wraps around upon reaching FIFO width. </p>
645 </td></tr>
646 </table>
647 </dd>
648 </dl>
650 </div>
651 </div>
652 <a class="anchor" id="ga1cc0705e142298a424a312034bd3b2c2"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_SyncType" ref="ga1cc0705e142298a424a312034bd3b2c2" args="" -->
653 <div class="memitem">
654 <div class="memproto">
655 <table class="memname">
656 <tr>
657 <td class="memname">enum <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga1cc0705e142298a424a312034bd3b2c2">EDMA3_DRV_SyncType</a></td>
658 </tr>
659 </table>
660 </div>
661 <div class="memdoc">
663 <p>EDMA Transfer Synchronization type. </p>
664 <p>Two types of Synchronization of transfers are possible</p>
665 <ol type="1">
666 <li>A Synchronized</li>
667 <li>AB Syncronized</li>
668 </ol>
669 <p>A Sync</p>
670 <ol type="1">
671 <li>Each Array is submitted as one TR</li>
672 <li>(BCNT*CCNT) number of sync events are needed to completely service a PaRAM set. (Where BCNT = Num of Arrays in a Frame; CCNT = Num of Frames in a Block)</li>
673 <li>(S/D)CIDX = (Addr of First array in next frame) minus (Addr of Last array in present frame) (Where CIDX is the Inter-Frame index)</li>
674 </ol>
675 <ul>
676 <li>AB Sync<ol type="a">
677 <li>Each Frame is submitted as one TR</li>
678 <li>Only CCNT number of sync events are needed to completely service a PaRAM set</li>
679 <li>(S/D)CIDX = (Addr of First array in next frame) minus (Addr of First array of present frame)</li>
680 </ol>
681 </li>
682 </ul>
683 <dl class="note"><dt><b>Note:</b></dt><dd>ABC sync transfers can be achieved logically by chaining multiple AB sync transfers </dd></dl>
684 <dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
685 <tr><td valign="top"><em><a class="anchor" id="gga1cc0705e142298a424a312034bd3b2c2a9466936ba82ec52a8177b725de56db3a"></a><!-- doxytag: member="EDMA3_DRV_SYNC_A" ref="gga1cc0705e142298a424a312034bd3b2c2a9466936ba82ec52a8177b725de56db3a" args="" -->EDMA3_DRV_SYNC_A</em> </td><td>
686 <p>A-synchronized. Each event triggers the transfer of a single array of ACNT bytes </p>
687 </td></tr>
688 <tr><td valign="top"><em><a class="anchor" id="gga1cc0705e142298a424a312034bd3b2c2a2f29eabc70ef33ba7f9a93d0d0c1215b"></a><!-- doxytag: member="EDMA3_DRV_SYNC_AB" ref="gga1cc0705e142298a424a312034bd3b2c2a2f29eabc70ef33ba7f9a93d0d0c1215b" args="" -->EDMA3_DRV_SYNC_AB</em> </td><td>
689 <p>AB-synchronized. Each event triggers the transfer of BCNT arrays of ACNT bytes </p>
690 </td></tr>
691 </table>
692 </dd>
693 </dl>
695 </div>
696 </div>
697 <a class="anchor" id="ga99452326904fbebfaaca597d7be30c80"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_StaticMode" ref="ga99452326904fbebfaaca597d7be30c80" args="" -->
698 <div class="memitem">
699 <div class="memproto">
700 <table class="memname">
701 <tr>
702 <td class="memname">enum <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga99452326904fbebfaaca597d7be30c80">EDMA3_DRV_StaticMode</a></td>
703 </tr>
704 </table>
705 </div>
706 <div class="memdoc">
708 <p>True/False: PaRAM set is Static or not. A Static PaRAM set is updated or linked after TR is submitted. </p>
709 <dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
710 <tr><td valign="top"><em><a class="anchor" id="gga99452326904fbebfaaca597d7be30c80a428dccaa64904312a71645116a1ce544"></a><!-- doxytag: member="EDMA3_DRV_STATIC_DIS" ref="gga99452326904fbebfaaca597d7be30c80a428dccaa64904312a71645116a1ce544" args="" -->EDMA3_DRV_STATIC_DIS</em> </td><td>
711 <p>PaRAM set is not Static. PaRAM set is updated or linked after TR is submitted. A value of 0 should be used for DMA channels and for nonfinal transfers in a linked list of QDMA transfers </p>
712 </td></tr>
713 <tr><td valign="top"><em><a class="anchor" id="gga99452326904fbebfaaca597d7be30c80af9845bfc4f20e338a4c463c6aead3a1f"></a><!-- doxytag: member="EDMA3_DRV_STATIC_EN" ref="gga99452326904fbebfaaca597d7be30c80af9845bfc4f20e338a4c463c6aead3a1f" args="" -->EDMA3_DRV_STATIC_EN</em> </td><td>
714 <p>PaRAM set is Static. PaRAM set is not updated or linked after TR is submitted. A value of 1 should be used for isolated QDMA transfers or for the final transfer in a linked list of QDMA transfers. </p>
715 </td></tr>
716 </table>
717 </dd>
718 </dl>
720 </div>
721 </div>
722 <a class="anchor" id="ga8c37673293432ed46f9e26f04f5681dc"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_FifoWidth" ref="ga8c37673293432ed46f9e26f04f5681dc" args="" -->
723 <div class="memitem">
724 <div class="memproto">
725 <table class="memname">
726 <tr>
727 <td class="memname">enum <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8c37673293432ed46f9e26f04f5681dc">EDMA3_DRV_FifoWidth</a></td>
728 </tr>
729 </table>
730 </div>
731 <div class="memdoc">
733 <p>EDMA3 FIFO width. </p>
734 <p>The user can set the width of the FIFO using this enum. This is done via the OPT register. This is valid only if the EDMA3_DRV_ADDR_MODE_FIFO value is used for the enum EDMA3_DRV_AddrMode. </p>
735 <dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
736 <tr><td valign="top"><em><a class="anchor" id="gga8c37673293432ed46f9e26f04f5681dcad157735d8521fee719f2ca986777da0b"></a><!-- doxytag: member="EDMA3_DRV_W8BIT" ref="gga8c37673293432ed46f9e26f04f5681dcad157735d8521fee719f2ca986777da0b" args="" -->EDMA3_DRV_W8BIT</em> </td><td>
737 <p>FIFO width is 8-bit. </p>
738 </td></tr>
739 <tr><td valign="top"><em><a class="anchor" id="gga8c37673293432ed46f9e26f04f5681dca4c7d71dbae74a8fcbfa175ec12372bf8"></a><!-- doxytag: member="EDMA3_DRV_W16BIT" ref="gga8c37673293432ed46f9e26f04f5681dca4c7d71dbae74a8fcbfa175ec12372bf8" args="" -->EDMA3_DRV_W16BIT</em> </td><td>
740 <p>FIFO width is 16-bit. </p>
741 </td></tr>
742 <tr><td valign="top"><em><a class="anchor" id="gga8c37673293432ed46f9e26f04f5681dcad1eaf7a2e98ccf591f6bba89160857d8"></a><!-- doxytag: member="EDMA3_DRV_W32BIT" ref="gga8c37673293432ed46f9e26f04f5681dcad1eaf7a2e98ccf591f6bba89160857d8" args="" -->EDMA3_DRV_W32BIT</em> </td><td>
743 <p>FIFO width is 32-bit. </p>
744 </td></tr>
745 <tr><td valign="top"><em><a class="anchor" id="gga8c37673293432ed46f9e26f04f5681dcaa5b92871ecada67f067ad5d76d2ae887"></a><!-- doxytag: member="EDMA3_DRV_W64BIT" ref="gga8c37673293432ed46f9e26f04f5681dcaa5b92871ecada67f067ad5d76d2ae887" args="" -->EDMA3_DRV_W64BIT</em> </td><td>
746 <p>FIFO width is 64-bit. </p>
747 </td></tr>
748 <tr><td valign="top"><em><a class="anchor" id="gga8c37673293432ed46f9e26f04f5681dca6182f4ed18ba89d22c6be0f8ea91f392"></a><!-- doxytag: member="EDMA3_DRV_W128BIT" ref="gga8c37673293432ed46f9e26f04f5681dca6182f4ed18ba89d22c6be0f8ea91f392" args="" -->EDMA3_DRV_W128BIT</em> </td><td>
749 <p>FIFO width is 128-bit. </p>
750 </td></tr>
751 <tr><td valign="top"><em><a class="anchor" id="gga8c37673293432ed46f9e26f04f5681dca28cdc27a7907130b42d56be0ef4368dc"></a><!-- doxytag: member="EDMA3_DRV_W256BIT" ref="gga8c37673293432ed46f9e26f04f5681dca28cdc27a7907130b42d56be0ef4368dc" args="" -->EDMA3_DRV_W256BIT</em> </td><td>
752 <p>FIFO width is 256-bit. </p>
753 </td></tr>
754 </table>
755 </dd>
756 </dl>
758 </div>
759 </div>
760 <a class="anchor" id="ga17890a22b88466fbd0a14258aa1d0e9c"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_TccMode" ref="ga17890a22b88466fbd0a14258aa1d0e9c" args="" -->
761 <div class="memitem">
762 <div class="memproto">
763 <table class="memname">
764 <tr>
765 <td class="memname">enum <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga17890a22b88466fbd0a14258aa1d0e9c">EDMA3_DRV_TccMode</a></td>
766 </tr>
767 </table>
768 </div>
769 <div class="memdoc">
771 <p>Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation. </p>
772 <dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
773 <tr><td valign="top"><em><a class="anchor" id="gga17890a22b88466fbd0a14258aa1d0e9ca686d71e31f3fe47f64e41a47c2212882"></a><!-- doxytag: member="EDMA3_DRV_TCCMODE_NORMAL" ref="gga17890a22b88466fbd0a14258aa1d0e9ca686d71e31f3fe47f64e41a47c2212882" args="" -->EDMA3_DRV_TCCMODE_NORMAL</em> </td><td>
774 <p>A transfer is considered completed after transfer of data </p>
775 </td></tr>
776 <tr><td valign="top"><em><a class="anchor" id="gga17890a22b88466fbd0a14258aa1d0e9ca8d6a8086b0f466c688ad3ae3adef070b"></a><!-- doxytag: member="EDMA3_DRV_TCCMODE_EARLY" ref="gga17890a22b88466fbd0a14258aa1d0e9ca8d6a8086b0f466c688ad3ae3adef070b" args="" -->EDMA3_DRV_TCCMODE_EARLY</em> </td><td>
777 <p>A transfer is considered completed after the EDMA3CC submits a TR to the EDMA3TC. TC may still be transferring data when interrupt/chain is triggered. </p>
778 </td></tr>
779 </table>
780 </dd>
781 </dl>
783 </div>
784 </div>
785 <a class="anchor" id="ga17af0bbf00a59ea1ac3352098fe44a89"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_TcintEn" ref="ga17af0bbf00a59ea1ac3352098fe44a89" args="" -->
786 <div class="memitem">
787 <div class="memproto">
788 <table class="memname">
789 <tr>
790 <td class="memname">enum <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga17af0bbf00a59ea1ac3352098fe44a89">EDMA3_DRV_TcintEn</a></td>
791 </tr>
792 </table>
793 </div>
794 <div class="memdoc">
796 <p>Transfer complete interrupt enable. </p>
797 <dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
798 <tr><td valign="top"><em><a class="anchor" id="gga17af0bbf00a59ea1ac3352098fe44a89a73ea2b6eec1b241028ca166be468c84b"></a><!-- doxytag: member="EDMA3_DRV_TCINTEN_DIS" ref="gga17af0bbf00a59ea1ac3352098fe44a89a73ea2b6eec1b241028ca166be468c84b" args="" -->EDMA3_DRV_TCINTEN_DIS</em> </td><td>
799 <p>Transfer complete interrupt is disabled </p>
800 </td></tr>
801 <tr><td valign="top"><em><a class="anchor" id="gga17af0bbf00a59ea1ac3352098fe44a89addd5cb442f49c6d3309e88a10ce15be3"></a><!-- doxytag: member="EDMA3_DRV_TCINTEN_EN" ref="gga17af0bbf00a59ea1ac3352098fe44a89addd5cb442f49c6d3309e88a10ce15be3" args="" -->EDMA3_DRV_TCINTEN_EN</em> </td><td>
802 <p>Transfer complete interrupt is enabled. When enabled, the interrupt pending register (IPR/IPRH) bit is set on transfer completion (upon completion of the final TR in the PaRAM set). The bit (position) set in IPR or IPRH is the TCC value specified. In order to generate a completion interrupt to the CPU, the corresponding IER [TCC] / IERH [TCC] bit must be set to 1. </p>
803 </td></tr>
804 </table>
805 </dd>
806 </dl>
808 </div>
809 </div>
810 <a class="anchor" id="ga58a32aad3b685509b9f74f63ec2b9d94"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_ItcintEn" ref="ga58a32aad3b685509b9f74f63ec2b9d94" args="" -->
811 <div class="memitem">
812 <div class="memproto">
813 <table class="memname">
814 <tr>
815 <td class="memname">enum <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga58a32aad3b685509b9f74f63ec2b9d94">EDMA3_DRV_ItcintEn</a></td>
816 </tr>
817 </table>
818 </div>
819 <div class="memdoc">
821 <p>Intermediate Transfer complete interrupt enable. </p>
822 <dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
823 <tr><td valign="top"><em><a class="anchor" id="gga58a32aad3b685509b9f74f63ec2b9d94a943e78d910f2085bd416b590fbad0dbe"></a><!-- doxytag: member="EDMA3_DRV_ITCINTEN_DIS" ref="gga58a32aad3b685509b9f74f63ec2b9d94a943e78d910f2085bd416b590fbad0dbe" args="" -->EDMA3_DRV_ITCINTEN_DIS</em> </td><td>
824 <p>Intermediate Transfer complete interrupt is disabled </p>
825 </td></tr>
826 <tr><td valign="top"><em><a class="anchor" id="gga58a32aad3b685509b9f74f63ec2b9d94a71e67e98224a3ee95e61f70e62a4f834"></a><!-- doxytag: member="EDMA3_DRV_ITCINTEN_EN" ref="gga58a32aad3b685509b9f74f63ec2b9d94a71e67e98224a3ee95e61f70e62a4f834" args="" -->EDMA3_DRV_ITCINTEN_EN</em> </td><td>
827 <p>Intermediate transfer complete interrupt is enabled. When enabled, the interrupt pending register (IPR/IPRH) bit is set on every intermediate transfer completion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the PaRAM set). The bit (position) set in IPR or IPRH is the TCC value specified. In order to generate a completion interrupt to the CPU, the corresponding IER [TCC] / IERH [TCC] bit must be set to 1. </p>
828 </td></tr>
829 </table>
830 </dd>
831 </dl>
833 </div>
834 </div>
835 <a class="anchor" id="ga9904b897549665b3cfacce106fa47d54"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_TcchEn" ref="ga9904b897549665b3cfacce106fa47d54" args="" -->
836 <div class="memitem">
837 <div class="memproto">
838 <table class="memname">
839 <tr>
840 <td class="memname">enum <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9904b897549665b3cfacce106fa47d54">EDMA3_DRV_TcchEn</a></td>
841 </tr>
842 </table>
843 </div>
844 <div class="memdoc">
846 <p>Transfer complete chaining enable. </p>
847 <dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
848 <tr><td valign="top"><em><a class="anchor" id="gga9904b897549665b3cfacce106fa47d54a6c1914663e61e8904dc24d03535d0daf"></a><!-- doxytag: member="EDMA3_DRV_TCCHEN_DIS" ref="gga9904b897549665b3cfacce106fa47d54a6c1914663e61e8904dc24d03535d0daf" args="" -->EDMA3_DRV_TCCHEN_DIS</em> </td><td>
849 <p>Transfer complete chaining is disabled </p>
850 </td></tr>
851 <tr><td valign="top"><em><a class="anchor" id="gga9904b897549665b3cfacce106fa47d54a40b66d814cdf1a555d445d8dee4aeedb"></a><!-- doxytag: member="EDMA3_DRV_TCCHEN_EN" ref="gga9904b897549665b3cfacce106fa47d54a40b66d814cdf1a555d445d8dee4aeedb" args="" -->EDMA3_DRV_TCCHEN_EN</em> </td><td>
852 <p>Transfer complete chaining is enabled. When enabled, the chained event register (CER/CERH) bit is set on final chained transfer completion (upon completion of the final / last TR in the PaRAM set). The bit (position) set in CER or CERH is the TCC value specified. </p>
853 </td></tr>
854 </table>
855 </dd>
856 </dl>
858 </div>
859 </div>
860 <a class="anchor" id="gaf310b7fc131330276a0757054987c4d4"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_ItcchEn" ref="gaf310b7fc131330276a0757054987c4d4" args="" -->
861 <div class="memitem">
862 <div class="memproto">
863 <table class="memname">
864 <tr>
865 <td class="memname">enum <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gaf310b7fc131330276a0757054987c4d4">EDMA3_DRV_ItcchEn</a></td>
866 </tr>
867 </table>
868 </div>
869 <div class="memdoc">
871 <p>Intermediate Transfer complete chaining enable. </p>
872 <dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
873 <tr><td valign="top"><em><a class="anchor" id="ggaf310b7fc131330276a0757054987c4d4af4b23933674163b5cbda9c89e27c280a"></a><!-- doxytag: member="EDMA3_DRV_ITCCHEN_DIS" ref="ggaf310b7fc131330276a0757054987c4d4af4b23933674163b5cbda9c89e27c280a" args="" -->EDMA3_DRV_ITCCHEN_DIS</em> </td><td>
874 <p>Intermediate Transfer complete chaining is disabled </p>
875 </td></tr>
876 <tr><td valign="top"><em><a class="anchor" id="ggaf310b7fc131330276a0757054987c4d4acef8781cbeac3dadce5de47c603566e9"></a><!-- doxytag: member="EDMA3_DRV_ITCCHEN_EN" ref="ggaf310b7fc131330276a0757054987c4d4acef8781cbeac3dadce5de47c603566e9" args="" -->EDMA3_DRV_ITCCHEN_EN</em> </td><td>
877 <p>Intermediate transfer complete chaining is enabled. When enabled, the chained event register (CER/CERH) bit is set on every intermediate chained transfer completion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the PaRAM set). The bit (position) set in CER or CERH is the TCC value specified. </p>
878 </td></tr>
879 </table>
880 </dd>
881 </dl>
883 </div>
884 </div>
885 <a class="anchor" id="ga9a3d4fdcf4d2d089d4defebe3ef3880e"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_TrigMode" ref="ga9a3d4fdcf4d2d089d4defebe3ef3880e" args="" -->
886 <div class="memitem">
887 <div class="memproto">
888 <table class="memname">
889 <tr>
890 <td class="memname">enum <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a></td>
891 </tr>
892 </table>
893 </div>
894 <div class="memdoc">
896 <p>EDMA Trigger Mode Selection. </p>
897 <p>Use this enum to select the EDMA trigger mode while enabling the EDMA transfer </p>
898 <dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
899 <tr><td valign="top"><em><a class="anchor" id="gga9a3d4fdcf4d2d089d4defebe3ef3880ea1ec2aa1fb8ed48534aa4190622792ea6"></a><!-- doxytag: member="EDMA3_DRV_TRIG_MODE_MANUAL" ref="gga9a3d4fdcf4d2d089d4defebe3ef3880ea1ec2aa1fb8ed48534aa4190622792ea6" args="" -->EDMA3_DRV_TRIG_MODE_MANUAL</em> </td><td>
900 <p>Set the Trigger mode to Manual . The CPU manually triggers a transfer by writing a 1 to the corresponding bit in the event set register (ESR/ESRH). </p>
901 </td></tr>
902 <tr><td valign="top"><em><a class="anchor" id="gga9a3d4fdcf4d2d089d4defebe3ef3880ea7cbf536d24f7cb45fcaadc46ebf229ad"></a><!-- doxytag: member="EDMA3_DRV_TRIG_MODE_QDMA" ref="gga9a3d4fdcf4d2d089d4defebe3ef3880ea7cbf536d24f7cb45fcaadc46ebf229ad" args="" -->EDMA3_DRV_TRIG_MODE_QDMA</em> </td><td>
903 <p>Set the Trigger mode to QDMA. A QDMA transfer is triggered when a CPU (or other EDMA3 programmer) writes to the trigger word of the QDMA channel parameter set (autotriggered) or when the EDMA3CC performs a link update on a PaRAM set that has been mapped to a QDMA channel (link triggered). </p>
904 </td></tr>
905 <tr><td valign="top"><em><a class="anchor" id="gga9a3d4fdcf4d2d089d4defebe3ef3880ea34671e10c511d857963484c4712d322d"></a><!-- doxytag: member="EDMA3_DRV_TRIG_MODE_EVENT" ref="gga9a3d4fdcf4d2d089d4defebe3ef3880ea34671e10c511d857963484c4712d322d" args="" -->EDMA3_DRV_TRIG_MODE_EVENT</em> </td><td>
906 <p>Set the Trigger mode to Event. Allows for a peripheral, system, or externally-generated event to trigger a transfer request. </p>
907 </td></tr>
908 <tr><td valign="top"><em><a class="anchor" id="gga9a3d4fdcf4d2d089d4defebe3ef3880ea45338caea71cdf45250e863c5fe4ed8d"></a><!-- doxytag: member="EDMA3_DRV_TRIG_MODE_NONE" ref="gga9a3d4fdcf4d2d089d4defebe3ef3880ea45338caea71cdf45250e863c5fe4ed8d" args="" -->EDMA3_DRV_TRIG_MODE_NONE</em> </td><td>
909 <p>Used to specify the trigger mode NONE </p>
910 </td></tr>
911 </table>
912 </dd>
913 </dl>
915 </div>
916 </div>
917 <a class="anchor" id="ga82b01ec2292a13ad48a5bfcc724dfac6"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_PaRAMEntry" ref="ga82b01ec2292a13ad48a5bfcc724dfac6" args="" -->
918 <div class="memitem">
919 <div class="memproto">
920 <table class="memname">
921 <tr>
922 <td class="memname">enum <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga82b01ec2292a13ad48a5bfcc724dfac6">EDMA3_DRV_PaRAMEntry</a></td>
923 </tr>
924 </table>
925 </div>
926 <div class="memdoc">
928 <p>PaRAM Set Entry type. </p>
929 <p>Use this enum to set or get any of the 8 DWords(uint32_t) within a Parameter RAM set </p>
930 <dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
931 <tr><td valign="top"><em><a class="anchor" id="gga82b01ec2292a13ad48a5bfcc724dfac6a5cb3c2eda075435c8f48ef685a28971b"></a><!-- doxytag: member="EDMA3_DRV_PARAM_ENTRY_OPT" ref="gga82b01ec2292a13ad48a5bfcc724dfac6a5cb3c2eda075435c8f48ef685a28971b" args="" -->EDMA3_DRV_PARAM_ENTRY_OPT</em> </td><td>
932 <p>The OPT field (Offset Address 0x0 Bytes) </p>
933 </td></tr>
934 <tr><td valign="top"><em><a class="anchor" id="gga82b01ec2292a13ad48a5bfcc724dfac6a08d5dcf368b15427e1b63023be97c699"></a><!-- doxytag: member="EDMA3_DRV_PARAM_ENTRY_SRC" ref="gga82b01ec2292a13ad48a5bfcc724dfac6a08d5dcf368b15427e1b63023be97c699" args="" -->EDMA3_DRV_PARAM_ENTRY_SRC</em> </td><td>
935 <p>The SRC field (Offset Address 0x4 Bytes) </p>
936 </td></tr>
937 <tr><td valign="top"><em><a class="anchor" id="gga82b01ec2292a13ad48a5bfcc724dfac6a80beff4474df6d7a8d217d86bd0faac9"></a><!-- doxytag: member="EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT" ref="gga82b01ec2292a13ad48a5bfcc724dfac6a80beff4474df6d7a8d217d86bd0faac9" args="" -->EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT</em> </td><td>
938 <p>The (ACNT+BCNT) field (Offset Address 0x8 Bytes) </p>
939 </td></tr>
940 <tr><td valign="top"><em><a class="anchor" id="gga82b01ec2292a13ad48a5bfcc724dfac6a74640bb1fe574606fb7a0266e32c43fb"></a><!-- doxytag: member="EDMA3_DRV_PARAM_ENTRY_DST" ref="gga82b01ec2292a13ad48a5bfcc724dfac6a74640bb1fe574606fb7a0266e32c43fb" args="" -->EDMA3_DRV_PARAM_ENTRY_DST</em> </td><td>
941 <p>The DST field (Offset Address 0xC Bytes) </p>
942 </td></tr>
943 <tr><td valign="top"><em><a class="anchor" id="gga82b01ec2292a13ad48a5bfcc724dfac6ad644f9995a90ea8a52c8c25a84550c64"></a><!-- doxytag: member="EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX" ref="gga82b01ec2292a13ad48a5bfcc724dfac6ad644f9995a90ea8a52c8c25a84550c64" args="" -->EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX</em> </td><td>
944 <p>The (SRCBIDX+DSTBIDX) field (Offset Address 0x10 Bytes) </p>
945 </td></tr>
946 <tr><td valign="top"><em><a class="anchor" id="gga82b01ec2292a13ad48a5bfcc724dfac6a360b634a41639c9f7ce60f402d346393"></a><!-- doxytag: member="EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD" ref="gga82b01ec2292a13ad48a5bfcc724dfac6a360b634a41639c9f7ce60f402d346393" args="" -->EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD</em> </td><td>
947 <p>The (LINK+BCNTRLD) field (Offset Address 0x14 Bytes) </p>
948 </td></tr>
949 <tr><td valign="top"><em><a class="anchor" id="gga82b01ec2292a13ad48a5bfcc724dfac6a03c6fd4b46aec54aee8f21ba515ff35b"></a><!-- doxytag: member="EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX" ref="gga82b01ec2292a13ad48a5bfcc724dfac6a03c6fd4b46aec54aee8f21ba515ff35b" args="" -->EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX</em> </td><td>
950 <p>The (SRCCIDX+DSTCIDX) field (Offset Address 0x18 Bytes) </p>
951 </td></tr>
952 <tr><td valign="top"><em><a class="anchor" id="gga82b01ec2292a13ad48a5bfcc724dfac6ae4ef2bad3f40788bfd46f198e646d3be"></a><!-- doxytag: member="EDMA3_DRV_PARAM_ENTRY_CCNT" ref="gga82b01ec2292a13ad48a5bfcc724dfac6ae4ef2bad3f40788bfd46f198e646d3be" args="" -->EDMA3_DRV_PARAM_ENTRY_CCNT</em> </td><td>
953 <p>The (CCNT+RSVD) field (Offset Address 0x1C Bytes) </p>
954 </td></tr>
955 </table>
956 </dd>
957 </dl>
959 </div>
960 </div>
961 <a class="anchor" id="ga3e31ba1b02dcbace3044c11c83ef5466"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_PaRAMField" ref="ga3e31ba1b02dcbace3044c11c83ef5466" args="" -->
962 <div class="memitem">
963 <div class="memproto">
964 <table class="memname">
965 <tr>
966 <td class="memname">enum <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga3e31ba1b02dcbace3044c11c83ef5466">EDMA3_DRV_PaRAMField</a></td>
967 </tr>
968 </table>
969 </div>
970 <div class="memdoc">
972 <p>PaRAM Set Field type. </p>
973 <p>Use this enum to set or get any of the PaRAM set fields </p>
974 <dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
975 <tr><td valign="top"><em><a class="anchor" id="gga3e31ba1b02dcbace3044c11c83ef5466a4e5f6bbfb68c8a5981b321ea2c96400f"></a><!-- doxytag: member="EDMA3_DRV_PARAM_FIELD_OPT" ref="gga3e31ba1b02dcbace3044c11c83ef5466a4e5f6bbfb68c8a5981b321ea2c96400f" args="" -->EDMA3_DRV_PARAM_FIELD_OPT</em> </td><td>
976 <p>OPT field of PaRAM Set </p>
977 </td></tr>
978 <tr><td valign="top"><em><a class="anchor" id="gga3e31ba1b02dcbace3044c11c83ef5466ace688d06479875eed547e49c7c53a7dd"></a><!-- doxytag: member="EDMA3_DRV_PARAM_FIELD_SRCADDR" ref="gga3e31ba1b02dcbace3044c11c83ef5466ace688d06479875eed547e49c7c53a7dd" args="" -->EDMA3_DRV_PARAM_FIELD_SRCADDR</em> </td><td>
979 <p>Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address. </p>
980 </td></tr>
981 <tr><td valign="top"><em><a class="anchor" id="gga3e31ba1b02dcbace3044c11c83ef5466a331bd6b991f25211c9e330dca0df0f9c"></a><!-- doxytag: member="EDMA3_DRV_PARAM_FIELD_ACNT" ref="gga3e31ba1b02dcbace3044c11c83ef5466a331bd6b991f25211c9e330dca0df0f9c" args="" -->EDMA3_DRV_PARAM_FIELD_ACNT</em> </td><td>
982 <p>Number of bytes in each Array (ACNT). </p>
983 </td></tr>
984 <tr><td valign="top"><em><a class="anchor" id="gga3e31ba1b02dcbace3044c11c83ef5466a6b1fa5f67bb599bcb53511d709f4b0b4"></a><!-- doxytag: member="EDMA3_DRV_PARAM_FIELD_BCNT" ref="gga3e31ba1b02dcbace3044c11c83ef5466a6b1fa5f67bb599bcb53511d709f4b0b4" args="" -->EDMA3_DRV_PARAM_FIELD_BCNT</em> </td><td>
985 <p>Number of Arrays in each Frame (BCNT). </p>
986 </td></tr>
987 <tr><td valign="top"><em><a class="anchor" id="gga3e31ba1b02dcbace3044c11c83ef5466aac116996738f643163f45ae1472aa84b"></a><!-- doxytag: member="EDMA3_DRV_PARAM_FIELD_DESTADDR" ref="gga3e31ba1b02dcbace3044c11c83ef5466aac116996738f643163f45ae1472aa84b" args="" -->EDMA3_DRV_PARAM_FIELD_DESTADDR</em> </td><td>
988 <p>Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. </p>
989 </td></tr>
990 <tr><td valign="top"><em><a class="anchor" id="gga3e31ba1b02dcbace3044c11c83ef5466a60a6dbf01d64675758281d3ac8d30791"></a><!-- doxytag: member="EDMA3_DRV_PARAM_FIELD_SRCBIDX" ref="gga3e31ba1b02dcbace3044c11c83ef5466a60a6dbf01d64675758281d3ac8d30791" args="" -->EDMA3_DRV_PARAM_FIELD_SRCBIDX</em> </td><td>
991 <p>Index between consec. arrays of a Source Frame (SRCBIDX) If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes. </p>
992 </td></tr>
993 <tr><td valign="top"><em><a class="anchor" id="gga3e31ba1b02dcbace3044c11c83ef5466ae1e0807fd4f93c272585e417136ece9d"></a><!-- doxytag: member="EDMA3_DRV_PARAM_FIELD_DESTBIDX" ref="gga3e31ba1b02dcbace3044c11c83ef5466ae1e0807fd4f93c272585e417136ece9d" args="" -->EDMA3_DRV_PARAM_FIELD_DESTBIDX</em> </td><td>
994 <p>Index between consec. arrays of a Destination Frame (DSTBIDX) If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes. </p>
995 </td></tr>
996 <tr><td valign="top"><em><a class="anchor" id="gga3e31ba1b02dcbace3044c11c83ef5466a99f25744315b46aa4de1e11011f9d334"></a><!-- doxytag: member="EDMA3_DRV_PARAM_FIELD_LINKADDR" ref="gga3e31ba1b02dcbace3044c11c83ef5466a99f25744315b46aa4de1e11011f9d334" args="" -->EDMA3_DRV_PARAM_FIELD_LINKADDR</em> </td><td>
997 <p>Address for linking (AutoReloading of a PaRAM Set) This must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking Linking is especially useful for use with ping-pong buffers and circular buffers. </p>
998 </td></tr>
999 <tr><td valign="top"><em><a class="anchor" id="gga3e31ba1b02dcbace3044c11c83ef5466a10933409050bda13b4650123a9fed111"></a><!-- doxytag: member="EDMA3_DRV_PARAM_FIELD_BCNTRELOAD" ref="gga3e31ba1b02dcbace3044c11c83ef5466a10933409050bda13b4650123a9fed111" args="" -->EDMA3_DRV_PARAM_FIELD_BCNTRELOAD</em> </td><td>
1000 <p>Reload value of the numArrInFrame (BCNT) Relevant only for A-sync transfers. </p>
1001 </td></tr>
1002 <tr><td valign="top"><em><a class="anchor" id="gga3e31ba1b02dcbace3044c11c83ef5466a01814312c8c7dd46d18c3d315fad737f"></a><!-- doxytag: member="EDMA3_DRV_PARAM_FIELD_SRCCIDX" ref="gga3e31ba1b02dcbace3044c11c83ef5466a01814312c8c7dd46d18c3d315fad737f" args="" -->EDMA3_DRV_PARAM_FIELD_SRCCIDX</em> </td><td>
1003 <p>Index between consecutive frames of a Source Block (SRCCIDX). </p>
1004 </td></tr>
1005 <tr><td valign="top"><em><a class="anchor" id="gga3e31ba1b02dcbace3044c11c83ef5466a4be8857b84549ceb9ae2f533f8db3923"></a><!-- doxytag: member="EDMA3_DRV_PARAM_FIELD_DESTCIDX" ref="gga3e31ba1b02dcbace3044c11c83ef5466a4be8857b84549ceb9ae2f533f8db3923" args="" -->EDMA3_DRV_PARAM_FIELD_DESTCIDX</em> </td><td>
1006 <p>Index between consecutive frames of a Dest Block (DSTCIDX). </p>
1007 </td></tr>
1008 <tr><td valign="top"><em><a class="anchor" id="gga3e31ba1b02dcbace3044c11c83ef5466affd4ae69a7feb876b6b4aa40d5099017"></a><!-- doxytag: member="EDMA3_DRV_PARAM_FIELD_CCNT" ref="gga3e31ba1b02dcbace3044c11c83ef5466affd4ae69a7feb876b6b4aa40d5099017" args="" -->EDMA3_DRV_PARAM_FIELD_CCNT</em> </td><td>
1009 <p>Number of Frames in a block (CCNT). </p>
1010 </td></tr>
1011 </table>
1012 </dd>
1013 </dl>
1015 </div>
1016 </div>
1017 <a class="anchor" id="ga8577940463f7ca5a8977b2fb65fae19a"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_IoctlCmd" ref="ga8577940463f7ca5a8977b2fb65fae19a" args="" -->
1018 <div class="memitem">
1019 <div class="memproto">
1020 <table class="memname">
1021 <tr>
1022 <td class="memname">enum <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8577940463f7ca5a8977b2fb65fae19a">EDMA3_DRV_IoctlCmd</a></td>
1023 </tr>
1024 </table>
1025 </div>
1026 <div class="memdoc">
1028 <p>EDMA3 Driver IOCTL commands. </p>
1029 <dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
1030 <tr><td valign="top"><em><a class="anchor" id="gga8577940463f7ca5a8977b2fb65fae19aac79f621f036d0e97746c5776ccc18a2e"></a><!-- doxytag: member="EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION" ref="gga8577940463f7ca5a8977b2fb65fae19aac79f621f036d0e97746c5776ccc18a2e" args="" -->EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION</em> </td><td>
1031 <p>PaRAM Sets will be cleared OR will not be cleared during allocation, depending upon this option.</p>
1032 <p>For e.g., To clear the PaRAM Sets during allocation, cmdArg = (void *)1;</p>
1033 <p>To NOT clear the PaRAM Sets during allocation, cmdArg = (void *)0;</p>
1034 <p>For all other values, it will return error.</p>
1035 <p>By default, PaRAM Sets will be cleared during allocation. Note: Since this enum can change the behavior how the resources are initialized during their allocation, user is adviced to not use this command while allocating the resources. User should first change the behavior of resources' initialization and then should use start allocating resources. </p>
1036 </td></tr>
1037 <tr><td valign="top"><em><a class="anchor" id="gga8577940463f7ca5a8977b2fb65fae19aa9ef62634a561e221c136e62de9694f48"></a><!-- doxytag: member="EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION" ref="gga8577940463f7ca5a8977b2fb65fae19aa9ef62634a561e221c136e62de9694f48" args="" -->EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION</em> </td><td>
1038 <p>To check whether PaRAM Sets will be cleared or not during allocation. If the value read is '1', it means that PaRAM Sets are getting cleared during allocation. If the value read is '0', it means that PaRAM Sets are NOT getting cleared during allocation. For e.g., uint16_t isParamClearingDone; cmdArg = </p>
1039 </td></tr>
1040 </table>
1041 </dd>
1042 </dl>
1044 </div>
1045 </div>
1046 <a class="anchor" id="ga2b3b55b1d7c987a7873d8b0b085173b2"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_Tc_Err" ref="ga2b3b55b1d7c987a7873d8b0b085173b2" args="" -->
1047 <div class="memitem">
1048 <div class="memproto">
1049 <table class="memname">
1050 <tr>
1051 <td class="memname">enum <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga2b3b55b1d7c987a7873d8b0b085173b2">EDMA3_DRV_Tc_Err</a></td>
1052 </tr>
1053 </table>
1054 </div>
1055 <div class="memdoc">
1057 <p>TC Error Enablers. </p>
1058 <p>Use this enum to enable/disable the specific EDMA3 Transfer Controller Interrupts. </p>
1059 <dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
1060 <tr><td valign="top"><em><a class="anchor" id="gga2b3b55b1d7c987a7873d8b0b085173b2a110f0b3a441d3cc8eddde87e1ef22de9"></a><!-- doxytag: member="EDMA3_DRV_TC_ERR_BUSERR_DIS" ref="gga2b3b55b1d7c987a7873d8b0b085173b2a110f0b3a441d3cc8eddde87e1ef22de9" args="" -->EDMA3_DRV_TC_ERR_BUSERR_DIS</em> </td><td>
1061 <p>Interrupt disable for bus error </p>
1062 </td></tr>
1063 <tr><td valign="top"><em><a class="anchor" id="gga2b3b55b1d7c987a7873d8b0b085173b2a92df5a4324184dfa6b910a5f326fe87e"></a><!-- doxytag: member="EDMA3_DRV_TC_ERR_BUSERR_EN" ref="gga2b3b55b1d7c987a7873d8b0b085173b2a92df5a4324184dfa6b910a5f326fe87e" args="" -->EDMA3_DRV_TC_ERR_BUSERR_EN</em> </td><td>
1064 <p>Interrupt enable for bus error </p>
1065 </td></tr>
1066 <tr><td valign="top"><em><a class="anchor" id="gga2b3b55b1d7c987a7873d8b0b085173b2a087691858a676ef6db124941660ff976"></a><!-- doxytag: member="EDMA3_DRV_TC_ERR_TRERR_DIS" ref="gga2b3b55b1d7c987a7873d8b0b085173b2a087691858a676ef6db124941660ff976" args="" -->EDMA3_DRV_TC_ERR_TRERR_DIS</em> </td><td>
1067 <p>Interrupt disable for transfer request error </p>
1068 </td></tr>
1069 <tr><td valign="top"><em><a class="anchor" id="gga2b3b55b1d7c987a7873d8b0b085173b2a570e19187612848c18a510d1fa1ea5cc"></a><!-- doxytag: member="EDMA3_DRV_TC_ERR_TRERR_EN" ref="gga2b3b55b1d7c987a7873d8b0b085173b2a570e19187612848c18a510d1fa1ea5cc" args="" -->EDMA3_DRV_TC_ERR_TRERR_EN</em> </td><td>
1070 <p>Interrupt enable for transfer request error </p>
1071 </td></tr>
1072 <tr><td valign="top"><em><a class="anchor" id="gga2b3b55b1d7c987a7873d8b0b085173b2ac9c1819e715355de30b5905863fdf0a0"></a><!-- doxytag: member="EDMA3_DRV_TC_ERR_MMRAERR_DIS" ref="gga2b3b55b1d7c987a7873d8b0b085173b2ac9c1819e715355de30b5905863fdf0a0" args="" -->EDMA3_DRV_TC_ERR_MMRAERR_DIS</em> </td><td>
1073 <p>Interrupt disable for MMR address error </p>
1074 </td></tr>
1075 <tr><td valign="top"><em><a class="anchor" id="gga2b3b55b1d7c987a7873d8b0b085173b2af883f7b1ce601de018e3644535f72446"></a><!-- doxytag: member="EDMA3_DRV_TC_ERR_MMRAERR_EN" ref="gga2b3b55b1d7c987a7873d8b0b085173b2af883f7b1ce601de018e3644535f72446" args="" -->EDMA3_DRV_TC_ERR_MMRAERR_EN</em> </td><td>
1076 <p>Interrupt enable for MMR address error </p>
1077 </td></tr>
1078 <tr><td valign="top"><em><a class="anchor" id="gga2b3b55b1d7c987a7873d8b0b085173b2ae24b256e04df975d45269caf2325dcd7"></a><!-- doxytag: member="EDMA3_DRV_TC_ERR_DIS" ref="gga2b3b55b1d7c987a7873d8b0b085173b2ae24b256e04df975d45269caf2325dcd7" args="" -->EDMA3_DRV_TC_ERR_DIS</em> </td><td>
1079 <p>Disable all TC error interrupts </p>
1080 </td></tr>
1081 <tr><td valign="top"><em><a class="anchor" id="gga2b3b55b1d7c987a7873d8b0b085173b2acc54d0adc6465d49a94d6571cc704093"></a><!-- doxytag: member="EDMA3_DRV_TC_ERR_EN" ref="gga2b3b55b1d7c987a7873d8b0b085173b2acc54d0adc6465d49a94d6571cc704093" args="" -->EDMA3_DRV_TC_ERR_EN</em> </td><td>
1082 <p>Enable all TC error interrupts </p>
1083 </td></tr>
1084 </table>
1085 </dd>
1086 </dl>
1088 </div>
1089 </div>
1090 </div>
1091 <hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:00 2011 for EDMA3 Driver by
1092 <a href="http://www.doxygen.org/index.html">
1093 <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
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