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26 <h1>EDMA3_DRV_GblConfigParams Struct Reference<br>
27 <small>
28 [<a class="el" href="group__Edma3DrvMain.html">EDMA3 Driver Interface Definition</a>]</small>
29 </h1><!-- doxytag: class="EDMA3_DRV_GblConfigParams" -->Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information.
30 <a href="#_details">More...</a>
31 <p>
32 <code>#include <<a class="el" href="edma3__drv_8h-source.html">edma3_drv.h</a>></code>
33 <p>
34 <table border="0" cellpadding="0" cellspacing="0">
35 <tr><td></td></tr>
36 <tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
37 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#1d71e6ded1e1b3d3b14b20a11f896ce3">numDmaChannels</a></td></tr>
39 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#629d5fc8d59adc8644f5f7a2691b8230">numQdmaChannels</a></td></tr>
41 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#14c6249081e4225ea140904758377c53">numTccs</a></td></tr>
43 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#9bf9fc29152fe9ddb63bc86683149fc9">numPaRAMSets</a></td></tr>
45 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#d27e2c83868656fa72ee70a64ac3a534">numEvtQueue</a></td></tr>
47 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#8285aab9b38d6369896777f08cb8febd">numTcs</a></td></tr>
49 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#30316db491c3d5f08182dc5bdde92463">numRegions</a></td></tr>
51 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned short </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#88918a9382b64b804bb8ce972819afeb">dmaChPaRAMMapExists</a></td></tr>
53 <tr><td class="mdescLeft"> </td><td class="mdescRight">Channel mapping existence. <a href="#88918a9382b64b804bb8ce972819afeb"></a><br></td></tr>
54 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned short </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#7e5fd1b9196af0e6b35819404718923d">memProtectionExists</a></td></tr>
56 <tr><td class="memItemLeft" nowrap align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#5efff8708e94a49f71b055578549c97a">globalRegs</a></td></tr>
58 <tr><td class="memItemLeft" nowrap align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#31847b941f3a290ef68992ea3683228f">tcRegs</a> [EDMA3_MAX_TC]</td></tr>
60 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#08b4ad4be6b0cd9c6dd046dfe4f68c1e">xferCompleteInt</a></td></tr>
62 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#5f7297703c68fdb4d6e9b2a5d4750040">ccError</a></td></tr>
64 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#3fdbb69b709ecd01dc903ec47e59f5a8">tcError</a> [EDMA3_MAX_TC]</td></tr>
66 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#8970e4cce82366cef852a60cc5dc1a5a">evtQPri</a> [EDMA3_MAX_EVT_QUE]</td></tr>
68 <tr><td class="mdescLeft"> </td><td class="mdescRight">EDMA3 TC priority setting. <a href="#8970e4cce82366cef852a60cc5dc1a5a"></a><br></td></tr>
69 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#60f00b339733c6126951a688072b53b3">evtQueueWaterMarkLvl</a> [EDMA3_MAX_EVT_QUE]</td></tr>
71 <tr><td class="mdescLeft"> </td><td class="mdescRight">Event Queues Watermark Levels. <a href="#60f00b339733c6126951a688072b53b3"></a><br></td></tr>
72 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#a217c4ed918c9d5d695ee19ced91ef00">tcDefaultBurstSize</a> [EDMA3_MAX_TC]</td></tr>
74 <tr><td class="mdescLeft"> </td><td class="mdescRight">Default Burst Size (DBS) of TCs. <a href="#a217c4ed918c9d5d695ee19ced91ef00"></a><br></td></tr>
75 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#ef6b47382a74f4aabfa050f6213512d4">dmaChannelPaRAMMap</a> [EDMA3_MAX_DMA_CH]</td></tr>
77 <tr><td class="mdescLeft"> </td><td class="mdescRight">Mapping from DMA channels to PaRAM Sets. <a href="#ef6b47382a74f4aabfa050f6213512d4"></a><br></td></tr>
78 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#09dc86e6c4cbda84547c3033532e1b98">dmaChannelTccMap</a> [EDMA3_MAX_DMA_CH]</td></tr>
80 <tr><td class="mdescLeft"> </td><td class="mdescRight">Mapping from DMA channels to TCCs. <a href="#09dc86e6c4cbda84547c3033532e1b98"></a><br></td></tr>
81 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html#c205feb9fd0a3575627dbec2f95d176c">dmaChannelHwEvtMap</a> [EDMA3_MAX_DMA_CHAN_DWRDS]</td></tr>
83 <tr><td class="mdescLeft"> </td><td class="mdescRight">Mapping from DMA channels to Hardware Events. <a href="#c205feb9fd0a3575627dbec2f95d176c"></a><br></td></tr>
84 </table>
85 <hr><a name="_details"></a><h2>Detailed Description</h2>
86 Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information.
87 <p>
88 This configuration structure is used to specify the EDMA3 Driver global settings, specific to the SoC. For e.g. number of DMA/QDMA channels, number of PaRAM sets, TCCs, event queues, transfer controllers, base addresses of CC global registers and TC registers, interrupt number for EDMA3 transfer completion, CC error, event queues' priority, watermark threshold level etc. This configuration information is SoC specific and could be provided by the user at run-time while creating the EDMA3 Driver Object, using API EDMA3_DRV_create. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available. <hr><h2>Field Documentation</h2>
89 <a class="anchor" name="1d71e6ded1e1b3d3b14b20a11f896ce3"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::numDmaChannels" ref="1d71e6ded1e1b3d3b14b20a11f896ce3" args="" -->
90 <div class="memitem">
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94 <td class="memname">unsigned int <a class="el" href="structEDMA3__DRV__GblConfigParams.html#1d71e6ded1e1b3d3b14b20a11f896ce3">EDMA3_DRV_GblConfigParams::numDmaChannels</a> </td>
95 </tr>
96 </table>
97 </div>
98 <div class="memdoc">
100 <p>
101 Number of DMA Channels supported by the underlying EDMA3 Controller.
102 <p>Referenced by <a class="el" href="edma3__drv__basic_8c-source.html#l00274">EDMA3_DRV_requestChannel()</a>.</p>
104 </div>
105 </div><p>
106 <a class="anchor" name="629d5fc8d59adc8644f5f7a2691b8230"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::numQdmaChannels" ref="629d5fc8d59adc8644f5f7a2691b8230" args="" -->
107 <div class="memitem">
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111 <td class="memname">unsigned int <a class="el" href="structEDMA3__DRV__GblConfigParams.html#629d5fc8d59adc8644f5f7a2691b8230">EDMA3_DRV_GblConfigParams::numQdmaChannels</a> </td>
112 </tr>
113 </table>
114 </div>
115 <div class="memdoc">
117 <p>
118 Number of QDMA Channels supported by the underlying EDMA3 Controller
119 </div>
120 </div><p>
121 <a class="anchor" name="14c6249081e4225ea140904758377c53"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::numTccs" ref="14c6249081e4225ea140904758377c53" args="" -->
122 <div class="memitem">
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125 <tr>
126 <td class="memname">unsigned int <a class="el" href="structEDMA3__DRV__GblConfigParams.html#14c6249081e4225ea140904758377c53">EDMA3_DRV_GblConfigParams::numTccs</a> </td>
127 </tr>
128 </table>
129 </div>
130 <div class="memdoc">
132 <p>
133 Number of Interrupt Channels supported by the underlying EDMA3 Controller
134 <p>Referenced by <a class="el" href="edma3__drv__adv_8c-source.html#l02000">EDMA3_DRV_checkAndClearTcc()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l00716">EDMA3_DRV_freeChannel()</a>, and <a class="el" href="edma3__drv__adv_8c-source.html#l01870">EDMA3_DRV_waitAndClearTcc()</a>.</p>
136 </div>
137 </div><p>
138 <a class="anchor" name="9bf9fc29152fe9ddb63bc86683149fc9"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::numPaRAMSets" ref="9bf9fc29152fe9ddb63bc86683149fc9" args="" -->
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143 <td class="memname">unsigned int <a class="el" href="structEDMA3__DRV__GblConfigParams.html#9bf9fc29152fe9ddb63bc86683149fc9">EDMA3_DRV_GblConfigParams::numPaRAMSets</a> </td>
144 </tr>
145 </table>
146 </div>
147 <div class="memdoc">
149 <p>
150 Number of PaRAM Sets supported by the underlying EDMA3 Controller
151 <p>Referenced by <a class="el" href="edma3__drv__adv_8c-source.html#l00385">EDMA3_DRV_chainChannel()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l00716">EDMA3_DRV_freeChannel()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l01170">EDMA3_DRV_getOptField()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l00774">EDMA3_DRV_getPaRAM()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l00946">EDMA3_DRV_getPaRAMEntry()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l01225">EDMA3_DRV_getPaRAMField()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l02132">EDMA3_DRV_getPaRAMPhyAddr()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l00169">EDMA3_DRV_linkChannel()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l01762">EDMA3_DRV_setDestIndex()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l01466">EDMA3_DRV_setDestParams()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l01018">EDMA3_DRV_setOptField()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l00693">EDMA3_DRV_setPaRAM()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l00864">EDMA3_DRV_setPaRAMEntry()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l01038">EDMA3_DRV_setPaRAMField()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l01632">EDMA3_DRV_setSrcIndex()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l01306">EDMA3_DRV_setSrcParams()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l01918">EDMA3_DRV_setTransferParams()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l00521">EDMA3_DRV_unchainChannel()</a>, and <a class="el" href="edma3__drv__adv_8c-source.html#l00286">EDMA3_DRV_unlinkChannel()</a>.</p>
153 </div>
154 </div><p>
155 <a class="anchor" name="d27e2c83868656fa72ee70a64ac3a534"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::numEvtQueue" ref="d27e2c83868656fa72ee70a64ac3a534" args="" -->
156 <div class="memitem">
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160 <td class="memname">unsigned int <a class="el" href="structEDMA3__DRV__GblConfigParams.html#d27e2c83868656fa72ee70a64ac3a534">EDMA3_DRV_GblConfigParams::numEvtQueue</a> </td>
161 </tr>
162 </table>
163 </div>
164 <div class="memdoc">
166 <p>
167 Number of Event Queues in the underlying EDMA3 Controller
168 <p>Referenced by <a class="el" href="edma3__drv__basic_8c-source.html#l00895">EDMA3_DRV_clearErrorBits()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l01483">EDMA3_DRV_mapChToEvtQ()</a>, and <a class="el" href="edma3__drv__basic_8c-source.html#l00274">EDMA3_DRV_requestChannel()</a>.</p>
170 </div>
171 </div><p>
172 <a class="anchor" name="8285aab9b38d6369896777f08cb8febd"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::numTcs" ref="8285aab9b38d6369896777f08cb8febd" args="" -->
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176 <tr>
177 <td class="memname">unsigned int <a class="el" href="structEDMA3__DRV__GblConfigParams.html#8285aab9b38d6369896777f08cb8febd">EDMA3_DRV_GblConfigParams::numTcs</a> </td>
178 </tr>
179 </table>
180 </div>
181 <div class="memdoc">
183 <p>
184 Number of Transfer Controllers (TCs) in the underlying EDMA3 Controller
185 </div>
186 </div><p>
187 <a class="anchor" name="30316db491c3d5f08182dc5bdde92463"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::numRegions" ref="30316db491c3d5f08182dc5bdde92463" args="" -->
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192 <td class="memname">unsigned int <a class="el" href="structEDMA3__DRV__GblConfigParams.html#30316db491c3d5f08182dc5bdde92463">EDMA3_DRV_GblConfigParams::numRegions</a> </td>
193 </tr>
194 </table>
195 </div>
196 <div class="memdoc">
198 <p>
199 Number of Regions in the underlying EDMA3 Controller
200 <p>Referenced by <a class="el" href="edma3__drv__init_8c-source.html#l00182">EDMA3_DRV_create()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l02342">EDMA3_DRV_getInstHandle()</a>, and <a class="el" href="edma3__drv__init_8c-source.html#l00413">EDMA3_DRV_open()</a>.</p>
202 </div>
203 </div><p>
204 <a class="anchor" name="88918a9382b64b804bb8ce972819afeb"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::dmaChPaRAMMapExists" ref="88918a9382b64b804bb8ce972819afeb" args="" -->
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209 <td class="memname">unsigned short <a class="el" href="structEDMA3__DRV__GblConfigParams.html#88918a9382b64b804bb8ce972819afeb">EDMA3_DRV_GblConfigParams::dmaChPaRAMMapExists</a> </td>
210 </tr>
211 </table>
212 </div>
213 <div class="memdoc">
215 <p>
216 Channel mapping existence.
217 <p>
218 A value of 0 (No channel mapping) implies that there is fixed association between a DMA channel and a PaRAM Set or, in other words, DMA channel n can ONLY use PaRAM Set n (No availability of DCHMAP registers) for transfers to happen.<p>
219 A value of 1 implies the presence of DCHMAP registers for the DMA channels and hence the flexibility of associating any DMA channel to any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA channel (like QDMA Channels).
220 <p>Referenced by <a class="el" href="edma3__drv__basic_8c-source.html#l00274">EDMA3_DRV_requestChannel()</a>, and <a class="el" href="edma3__drv__basic_8c-source.html#l02384">edma3RemoveMapping()</a>.</p>
222 </div>
223 </div><p>
224 <a class="anchor" name="7e5fd1b9196af0e6b35819404718923d"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::memProtectionExists" ref="7e5fd1b9196af0e6b35819404718923d" args="" -->
225 <div class="memitem">
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228 <tr>
229 <td class="memname">unsigned short <a class="el" href="structEDMA3__DRV__GblConfigParams.html#7e5fd1b9196af0e6b35819404718923d">EDMA3_DRV_GblConfigParams::memProtectionExists</a> </td>
230 </tr>
231 </table>
232 </div>
233 <div class="memdoc">
235 <p>
236 Existence of memory protection feature
237 </div>
238 </div><p>
239 <a class="anchor" name="5efff8708e94a49f71b055578549c97a"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::globalRegs" ref="5efff8708e94a49f71b055578549c97a" args="" -->
240 <div class="memitem">
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243 <tr>
244 <td class="memname">void* <a class="el" href="structEDMA3__DRV__GblConfigParams.html#5efff8708e94a49f71b055578549c97a">EDMA3_DRV_GblConfigParams::globalRegs</a> </td>
245 </tr>
246 </table>
247 </div>
248 <div class="memdoc">
250 <p>
251 Base address of EDMA3 CC memory mapped registers.
252 <p>Referenced by <a class="el" href="edma3__drv__adv_8c-source.html#l00385">EDMA3_DRV_chainChannel()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l02000">EDMA3_DRV_checkAndClearTcc()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l00895">EDMA3_DRV_clearErrorBits()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l02217">EDMA3_DRV_disableTransfer()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l02051">EDMA3_DRV_enableTransfer()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l01788">EDMA3_DRV_getCCRegister()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l01604">EDMA3_DRV_getMapChToEvtQ()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l01170">EDMA3_DRV_getOptField()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l00774">EDMA3_DRV_getPaRAM()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l00946">EDMA3_DRV_getPaRAMEntry()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l01225">EDMA3_DRV_getPaRAMField()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l02132">EDMA3_DRV_getPaRAMPhyAddr()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l00169">EDMA3_DRV_linkChannel()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l01483">EDMA3_DRV_mapChToEvtQ()</a>, <a class="el" href="edma3__drv__init_8c-source.html#l00413">EDMA3_DRV_open()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l00274">EDMA3_DRV_requestChannel()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l01699">EDMA3_DRV_setCCRegister()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l01762">EDMA3_DRV_setDestIndex()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l01466">EDMA3_DRV_setDestParams()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l01379">EDMA3_DRV_setEvtQPriority()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l01018">EDMA3_DRV_setOptField()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l00693">EDMA3_DRV_setPaRAM()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l00864">EDMA3_DRV_setPaRAMEntry()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l01038">EDMA3_DRV_setPaRAMField()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l00612">EDMA3_DRV_setQdmaTrigWord()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l01632">EDMA3_DRV_setSrcIndex()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l01306">EDMA3_DRV_setSrcParams()</a>, <a class="el" href="edma3__drv__basic_8c-source.html#l01918">EDMA3_DRV_setTransferParams()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l00521">EDMA3_DRV_unchainChannel()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l00286">EDMA3_DRV_unlinkChannel()</a>, <a class="el" href="edma3__drv__adv_8c-source.html#l01870">EDMA3_DRV_waitAndClearTcc()</a>, and <a class="el" href="edma3__drv__basic_8c-source.html#l02384">edma3RemoveMapping()</a>.</p>
254 </div>
255 </div><p>
256 <a class="anchor" name="31847b941f3a290ef68992ea3683228f"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::tcRegs" ref="31847b941f3a290ef68992ea3683228f" args="[EDMA3_MAX_TC]" -->
257 <div class="memitem">
258 <div class="memproto">
259 <table class="memname">
260 <tr>
261 <td class="memname">void* <a class="el" href="structEDMA3__DRV__GblConfigParams.html#31847b941f3a290ef68992ea3683228f">EDMA3_DRV_GblConfigParams::tcRegs</a>[EDMA3_MAX_TC] </td>
262 </tr>
263 </table>
264 </div>
265 <div class="memdoc">
267 <p>
268 Base address of EDMA3 TCs memory mapped registers.
269 </div>
270 </div><p>
271 <a class="anchor" name="08b4ad4be6b0cd9c6dd046dfe4f68c1e"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::xferCompleteInt" ref="08b4ad4be6b0cd9c6dd046dfe4f68c1e" args="" -->
272 <div class="memitem">
273 <div class="memproto">
274 <table class="memname">
275 <tr>
276 <td class="memname">unsigned int <a class="el" href="structEDMA3__DRV__GblConfigParams.html#08b4ad4be6b0cd9c6dd046dfe4f68c1e">EDMA3_DRV_GblConfigParams::xferCompleteInt</a> </td>
277 </tr>
278 </table>
279 </div>
280 <div class="memdoc">
282 <p>
283 EDMA3 transfer completion interrupt line (could be different for ARM and DSP)
284 </div>
285 </div><p>
286 <a class="anchor" name="5f7297703c68fdb4d6e9b2a5d4750040"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::ccError" ref="5f7297703c68fdb4d6e9b2a5d4750040" args="" -->
287 <div class="memitem">
288 <div class="memproto">
289 <table class="memname">
290 <tr>
291 <td class="memname">unsigned int <a class="el" href="structEDMA3__DRV__GblConfigParams.html#5f7297703c68fdb4d6e9b2a5d4750040">EDMA3_DRV_GblConfigParams::ccError</a> </td>
292 </tr>
293 </table>
294 </div>
295 <div class="memdoc">
297 <p>
298 EDMA3 CC error interrupt line (could be different for ARM and DSP)
299 </div>
300 </div><p>
301 <a class="anchor" name="3fdbb69b709ecd01dc903ec47e59f5a8"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::tcError" ref="3fdbb69b709ecd01dc903ec47e59f5a8" args="[EDMA3_MAX_TC]" -->
302 <div class="memitem">
303 <div class="memproto">
304 <table class="memname">
305 <tr>
306 <td class="memname">unsigned int <a class="el" href="structEDMA3__DRV__GblConfigParams.html#3fdbb69b709ecd01dc903ec47e59f5a8">EDMA3_DRV_GblConfigParams::tcError</a>[EDMA3_MAX_TC] </td>
307 </tr>
308 </table>
309 </div>
310 <div class="memdoc">
312 <p>
313 EDMA3 TCs error interrupt line (could be different for ARM and DSP)
314 </div>
315 </div><p>
316 <a class="anchor" name="8970e4cce82366cef852a60cc5dc1a5a"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::evtQPri" ref="8970e4cce82366cef852a60cc5dc1a5a" args="[EDMA3_MAX_EVT_QUE]" -->
317 <div class="memitem">
318 <div class="memproto">
319 <table class="memname">
320 <tr>
321 <td class="memname">unsigned int <a class="el" href="structEDMA3__DRV__GblConfigParams.html#8970e4cce82366cef852a60cc5dc1a5a">EDMA3_DRV_GblConfigParams::evtQPri</a>[EDMA3_MAX_EVT_QUE] </td>
322 </tr>
323 </table>
324 </div>
325 <div class="memdoc">
327 <p>
328 EDMA3 TC priority setting.
329 <p>
330 User can program the priority of the Event Queues at a system-wide level. This means that the user can set the priority of an IO initiated by either of the TCs (Transfer Controllers) relative to IO initiated by the other bus masters on the device (ARM, DSP, USB, etc)
331 </div>
332 </div><p>
333 <a class="anchor" name="60f00b339733c6126951a688072b53b3"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::evtQueueWaterMarkLvl" ref="60f00b339733c6126951a688072b53b3" args="[EDMA3_MAX_EVT_QUE]" -->
334 <div class="memitem">
335 <div class="memproto">
336 <table class="memname">
337 <tr>
338 <td class="memname">unsigned int <a class="el" href="structEDMA3__DRV__GblConfigParams.html#60f00b339733c6126951a688072b53b3">EDMA3_DRV_GblConfigParams::evtQueueWaterMarkLvl</a>[EDMA3_MAX_EVT_QUE] </td>
339 </tr>
340 </table>
341 </div>
342 <div class="memdoc">
344 <p>
345 Event Queues Watermark Levels.
346 <p>
347 To Configure the Threshold level of number of events that can be queued up in the Event queues. EDMA3CC error register (CCERR) will indicate whether or not at any instant of time the number of events queued up in any of the event queues exceeds or equals the threshold/watermark value that is set in the queue watermark threshold register (QWMTHRA).
348 </div>
349 </div><p>
350 <a class="anchor" name="a217c4ed918c9d5d695ee19ced91ef00"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::tcDefaultBurstSize" ref="a217c4ed918c9d5d695ee19ced91ef00" args="[EDMA3_MAX_TC]" -->
351 <div class="memitem">
352 <div class="memproto">
353 <table class="memname">
354 <tr>
355 <td class="memname">unsigned int <a class="el" href="structEDMA3__DRV__GblConfigParams.html#a217c4ed918c9d5d695ee19ced91ef00">EDMA3_DRV_GblConfigParams::tcDefaultBurstSize</a>[EDMA3_MAX_TC] </td>
356 </tr>
357 </table>
358 </div>
359 <div class="memdoc">
361 <p>
362 Default Burst Size (DBS) of TCs.
363 <p>
364 An optimally-sized command is defined by the transfer controller default burst size (DBS). Different TCs can have different DBS values. It is defined in Bytes.
365 <p>Referenced by <a class="el" href="edma3__drv__basic_8c-source.html#l01466">EDMA3_DRV_setDestParams()</a>, and <a class="el" href="edma3__drv__basic_8c-source.html#l01306">EDMA3_DRV_setSrcParams()</a>.</p>
367 </div>
368 </div><p>
369 <a class="anchor" name="ef6b47382a74f4aabfa050f6213512d4"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::dmaChannelPaRAMMap" ref="ef6b47382a74f4aabfa050f6213512d4" args="[EDMA3_MAX_DMA_CH]" -->
370 <div class="memitem">
371 <div class="memproto">
372 <table class="memname">
373 <tr>
374 <td class="memname">unsigned int <a class="el" href="structEDMA3__DRV__GblConfigParams.html#ef6b47382a74f4aabfa050f6213512d4">EDMA3_DRV_GblConfigParams::dmaChannelPaRAMMap</a>[EDMA3_MAX_DMA_CH] </td>
375 </tr>
376 </table>
377 </div>
378 <div class="memdoc">
380 <p>
381 Mapping from DMA channels to PaRAM Sets.
382 <p>
383 If channel mapping exists (DCHMAP registers are present), this array stores the respective PaRAM Set for each DMA channel. User can initialize each array member with a specific PaRAM Set or with EDMA3_DRV_CH_NO_PARAM_MAP. If channel mapping doesn't exist, it is of no use as the EDMA3 RM automatically uses the right PaRAM Set for that DMA channel. Useful only if mapping exists, otherwise of no use.
384 <p>Referenced by <a class="el" href="edma3__drv__basic_8c-source.html#l00274">EDMA3_DRV_requestChannel()</a>.</p>
386 </div>
387 </div><p>
388 <a class="anchor" name="09dc86e6c4cbda84547c3033532e1b98"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::dmaChannelTccMap" ref="09dc86e6c4cbda84547c3033532e1b98" args="[EDMA3_MAX_DMA_CH]" -->
389 <div class="memitem">
390 <div class="memproto">
391 <table class="memname">
392 <tr>
393 <td class="memname">unsigned int <a class="el" href="structEDMA3__DRV__GblConfigParams.html#09dc86e6c4cbda84547c3033532e1b98">EDMA3_DRV_GblConfigParams::dmaChannelTccMap</a>[EDMA3_MAX_DMA_CH] </td>
394 </tr>
395 </table>
396 </div>
397 <div class="memdoc">
399 <p>
400 Mapping from DMA channels to TCCs.
401 <p>
402 This array stores the respective TCC (interrupt channel) for each DMA channel. User can initialize each array member with a specific TCC or with EDMA3_DRV_CH_NO_TCC_MAP. This specific TCC code will be returned when the transfer is completed on the mapped DMA channel.
403 <p>Referenced by <a class="el" href="edma3__drv__basic_8c-source.html#l00274">EDMA3_DRV_requestChannel()</a>.</p>
405 </div>
406 </div><p>
407 <a class="anchor" name="c205feb9fd0a3575627dbec2f95d176c"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap" ref="c205feb9fd0a3575627dbec2f95d176c" args="[EDMA3_MAX_DMA_CHAN_DWRDS]" -->
408 <div class="memitem">
409 <div class="memproto">
410 <table class="memname">
411 <tr>
412 <td class="memname">unsigned int <a class="el" href="structEDMA3__DRV__GblConfigParams.html#c205feb9fd0a3575627dbec2f95d176c">EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap</a>[EDMA3_MAX_DMA_CHAN_DWRDS] </td>
413 </tr>
414 </table>
415 </div>
416 <div class="memdoc">
418 <p>
419 Mapping from DMA channels to Hardware Events.
420 <p>
421 Each bit in this array corresponds to one DMA channel and tells whether this DMA channel is tied to any peripheral. That is whether any peripheral can send the synch event on this DMA channel or not. 1 means the channel is tied to some peripheral; 0 means it is not. DMA channels which are tied to some peripheral are RESERVED for that peripheral only. They are not allocated when user asks for 'ANY' DMA channel. All channels need not be mapped, some can be free also.
422 <p>Referenced by <a class="el" href="edma3__drv__basic_8c-source.html#l02217">EDMA3_DRV_disableTransfer()</a>, and <a class="el" href="edma3__drv__basic_8c-source.html#l02051">EDMA3_DRV_enableTransfer()</a>.</p>
424 </div>
425 </div><p>
426 <hr>The documentation for this struct was generated from the following file:<ul>
427 <li><a class="el" href="edma3__drv_8h-source.html">edma3_drv.h</a></ul>
428 </div>
429 <hr size="1"><address style="text-align: right;"><small>Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by
430 <a href="http://www.doxygen.org/index.html">
431 <img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.5.6 </small></address>
432 </body>
433 </html>