1 /*******************************************************************************\r
2 **+--------------------------------------------------------------------------+**\r
3 **| **** |**\r
4 **| **** |**\r
5 **| ******o*** |**\r
6 **| ********_///_**** |**\r
7 **| ***** /_//_/ **** |**\r
8 **| ** ** (__/ **** |**\r
9 **| ********* |**\r
10 **| **** |**\r
11 **| *** |**\r
12 **| |**\r
13 **| Copyright (c) 1998-2006 Texas Instruments Incorporated |**\r
14 **| ALL RIGHTS RESERVED |**\r
15 **| |**\r
16 **| Permission is hereby granted to licensees of Texas Instruments |**\r
17 **| Incorporated (TI) products to use this computer program for the sole |**\r
18 **| purpose of implementing a licensee product based on TI products. |**\r
19 **| No other rights to reproduce, use, or disseminate this computer |**\r
20 **| program, whether in part or in whole, are granted. |**\r
21 **| |**\r
22 **| TI makes no representation or warranties with respect to the |**\r
23 **| performance of this computer program, and specifically disclaims |**\r
24 **| any responsibility for any damages, special or consequential, |**\r
25 **| connected with the use of this program. |**\r
26 **| |**\r
27 **+--------------------------------------------------------------------------+**\r
28 *******************************************************************************/\r
29 \r
30 /** \file edma3_drv.h\r
31 \brief EDMA3 Controller\r
32 \r
33 This file contains Application Interface for the EDMA3 Driver. EDMA3 Driver\r
34 uses the EDMA3 Resource Manager internally for resource allocation,\r
35 interrupt handling and EDMA3 registers programming.\r
36 \r
37 (C) Copyright 2006, Texas Instruments, Inc\r
38 \r
39 \version 0.0.1 Purushotam Kumar - Created\r
40 0.1.0 Joseph Fernandez - Made generic\r
41 - Added documentation\r
42 - Moved SoC specific defines\r
43 to SoC specific header.\r
44 0.2.0 Anuj Aggarwal - Modified it for EDMA3 package\r
45 - Added multiple instances\r
46 capability\r
47 0.2.1 Anuj Aggarwal - Modified it for more run time\r
48 configuration.\r
49 - Made EDMA3 package OS\r
50 independent.\r
51 0.2.2 Anuj Aggarwal - Critical section handling code\r
52 modification. Uses semaphore and\r
53 interrupts disabling mechanism\r
54 for resource sharing.\r
55 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV\r
56 - IPR bit clearing in RM ISR\r
57 issue fixed.\r
58 - Sample application made generic\r
59 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC\r
60 mapping, to fix QDMA missed\r
61 event issue.\r
62 0.3.2 Anuj Aggarwal - Added support for POLL mode\r
63 - Added a new API to modify the\r
64 CC Register.\r
65 1.0.0 Anuj Aggarwal - Fixed resource allocation related\r
66 bugs.\r
67 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event\r
68 generation related bug.\r
69 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC\r
70 compliant.\r
71 1.0.0.3 Anuj Aggarwal - Changed the directory structure\r
72 as per RTSC standard.\r
73 1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate\r
74 logical channels\r
75 b) Created EDMA3 config files\r
76 for different platforms\r
77 c) Misc changes\r
78 1.02.00.01 Anuj Aggarwal - a) Added DM6467 support\r
79 b) Fixed some MRs\r
80 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files\r
81 b) IOCTL Interface added.\r
82 c) Fixed some MRs.\r
83 1.04 Anuj Aggarwal - a) Header files modified to have\r
84 extern "C" declarations.\r
85 b) Implemented ECNs DPSP00009815\r
86 & DPSP00010035.\r
87 \r
88 */\r
89 \r
90 #ifndef _EDMA3_DRV_H_\r
91 #define _EDMA3_DRV_H_\r
92 \r
93 \r
94 /* Include the Resource Manager header file */\r
95 #include <ti/sdo/edma3/rm/edma3_rm.h>\r
96 \r
97 #ifdef __cplusplus\r
98 extern "C" {\r
99 #endif\r
100 \r
101 /**\r
102 * \defgroup Edma3DrvMain EDMA3 Driver Interface Definition\r
103 *\r
104 * Top-level Encapsulation of all documentation for EDMA3 Driver\r
105 *\r
106 * @{\r
107 */\r
108 \r
109 \r
110 /*---------------------------------------------------------------------------*/\r
111 /*------------------Usage Guidelines Start-----------------------------------*/\r
112 /*---------------------------------------------------------------------------*/\r
113 \r
114 /**\r
115 * \defgroup Edma3DrvUsage EDMA3 Driver Usage Guidelines\r
116 *\r
117 * Guidelines for typical usage of EDMA3 Driver.\r
118 *\r
119 * @{\r
120 */\r
121 \r
122 \r
123 /**\r
124 \brief Usage of EDMA3 Driver.\r
125 \r
126 -# Create EDMA3 Driver Object (one for each EDMA3 hardware instance)\r
127 - EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
128 - unsigned int edma3HwInstanceId = 0;\r
129 - EDMA3_DRV_GblConfigParams *gblCfgParams = NULL;\r
130 - Init-time Configuration structure for EDMA3 controller, to provide\r
131 Global SoC specific Information. This could be NULL also. In that\r
132 case, static configuration will be taken.\r
133 - result = EDMA3_DRV_create (edma3HwInstanceId, gblCfgParams, NULL);\r
134 \r
135 -# Open EDMA3 driver Instance\r
136 - Steps\r
137 - EDMA3_DRV_InitConfig initCfg;\r
138 - EDMA3_DRV_Handle hEdma = NULL;\r
139 - EDMA3_OS_SemAttrs semAttrs = {EDMA3_OS_SEMTYPE_FIFO, NULL};\r
140 - EDMA3_DRV_Result edmaResult;\r
141 -To get the error code while opening driver instance\r
142 \r
143 -# initCfg.regionId = One of the possible regions available\r
144 for eg, (EDMA3_RM_RegionId)0 or (EDMA3_RM_RegionId)1 etc, for\r
145 different masters.\r
146 \r
147 -# initCfg.isMaster = TRUE/FALSE (Whether this EDMA3\r
148 DRV instance is Master or not. The EDMA3 Shadow Region tied to\r
149 the Master DRV Instance will ONLY receive the EDMA3 interrupts\r
150 (error or completion), if enabled).\r
151 \r
152 -# initCfg.drvSemHandle =\r
153 EDMA3 DRV Instance specific semaphore handle. It should\r
154 be provided by the user for proper sharing of resources.\r
155 - edma3Result = edma3OsSemCreate(1, &semAttrs,\r
156 &initCfg.drvSemHandle);\r
157 \r
158 -# initCfg.drvInstInitConfig =\r
159 Init-time Region Specific Configuration Structure. It can be\r
160 provided by the user at run-time. If not provided by the user,\r
161 this info would be taken from the platform specific config file,\r
162 if it exists.\r
163 \r
164 -# initCfg.drvInstInitConfig->ownDmaChannels[] =\r
165 The bitmap(s) which indicate the DMA channels owned by this\r
166 instance of the EDMA3 Driver\n\r
167 E.g. A '1' at bit position 24 indicates that this instance of\r
168 the EDMA3 Driver owns DMA Channel Id 24\n\r
169 Later when a request is made based on a particular Channel Id,\r
170 the EDMA3 Driver will check first if it owns that channel.\r
171 If it doesnot own it, EDMA3 Driver returns error.\r
172 -# initCfg.drvInstInitConfig->ownQdmaChannels[] =\r
173 The bitmap(s) which indicate the QDMA channels owned by this\r
174 instance of the EDMA3 Driver \n\r
175 -# initCfg.drvInstInitConfig->ownPaRAMSets[] =\r
176 The bitmap(s) which indicate the PaRAM Sets owned by this\r
177 instance of the EDMA3 Driver \n\r
178 -# initCfg.drvInstInitConfig->ownTccs[] =\r
179 The bitmap(s) which indicate the TCCs owned by this\r
180 instance of the EDMA3 Driver \n\r
181 \r
182 -# initCfg.drvInstInitConfig->resvdDmaChannels[] =\r
183 The bitmap(s) which indicate the DMA channels reserved by this\r
184 instance of the EDMA3 Driver \n\r
185 E.g. A '1' at bit position 24 indicates that this instance of\r
186 the EDMA3 Driver reserves Channel Id 24\n\r
187 These channels are reserved and may be mapped to HW events,\r
188 these are not given to 'EDMA3_DRV_DMA_CHANNEL_ANY' requests.\n\r
189 -# initCfg.drvInstInitConfig->resvdQdmaChannels[] =\r
190 The bitmap(s) which indicate the QDMA channels reserved by this\r
191 instance of the EDMA3 Driver \n\r
192 E.g. A '1' at bit position 1 indicates that this instance of\r
193 the EDMA3 Driver reserves QDMA Channel Id 1\n\r
194 These channels are reserved for some specific purpose,\r
195 these are not given to 'EDMA3_DRV_QDMA_CHANNEL_ANY' request\n\r
196 -# initCfg.drvInstInitConfig->resvdPaRAMSets[] =\r
197 PaRAM Sets which are reserved by this Region;\r
198 -# initCfg.drvInstInitConfig->resvdTccs[] =\r
199 TCCs which are reserved by this Region;\r
200 \r
201 \r
202 -# initCfg.gblerrCb =\r
203 Instance wide callback function to catch non-channel specific\r
204 errors;\r
205 -# initCfg.gblerrData =\r
206 Application data to be passed back to the callback function;\r
207 \r
208 -# hEdma = EDMA3_DRV_open(edma3HwInstanceId, &initCfg, &edmaResult);\r
209 \r
210 -# EDMA3 driver APIs\r
211 - EDMA3_RM_ResDesc resObj;\r
212 - EDMA3_DRV_Result result;\r
213 - unsigned int ch1Id = 0;\r
214 - unsigned int ch2Id = 0;\r
215 - unsigned int tcc1 = 0;\r
216 - unsigned int tcc2 = 0;\r
217 - unsigned int qCh1Id = 0;\r
218 - unsigned int qTcc1 = 0;\r
219 - unsigned int qCh2Id = 0;\r
220 - unsigned int qTcc2 = 0;\r
221 - unsigned int paRAMId;\r
222 - int srcbidx = 0;\r
223 - int desbidx = 0;\r
224 - int srccidx = 0;\r
225 - int descidx = 0;\r
226 - unsigned int acnt = 0;\r
227 - unsigned int bcnt = 0;\r
228 - unsigned int ccnt = 0;\r
229 - unsigned int bcntreload = 0;\r
230 - EDMA3_DRV_SyncType synctype;\r
231 - EDMA3_RM_TccCallback tccCb;\r
232 - void *cbData;\r
233 -\r
234 - Use Case 1: Memory to memory transfer on any available\r
235 - DMA Channel\n\n\r
236 - tcc1 = EDMA3_DRV_TCC_ANY;\r
237 - ch1Id = EDMA3_DRV_DMA_CHANNEL_ANY;\r
238 - result = EDMA3_DRV_requestChannel (hEdma, &ch1Id, &tcc1,\r
239 (EDMA3_RM_EventQueue)0, &callback1, NULL);\r
240 \r
241 - result = EDMA3_DRV_setSrcParams (hEdma, ch1Id,\r
242 (unsigned int)(srcBuff1),\r
243 EDMA3_DRV_ADDR_MODE_INCR,\r
244 EDMA3_DRV_W8BIT);\r
245 - result = EDMA3_DRV_setDestParams (hEdma, ch1Id,\r
246 (unsigned int)(dstBuff1),\r
247 EDMA3_DRV_ADDR_MODE_INCR,\r
248 EDMA3_DRV_W8BIT);\r
249 \r
250 - Set EDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload,\r
251 SyncType)\r
252 acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0;\r
253 synctype = EDMA3_DRV_SYNC_A;\r
254 - result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt,\r
255 ccnt, bcntreload, synctype);\r
256 \r
257 - Set srcbidx and srccidx to the appropriate values\r
258 - srcbidx = acnt; srccidx = acnt;\r
259 - result = EDMA3_DRV_setSrcIndex (hEdma, ch1Id, srcbidx, srccidx);\r
260 \r
261 - Set desbidx and descidx to the appropriate values\r
262 - desbidx = acnt; descidx = acnt;\r
263 - result = EDMA3_DRV_setDestIndex (hEdma, ch1Id, desbidx, descidx);\r
264 \r
265 - Enable the final completion interrupt.\r
266 - result = EDMA3_DRV_setOptField (hEdma, ch1Id,\r
267 EDMA3_DRV_OPT_FIELD_TCINTEN, 1);\r
268 \r
269 - Enable the transfer\r
270 - result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,\r
271 EDMA3_DRV_TRIG_MODE_MANUAL);\r
272 \r
273 - Use Case 2: Linked memory to memory transfer on any available\r
274 - DMA Channel\n\n\r
275 - Perform steps as for Use Case 1 for the Master logical channel\r
276 ch1Id for configuration. DONOT enable the transfer for ch1Id.\r
277 - Configure link channel, ch2Id.\r
278 - tcc2 = EDMA3_DRV_TCC_ANY;\r
279 - ch2Id = EDMA3_DRV_LINK_CHANNEL;\r
280 - result = EDMA3_DRV_requestChannel (hEdma, &ch2Id, &tcc2,\r
281 (EDMA3_RM_EventQueue)0, &callback2, NULL);\r
282 \r
283 - result = EDMA3_DRV_setSrcParams (hEdma, ch2Id,\r
284 (unsigned int)(srcBuff2),\r
285 EDMA3_DRV_ADDR_MODE_INCR,\r
286 EDMA3_DRV_W8BIT);\r
287 - result = EDMA3_DRV_setDestParams (hEdma, ch2Id,(\r
288 unsigned int)(dstBuff2),\r
289 EDMA3_DRV_ADDR_MODE_INCR,\r
290 EDMA3_DRV_W8BIT);\r
291 \r
292 - result = EDMA3_DRV_setSrcIndex (hEdma, ch2Id, srcbidx, srccidx);\r
293 - result = EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx);\r
294 \r
295 - result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,\r
296 ccnt, bcntreload, synctype);\r
297 \r
298 - Link both the channels\r
299 - result = EDMA3_DRV_linkChannel (hEdma, ch1Id, ch2Id);\r
300 \r
301 - Enable the final completion interrupts on both the channels\r
302 - result = EDMA3_DRV_setOptField (hEdma, ch1Id,\r
303 EDMA3_DRV_OPT_FIELD_TCINTEN, 1);\r
304 - result = EDMA3_DRV_setOptField (hEdma, ch2Id,\r
305 EDMA3_DRV_OPT_FIELD_TCINTEN, 1);\r
306 \r
307 - Enable the transfer on channel 1.\r
308 - result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,\r
309 EDMA3_DRV_TRIG_MODE_MANUAL);\r
310 - Wait for the completion interrupt on Ch1 and then enable the\r
311 transfer again for the LINK channel, to provide the required\r
312 sync event.\r
313 - result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,\r
314 EDMA3_DRV_TRIG_MODE_MANUAL);\r
315 \r
316 - Note: Enabling of transfers on channel 1 (for master and link\r
317 channel) is required as many number of times as the sync events\r
318 are required. For ASync mode, number of sync events=(bcnt * ccnt)\r
319 and for ABSync mode, number of sync events = ccnt.\r
320 \r
321 - Use Case 3: Memory to memory transfer on any available\r
322 - QDMA Channel\n\n\r
323 - qTcc1 = EDMA3_DRV_TCC_ANY;\r
324 - qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;\r
325 \r
326 - result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1,\r
327 (EDMA3_RM_EventQueue)0, &callback1, NULL);\r
328 \r
329 - Set the QDMA trigger word.\r
330 - result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id,\r
331 EDMA3_RM_QDMA_TRIG_DST);\r
332 - Note: DONOT write the destination address (trigger word) before\r
333 completing the configuration as it will trigger the\r
334 transfer. Also, DONOT use EDMA3_DRV_setDestParams() to set\r
335 the destination address as it also sets other parameters.\r
336 Use EDMA3_DRV_setPaRAMEntry() to set the destination address\r
337 \r
338 - result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id,\r
339 (unsigned int)(srcBuff1),\r
340 EDMA3_DRV_ADDR_MODE_INCR,\r
341 EDMA3_DRV_W8BIT);\r
342 \r
343 - Set QDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload,\r
344 SyncType)\r
345 acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0;\r
346 synctype = EDMA3_DRV_SYNC_A;\r
347 - result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt,\r
348 ccnt, bcntreload, synctype);\r
349 \r
350 - srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;\r
351 - result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);\r
352 - result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);\r
353 \r
354 - Enable the final completion interrupt.\r
355 - result = EDMA3_DRV_setOptField (hEdma, qCh1Id,\r
356 EDMA3_DRV_OPT_FIELD_TCINTEN, 1);\r
357 \r
358 - Set the Destination Addressing Mode as Increment\r
359 - result = EDMA3_DRV_setOptField (hEdma, qCh1Id,\r
360 EDMA3_DRV_OPT_FIELD_DAM,\r
361 EDMA3_DRV_ADDR_MODE_INCR);\r
362 \r
363 - Trigger the QDMA channel by writing the destination address\r
364 - result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id,\r
365 EDMA3_DRV_PARAM_ENTRY_DST,\r
366 (unsigned int)(dstBuff1));\r
367 \r
368 -\r
369 - Use Case 4: Linked memory to memory transfer on any available\r
370 - QDMA Channel\n\n\r
371 - Setup for any QDMA Channel\r
372 - qTcc1 = EDMA3_DRV_TCC_ANY;\r
373 - qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;\r
374 - result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1,\r
375 (EDMA3_RM_EventQueue)0, &callback1, NULL);\r
376 \r
377 - Setup for Channel 2\r
378 - qCh2Id = EDMA3_DRV_LINK_CHANNEL;\r
379 - qTcc2 = EDMA3_DRV_TCC_ANY;\r
380 - result = EDMA3_DRV_requestChannel (hEdma, &qCh2Id, &qTcc2,\r
381 (EDMA3_RM_EventQueue)0,\r
382 &callback2, NULL);\r
383 \r
384 - result = EDMA3_DRV_setSrcParams (hEdma, qCh2Id,\r
385 (unsigned int)(srcBuff2),\r
386 EDMA3_DRV_ADDR_MODE_INCR,\r
387 EDMA3_DRV_W8BIT);\r
388 - result = EDMA3_DRV_setDestParams(hEdma, qCh2Id,\r
389 (unsigned int)(dstBuff2),\r
390 EDMA3_DRV_ADDR_MODE_INCR,\r
391 EDMA3_DRV_W8BIT);\r
392 \r
393 - acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0;\r
394 synctype = EDMA3_DRV_SYNC_A;\r
395 - result = EDMA3_DRV_setTransferParams (hEdma, qCh2Id, acnt, bcnt,\r
396 ccnt, BRCnt,\r
397 EDMA3_DRV_SYNC_A);\r
398 \r
399 - srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;\r
400 - result = EDMA3_DRV_setSrcIndex (hEdma, qCh2Id, srcbidx, srccidx);\r
401 - result = EDMA3_DRV_setDestIndex (hEdma, qCh2Id, desbidx, descidx);\r
402 \r
403 - result = EDMA3_DRV_setOptField (hEdma, qCh2Id,\r
404 EDMA3_DRV_OPT_FIELD_TCINTEN, 1);\r
405 \r
406 - Make the PaRAM Set associated with qCh2Id as Static\r
407 - result = EDMA3_DRV_setOptField (hEdma, qCh2Id,\r
408 EDMA3_DRV_OPT_FIELD_STATIC, 1u);\r
409 \r
410 - Link both the channels\r
411 - result = EDMA3_DRV_linkChannel (hEdma,qCh1Id,qCh2Id);\r
412 \r
413 - Set the QDMA trigger word.\r
414 - result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id,\r
415 EDMA3_DRV_QDMA_TRIG_DST);\r
416 - Note: DONOT write the destination address (trigger word) before\r
417 completing the configuration as it'll trigger the transfer.\r
418 Also, DONOT use EDMA3_DRV_setDestParams () function to set\r
419 the destination address as it also sets other parameters.\r
420 Use EDMA3_DRV_setPaRAMEntry() to set the dest address.\r
421 \r
422 - result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id,\r
423 (unsigned int)(srcBuff1),\r
424 EDMA3_DRV_ADDR_MODE_INCR,\r
425 EDMA3_DRV_W8BIT);\r
426 \r
427 - Set QDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload,\r
428 SyncType)\r
429 acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0;\r
430 synctype = EDMA3_DRV_SYNC_A;\r
431 - result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt,\r
432 ccnt, bcntreload, synctype);\r
433 \r
434 - srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;\r
435 - result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);\r
436 - result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);\r
437 \r
438 - result = EDMA3_DRV_setOptField (hEdma, qCh1Id,\r
439 EDMA3_DRV_OPT_FIELD_TCINTEN, 1);\r
440 \r
441 - Set the Destination Addressing Mode as Increment\r
442 - result = EDMA3_DRV_setOptField (hEdma, qCh1Id,\r
443 EDMA3_DRV_OPT_FIELD_DAM,\r
444 EDMA3_DRV_ADDR_MODE_INCR);\r
445 \r
446 - Trigger the QDMA channel by writing the destination address\r
447 - result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id,\r
448 EDMA3_DRV_PARAM_ENTRY_DST,\r
449 (unsigned int)(dstBuff1));\r
450 \r
451 */\r
452 /* @} Edma3DrvUsage */\r
453 \r
454 /*---------------------------------------------------------------------------*/\r
455 /*------------------Usage Guidelines End-------------------------------------*/\r
456 /*---------------------------------------------------------------------------*/\r
457 \r
458 \r
459 /**\r
460 * \defgroup Edma3DrvErrorCode EDMA3 Driver Error Codes\r
461 *\r
462 * Error Codes returned by the EDMA3 Driver\r
463 *\r
464 * @{\r
465 */\r
466 /** EDMA3 Driver Error Codes Base define */\r
467 #define EDMA3_DRV_E_BASE (-128)\r
468 \r
469 /**\r
470 * EDMA3 Driver Object Not Deleted yet.\r
471 * So it cannot be created.\r
472 */\r
473 #define EDMA3_DRV_E_OBJ_NOT_DELETED (EDMA3_DRV_E_BASE)\r
474 \r
475 /**\r
476 * EDMA3 Driver Object Not Closed yet.\r
477 * So it cannot be deleted.\r
478 */\r
479 #define EDMA3_DRV_E_OBJ_NOT_CLOSED (EDMA3_DRV_E_BASE-1)\r
480 \r
481 /**\r
482 * EDMA3 Driver Object Not Opened yet\r
483 * So it cannot be closed.\r
484 */\r
485 #define EDMA3_DRV_E_OBJ_NOT_OPENED (EDMA3_DRV_E_BASE-2)\r
486 \r
487 /**\r
488 * While closing EDMA3 Driver, Resource Manager\r
489 * Close Failed.\r
490 */\r
491 #define EDMA3_DRV_E_RM_CLOSE_FAIL (EDMA3_DRV_E_BASE-3)\r
492 \r
493 /** The requested DMA Channel not available */\r
494 #define EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-4)\r
495 \r
496 /** The requested QDMA Channel not available */\r
497 #define EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-5)\r
498 \r
499 /** The requested PaRAM Set not available */\r
500 #define EDMA3_DRV_E_PARAM_SET_UNAVAIL (EDMA3_DRV_E_BASE-6)\r
501 \r
502 /** The requested TCC not available */\r
503 #define EDMA3_DRV_E_TCC_UNAVAIL (EDMA3_DRV_E_BASE-7)\r
504 \r
505 /** The registration of TCC failed */\r
506 #define EDMA3_DRV_E_TCC_REGISTER_FAIL (EDMA3_DRV_E_BASE-8)\r
507 \r
508 /** The binding of Channel and PaRAM Set failed */\r
509 #define EDMA3_DRV_E_CH_PARAM_BIND_FAIL (EDMA3_DRV_E_BASE-9)\r
510 \r
511 /**\r
512 * The address of the memory location passed as argument\r
513 * is not properly aligned. It should be 32 bytes aligned.\r
514 */\r
515 #define EDMA3_DRV_E_ADDRESS_NOT_ALIGNED (EDMA3_DRV_E_BASE-10)\r
516 \r
517 /** Invalid Parameter passed to API */\r
518 #define EDMA3_DRV_E_INVALID_PARAM (EDMA3_DRV_E_BASE-11)\r
519 \r
520 /** Invalid State of EDMA3 HW Obj */\r
521 #define EDMA3_DRV_E_INVALID_STATE (EDMA3_DRV_E_BASE-12)\r
522 \r
523 /** EDMA3 Driver instance already exists for the specified region */\r
524 #define EDMA3_DRV_E_INST_ALREADY_EXISTS (EDMA3_DRV_E_BASE-13)\r
525 \r
526 /** FIFO width not supported by the requested TC */\r
527 #define EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED (EDMA3_DRV_E_BASE-14)\r
528 \r
529 /** Semaphore related error */\r
530 #define EDMA3_DRV_E_SEMAPHORE (EDMA3_DRV_E_BASE-15)\r
531 \r
532 /** EDMA3 Driver Instance does not exist, it is not opened yet */\r
533 #define EDMA3_DRV_E_INST_NOT_OPENED (EDMA3_DRV_E_BASE-16)\r
534 \r
535 /* @} Edma3DrvErrorCode */\r
536 \r
537 \r
538 /**\r
539 * This define is used to specify that a DMA channel is NOT tied to any PaRAM\r
540 * Set and hence any available PaRAM Set could be used for that DMA channel.\r
541 * It could be used in dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH], in global\r
542 * configuration structure EDMA3_RM_GblConfigParams.\r
543 *\r
544 * This value should mandatorily be used to mark DMA channels with no initial\r
545 * mapping to specific PaRAM Sets.\r
546 */\r
547 #define EDMA3_DRV_CH_NO_PARAM_MAP EDMA3_RM_CH_NO_PARAM_MAP\r
548 \r
549 /**\r
550 * This define is used to specify that the DMA/QDMA channel is not tied to any\r
551 * TCC and hence any available TCC could be used for that DMA/QDMA channel.\r
552 * It could be used in dmaChannelTccMap [EDMA3_MAX_DMA_CH], in global\r
553 * configuration structure EDMA3_RM_GblConfigParams.\r
554 *\r
555 * This value should mandatorily be used to mark DMA channels with no initial\r
556 * mapping to specific TCCs.\r
557 */\r
558 #define EDMA3_DRV_CH_NO_TCC_MAP EDMA3_RM_CH_NO_TCC_MAP\r
559 \r
560 \r
561 \r
562 /**\struct EDMA3_DRV_GblConfigParams\r
563 * \brief Init-time Configuration structure for EDMA3\r
564 * controller, to provide Global SoC specific Information.\r
565 *\r
566 * This configuration structure is used to specify the EDMA3 Driver\r
567 * global settings, specific to the SoC. For e.g. number of DMA/QDMA channels,\r
568 * number of PaRAM sets, TCCs, event queues, transfer controllers, base\r
569 * addresses of CC global registers and TC registers, interrupt number for\r
570 * EDMA3 transfer completion, CC error, event queues' priority, watermark\r
571 * threshold level etc.\r
572 * This configuration information is SoC specific and could be provided by the\r
573 * user at run-time while creating the EDMA3 Driver Object, using API\r
574 * EDMA3_DRV_create. In case user doesn't provide it, this information could be\r
575 * taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in\r
576 * case it is available.\r
577 */\r
578 typedef struct {\r
579 /** Number of DMA Channels supported by the underlying EDMA3 Controller. */\r
580 unsigned int numDmaChannels;\r
581 \r
582 /** Number of QDMA Channels supported by the underlying EDMA3 Controller */\r
583 unsigned int numQdmaChannels;\r
584 \r
585 /**\r
586 * Number of Interrupt Channels supported by the underlying EDMA3\r
587 * Controller\r
588 */\r
589 unsigned int numTccs;\r
590 \r
591 /** Number of PaRAM Sets supported by the underlying EDMA3 Controller */\r
592 unsigned int numPaRAMSets;\r
593 \r
594 /** Number of Event Queues in the underlying EDMA3 Controller */\r
595 unsigned int numEvtQueue;\r
596 \r
597 /**\r
598 * Number of Transfer Controllers (TCs) in the underlying EDMA3 Controller\r
599 */\r
600 unsigned int numTcs;\r
601 \r
602 /** Number of Regions in the underlying EDMA3 Controller */\r
603 unsigned int numRegions;\r
604 \r
605 /**\r
606 * \brief Channel mapping existence\r
607 *\r
608 * A value of 0 (No channel mapping) implies that there is fixed\r
609 * association between a DMA channel and a PaRAM Set or, in other words,\r
610 * DMA channel n can ONLY use PaRAM Set n (No availability of DCHMAP\r
611 * registers) for transfers to happen.\r
612 *\r
613 * A value of 1 implies the presence of DCHMAP registers for the DMA\r
614 * channels and hence the flexibility of associating any DMA channel to\r
615 * any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA\r
616 * channel (like QDMA Channels).\r
617 */\r
618 unsigned short dmaChPaRAMMapExists;\r
619 \r
620 /** Existence of memory protection feature */\r
621 unsigned short memProtectionExists;\r
622 \r
623 /** Base address of EDMA3 CC memory mapped registers. */\r
624 void *globalRegs;\r
625 \r
626 /** Base address of EDMA3 TCs memory mapped registers. */\r
627 void *tcRegs[EDMA3_MAX_TC];\r
628 \r
629 /**\r
630 * EDMA3 transfer completion interrupt line (could be different for ARM\r
631 * and DSP)\r
632 */\r
633 unsigned int xferCompleteInt;\r
634 \r
635 /** EDMA3 CC error interrupt line (could be different for ARM and DSP) */\r
636 unsigned int ccError;\r
637 \r
638 /** EDMA3 TCs error interrupt line (could be different for ARM and DSP) */\r
639 unsigned int tcError[EDMA3_MAX_TC];\r
640 \r
641 /**\r
642 * \brief EDMA3 TC priority setting\r
643 *\r
644 * User can program the priority of the Event Queues\r
645 * at a system-wide level. This means that the user can set the\r
646 * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
647 * relative to IO initiated by the other bus masters on the\r
648 * device (ARM, DSP, USB, etc)\r
649 */\r
650 unsigned int evtQPri [EDMA3_MAX_EVT_QUE];\r
651 \r
652 /**\r
653 * \brief Event Queues Watermark Levels\r
654 \r
655 * To Configure the Threshold level of number of events\r
656 * that can be queued up in the Event queues. EDMA3CC error register\r
657 * (CCERR) will indicate whether or not at any instant of time the\r
658 * number of events queued up in any of the event queues exceeds\r
659 * or equals the threshold/watermark value that is set\r
660 * in the queue watermark threshold register (QWMTHRA).\r
661 */\r
662 unsigned int evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE];\r
663 \r
664 /**\r
665 * \brief Default Burst Size (DBS) of TCs.\r
666 \r
667 * An optimally-sized command is defined by the transfer controller\r
668 * default burst size (DBS). Different TCs can have different\r
669 * DBS values. It is defined in Bytes.\r
670 */\r
671 unsigned int tcDefaultBurstSize[EDMA3_MAX_TC];\r
672 \r
673 /**\r
674 * \brief Mapping from DMA channels to PaRAM Sets\r
675 \r
676 * If channel mapping exists (DCHMAP registers are present), this array\r
677 * stores the respective PaRAM Set for each DMA channel. User can\r
678 * initialize each array member with a specific PaRAM Set or with\r
679 * EDMA3_DRV_CH_NO_PARAM_MAP.\r
680 * If channel mapping doesn't exist, it is of no use as the EDMA3 RM\r
681 * automatically uses the right PaRAM Set for that DMA channel.\r
682 * Useful only if mapping exists, otherwise of no use.\r
683 */\r
684 unsigned int dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH];\r
685 \r
686 /**\r
687 * \brief Mapping from DMA channels to TCCs\r
688 *\r
689 * This array stores the respective TCC (interrupt channel) for each\r
690 * DMA channel. User can initialize each array member with a specific TCC\r
691 * or with EDMA3_DRV_CH_NO_TCC_MAP. This specific\r
692 * TCC code will be returned when the transfer is completed\r
693 * on the mapped DMA channel.\r
694 */\r
695 unsigned int dmaChannelTccMap [EDMA3_MAX_DMA_CH];\r
696 \r
697 /**\r
698 * \brief Mapping from DMA channels to Hardware Events\r
699 *\r
700 * Each bit in this array corresponds to one DMA channel and tells whether\r
701 * this DMA channel is tied to any peripheral. That is whether any\r
702 * peripheral can send the synch event on this DMA channel or not.\r
703 * 1 means the channel is tied to some peripheral; 0 means it is not.\r
704 * DMA channels which are tied to some peripheral are RESERVED for that\r
705 * peripheral only. They are not allocated when user asks for 'ANY' DMA\r
706 * channel.\r
707 * All channels need not be mapped, some can be free also.\r
708 */\r
709 unsigned int dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS];\r
710 } EDMA3_DRV_GblConfigParams;\r
711 \r
712 \r
713 \r
714 /**\struct EDMA3_DRV_InstanceInitConfig\r
715 * \brief Init-time Region Specific Configuration structure for\r
716 * EDMA3 Driver, to provide region specific Information.\r
717 *\r
718 * This configuration structure is used to specify which EDMA3 resources are\r
719 * owned and reserved by the EDMA3 Driver instance. This configuration\r
720 * structure is shadow region specific and will be provided by the user at\r
721 * run-time while calling EDMA3_DRV_open ().\r
722 *\r
723 * Owned resources:\r
724 * ****************\r
725 *\r
726 * EDMA3 Driver Instances are tied to different shadow regions and hence different\r
727 * masters. Regions could be:\r
728 *\r
729 * a) ARM,\r
730 * b) DSP,\r
731 * c) IMCOP (Imaging Co-processor) etc.\r
732 *\r
733 * User can assign each EDMA3 resource to a shadow region using this structure.\r
734 * In this way, user specifies which resources are owned by the specific EDMA3\r
735 * DRV Instance.\r
736 * This assignment should also ensure that the same resource is not assigned\r
737 * to more than one shadow regions (unless desired in that way). Any assignment\r
738 * not following the above mentioned approach may have catastrophic\r
739 * consequences.\r
740 *\r
741 *\r
742 * Reserved resources:\r
743 * *******************\r
744 *\r
745 * During EDMA3 DRV initialization, user can reserve some of the EDMA3 resources\r
746 * for future use, by specifying which resources to reserve in the configuration\r
747 * data structure. These (critical) resources are reserved in advance so that\r
748 * they should not be allocated to someone else and thus could be used in\r
749 * future for some specific purpose.\r
750 *\r
751 * User can request different EDMA3 resources using two methods:\r
752 * a) By passing the resource type and the actual resource id,\r
753 * b) By passing the resource type and ANY as resource id\r
754 *\r
755 * For e.g. to request DMA channel 31, user will pass 31 as the resource id.\r
756 * But to request ANY available DMA channel (mainly used for memory-to-memory\r
757 * data transfer operations), user will pass EDMA3_DRV_DMA_CHANNEL_ANY as the\r
758 * resource id.\r
759 *\r
760 * During initialization, user may have reserved some of the DMA channels for\r
761 * some specific purpose (mainly for peripherals using EDMA). These reserved\r
762 * DMA channels then will not be returned when user requests ANY as the\r
763 * resource id.\r
764 *\r
765 * Same logic applies for QDMA channels and TCCs.\r
766 *\r
767 * For PaRAM Set, there is one difference. If the DMA channels are one-to-one\r
768 * tied to their respective PaRAM Sets (i.e. user cannot 'choose' the PaRAM Set\r
769 * for a particular DMA channel), EDMA3 Driver automatically reserves all those\r
770 * PaRAM Sets which are tied to the DMA channels. Then those PaRAM Sets would\r
771 * not be returned when user requests for ANY PaRAM Set (specifically for\r
772 * linking purpose). This is done in order to avoid allocating the PaRAM Set,\r
773 * tied to a particular DMA channel, for linking purpose. If this constraint is\r
774 * not there, that DMA channel thus could not be used at all, because of the\r
775 * unavailability of the desired PaRAM Set.\r
776 */\r
777 typedef struct\r
778 {\r
779 /** PaRAM Sets owned by the EDMA3 Driver Instance. */\r
780 unsigned int ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS];\r
781 \r
782 /** DMA Channels owned by the EDMA3 Driver Instance. */\r
783 unsigned int ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];\r
784 \r
785 /** QDMA Channels owned by the EDMA3 Driver Instance. */\r
786 unsigned int ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];\r
787 \r
788 /** TCCs owned by the EDMA3 Driver Instance. */\r
789 unsigned int ownTccs[EDMA3_MAX_TCC_DWRDS];\r
790 \r
791 /**\r
792 * \brief Reserved PaRAM Sets\r
793 *\r
794 * PaRAM Sets reserved during initialization for future use. These will not\r
795 * be given when user requests for ANY available PaRAM Set for linking\r
796 * using 'EDMA3_DRV_LINK_CHANNEL' as channel id.\r
797 */\r
798 unsigned int resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS];\r
799 \r
800 /**\r
801 * \brief Reserved DMA channels\r
802 *\r
803 * DMA channels reserved during initialization for future use. These will\r
804 * not be given when user requests for ANY available DMA channel using\r
805 * 'EDMA3_DRV_DMA_CHANNEL_ANY' as channel id.\r
806 */\r
807 unsigned int resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];\r
808 \r
809 /**\r
810 * \brief Reserved QDMA channels\r
811 *\r
812 * QDMA channels reserved during initialization for future use. These will\r
813 * not be given when user requests for ANY available QDMA channel using\r
814 * 'EDMA3_DRV_QDMA_CHANNEL_ANY' as channel id.\r
815 */\r
816 unsigned int resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];\r
817 \r
818 /**\r
819 * \brief Reserved TCCs\r
820 *\r
821 * TCCs reserved during initialization for future use. These will not\r
822 * be given when user requests for ANY available TCC using\r
823 * 'EDMA3_DRV_TCC_ANY' as resource id.\r
824 */\r
825 unsigned int resvdTccs[EDMA3_MAX_TCC_DWRDS];\r
826 }EDMA3_DRV_InstanceInitConfig;\r
827 \r
828 \r
829 \r
830 /**\struct EDMA3_DRV_InitConfig\r
831 * \brief Used to Initialize the EDMA3 Driver Instance\r
832 *\r
833 * This configuration structure is used to initialize the EDMA3 DRV Instance.\r
834 * This configuration information is passed while opening the DRV instance.\r
835 */\r
836 typedef struct\r
837 {\r
838 /** Region Identification */\r
839 EDMA3_RM_RegionId regionId;\r
840 \r
841 /**\r
842 * It tells whether the EDMA3 DRV instance is Master or not. Only the shadow\r
843 * region associated with this master instance will receive the EDMA3\r
844 * interrupts (if enabled).\r
845 */\r
846 unsigned short isMaster;\r
847 \r
848 /**\r
849 * EDMA3 resources related shadow region specific information. Which all\r
850 * EDMA3 resources are owned and reserved by this particular instance are\r
851 * told in this configuration structure.\r
852 * User can also pass this structure as NULL. In that case, default static\r
853 * configuration would be taken from the platform specific configuration\r
854 * files (part of the Resource Manager), if available.\r
855 */\r
856 EDMA3_DRV_InstanceInitConfig *drvInstInitConfig;\r
857 \r
858 /**\r
859 * EDMA3 Driver Instance specific semaphore handle.\r
860 * Used to share resources (DMA/QDMA channels, PaRAM Sets, TCCs etc)\r
861 * among different users.\r
862 */\r
863 void *drvSemHandle;\r
864 \r
865 /**\r
866 * Instance wide global callback function to catch non-channel\r
867 * specific errors from the Channel controller. for eg, TCC\r
868 * error, queue threshold exceed error etc.\r
869 */\r
870 EDMA3_RM_GblErrCallback gblerrCb;\r
871 \r
872 /**\r
873 * Application data to be passed back to the global error callback\r
874 * function\r
875 */\r
876 void *gblerrData;\r
877 } EDMA3_DRV_InitConfig;\r
878 \r
879 \r
880 \r
881 /**\struct EDMA3_DRV_MiscParam\r
882 * \brief Used to specify the miscellaneous options during EDMA3 Driver\r
883 * Initialization.\r
884 *\r
885 * This configuration structure is used to specify some misc options\r
886 * while creating the Driver object. New options may also be added into this\r
887 * structure in future.\r
888 */\r
889 typedef struct {\r
890 /**\r
891 * In a multi-master system (for e.g. ARM + DSP), this option is used to\r
892 * distinguish between Master and Slave. Only the Master is allowed to\r
893 * program the global EDMA3 registers (like Queue priority, Queue water-\r
894 * mark level, error registers etc).\r
895 */\r
896 unsigned short isSlave;\r
897 \r
898 /** For future use **/\r
899 unsigned short param;\r
900 }EDMA3_DRV_MiscParam;\r
901 \r
902 \r
903 /**\r
904 * \brief Create EDMA3 Driver Object\r
905 *\r
906 * This API is used to create the EDMA3 Driver Object. It should be\r
907 * called only ONCE for each EDMA3 hardware instance.\r
908 *\r
909 * Init-time Configuration structure for EDMA3 hardware is provided to pass the\r
910 * SoC specific information. This configuration information could be provided\r
911 * by the user at init-time. In case user doesn't provide it, this information\r
912 * could be taken from the SoC specific configuration file\r
913 * edma3_<SOC_NAME>_cfg.c, in case it is available.\r
914 *\r
915 * This API clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR)\r
916 * and sets the TCs priorities and Event Queues' watermark levels, if the 'miscParam'\r
917 * argument is NULL. User can avoid these registers' programming (in some specific\r
918 * use cases) by SETTING the 'isSlave' field of 'EDMA3_RM_MiscParam' configuration\r
919 * structure and passing this structure as the third argument (miscParam).\r
920 *\r
921 * After successful completion of this API, Driver Object's state\r
922 * changes to EDMA3_DRV_CREATED from EDMA3_DRV_DELETED.\r
923 *\r
924 * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id\r
925 * (Hardware instance id, starting from 0).\r
926 * \param gblCfgParams [IN] SoC specific configuration structure for the\r
927 * EDMA3 Hardware.\r
928 * \param miscParam [IN] Misc configuration options provided in the\r
929 * structure 'EDMA3_DRV_MiscParam'.\r
930 * For default options, user can pass NULL\r
931 * in this argument.\r
932 *\r
933 * \return EDMA3_DRV_SOK or EDMA3_DRV Error code\r
934 */\r
935 EDMA3_DRV_Result EDMA3_DRV_create (unsigned int phyCtrllerInstId,\r
936 const EDMA3_DRV_GblConfigParams *gblCfgParams,\r
937 const void *miscParam);\r
938 \r
939 \r
940 /**\r
941 * \brief Delete EDMA3 Driver Object\r
942 *\r
943 * Use this API to delete the EDMA3 Driver Object. It should be called only\r
944 * ONCE for each EDMA3 hardware instance. It should be called ONLY after\r
945 * closing all the EDMA3 Driver Instances.\r
946 *\r
947 * This API is used to delete the EDMA3 Driver Object. It should be called\r
948 * once for each EDMA3 hardware instance, ONLY after closing all the\r
949 * previously opened EDMA3 Driver Instances.\r
950 *\r
951 * After successful completion of this API, Driver Object's state\r
952 * changes to EDMA3_DRV_DELETED.\r
953 *\r
954 * \param phyCtrllerInstId [IN] EDMA3 Phy Controller Instance Id (Hardware\r
955 * instance id, starting from 0).\r
956 * \param param [IN] For possible future use.\r
957 *\r
958 * \return EDMA3_DRV_SOK or EDMA3_DRV Error code\r
959 */\r
960 EDMA3_DRV_Result EDMA3_DRV_delete (unsigned int phyCtrllerInstId,\r
961 const void *param);\r
962 \r
963 \r
964 \r
965 /**\r
966 * \brief Open EDMA3 Driver Instance\r
967 *\r
968 * This API is used to open an EDMA3 Driver Instance. It could be\r
969 * called multiple times, for each possible EDMA3 shadow region. Maximum\r
970 * EDMA3_MAX_REGIONS instances are allowed for each EDMA3 hardware\r
971 * instance. Multiple instances on the same shadow region are NOT allowed.\r
972 *\r
973 * Also, only ONE Master Driver Instance is permitted. This master\r
974 * instance (and hence the region to which it belongs) will only receive the\r
975 * EDMA3 interrupts, if enabled.\r
976 *\r
977 * User could pass the instance specific configuration structure\r
978 * (initCfg.drvInstInitConfig) as a part of the 'initCfg' structure,\r
979 * during init-time. In case user doesn't provide it, this information could\r
980 * be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c,\r
981 * in case it is available.\r
982 *\r
983 * By default, this EDMA3 Driver instance will clear the PaRAM Sets while\r
984 * allocating them. To change the default behavior, user should use the IOCTL\r
985 * interface appropriately.\r
986 *\r
987 * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id (Hardware\r
988 * instance id, starting from 0).\r
989 * \param initCfg [IN] Used to Initialize the EDMA3 Driver\r
990 * Instance (Master or Slave).\r
991 * \param errorCode [OUT] Error code while opening DRV instance.\r
992 *\r
993 * \return EDMA3_DRV_Handle : If successfully opened, the API will return the\r
994 * associated driver's instance handle.\r
995 *\r
996 * \note This function disables the global interrupts (by calling API\r
997 * edma3OsProtectEntry with protection level\r
998 * EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data\r
999 * structures, to make it re-entrant.\r
1000 */\r
1001 EDMA3_DRV_Handle EDMA3_DRV_open (unsigned int phyCtrllerInstId,\r
1002 const EDMA3_DRV_InitConfig *initCfg,\r
1003 EDMA3_DRV_Result *errorCode);\r
1004 \r
1005 \r
1006 /**\r
1007 * \brief Close the EDMA3 Driver Instance.\r
1008 *\r
1009 * This API is used to close a previously opened EDMA3 Driver Instance.\r
1010 *\r
1011 * \param hEdma [IN] Handle to the previously opened EDMA3\r
1012 * Driver Instance.\r
1013 * \param param [IN] For possible future use\r
1014 *\r
1015 * \return EDMA3_DRV_SOK or EDMA3_DRV Error code\r
1016 *\r
1017 * \note This function disables the global interrupts (by calling API\r
1018 * edma3OsProtectEntry with protection level\r
1019 * EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data\r
1020 * structures, to make it re-entrant.\r
1021 */\r
1022 EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma,\r
1023 const void *param);\r
1024 \r
1025 \r
1026 \r
1027 /**\r
1028 * \defgroup Edma3DrvChannelSetup EDMA3 Driver Channel Setup\r
1029 *\r
1030 * Channel related Interface of the EDMA3 Driver\r
1031 *\r
1032 * @{\r
1033 */\r
1034 \r
1035 /* Defines for Logical Channel Values */\r
1036 /*---------------------------------------------------------------------------*/\r
1037 /**\r
1038 * Used to specify any available DMA Channel while requesting\r
1039 * one. Used in the API EDMA3_DRV_requestChannel().\r
1040 * DMA channel from the pool of (owned && non_reserved && available_right_now)\r
1041 * DMA channels will be chosen and returned.\r
1042 */\r
1043 #define EDMA3_DRV_DMA_CHANNEL_ANY 1002u\r
1044 \r
1045 /**\r
1046 * Used to specify any available QDMA Channel while requesting\r
1047 * one. Used in the API EDMA3_DRV_requestChannel().\r
1048 * QDMA channel from the pool of (owned && non_reserved && available_right_now)\r
1049 * QDMA channels will be chosen and returned.\r
1050 */\r
1051 #define EDMA3_DRV_QDMA_CHANNEL_ANY 1003u\r
1052 \r
1053 /**\r
1054 * Used to specify any available TCC while requesting\r
1055 * one. Used in the API EDMA3_DRV_requestChannel(), for\r
1056 * both DMA and QDMA channels.\r
1057 * TCC from the pool of (owned && non_reserved && available_right_now)\r
1058 * TCCs will be chosen and returned.\r
1059 */\r
1060 #define EDMA3_DRV_TCC_ANY 1004u\r
1061 \r
1062 /**\r
1063 * Used to specify any available PaRAM Set while requesting\r
1064 * one. Used in the API EDMA3_DRV_requestChannel(), for Link channels.\r
1065 * PaRAM Set from the pool of (owned && non_reserved && available_right_now)\r
1066 * PaRAM Sets will be chosen and returned.\r
1067 */\r
1068 #define EDMA3_DRV_LINK_CHANNEL 1005u\r
1069 /*---------------------------------------------------------------------------*/\r
1070 \r
1071 \r
1072 /**\r
1073 * \brief DMA Channels assigned to different Hardware Events.\r
1074 * They should be used while requesting a specific DMA channel.\r
1075 * One possible usage is to maintain a SoC specific file, which will\r
1076 * contain the mapping of these hardware events to the respective\r
1077 * peripherals for better understanding and lesser probability of\r
1078 * errors. Also, if any event associated with a particular peripheral\r
1079 * gets changed, only that SoC specific file needs to be changed.\r
1080 *\r
1081 * for eg, the sample SoC specific file "soc.h" can have these defines:\r
1082 *\r
1083 * #define EDMA3_DRV_HW_CHANNEL_MCBSP_TX EDMA3_DRV_HW_CHANNEL_EVENT_2\r
1084 * #define EDMA3_DRV_HW_CHANNEL_MCBSP_RX EDMA3_DRV_HW_CHANNEL_EVENT_3\r
1085 *\r
1086 * These defines will be used by the MCBSP driver. The same event\r
1087 * EDMA3_DRV_HW_CHANNEL_EVENT_2/3 could be mapped to some other\r
1088 * peripheral also.\r
1089 */\r
1090 typedef enum\r
1091 {\r
1092 /** Channel assigned to EDMA3 Event 0 */\r
1093 EDMA3_DRV_HW_CHANNEL_EVENT_0 = 0,\r
1094 /** Channel assigned to EDMA3 Event 1 */\r
1095 EDMA3_DRV_HW_CHANNEL_EVENT_1,\r
1096 /** Channel assigned to EDMA3 Event 2 */\r
1097 EDMA3_DRV_HW_CHANNEL_EVENT_2,\r
1098 /** Channel assigned to EDMA3 Event 3 */\r
1099 EDMA3_DRV_HW_CHANNEL_EVENT_3,\r
1100 /** Channel assigned to EDMA3 Event 4 */\r
1101 EDMA3_DRV_HW_CHANNEL_EVENT_4,\r
1102 /** Channel assigned to EDMA3 Event 5 */\r
1103 EDMA3_DRV_HW_CHANNEL_EVENT_5,\r
1104 /** Channel assigned to EDMA3 Event 6 */\r
1105 EDMA3_DRV_HW_CHANNEL_EVENT_6,\r
1106 /** Channel assigned to EDMA3 Event 7 */\r
1107 EDMA3_DRV_HW_CHANNEL_EVENT_7,\r
1108 /** Channel assigned to EDMA3 Event 8 */\r
1109 EDMA3_DRV_HW_CHANNEL_EVENT_8,\r
1110 /** Channel assigned to EDMA3 Event 9 */\r
1111 EDMA3_DRV_HW_CHANNEL_EVENT_9,\r
1112 /** Channel assigned to EDMA3 Event 10 */\r
1113 EDMA3_DRV_HW_CHANNEL_EVENT_10,\r
1114 /** Channel assigned to EDMA3 Event 11 */\r
1115 EDMA3_DRV_HW_CHANNEL_EVENT_11,\r
1116 /** Channel assigned to EDMA3 Event 12 */\r
1117 EDMA3_DRV_HW_CHANNEL_EVENT_12,\r
1118 /** Channel assigned to EDMA3 Event 13 */\r
1119 EDMA3_DRV_HW_CHANNEL_EVENT_13,\r
1120 /** Channel assigned to EDMA3 Event 14 */\r
1121 EDMA3_DRV_HW_CHANNEL_EVENT_14,\r
1122 /** Channel assigned to EDMA3 Event 15 */\r
1123 EDMA3_DRV_HW_CHANNEL_EVENT_15,\r
1124 /** Channel assigned to EDMA3 Event 16 */\r
1125 EDMA3_DRV_HW_CHANNEL_EVENT_16,\r
1126 /** Channel assigned to EDMA3 Event 17 */\r
1127 EDMA3_DRV_HW_CHANNEL_EVENT_17,\r
1128 /** Channel assigned to EDMA3 Event 18 */\r
1129 EDMA3_DRV_HW_CHANNEL_EVENT_18,\r
1130 /** Channel assigned to EDMA3 Event 19 */\r
1131 EDMA3_DRV_HW_CHANNEL_EVENT_19,\r
1132 /** Channel assigned to EDMA3 Event 20 */\r
1133 EDMA3_DRV_HW_CHANNEL_EVENT_20,\r
1134 /** Channel assigned to EDMA3 Event 21 */\r
1135 EDMA3_DRV_HW_CHANNEL_EVENT_21,\r
1136 /** Channel assigned to EDMA3 Event 22 */\r
1137 EDMA3_DRV_HW_CHANNEL_EVENT_22,\r
1138 /** Channel assigned to EDMA3 Event 23 */\r
1139 EDMA3_DRV_HW_CHANNEL_EVENT_23,\r
1140 /** Channel assigned to EDMA3 Event 24 */\r
1141 EDMA3_DRV_HW_CHANNEL_EVENT_24,\r
1142 /** Channel assigned to EDMA3 Event 25 */\r
1143 EDMA3_DRV_HW_CHANNEL_EVENT_25,\r
1144 /** Channel assigned to EDMA3 Event 26 */\r
1145 EDMA3_DRV_HW_CHANNEL_EVENT_26,\r
1146 /** Channel assigned to EDMA3 Event 27 */\r
1147 EDMA3_DRV_HW_CHANNEL_EVENT_27,\r
1148 /** Channel assigned to EDMA3 Event 28 */\r
1149 EDMA3_DRV_HW_CHANNEL_EVENT_28,\r
1150 /** Channel assigned to EDMA3 Event 29 */\r
1151 EDMA3_DRV_HW_CHANNEL_EVENT_29,\r
1152 /** Channel assigned to EDMA3 Event 30 */\r
1153 EDMA3_DRV_HW_CHANNEL_EVENT_30,\r
1154 /** Channel assigned to EDMA3 Event 31 */\r
1155 EDMA3_DRV_HW_CHANNEL_EVENT_31,\r
1156 /** Channel assigned to EDMA3 Event 32 */\r
1157 EDMA3_DRV_HW_CHANNEL_EVENT_32,\r
1158 /** Channel assigned to EDMA3 Event 33 */\r
1159 EDMA3_DRV_HW_CHANNEL_EVENT_33,\r
1160 /** Channel assigned to EDMA3 Event 34 */\r
1161 EDMA3_DRV_HW_CHANNEL_EVENT_34,\r
1162 /** Channel assigned to EDMA3 Event 35 */\r
1163 EDMA3_DRV_HW_CHANNEL_EVENT_35,\r
1164 /** Channel assigned to EDMA3 Event 36 */\r
1165 EDMA3_DRV_HW_CHANNEL_EVENT_36,\r
1166 /** Channel assigned to EDMA3 Event 37 */\r
1167 EDMA3_DRV_HW_CHANNEL_EVENT_37,\r
1168 /** Channel assigned to EDMA3 Event 38 */\r
1169 EDMA3_DRV_HW_CHANNEL_EVENT_38,\r
1170 /** Channel assigned to EDMA3 Event 39 */\r
1171 EDMA3_DRV_HW_CHANNEL_EVENT_39,\r
1172 /** Channel assigned to EDMA3 Event 40 */\r
1173 EDMA3_DRV_HW_CHANNEL_EVENT_40,\r
1174 /** Channel assigned to EDMA3 Event 41 */\r
1175 EDMA3_DRV_HW_CHANNEL_EVENT_41,\r
1176 /** Channel assigned to EDMA3 Event 42 */\r
1177 EDMA3_DRV_HW_CHANNEL_EVENT_42,\r
1178 /** Channel assigned to EDMA3 Event 43 */\r
1179 EDMA3_DRV_HW_CHANNEL_EVENT_43,\r
1180 /** Channel assigned to EDMA3 Event 44 */\r
1181 EDMA3_DRV_HW_CHANNEL_EVENT_44,\r
1182 /** Channel assigned to EDMA3 Event 45 */\r
1183 EDMA3_DRV_HW_CHANNEL_EVENT_45,\r
1184 /** Channel assigned to EDMA3 Event 46 */\r
1185 EDMA3_DRV_HW_CHANNEL_EVENT_46,\r
1186 /** Channel assigned to EDMA3 Event 47 */\r
1187 EDMA3_DRV_HW_CHANNEL_EVENT_47,\r
1188 /** Channel assigned to EDMA3 Event 48 */\r
1189 EDMA3_DRV_HW_CHANNEL_EVENT_48,\r
1190 /** Channel assigned to EDMA3 Event 49 */\r
1191 EDMA3_DRV_HW_CHANNEL_EVENT_49,\r
1192 /** Channel assigned to EDMA3 Event 50 */\r
1193 EDMA3_DRV_HW_CHANNEL_EVENT_50,\r
1194 /** Channel assigned to EDMA3 Event 51 */\r
1195 EDMA3_DRV_HW_CHANNEL_EVENT_51,\r
1196 /** Channel assigned to EDMA3 Event 52 */\r
1197 EDMA3_DRV_HW_CHANNEL_EVENT_52,\r
1198 /** Channel assigned to EDMA3 Event 53 */\r
1199 EDMA3_DRV_HW_CHANNEL_EVENT_53,\r
1200 /** Channel assigned to EDMA3 Event 54 */\r
1201 EDMA3_DRV_HW_CHANNEL_EVENT_54,\r
1202 /** Channel assigned to EDMA3 Event 55 */\r
1203 EDMA3_DRV_HW_CHANNEL_EVENT_55,\r
1204 /** Channel assigned to EDMA3 Event 56 */\r
1205 EDMA3_DRV_HW_CHANNEL_EVENT_56,\r
1206 /** Channel assigned to EDMA3 Event 57 */\r
1207 EDMA3_DRV_HW_CHANNEL_EVENT_57,\r
1208 /** Channel assigned to EDMA3 Event 58 */\r
1209 EDMA3_DRV_HW_CHANNEL_EVENT_58,\r
1210 /** Channel assigned to EDMA3 Event 59 */\r
1211 EDMA3_DRV_HW_CHANNEL_EVENT_59,\r
1212 /** Channel assigned to EDMA3 Event 60 */\r
1213 EDMA3_DRV_HW_CHANNEL_EVENT_60,\r
1214 /** Channel assigned to EDMA3 Event 61 */\r
1215 EDMA3_DRV_HW_CHANNEL_EVENT_61,\r
1216 /** Channel assigned to EDMA3 Event 62 */\r
1217 EDMA3_DRV_HW_CHANNEL_EVENT_62,\r
1218 /** Channel assigned to EDMA3 Event 63 */\r
1219 EDMA3_DRV_HW_CHANNEL_EVENT_63\r
1220 } EDMA3_DRV_HW_CHANNEL_EVENT;\r
1221 \r
1222 \r
1223 /**\r
1224 * \brief QDMA Channel defines\r
1225 * They should be used while requesting a specific QDMA channel.\r
1226 */\r
1227 /** QDMA Channel 0 */\r
1228 #define EDMA3_DRV_QDMA_CHANNEL_0 (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)\r
1229 /** QDMA Channel 1 */\r
1230 #define EDMA3_DRV_QDMA_CHANNEL_1 (EDMA3_DRV_QDMA_CHANNEL_0+1u)\r
1231 /** QDMA Channel 2 */\r
1232 #define EDMA3_DRV_QDMA_CHANNEL_2 (EDMA3_DRV_QDMA_CHANNEL_0+2u)\r
1233 /** QDMA Channel 3 */\r
1234 #define EDMA3_DRV_QDMA_CHANNEL_3 (EDMA3_DRV_QDMA_CHANNEL_0+3u)\r
1235 /** QDMA Channel 4 */\r
1236 #define EDMA3_DRV_QDMA_CHANNEL_4 (EDMA3_DRV_QDMA_CHANNEL_0+4u)\r
1237 /** QDMA Channel 5 */\r
1238 #define EDMA3_DRV_QDMA_CHANNEL_5 (EDMA3_DRV_QDMA_CHANNEL_0+5u)\r
1239 /** QDMA Channel 6 */\r
1240 #define EDMA3_DRV_QDMA_CHANNEL_6 (EDMA3_DRV_QDMA_CHANNEL_0+6u)\r
1241 /** QDMA Channel 7 */\r
1242 #define EDMA3_DRV_QDMA_CHANNEL_7 (EDMA3_DRV_QDMA_CHANNEL_0+7u)\r
1243 \r
1244 \r
1245 \r
1246 /**\r
1247 * \brief Request a DMA/QDMA/Link channel.\r
1248 *\r
1249 * Each channel (DMA/QDMA/Link) must be requested before initiating a DMA\r
1250 * transfer on that channel.\r
1251 *\r
1252 * This API is used to allocate a logical channel (DMA/QDMA/Link) along with\r
1253 * the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are\r
1254 * also allocated along with the requested channel. For Link channel, ONLY a\r
1255 * PaRAM Set is allocated.\r
1256 *\r
1257 * User can request a specific logical channel by passing the channel id in\r
1258 * 'pLCh'. Note that the channel id is the same as the actual resource id in\r
1259 * case of DMA channels. To allocate specific QDMA channels, user SHOULD use the\r
1260 * defines EDMA3_DRV_QDMA_CHANNEL_X mentioned above.\r
1261 *\r
1262 * User can also request ANY available logical channel also by specifying the\r
1263 * below mentioned values in '*pLCh':\r
1264 * a) EDMA3_DRV_DMA_CHANNEL_ANY: For DMA channels\r
1265 * b) EDMA3_DRV_QDMA_CHANNEL_ANY: For QDMA channels, and\r
1266 * c) EDMA3_DRV_LINK_CHANNEL: For Link channels. Normally user should use this\r
1267 * value to request link channels (PaRAM Sets used for linking purpose\r
1268 * only), unless he wants to use some specific link channels (PaRAM Sets)\r
1269 * which is also allowed.\r
1270 *\r
1271 * This API internally uses EDMA3_RM_allocResource () to allocate the desired\r
1272 * resources (DMA/QDMA channel, PaRAM Set and TCC).\r
1273 *\r
1274 * This API also registers a specific callback function against the allocated\r
1275 * TCC.\r
1276 *\r
1277 * For DMA/QDMA channels, after allocating all the EDMA3 resources, this API\r
1278 * sets the TCC field of the OPT PaRAM Word with the allocated TCC. It also sets\r
1279 * the event queue for the channel allocated. The event queue needs to be\r
1280 * specified by the user.\r
1281 *\r
1282 * For DMA channel, it also sets the DCHMAP register, if required.\r
1283 *\r
1284 * For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and\r
1285 * enables the QDMA channel by writing to the QEESR register.\r
1286 *\r
1287 * \param hEdma [IN] Handle to the previously opened Driver\r
1288 * Instance.\r
1289 * \param pLCh [IN/OUT] Requested logical channel id.\r
1290 * Examples:\r
1291 * - EDMA3_DRV_HW_CHANNEL_EVENT_0\r
1292 * - To request a DMA Master Channel\r
1293 * mapped to EDMA Event 0.\r
1294 *\r
1295 * - EDMA3_DRV_DMA_CHANNEL_ANY\r
1296 * - For requesting any DMA Master channel\r
1297 * with no event mapping.\r
1298 *\r
1299 * - EDMA3_DRV_QDMA_CHANNEL_ANY\r
1300 * - For requesting any QDMA Master channel\r
1301 *\r
1302 * - EDMA3_DRV_QDMA_CHANNEL_0\r
1303 * - For requesting the QDMA Channel 0.\r
1304 *\r
1305 * - EDMA3_DRV_LINK_CHANNEL\r
1306 * - For requesting a DMA Slave Channel,\r
1307 * - to be linked to some other Master\r
1308 * - channel.\r
1309 *\r
1310 * In case user passes a specific channel\r
1311 * Id, pLCh value is left unchanged. In\r
1312 * case user requests ANY available\r
1313 * resource, the allocated channel id is\r
1314 * returned in pLCh.\r
1315 *\r
1316 * \note To request a PaRAM Set for the purpose of\r
1317 * linking to another channel, call the function with\r
1318 *\r
1319 * *pLCh = EDMA3_DRV_LINK_CHANNEL;\r
1320 *\r
1321 * This function will update *pLCh with the allocated Link channel\r
1322 * handle. This handle could be DIFFERENT from the actual PaRAM Set\r
1323 * allocated by the Resource Manager internally. So user SHOULD NOT\r
1324 * assume the handle as the PaRAM Set Id.\r
1325 *\r
1326 * \param pTcc [IN/OUT] The channel number on which the\r
1327 * completion/error interrupt is generated.\r
1328 * Not used if user requested for a Link\r
1329 * channel.\r
1330 * Examples:\r
1331 * - EDMA3_DRV_HW_CHANNEL_EVENT_0\r
1332 * - To request TCC associated with\r
1333 * - DMA Master Channel mapped to EDMA\r
1334 * - event 0.\r
1335 *\r
1336 * - EDMA3_DRV_TCC_ANY\r
1337 * - For requesting any TCC with no\r
1338 * - channel mapping.\r
1339 * In case user passes a specific TCC\r
1340 * value, pTcc value is left unchanged.\r
1341 * In case user requests ANY available TCC,\r
1342 * the allocated one is returned in pTcc\r
1343 *\r
1344 * \param evtQueue [IN] Event Queue Number to which the channel\r
1345 * will be mapped (valid only for the\r
1346 * Master Channel (DMA/QDMA) request)\r
1347 *\r
1348 * \param tccCb [IN] TCC callback - caters to channel-\r
1349 * specific events like "Event Miss Error"\r
1350 * or "Transfer Complete"\r
1351 *\r
1352 * \param cbData [IN] Data which will be passed directly to\r
1353 * the tccCb callback function\r
1354 *\r
1355 * \return EDMA3_DRV_SOK or EDMA3_DRV Error code\r
1356 *\r
1357 * \note This function internally uses EDMA3 Resource Manager, which\r
1358 * acquires a RM Instance specific semaphore\r
1359 * to prevent simultaneous access to the global pool of resources.\r
1360 * It also disables the global interrupts while modifying\r
1361 * the global CC registers.\r
1362 * It is re-entrant, but SHOULD NOT be called from the user callback\r
1363 * function (ISR context).\r
1364 */\r
1365 EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,\r
1366 unsigned int *pLCh,\r
1367 unsigned int *pTcc,\r
1368 EDMA3_RM_EventQueue evtQueue,\r
1369 EDMA3_RM_TccCallback tccCb,\r
1370 void *cbData);\r
1371 \r
1372 \r
1373 /**\r
1374 * \brief Free the specified channel (DMA/QDMA/Link) and its associated\r
1375 * resources (PaRAM Set, TCC etc) and removes various mappings.\r
1376 *\r
1377 * This API internally uses EDMA3_RM_freeResource () to free the desired\r
1378 * resources.\r
1379 *\r
1380 * For Link channels, this API only frees the associated PaRAM Set.\r
1381 *\r
1382 * For DMA/QDMA channels, it does the following operations:\r
1383 * a) Disable any ongoing transfer on the channel,\r
1384 * b) Unregister the TCC Callback function and disable the interrupts,\r
1385 * c) Remove the channel to Event Queue mapping,\r
1386 * d) For DMA channels, clear the DCHMAP register, if available\r
1387 * e) For QDMA channels, clear the QCHMAP register,\r
1388 * f) Frees the DMA/QDMA channel in the end.\r
1389 *\r
1390 * \param hEdma [IN] Handle to the EDMA Driver Instance.\r
1391 * \param channelId [IN] Logical Channel number to be freed.\r
1392 *\r
1393 * \return EDMA3_DRV_SOK or EDMA3_DRV Error code\r
1394 *\r
1395 * \note This function disables the global interrupts while modifying\r
1396 * the global CC registers and while modifying global data structures,\r
1397 * to prevent simultaneous access to the global pool of resources.\r
1398 * It internally calls EDMA3_RM_freeResource () for resource\r
1399 * de-allocation. It is re-entrant.\r
1400 */\r
1401 EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,\r
1402 unsigned int channelId);\r
1403 \r
1404 \r
1405 \r
1406 /**\r
1407 * \brief Clears Event Register and Error Register for a specific\r
1408 * DMA channel and brings back EDMA3 to its initial state.\r
1409 *\r
1410 * This API clears the Event register, Event Miss register Event Enable\r
1411 * register for a specific DMA channel. It also clears the CC Error register.\r
1412 *\r
1413 * \param hEdma [IN] Handle to the EDMA Driver Instance.\r
1414 * \param channelId [IN] DMA Channel needs to be cleaned.\r
1415 *\r
1416 * \return EDMA3_DRV_SOK or EDMA3_DRV Error code\r
1417 *\r
1418 * \note This function is re-entrant for unique channelId values. It is non-\r
1419 * re-entrant for same channelId value.\r
1420 */\r
1421 EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma,\r
1422 unsigned int channelId);\r
1423 \r
1424 \r
1425 /**\r
1426 * \brief Link two logical channels.\r
1427 *\r
1428 * This API is used to link two previously allocated logical (DMA/QDMA/Link)\r
1429 * channels.\r
1430 *\r
1431 * It sets the Link field of the PaRAM set associated with first logical\r
1432 * channel (lCh1) to point it to the PaRAM set associated with second logical\r
1433 * channel (lCh2).\r
1434 *\r
1435 * It also sets the TCC field of PaRAM set associated with second logical\r
1436 * channel to the same as that of the first logical channel.\r
1437 *\r
1438 * After linking the channels, user should not update any PaRAM Set of the\r
1439 * channel.\r
1440 *\r
1441 * \param hEdma [IN] Handle to the EDMA Driver Instance.\r
1442 * \param lCh1 [IN] Logical Channel to which particular channel\r
1443 * will be linked.\r
1444 * \param lCh2 [IN] Logical Channel which needs to be linked to\r
1445 * the first channel.\r
1446 * After the transfer based on the PaRAM set\r
1447 * of lCh1 is over, the PaRAM set of lCh2 will\r
1448 * be copied to the PaRAM set of lCh1 and\r
1449 * transfer will resume.\r
1450 * For DMA channels, another sync event is\r
1451 * required to initiate the transfer on the\r
1452 * Link channel.\r
1453 *\r
1454 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
1455 *\r
1456 * \note This function is re-entrant for unique lCh1 & lCh2 values. It is\r
1457 * non-re-entrant for same lCh1 & lCh2 values.\r
1458 */\r
1459 EDMA3_DRV_Result EDMA3_DRV_linkChannel ( EDMA3_DRV_Handle hEdma,\r
1460 unsigned int lCh1,\r
1461 unsigned int lCh2);\r
1462 \r
1463 \r
1464 \r
1465 /**\r
1466 * \brief Unlink the channel from the earlier linked logical channel.\r
1467 *\r
1468 * This function breaks the link between the specified\r
1469 * channel and the earlier linked logical channel\r
1470 * by clearing the Link Address field.\r
1471 *\r
1472 * \param hEdma [IN] Handle to the EDMA Driver Instance.\r
1473 * \param lCh [IN] Channel for which linking has to be removed\r
1474 *\r
1475 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
1476 *\r
1477 * \note This function is re-entrant for unique lCh values. It is non-\r
1478 * re-entrant for same lCh value.\r
1479 */\r
1480 EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma,\r
1481 unsigned int lCh);\r
1482 \r
1483 /* @} Edma3DrvChannelSetup */\r
1484 \r
1485 \r
1486 \r
1487 /**\r
1488 * \defgroup Edma3DrvTransferSetupType EDMA3 Driver Typical EDMA Transfer Setup\r
1489 *\r
1490 * The typical EDMA transfer related Interface of the EDMA3 Driver\r
1491 *\r
1492 * @{\r
1493 */\r
1494 \r
1495 /**\r
1496 * \brief OPT Field Offset.\r
1497 *\r
1498 * Use this enum to set or get any of the\r
1499 * Fields within an OPT of a Parameter RAM set.\r
1500 */\r
1501 typedef enum\r
1502 {\r
1503 /**\r
1504 * Source addressing mode (INCR / FIFO)\r
1505 * (Bit 0)\r
1506 */\r
1507 EDMA3_DRV_OPT_FIELD_SAM = 0,\r
1508 \r
1509 /**\r
1510 * Destination addressing mode (INCR / FIFO)\r
1511 * (Bit 1)\r
1512 */\r
1513 EDMA3_DRV_OPT_FIELD_DAM = 1,\r
1514 \r
1515 /**\r
1516 * Transfer synchronization dimension (A-synchronized / AB-synchronized)\r
1517 * (Bit 2)\r
1518 */\r
1519 EDMA3_DRV_OPT_FIELD_SYNCDIM = 2,\r
1520 \r
1521 /**\r
1522 * The STATIC field\r
1523 * PaRAM set is static/non-static?\r
1524 * (Bit 3)\r
1525 */\r
1526 EDMA3_DRV_OPT_FIELD_STATIC = 3,\r
1527 \r
1528 /**\r
1529 * FIFO Width. Applies if either SAM or DAM is set to FIFO mode.\r
1530 * (Bitfield 8-10)\r
1531 */\r
1532 EDMA3_DRV_OPT_FIELD_FWID = 4,\r
1533 \r
1534 /**\r
1535 * Transfer complete code mode. Indicates the point at which a\r
1536 * transfer is considered completed for chaining and interrupt\r
1537 * generation.\r
1538 * (Bit 11)\r
1539 */\r
1540 EDMA3_DRV_OPT_FIELD_TCCMODE = 5,\r
1541 \r
1542 /**\r
1543 * Transfer Complete Code (TCC).\r
1544 * This 6-bit code is used to set the relevant bit in chaining enable\r
1545 * register (CER[TCC]/CERH[TCC]) for chaining or in interrupt pending\r
1546 * register (IPR[TCC]/IPRH[TCC]) for interrupts.\r
1547 * (Bitfield 12-17)\r
1548 */\r
1549 EDMA3_DRV_OPT_FIELD_TCC = 6,\r
1550 \r
1551 /**\r
1552 * Transfer complete interrupt enable/disable.\r
1553 * (Bit 20)\r
1554 */\r
1555 EDMA3_DRV_OPT_FIELD_TCINTEN = 7,\r
1556 \r
1557 /**\r
1558 * Intermediate transfer complete interrupt enable/disable.\r
1559 * (Bit 21)\r
1560 */\r
1561 EDMA3_DRV_OPT_FIELD_ITCINTEN = 8,\r
1562 \r
1563 /**\r
1564 * Transfer complete chaining enable/disable\r
1565 * (Bit 22)\r
1566 */\r
1567 EDMA3_DRV_OPT_FIELD_TCCHEN = 9,\r
1568 \r
1569 /**\r
1570 * Intermediate transfer completion chaining enable/disable\r
1571 * (Bit 23)\r
1572 */\r
1573 EDMA3_DRV_OPT_FIELD_ITCCHEN = 10\r
1574 \r
1575 } EDMA3_DRV_OptField;\r
1576 \r
1577 \r
1578 /**\r
1579 * \brief EDMA Addressing modes\r
1580 *\r
1581 * The EDMA3 TC supports two addressing modes\r
1582 * -# Increment transfer\r
1583 * -# FIFO transfer\r
1584 *\r
1585 * The SAM (Source Addressing Mode) and the DAM (Destination Addressing Mode)\r
1586 * can be independently set to either of the two via the OPT register.\r
1587 *\r
1588 */\r
1589 typedef enum\r
1590 {\r
1591 /**\r
1592 * Increment (INCR) mode. Source addressing within an array increments.\r
1593 * Source is not a FIFO.\r
1594 */\r
1595 EDMA3_DRV_ADDR_MODE_INCR = 0,\r
1596 \r
1597 /**\r
1598 * FIFO mode. Source addressing within an array wraps around upon\r
1599 * reaching FIFO width.\r
1600 */\r
1601 EDMA3_DRV_ADDR_MODE_FIFO = 1\r
1602 \r
1603 } EDMA3_DRV_AddrMode;\r
1604 \r
1605 \r
1606 \r
1607 /**\r
1608 * \brief EDMA Transfer Synchronization type.\r
1609 *\r
1610 * Two types of Synchronization of transfers are possible\r
1611 * -# A Synchronized\r
1612 * -# AB Syncronized\r
1613 * - A Sync\r
1614 * -# Each Array is submitted as one TR\r
1615 * -# (BCNT*CCNT) number of sync events are needed to completely service\r
1616 * a PaRAM set. (Where BCNT = Num of Arrays in a Frame;\r
1617 * CCNT = Num of Frames in a Block)\r
1618 * -# (S/D)CIDX = (Addr of First array in next frame)\r
1619 * minus (Addr of Last array in present frame)\r
1620 * (Where CIDX is the Inter-Frame index)\r
1621 *\r
1622 * - AB Sync\r
1623 * -# Each Frame is submitted as one TR\r
1624 * -# Only CCNT number of sync events are needed to completely service\r
1625 * a PaRAM set\r
1626 * -# (S/D)CIDX = (Addr of First array in next frame)\r
1627 * minus (Addr of First array of present frame)\r
1628 *\r
1629 * \note ABC sync transfers can be achieved logically by chaining multiple\r
1630 * AB sync transfers\r
1631 *\r
1632 */\r
1633 typedef enum\r
1634 {\r
1635 /**\r
1636 * A-synchronized.\r
1637 * Each event triggers the transfer of a single array of ACNT bytes\r
1638 */\r
1639 EDMA3_DRV_SYNC_A = 0 ,\r
1640 \r
1641 /**\r
1642 * AB-synchronized.\r
1643 * Each event triggers the transfer of BCNT arrays of ACNT bytes\r
1644 */\r
1645 EDMA3_DRV_SYNC_AB = 1\r
1646 \r
1647 } EDMA3_DRV_SyncType;\r
1648 \r
1649 \r
1650 \r
1651 /**\r
1652 * \brief True/False: PaRAM set is Static or not. A Static PaRAM set\r
1653 * is updated or linked after TR is submitted.\r
1654 */\r
1655 typedef enum\r
1656 {\r
1657 /**\r
1658 * PaRAM set is not Static. PaRAM set is updated or linked\r
1659 * after TR is submitted. A value of 0 should be used for\r
1660 * DMA channels and for nonfinal transfers in a linked list\r
1661 * of QDMA transfers\r
1662 */\r
1663 EDMA3_DRV_STATIC_DIS = 0,\r
1664 \r
1665 /**\r
1666 * PaRAM set is Static. PaRAM set is not updated or linked\r
1667 * after TR is submitted. A value of 1 should be used for\r
1668 * isolated QDMA transfers or for the final transfer in a\r
1669 * linked list of QDMA transfers.\r
1670 */\r
1671 EDMA3_DRV_STATIC_EN = 1\r
1672 } EDMA3_DRV_StaticMode;\r
1673 \r
1674 \r
1675 /**\r
1676 * \brief EDMA3 FIFO width.\r
1677 *\r
1678 * The user can set the width of the FIFO using this enum.\r
1679 * This is done via the OPT register.\r
1680 * This is valid only if the EDMA3_DRV_ADDR_MODE_FIFO value is used for the\r
1681 * enum EDMA3_DRV_AddrMode.\r
1682 */\r
1683 typedef enum\r
1684 {\r
1685 /** FIFO width is 8-bit. */\r
1686 EDMA3_DRV_W8BIT = 0,\r
1687 \r
1688 /** FIFO width is 16-bit. */\r
1689 EDMA3_DRV_W16BIT = 1,\r
1690 \r
1691 /** FIFO width is 32-bit. */\r
1692 EDMA3_DRV_W32BIT = 2,\r
1693 \r
1694 /** FIFO width is 64-bit. */\r
1695 EDMA3_DRV_W64BIT = 3,\r
1696 \r
1697 /** FIFO width is 128-bit. */\r
1698 EDMA3_DRV_W128BIT = 4,\r
1699 \r
1700 /** FIFO width is 256-bit. */\r
1701 EDMA3_DRV_W256BIT = 5\r
1702 \r
1703 } EDMA3_DRV_FifoWidth;\r
1704 \r
1705 \r
1706 \r
1707 \r
1708 /**\r
1709 * \brief Transfer complete code mode.\r
1710 * Indicates the point at which a transfer is considered completed for\r
1711 * chaining and interrupt generation\r
1712 */\r
1713 typedef enum\r
1714 {\r
1715 /** A transfer is considered completed after transfer of data */\r
1716 EDMA3_DRV_TCCMODE_NORMAL = 0,\r
1717 \r
1718 /**\r
1719 * A transfer is considered completed after the EDMA3CC submits a TR\r
1720 * to the EDMA3TC. TC may still be transferring data when interrupt/chain\r
1721 * is triggered.\r
1722 */\r
1723 EDMA3_DRV_TCCMODE_EARLY = 1\r
1724 } EDMA3_DRV_TccMode;\r
1725 \r
1726 \r
1727 /**\r
1728 * \brief Transfer complete interrupt enable.\r
1729 */\r
1730 typedef enum\r
1731 {\r
1732 /** Transfer complete interrupt is disabled */\r
1733 EDMA3_DRV_TCINTEN_DIS = 0,\r
1734 \r
1735 /**\r
1736 * Transfer complete interrupt is enabled.\r
1737 * When enabled, the interrupt pending register (IPR/IPRH) bit is set on\r
1738 * transfer completion (upon completion of the final TR in the PaRAM set).\r
1739 * The bit (position) set in IPR or IPRH is the TCC value specified. In\r
1740 * order to generate a completion interrupt to the CPU, the corresponding\r
1741 * IER [TCC] / IERH [TCC] bit must be set to 1.\r
1742 */\r
1743 EDMA3_DRV_TCINTEN_EN = 1\r
1744 } EDMA3_DRV_TcintEn;\r
1745 \r
1746 \r
1747 /**\r
1748 * \brief Intermediate Transfer complete interrupt enable.\r
1749 */\r
1750 typedef enum\r
1751 {\r
1752 /** Intermediate Transfer complete interrupt is disabled */\r
1753 EDMA3_DRV_ITCINTEN_DIS = 0,\r
1754 \r
1755 /**\r
1756 * Intermediate transfer complete interrupt is enabled.\r
1757 * When enabled, the interrupt pending register (IPR/IPRH) bit is set on\r
1758 * every intermediate transfer completion (upon completion of every\r
1759 * intermediate TR in the PaRAM set, except the final TR in the PaRAM set).\r
1760 * The bit (position) set in IPR or IPRH is the TCC value specified. In\r
1761 * order to generate a completion interrupt to the CPU, the corresponding\r
1762 * IER [TCC] / IERH [TCC] bit must be set to 1.\r
1763 */\r
1764 EDMA3_DRV_ITCINTEN_EN = 1\r
1765 } EDMA3_DRV_ItcintEn;\r
1766 \r
1767 \r
1768 /**\r
1769 * \brief Transfer complete chaining enable.\r
1770 */\r
1771 typedef enum\r
1772 {\r
1773 /** Transfer complete chaining is disabled */\r
1774 EDMA3_DRV_TCCHEN_DIS = 0,\r
1775 \r
1776 /**\r
1777 * Transfer complete chaining is enabled.\r
1778 * When enabled, the chained event register (CER/CERH) bit is set on final\r
1779 * chained transfer completion (upon completion of the final / last TR in\r
1780 * the PaRAM set). The bit (position) set in CER or CERH is the TCC value\r
1781 * specified.\r
1782 */\r
1783 EDMA3_DRV_TCCHEN_EN = 1\r
1784 } EDMA3_DRV_TcchEn;\r
1785 \r
1786 \r
1787 /**\r
1788 * \brief Intermediate Transfer complete chaining enable.\r
1789 */\r
1790 typedef enum\r
1791 {\r
1792 /** Intermediate Transfer complete chaining is disabled */\r
1793 EDMA3_DRV_ITCCHEN_DIS = 0,\r
1794 \r
1795 /**\r
1796 * Intermediate transfer complete chaining is enabled.\r
1797 * When enabled, the chained event register (CER/CERH) bit is set on every\r
1798 * intermediate chained transfer completion (upon completion of every\r
1799 * intermediate TR in the PaRAM set, except the final TR in the PaRAM set).\r
1800 * The bit (position) set in CER or CERH is the TCC value specified.\r
1801 */\r
1802 EDMA3_DRV_ITCCHEN_EN = 1\r
1803 } EDMA3_DRV_ItcchEn;\r
1804 \r
1805 \r
1806 /**\r
1807 * \brief Structure to be used to configure interrupt generation\r
1808 * and chaining options.\r
1809 */\r
1810 typedef struct\r
1811 {\r
1812 /** Transfer complete chaining enable */\r
1813 EDMA3_DRV_TcchEn tcchEn;\r
1814 \r
1815 /** Intermediate Transfer complete chaining enable */\r
1816 EDMA3_DRV_ItcchEn itcchEn;\r
1817 \r
1818 /** Transfer complete interrupt enable */\r
1819 EDMA3_DRV_TcintEn tcintEn;\r
1820 \r
1821 /** Intermediate Transfer complete interrupt enable */\r
1822 EDMA3_DRV_ItcintEn itcintEn;\r
1823 } EDMA3_DRV_ChainOptions;\r
1824 \r
1825 \r
1826 \r
1827 /**\r
1828 * \brief Set a particular OPT field in the PaRAM set associated with the\r
1829 * logical channel 'lCh'.\r
1830 *\r
1831 * This API can be used to set various optional parameters for an EDMA3\r
1832 * transfer. Like enable/disable completion interrupts, enable/disable chaining,\r
1833 * setting the transfer mode (A/AB Sync), setting the FIFO width etc.\r
1834 *\r
1835 * \param hEdma [IN] Handle to the EDMA Driver Instance.\r
1836 * \param lCh [IN] Logical Channel, bound to which\r
1837 * PaRAM set OPT field needs to be set.\r
1838 * \param optField [IN] The particular field of OPT Word\r
1839 * that needs setting\r
1840 * \param newOptFieldVal [IN] The new OPT field value\r
1841 *\r
1842 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
1843 *\r
1844 * \note This function is re-entrant for unique lCh values. It is non-\r
1845 * re-entrant for same lCh value.\r
1846 */\r
1847 EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma,\r
1848 unsigned int lCh,\r
1849 EDMA3_DRV_OptField optField,\r
1850 unsigned int newOptFieldVal);\r
1851 \r
1852 \r
1853 /**\r
1854 * \brief Get a particular OPT field in the PaRAM set associated with the\r
1855 * logical channel 'lCh'.\r
1856 *\r
1857 * This API can be used to read various optional parameters for an EDMA3\r
1858 * transfer. Like enable/disable completion interrupts, enable/disable chaining,\r
1859 * setting the transfer mode (A/AB Sync), setting the FIFO width etc.\r
1860 *\r
1861 * \param hEdma [IN] Handle to the EDMA Driver Instance.\r
1862 * \param lCh [IN] Logical Channel, bound to which\r
1863 * PaRAM set OPT field is required.\r
1864 * \param optField [IN] The particular field of OPT Word\r
1865 * that is needed\r
1866 * \param optFieldVal [IN/OUT] Value of the OPT field\r
1867 *\r
1868 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
1869 *\r
1870 * \note This function is re-entrant.\r
1871 */\r
1872 EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma,\r
1873 unsigned int lCh,\r
1874 EDMA3_DRV_OptField optField,\r
1875 unsigned int *optFieldVal);\r
1876 \r
1877 \r
1878 /**\r
1879 * \brief DMA source parameters setup\r
1880 *\r
1881 * It is used to program the source address, source side addressing mode\r
1882 * (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.\r
1883 *\r
1884 * In FIFO Addressing mode, memory location must be 32 bytes aligned.\r
1885 *\r
1886 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
1887 * \param lCh [IN] Logical Channel for which the source parameters\r
1888 * are to be configured\r
1889 * \param srcAddr [IN] Source address\r
1890 * \param addrMode [IN] Address mode [FIFO or Increment]\r
1891 * \param fifoWidth [IN] Width of FIFO (Valid only if addrMode is FIFO)\r
1892 * -# 0 - 8 bit\r
1893 * -# 1 - 16 bit\r
1894 * -# 2 - 32 bit\r
1895 * -# 3 - 64 bit\r
1896 * -# 4 - 128 bit\r
1897 * -# 5 - 256 bit\r
1898 *\r
1899 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
1900 *\r
1901 * \note This function is re-entrant for unique lCh values. It is non-\r
1902 * re-entrant for same lCh value.\r
1903 */\r
1904 EDMA3_DRV_Result EDMA3_DRV_setSrcParams ( EDMA3_DRV_Handle hEdma,\r
1905 unsigned int lCh,\r
1906 unsigned int srcAddr,\r
1907 EDMA3_DRV_AddrMode addrMode,\r
1908 EDMA3_DRV_FifoWidth fifoWidth);\r
1909 \r
1910 \r
1911 \r
1912 /**\r
1913 * \brief DMA Destination parameters setup\r
1914 *\r
1915 * It is used to program the destination address, destination side addressing\r
1916 * mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.\r
1917 *\r
1918 * In FIFO Addressing mode, memory location must be 32 bytes aligned.\r
1919 *\r
1920 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
1921 * \param lCh [IN] Logical Channel for which the destination\r
1922 * parameters are to be configured\r
1923 * \param destAddr [IN] Destination address\r
1924 * \param addrMode [IN] Address mode [FIFO or Increment]\r
1925 * \param fifoWidth [IN] Width of FIFO (Valid only if addrMode is FIFO)\r
1926 * -# 0 - 8 bit\r
1927 * -# 1 - 16 bit\r
1928 * -# 2 - 32 bit\r
1929 * -# 3 - 64 bit\r
1930 * -# 4 - 128 bit\r
1931 * -# 5 - 256 bit\r
1932 *\r
1933 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
1934 *\r
1935 * \note This function is re-entrant for unique lCh values. It is non-\r
1936 * re-entrant for same lCh value.\r
1937 */\r
1938 EDMA3_DRV_Result EDMA3_DRV_setDestParams ( EDMA3_DRV_Handle hEdma,\r
1939 unsigned int lCh,\r
1940 unsigned int destAddr,\r
1941 EDMA3_DRV_AddrMode addrMode,\r
1942 EDMA3_DRV_FifoWidth fifoWidth );\r
1943 \r
1944 \r
1945 \r
1946 /**\r
1947 * \brief DMA source index setup\r
1948 *\r
1949 * It is used to program the source B index and source C index.\r
1950 *\r
1951 * SRCBIDX is a 16-bit signed value (2s complement) used for source address\r
1952 * modification between each array in the 2nd dimension. Valid values for\r
1953 * SRCBIDX are between -32768 and 32767. It provides a byte address offset\r
1954 * from the beginning of the source array to the beginning of the next source\r
1955 * array. It applies to both A-synchronized and AB-synchronized transfers.\r
1956 *\r
1957 * SRCCIDX is a 16-bit signed value (2s complement) used for source address\r
1958 * modification in the 3rd dimension. Valid values for SRCCIDX are between\r
1959 * -32768 and 32767. It provides a byte address offset from the beginning of\r
1960 * the current array (pointed to by SRC address) to the beginning of the first\r
1961 * source array in the next frame. It applies to both A-synchronized and\r
1962 * AB-synchronized transfers. Note that when SRCCIDX is applied, the current\r
1963 * array in an A-synchronized transfer is the last array in the frame, while\r
1964 * the current array in an AB-synchronized transfer is the first array in the\r
1965 * frame.\r
1966 *\r
1967 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
1968 * \param lCh [IN] Logical Channel for which source\r
1969 * indices are to be configured\r
1970 * \param srcBIdx [IN] Source B index\r
1971 * \param srcCIdx [IN] Source C index\r
1972 *\r
1973 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
1974 *\r
1975 * \note This function is re-entrant for unique lCh values. It is non-\r
1976 * re-entrant for same lCh value.\r
1977 */\r
1978 EDMA3_DRV_Result EDMA3_DRV_setSrcIndex ( EDMA3_DRV_Handle hEdma,\r
1979 unsigned int lCh,\r
1980 int srcBIdx,\r
1981 int srcCIdx );\r
1982 \r
1983 \r
1984 \r
1985 /**\r
1986 * \brief DMA destination index setup\r
1987 *\r
1988 * It is used to program the destination B index and destination C index.\r
1989 *\r
1990 * DSTBIDX is a 16-bit signed value (2s complement) used for destination\r
1991 * address modification between each array in the 2nd dimension. Valid values\r
1992 * for DSTBIDX are between -32768 and 32767. It provides a byte address offset\r
1993 * from the beginning of the destination array to the beginning of the next\r
1994 * destination array within the current frame. It applies to both\r
1995 * A-synchronized and AB-synchronized transfers.\r
1996 *\r
1997 * DSTCIDX is a 16-bit signed value (2s complement) used for destination address\r
1998 * modification in the 3rd dimension. Valid values are between -32768 and 32767.\r
1999 * It provides a byte address offset from the beginning of the current array\r
2000 * (pointed to by DST address) to the beginning of the first destination array\r
2001 * TR in the next frame. It applies to both A-synchronized and AB-synchronized\r
2002 * transfers. Note that when DSTCIDX is applied, the current array in an\r
2003 * A-synchronized transfer is the last array in the frame, while the current\r
2004 * array in a AB-synchronized transfer is the first array in the frame\r
2005 *\r
2006 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
2007 * \param lCh [IN] Logical Channel for which dest\r
2008 * indices are to be configured\r
2009 * \param destBIdx [IN] Destination B index\r
2010 * \param destCIdx [IN] Destination C index\r
2011 *\r
2012 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2013 *\r
2014 * \note This function is re-entrant for unique lCh values. It is non-\r
2015 * re-entrant for same lCh value.\r
2016 */\r
2017 EDMA3_DRV_Result EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma,\r
2018 unsigned int lCh,\r
2019 int destBIdx,\r
2020 int destCIdx);\r
2021 \r
2022 \r
2023 /**\r
2024 * \brief DMA transfer parameters setup\r
2025 *\r
2026 * It is used to specify the various counts (ACNT, BCNT and CCNT), B count\r
2027 * reload and the synchronization type\r
2028 *\r
2029 * ACNT represents the number of bytes within the 1st dimension of a transfer.\r
2030 * ACNT is a 16-bit unsigned value with valid values between 0 and 65535.\r
2031 * Therefore, the maximum number of bytes in an array is 65535 bytes (64K - 1\r
2032 * bytes). ACNT must be greater than or equal to 1 for a TR to be submitted to\r
2033 * EDMA3 Transfer Controller.\r
2034 * An ACNT equal to 0 is considered either a null or dummy transfer. A dummy or\r
2035 * null transfer generates a completion code depending on the settings of the\r
2036 * completion bit fields in OPT.\r
2037 \r
2038 * BCNT is a 16-bit unsigned value that specifies the number of arrays of length\r
2039 * ACNT. For normal operation, valid values for BCNT are between 1 and 65535.\r
2040 * Therefore, the maximum number of arrays in a frame is 65535 (64K - 1 arrays).\r
2041 * A BCNT equal to 0 is considered either a null or dummy transfer. A dummy or\r
2042 * null transfer generates a completion code depending on the settings of the\r
2043 * completion bit fields in OPT.\r
2044 *\r
2045 * CCNT is a 16-bit unsigned value that specifies the number of frames in a\r
2046 * block. Valid values for CCNT are between 1 and 65535. Therefore, the maximum\r
2047 * number of frames in a block is 65535 (64K - 1 frames). A CCNT equal to 0 is\r
2048 * considered either a null or dummy transfer. A dummy or null transfer\r
2049 * generates a completion code depending on the settings of the completion bit\r
2050 * fields in OPT. A CCNT value of 0 is considered either a null or dummy\r
2051 * transfer.\r
2052 *\r
2053 * BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the\r
2054 * last array in the 2nd dimension is transferred. This field is only used for\r
2055 * A-synchronized transfers. In this case, the EDMA3CC decrements the BCNT\r
2056 * value by 1 on each TR submission. When BCNT (conceptually) reaches 0, the\r
2057 * EDMA3CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT\r
2058 * value.\r
2059 * For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the\r
2060 * EDMA3TC decrements BCNT appropriately. For AB-synchronized transfers,\r
2061 * BCNTRLD is not used.\r
2062 \r
2063 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
2064 * \param lCh [IN] Logical Channel for which transfer\r
2065 * parameters are to be configured\r
2066 * \param aCnt [IN] Count for 1st Dimension.\r
2067 * \param bCnt [IN] Count for 2nd Dimension.\r
2068 * \param cCnt [IN] Count for 3rd Dimension.\r
2069 * \param bCntReload [IN] Reload value for bCnt.\r
2070 * \param syncType [IN] Transfer synchronization dimension\r
2071 * 0: A-synchronized. Each event triggers\r
2072 * the transfer of a single array of\r
2073 * ACNT bytes.\r
2074 * 1: AB-synchronized. Each event triggers\r
2075 * the transfer of BCNT arrays of ACNT\r
2076 * bytes.\r
2077 *\r
2078 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2079 *\r
2080 * \note This function is re-entrant for unique lCh values. It is non-\r
2081 * re-entrant for same lCh value.\r
2082 */\r
2083 EDMA3_DRV_Result EDMA3_DRV_setTransferParams (\r
2084 EDMA3_DRV_Handle hEdma,\r
2085 unsigned int lCh,\r
2086 unsigned int aCnt,\r
2087 unsigned int bCnt,\r
2088 unsigned int cCnt,\r
2089 unsigned int bCntReload,\r
2090 EDMA3_DRV_SyncType syncType);\r
2091 \r
2092 \r
2093 \r
2094 /**\r
2095 * \brief Chain the two specified channels.\r
2096 *\r
2097 * This API is used to chain two previously allocated logical (DMA/QDMA)\r
2098 * channels.\r
2099 *\r
2100 * Chaining is different from Linking. The EDMA3 link feature reloads the\r
2101 * current channel parameter set with the linked parameter set. The EDMA3\r
2102 * chaining feature does not modify or update any channel parameter set;\r
2103 * it provides a synchronization event to the chained channel.\r
2104 *\r
2105 * \param hEdma [IN] Handle to the EDMA Driver Instance.\r
2106 *\r
2107 * \param lCh1 [IN] Channel to which particular channel\r
2108 * will be chained.\r
2109 * \param lCh2 [IN] Channel which needs to be chained to\r
2110 * the first channel.\r
2111 * \param chainOptions [IN] Options such as intermediate interrupts\r
2112 * are required or not, intermediate/final\r
2113 * chaining is enabled or not etc.\r
2114 *\r
2115 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2116 *\r
2117 * \note This function is re-entrant for unique lCh1 & lCh2 values. It is\r
2118 * non-re-entrant for same lCh1 & lCh2 values.\r
2119 */\r
2120 EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma,\r
2121 unsigned int lCh1,\r
2122 unsigned int lCh2,\r
2123 const EDMA3_DRV_ChainOptions *chainOptions);\r
2124 \r
2125 \r
2126 /**\r
2127 * \brief Unchain the two channels.\r
2128 *\r
2129 * \param hEdma [IN] Handle to the EDMA Driver Instance.\r
2130 * \param lCh [IN] Channel whose chaining with the other\r
2131 * channel has to be removed.\r
2132 *\r
2133 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2134 *\r
2135 * \note This function is re-entrant for unique lCh values. It is non-\r
2136 * re-entrant for same lCh value.\r
2137 */\r
2138 EDMA3_DRV_Result EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle hEdma,\r
2139 unsigned int lCh);\r
2140 \r
2141 \r
2142 /**\r
2143 * \brief EDMA Trigger Mode Selection\r
2144 *\r
2145 * Use this enum to select the EDMA trigger mode while enabling\r
2146 * the EDMA transfer\r
2147 */\r
2148 typedef enum\r
2149 {\r
2150 /**\r
2151 * Set the Trigger mode to Manual .\r
2152 * The CPU manually triggers a transfer by writing a 1 to the\r
2153 * corresponding bit in the event set register (ESR/ESRH).\r
2154 */\r
2155 EDMA3_DRV_TRIG_MODE_MANUAL = 0,\r
2156 \r
2157 /**\r
2158 * Set the Trigger mode to QDMA.\r
2159 * A QDMA transfer is triggered when a CPU (or other EDMA3\r
2160 * programmer) writes to the trigger word of the\r
2161 * QDMA channel parameter set (autotriggered) or when the\r
2162 * EDMA3CC performs a link update on a PaRAM\r
2163 * set that has been mapped to a QDMA channel (link triggered).\r
2164 */\r
2165 EDMA3_DRV_TRIG_MODE_QDMA = 1,\r
2166 \r
2167 /**\r
2168 * Set the Trigger mode to Event.\r
2169 * Allows for a peripheral, system, or externally-generated\r
2170 * event to trigger a transfer request.\r
2171 */\r
2172 EDMA3_DRV_TRIG_MODE_EVENT = 2,\r
2173 \r
2174 /** Used to specify the trigger mode NONE */\r
2175 EDMA3_DRV_TRIG_MODE_NONE = 3\r
2176 } EDMA3_DRV_TrigMode;\r
2177 \r
2178 \r
2179 /**\r
2180 * \brief Start EDMA transfer on the specified channel.\r
2181 *\r
2182 * There are multiple ways to trigger an EDMA3 transfer. The triggering mode\r
2183 * option allows choosing from the available triggering modes: Event,\r
2184 * Manual or QDMA.\r
2185 *\r
2186 * In event triggered, a peripheral or an externally generated event triggers\r
2187 * the transfer. This API clears the Event and Event Miss Register and then\r
2188 * enables the DMA channel by writing to the EESR.\r
2189 *\r
2190 * In manual triggered mode, CPU manually triggers a transfer by writing a 1\r
2191 * in the Event Set Register (ESR/ESRH). This API writes to the ESR/ESRH to\r
2192 * start the transfer.\r
2193 *\r
2194 * In QDMA triggered mode, a QDMA transfer is triggered when a CPU (or other\r
2195 * EDMA3 programmer) writes to the trigger word of the QDMA channel PaRAM set\r
2196 * (auto-triggered) or when the EDMA3CC performs a link update on a PaRAM set\r
2197 * that has been mapped to a QDMA channel (link triggered). This API enables\r
2198 * the QDMA channel by writing to the QEESR register.\r
2199 *\r
2200 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
2201 * \param lCh [IN] Channel on which transfer has to be started\r
2202 * \param trigMode [IN] Mode of triggering start of transfer (Manual,\r
2203 * QDMA or Event)\r
2204 *\r
2205 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2206 *\r
2207 * \note This function is re-entrant for unique lCh values. It is non-\r
2208 * re-entrant for same lCh value.\r
2209 */\r
2210 EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,\r
2211 unsigned int lCh,\r
2212 EDMA3_DRV_TrigMode trigMode);\r
2213 \r
2214 \r
2215 /**\r
2216 * \brief Disable DMA transfer on the specified channel\r
2217 *\r
2218 * There are multiple ways by which an EDMA3 transfer could be triggered.\r
2219 * The triggering mode option allows choosing from the available triggering\r
2220 * modes: Event, Manual or QDMA.\r
2221 *\r
2222 * To disable a channel which was previously triggered in manual mode,\r
2223 * this API clears the Secondary Event Register and Event Miss Register,\r
2224 * if set, for the specific DMA channel.\r
2225 *\r
2226 * To disable a channel which was previously triggered in QDMA mode, this\r
2227 * API clears the QDMA Even Enable Register, for the specific QDMA channel.\r
2228 *\r
2229 * To disable a channel which was previously triggered in event mode, this API\r
2230 * clears the Event Enable Register, Event Register, Secondary Event Register\r
2231 * and Event Miss Register, if set, for the specific DMA channel.\r
2232 \r
2233 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
2234 * \param lCh [IN] Channel on which transfer has to be stopped\r
2235 * \param trigMode [IN] Mode of triggering start of transfer\r
2236 *\r
2237 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2238 *\r
2239 * \note This function is re-entrant for unique lCh values. It is non-\r
2240 * re-entrant for same lCh value.\r
2241 */\r
2242 EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,\r
2243 unsigned int lCh,\r
2244 EDMA3_DRV_TrigMode trigMode);\r
2245 \r
2246 /* @} Edma3DrvTransferSetupType */\r
2247 \r
2248 \r
2249 \r
2250 /**\r
2251 * \defgroup Edma3DrvTransferSetupOpt EDMA3 Driver Optional Setup for EDMA\r
2252 * Transfer.\r
2253 *\r
2254 * The Optional EDMA transfer related Interface of the EDMA3 Driver\r
2255 *\r
2256 * @{\r
2257 */\r
2258 \r
2259 /**\r
2260 * \brief PaRAM Set Entry type\r
2261 *\r
2262 * Use this enum to set or get any of the\r
2263 * 8 DWords(unsigned int) within a Parameter RAM set\r
2264 */\r
2265 typedef enum\r
2266 {\r
2267 /**\r
2268 * The OPT field (Offset Address 0x0 Bytes)\r
2269 */\r
2270 EDMA3_DRV_PARAM_ENTRY_OPT = 0,\r
2271 \r
2272 /**\r
2273 * The SRC field (Offset Address 0x4 Bytes)\r
2274 */\r
2275 EDMA3_DRV_PARAM_ENTRY_SRC = 1,\r
2276 \r
2277 /**\r
2278 * The (ACNT+BCNT) field (Offset Address 0x8 Bytes)\r
2279 */\r
2280 EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT = 2,\r
2281 \r
2282 /**\r
2283 * The DST field (Offset Address 0xC Bytes)\r
2284 */\r
2285 EDMA3_DRV_PARAM_ENTRY_DST = 3,\r
2286 \r
2287 /**\r
2288 * The (SRCBIDX+DSTBIDX) field (Offset Address 0x10 Bytes)\r
2289 */\r
2290 EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX = 4,\r
2291 \r
2292 /**\r
2293 * The (LINK+BCNTRLD) field (Offset Address 0x14 Bytes)\r
2294 */\r
2295 EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD = 5,\r
2296 \r
2297 /**\r
2298 * The (SRCCIDX+DSTCIDX) field (Offset Address 0x18 Bytes)\r
2299 */\r
2300 EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX = 6,\r
2301 \r
2302 /**\r
2303 * The (CCNT+RSVD) field (Offset Address 0x1C Bytes)\r
2304 */\r
2305 EDMA3_DRV_PARAM_ENTRY_CCNT = 7\r
2306 \r
2307 } EDMA3_DRV_PaRAMEntry;\r
2308 \r
2309 \r
2310 \r
2311 /**\r
2312 * \brief PaRAM Set Field type\r
2313 *\r
2314 * Use this enum to set or get any of the PaRAM set fields\r
2315 */\r
2316 typedef enum\r
2317 {\r
2318 /** OPT field of PaRAM Set */\r
2319 EDMA3_DRV_PARAM_FIELD_OPT = 0,\r
2320 \r
2321 /**\r
2322 * \brief Starting byte address of Source\r
2323 * For FIFO mode, srcAddr must be a 256-bit aligned address.\r
2324 */\r
2325 EDMA3_DRV_PARAM_FIELD_SRCADDR = 1,\r
2326 \r
2327 /**\r
2328 * \brief Number of bytes in each Array (ACNT)\r
2329 */\r
2330 EDMA3_DRV_PARAM_FIELD_ACNT = 2,\r
2331 \r
2332 /**\r
2333 * \brief Number of Arrays in each Frame (BCNT)\r
2334 */\r
2335 EDMA3_DRV_PARAM_FIELD_BCNT = 3,\r
2336 \r
2337 /**\r
2338 * \brief Starting byte address of destination\r
2339 * For FIFO mode, destAddr must be a 256-bit aligned address.\r
2340 */\r
2341 EDMA3_DRV_PARAM_FIELD_DESTADDR = 4,\r
2342 \r
2343 /**\r
2344 * \brief Index between consec. arrays of a Source Frame (SRCBIDX)\r
2345 * If SAM is set to 1 (via channelOptions) then srcInterArrIndex should\r
2346 * be an even multiple of 32 bytes.\r
2347 */\r
2348 EDMA3_DRV_PARAM_FIELD_SRCBIDX = 5,\r
2349 \r
2350 /**\r
2351 * \brief Index between consec. arrays of a Destination Frame (DSTBIDX)\r
2352 * If DAM is set to 1 (via channelOptions) then destInterArrIndex should\r
2353 * be an even multiple of 32 bytes\r
2354 */\r
2355 EDMA3_DRV_PARAM_FIELD_DESTBIDX = 6,\r
2356 \r
2357 /**\r
2358 * \brief Address for linking (AutoReloading of a PaRAM Set)\r
2359 * This must point to a valid aligned 32-byte PaRAM set\r
2360 * A value of 0xFFFF means no linking\r
2361 * Linking is especially useful for use with ping-pong buffers and\r
2362 * circular buffers\r
2363 */\r
2364 EDMA3_DRV_PARAM_FIELD_LINKADDR = 7,\r
2365 \r
2366 /**\r
2367 * \brief Reload value of the numArrInFrame (BCNT)\r
2368 * Relevant only for A-sync transfers\r
2369 */\r
2370 EDMA3_DRV_PARAM_FIELD_BCNTRELOAD = 8,\r
2371 \r
2372 /**\r
2373 * \brief Index between consecutive frames of a Source Block (SRCCIDX)\r
2374 */\r
2375 EDMA3_DRV_PARAM_FIELD_SRCCIDX = 9,\r
2376 \r
2377 /**\r
2378 * \brief Index between consecutive frames of a Dest Block (DSTCIDX)\r
2379 */\r
2380 EDMA3_DRV_PARAM_FIELD_DESTCIDX = 10,\r
2381 \r
2382 /**\r
2383 * \brief Number of Frames in a block (CCNT)\r
2384 */\r
2385 EDMA3_DRV_PARAM_FIELD_CCNT = 11\r
2386 \r
2387 } EDMA3_DRV_PaRAMField;\r
2388 \r
2389 \r
2390 \r
2391 /**\r
2392 * \brief EDMA3 PaRAM Set\r
2393 *\r
2394 * This is a mapping of the EDMA3 PaRAM set provided to the user\r
2395 * for ease of modification of the individual PaRAM words.\r
2396 */\r
2397 typedef struct {\r
2398 /** OPT field of PaRAM Set */\r
2399 volatile unsigned int OPT;\r
2400 \r
2401 /**\r
2402 * \brief Starting byte address of Source\r
2403 * For FIFO mode, srcAddr must be a 256-bit aligned address.\r
2404 */\r
2405 volatile unsigned int SRC;\r
2406 \r
2407 /**\r
2408 * Number of bytes in each Array (ACNT) (16 bits) and\r
2409 * Number of Arrays in each Frame (BCNT) (16 bits).\r
2410 */\r
2411 volatile unsigned int A_B_CNT;\r
2412 \r
2413 /**\r
2414 * \brief Starting byte address of destination\r
2415 * For FIFO mode, destAddr must be a 256-bit aligned address.\r
2416 * i.e. 5 LSBs should be 0.\r
2417 */\r
2418 volatile unsigned int DST;\r
2419 \r
2420 /**\r
2421 * Index between consec. arrays of a Source Frame (SRCBIDX) (16 bits) and\r
2422 * Index between consec. arrays of a Destination Frame (DSTBIDX) (16 bits).\r
2423 *\r
2424 * If SAM is set to 1 (via channelOptions) then srcInterArrIndex should\r
2425 * be an even multiple of 32 bytes.\r
2426 *\r
2427 * If DAM is set to 1 (via channelOptions) then destInterArrIndex should\r
2428 * be an even multiple of 32 bytes\r
2429 */\r
2430 volatile unsigned int SRC_DST_BIDX;\r
2431 \r
2432 /**\r
2433 * \brief Address for linking (AutoReloading of a PaRAM Set) (16 bits)\r
2434 * and Reload value of the numArrInFrame (BCNT) (16 bits).\r
2435 *\r
2436 * Link field must point to a valid aligned 32-byte PaRAM set\r
2437 * A value of 0xFFFF means no linking.\r
2438 *\r
2439 * B count reload field is relevant only for A-sync transfers.\r
2440 */\r
2441 volatile unsigned int LINK_BCNTRLD;\r
2442 \r
2443 /**\r
2444 * \brief Index between consecutive frames of a Source Block (SRCCIDX)\r
2445 * (16 bits) and Index between consecutive frames of a Dest Block\r
2446 * (DSTCIDX) (16 bits).\r
2447 */\r
2448 volatile unsigned int SRC_DST_CIDX;\r
2449 \r
2450 /**\r
2451 * \brief Number of Frames in a block (CCNT) (16 bits).\r
2452 */\r
2453 volatile unsigned int CCNT;\r
2454 \r
2455 } EDMA3_DRV_ParamentryRegs;\r
2456 \r
2457 \r
2458 \r
2459 /**\r
2460 * \brief EDMA3 Parameter RAM Set in User Configurable format\r
2461 *\r
2462 * This is a mapping of the EDMA3 PaRAM set provided to the user\r
2463 * for ease of modification of the individual fields\r
2464 */\r
2465 typedef struct {\r
2466 /** OPT field of PaRAM Set */\r
2467 volatile unsigned int opt;\r
2468 \r
2469 /**\r
2470 * \brief Starting byte address of Source\r
2471 * For FIFO mode, srcAddr must be a 256-bit aligned address.\r
2472 */\r
2473 volatile unsigned int srcAddr;\r
2474 \r
2475 /**\r
2476 * \brief Number of bytes in each Array (ACNT)\r
2477 */\r
2478 volatile unsigned short aCnt;\r
2479 \r
2480 /**\r
2481 * \brief Number of Arrays in each Frame (BCNT)\r
2482 */\r
2483 volatile unsigned short bCnt;\r
2484 \r
2485 /**\r
2486 * \brief Starting byte address of destination\r
2487 * For FIFO mode, destAddr must be a 256-bit aligned address.\r
2488 * i.e. 5 LSBs should be 0.\r
2489 */\r
2490 volatile unsigned int destAddr;\r
2491 \r
2492 /**\r
2493 * \brief Index between consec. arrays of a Source Frame (SRCBIDX)\r
2494 * If SAM is set to 1 (via channelOptions) then srcInterArrIndex should\r
2495 * be an even multiple of 32 bytes.\r
2496 */\r
2497 volatile short srcBIdx;\r
2498 \r
2499 /**\r
2500 * \brief Index between consec. arrays of a Destination Frame (DSTBIDX)\r
2501 * If DAM is set to 1 (via channelOptions) then destInterArrIndex should\r
2502 * be an even multiple of 32 bytes\r
2503 */\r
2504 volatile short destBIdx;\r
2505 \r
2506 /**\r
2507 * \brief Address for linking (AutoReloading of a PaRAM Set)\r
2508 * This must point to a valid aligned 32-byte PaRAM set\r
2509 * A value of 0xFFFF means no linking\r
2510 * Linking is especially useful for use with ping-pong buffers and\r
2511 * circular buffers\r
2512 */\r
2513 volatile unsigned short linkAddr;\r
2514 \r
2515 /**\r
2516 * \brief Reload value of the numArrInFrame (BCNT)\r
2517 * Relevant only for A-sync transfers\r
2518 */\r
2519 volatile unsigned short bCntReload;\r
2520 \r
2521 /**\r
2522 * \brief Index between consecutive frames of a Source Block (SRCCIDX)\r
2523 */\r
2524 volatile short srcCIdx;\r
2525 \r
2526 /**\r
2527 * \brief Index between consecutive frames of a Dest Block (DSTCIDX)\r
2528 */\r
2529 volatile short destCIdx;\r
2530 \r
2531 /**\r
2532 * \brief Number of Frames in a block (CCNT)\r
2533 */\r
2534 volatile unsigned short cCnt;\r
2535 \r
2536 } EDMA3_DRV_PaRAMRegs;\r
2537 \r
2538 \r
2539 /**\r
2540 * \brief Event queue priorities setup\r
2541 *\r
2542 * It allows to change the priority of the individual queues and the\r
2543 * priority of the transfer request (TR) associated with the\r
2544 * events queued in the queue.\r
2545 */\r
2546 typedef struct\r
2547 {\r
2548 /**\r
2549 * \brief Event Queue Priorities\r
2550 */\r
2551 unsigned int evtQPri[EDMA3_MAX_EVT_QUE];\r
2552 }EDMA3_DRV_EvtQuePriority;\r
2553 \r
2554 \r
2555 \r
2556 /**\r
2557 * \brief Assign a Trigger Word to the specified QDMA channel\r
2558 *\r
2559 * This API sets the Trigger word for the specific QDMA channel in the QCHMAP\r
2560 * Register. Default QDMA trigger word is CCNT.\r
2561 *\r
2562 * \param hEdma [IN] Handle to the EDMA Instance object\r
2563 * \param lCh [IN] QDMA Channel which needs to be assigned\r
2564 * the Trigger Word\r
2565 * \param trigWord [IN] The Trigger Word for the QDMA channel.\r
2566 * Trigger Word is the word in the PaRAM\r
2567 * Register Set which, when written to by CPU,\r
2568 * will start the QDMA transfer automatically.\r
2569 *\r
2570 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2571 *\r
2572 * \note This function is re-entrant for unique lCh values. It is non-\r
2573 * re-entrant for same lCh value.\r
2574 */\r
2575 EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle hEdma,\r
2576 unsigned int lCh,\r
2577 EDMA3_RM_QdmaTrigWord trigWord);\r
2578 \r
2579 \r
2580 /**\r
2581 * \brief Copy the user specified PaRAM Set onto the PaRAM Set\r
2582 * associated with the logical channel (DMA/QDMA/Link).\r
2583 *\r
2584 * This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set\r
2585 * associated with the logical channel. OPT field of the PaRAM Set is written\r
2586 * first and the CCNT field is written last.\r
2587 *\r
2588 * Caution: It should be used carefully when programming the QDMA channels whose\r
2589 * trigger words are not CCNT field.\r
2590 *\r
2591 * \param hEdma [IN] Handle to the EDMA Instance object\r
2592 * \param lCh [IN] Logical Channel for which new PaRAM set is\r
2593 * specified\r
2594 * \param newPaRAM [IN] Parameter RAM set to be copied onto existing PaRAM\r
2595 *\r
2596 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2597 *\r
2598 * \note This function is re-entrant for unique lCh values. It is non-\r
2599 * re-entrant for same lCh value.\r
2600 */\r
2601 EDMA3_DRV_Result EDMA3_DRV_setPaRAM ( EDMA3_DRV_Handle hEdma,\r
2602 unsigned int lCh,\r
2603 const EDMA3_DRV_PaRAMRegs *newPaRAM);\r
2604 \r
2605 \r
2606 /**\r
2607 * \brief Retrieve existing PaRAM set associated with specified logical\r
2608 * channel (DMA/QDMA/Link).\r
2609 *\r
2610 * \param hEdma [IN] Handle to the EDMA Instance object\r
2611 * \param lCh [IN] Logical Channel whose PaRAM set is\r
2612 * requested\r
2613 * \param currPaRAM [IN/OUT] User gets the existing PaRAM here\r
2614 *\r
2615 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2616 *\r
2617 * \note This function is re-entrant.\r
2618 */\r
2619 EDMA3_DRV_Result EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma,\r
2620 unsigned int lCh,\r
2621 EDMA3_DRV_PaRAMRegs *currPaRAM);\r
2622 \r
2623 \r
2624 \r
2625 /**\r
2626 * \brief Set a particular PaRAM set entry of the specified PaRAM set\r
2627 *\r
2628 *\r
2629 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
2630 * \param lCh [IN] Logical Channel bound to the Parameter RAM set\r
2631 * whose specified field needs to be set\r
2632 * \param paRAMEntry [IN] Specify the PaRAM set entry which needs\r
2633 * to be set\r
2634 * \param newPaRAMEntryVal [IN] The new field setting\r
2635 *\r
2636 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2637 *\r
2638 * \note This API should be used while setting the PaRAM set entry\r
2639 * for QDMA channels. If EDMA3_DRV_setPaRAMField () used,\r
2640 * it will trigger the QDMA channel before complete\r
2641 * PaRAM set entry is written. For DMA channels, no such\r
2642 * constraint is there.\r
2643 *\r
2644 * This function is re-entrant for unique lCh values. It is non-\r
2645 * re-entrant for same lCh value.\r
2646 */\r
2647 EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle hEdma,\r
2648 unsigned int lCh,\r
2649 EDMA3_DRV_PaRAMEntry paRAMEntry,\r
2650 unsigned int newPaRAMEntryVal);\r
2651 \r
2652 \r
2653 /**\r
2654 * \brief Get a particular PaRAM set entry of the specified PaRAM set\r
2655 *\r
2656 *\r
2657 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
2658 * \param lCh [IN] Logical Channel bound to the Parameter RAM set\r
2659 * whose specified field value is needed\r
2660 * \param paRAMEntry [IN] Specify the PaRAM set entry which needs\r
2661 * to be obtained\r
2662 * \param paRAMEntryVal [IN/OUT] The value of the field is returned here\r
2663 *\r
2664 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2665 *\r
2666 * \note This function is re-entrant.\r
2667 */\r
2668 EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle hEdma,\r
2669 unsigned int lCh,\r
2670 EDMA3_DRV_PaRAMEntry paRAMEntry,\r
2671 unsigned int *paRAMEntryVal);\r
2672 \r
2673 \r
2674 /**\r
2675 * \brief Set a particular PaRAM set field of the specified PaRAM set\r
2676 *\r
2677 *\r
2678 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
2679 * \param lCh [IN] Logical Channel bound to the PaRAM set\r
2680 * whose specified field needs to be set\r
2681 * \param paRAMField [IN] Specify the PaRAM set field which needs\r
2682 * to be set\r
2683 * \param newPaRAMFieldVal [IN] The new field setting\r
2684 *\r
2685 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2686 *\r
2687 * \note This API CANNOT be used while setting the PaRAM set\r
2688 * field for QDMA channels. It can trigger the QDMA channel before\r
2689 * complete PaRAM set ENTRY (4-bytes field) is written (for eg, as\r
2690 * soon one sets the ACNT field for QDMA channel, transfer is started,\r
2691 * before one modifies the BCNT field). For DMA channels, no such\r
2692 * constraint is there.\r
2693 *\r
2694 * This function is re-entrant for unique lCh values. It is non-\r
2695 * re-entrant for same lCh value.\r
2696 */\r
2697 EDMA3_DRV_Result EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle hEdma,\r
2698 unsigned int lCh,\r
2699 EDMA3_DRV_PaRAMField paRAMField,\r
2700 unsigned int newPaRAMFieldVal);\r
2701 \r
2702 \r
2703 /**\r
2704 * \brief Get a particular PaRAM set field of the specified PaRAM set\r
2705 *\r
2706 *\r
2707 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
2708 * \param lCh [IN] Logical Channel bound to the PaRAM set\r
2709 * whose specified field value is needed\r
2710 * \param paRAMField [IN] Specify the PaRAM set field which needs\r
2711 * to be obtained\r
2712 * \param currPaRAMFieldVal [IN/OUT] The value of the field is returned here\r
2713 *\r
2714 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2715 *\r
2716 * \note This function is re-entrant.\r
2717 */\r
2718 EDMA3_DRV_Result EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma,\r
2719 unsigned int lCh,\r
2720 EDMA3_DRV_PaRAMField paRAMField,\r
2721 unsigned int *currPaRAMFieldVal);\r
2722 \r
2723 \r
2724 /**\r
2725 * \brief Sets EDMA TC priority\r
2726 *\r
2727 * User can program the priority of the Event Queues at a system-wide level.\r
2728 * This means that the user can set the priority of an IO initiated by either\r
2729 * of the TCs (Transfer Ctrllers) relative to IO initiated by the other bus\r
2730 * masters on the device (ARM, DSP, USB, etc)\r
2731 *\r
2732 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
2733 * \param evtQPriObj [IN] Priority of the Event Queues\r
2734 *\r
2735 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2736 *\r
2737 * \note This function disables the global interrupts while modifying\r
2738 * the global CC Registers, to make it re-entrant.\r
2739 */\r
2740 EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle hEdma,\r
2741 const EDMA3_DRV_EvtQuePriority *evtQPriObj);\r
2742 \r
2743 \r
2744 /**\r
2745 * \brief Associate Channel to Event Queue\r
2746 *\r
2747 *\r
2748 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
2749 * \param channelId [IN] Logical Channel to which the Event\r
2750 * Queue is to be mapped\r
2751 * \param eventQ [IN] The Event Queue which is to be mapped\r
2752 * to the DMA channel\r
2753 *\r
2754 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2755 *\r
2756 * \note There should not be any data transfer going on\r
2757 * while setting the mapping. Results could be unpredictable.\r
2758 *\r
2759 * This function disables the global interrupts while modifying\r
2760 * the global CC Registers, to make it re-entrant.\r
2761 */\r
2762 EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ (EDMA3_DRV_Handle hEdma,\r
2763 unsigned int channelId,\r
2764 EDMA3_RM_EventQueue eventQ);\r
2765 \r
2766 \r
2767 /**\r
2768 * \brief Get the Event Queue mapped to the specified DMA/QDMA channel.\r
2769 *\r
2770 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
2771 * \param channelId [IN] Logical Channel whose associated\r
2772 * Event Queue is needed\r
2773 * \param mappedEvtQ [IN/OUT] The Event Queue which is mapped\r
2774 * to the DMA/QDMA channel\r
2775 *\r
2776 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2777 *\r
2778 * \note This function is re-entrant.\r
2779 */\r
2780 EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma,\r
2781 unsigned int channelId,\r
2782 unsigned int *mappedEvtQ);\r
2783 \r
2784 \r
2785 \r
2786 /**\r
2787 * \brief Set the Channel Controller (CC) Register value\r
2788 *\r
2789 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
2790 * \param regOffset [IN] CC Register offset whose value needs to be set\r
2791 * \param newRegValue [IN] New CC Register Value\r
2792 *\r
2793 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2794 *\r
2795 * \note This function is non re-entrant for users using the same\r
2796 * EDMA handle i.e. working on the same shadow region.\r
2797 * Before modifying a register, it tries to acquire a semaphore\r
2798 * (Driver instance specific), to protect simultaneous\r
2799 * modification of the same register by two different users.\r
2800 * After the successful change, it releases the semaphore.\r
2801 * For users working on different shadow regions, thus different\r
2802 * EDMA handles, this function is re-entrant.\r
2803 */\r
2804 EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma,\r
2805 unsigned int regOffset,\r
2806 unsigned int newRegValue);\r
2807 \r
2808 \r
2809 /**\r
2810 * \brief Get the Channel Controller (CC) Register value\r
2811 *\r
2812 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
2813 * \param regOffset [IN] CC Register offset whose value is needed\r
2814 * \param regValue [IN/OUT] CC Register Value\r
2815 *\r
2816 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2817 *\r
2818 * \note This function is re-entrant.\r
2819 */\r
2820 EDMA3_DRV_Result EDMA3_DRV_getCCRegister (EDMA3_DRV_Handle hEdma,\r
2821 unsigned int regOffset,\r
2822 unsigned int *regValue);\r
2823 \r
2824 \r
2825 \r
2826 /**\r
2827 * \brief Wait for a transfer completion interrupt to occur and clear it.\r
2828 *\r
2829 * This is a blocking function that returns when the IPR/IPRH bit corresponding\r
2830 * to the tccNo specified, is SET. It clears the corresponding bit while\r
2831 * returning also.\r
2832 *\r
2833 * This function waits for the specific bit indefinitely in a tight loop, with\r
2834 * out any delay in between. USE IT CAUTIOUSLY.\r
2835 *\r
2836 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
2837 * \param tccNo [IN] TCC, specific to which the function\r
2838 * waits on a IPR/IPRH bit.\r
2839 *\r
2840 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2841 *\r
2842 * \note This function is re-entrant for different tccNo.\r
2843 */\r
2844 EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma,\r
2845 unsigned int tccNo);\r
2846 \r
2847 \r
2848 \r
2849 \r
2850 /**\r
2851 * \brief Returns the status of a previously initiated transfer.\r
2852 *\r
2853 * This is a non-blocking function that returns the status of a previously\r
2854 * initiated transfer, based on the IPR/IPRH bit. This bit corresponds to\r
2855 * the tccNo specified by the user. It clears the corresponding bit, if SET,\r
2856 * while returning also.\r
2857 *\r
2858 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
2859 * \param tccNo [IN] TCC, specific to which the function\r
2860 * checks the status of the IPR/IPRH bit.\r
2861 * \param tccStatus [IN/OUT] Status of the transfer is returned here.\r
2862 * Returns "TRUE" if the transfer has\r
2863 * completed (IPR/IPRH bit SET),\r
2864 * "FALSE" if the transfer has not completed\r
2865 * successfully (IPR/IPRH bit NOT SET).\r
2866 *\r
2867 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2868 *\r
2869 * \note This function is re-entrant for different tccNo.\r
2870 */\r
2871 EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma,\r
2872 unsigned int tccNo,\r
2873 unsigned short *tccStatus);\r
2874 \r
2875 \r
2876 \r
2877 /**\r
2878 * \brief Get the PaRAM Set Physical Address associated with a logical channel\r
2879 *\r
2880 * This function returns the PaRAM Set Phy Address (unsigned 32 bits).\r
2881 * The returned address could be used by the advanced users to program the\r
2882 * PaRAM Set directly without using any APIs.\r
2883 *\r
2884 * Least significant 16 bits of this address could be used to program\r
2885 * the LINK field in the PaRAM Set.\r
2886 * Users which program the LINK field directly SHOULD use this API\r
2887 * to get the associated PaRAM Set address with the LINK channel.\r
2888 *\r
2889 *\r
2890 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
2891 * \param lCh [IN] Logical Channel for which the PaRAM set\r
2892 * physical address is required\r
2893 * \param paramPhyAddr [IN/OUT] PaRAM Set physical address is returned\r
2894 * here.\r
2895 *\r
2896 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2897 *\r
2898 * \note This function is re-entrant.\r
2899 */\r
2900 EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr(EDMA3_DRV_Handle hEdma,\r
2901 unsigned int lCh,\r
2902 unsigned int *paramPhyAddr);\r
2903 \r
2904 \r
2905 /**\enum EDMA3_DRV_IoctlCmd\r
2906 * \brief EDMA3 Driver IOCTL commands\r
2907 */\r
2908 typedef enum\r
2909 {\r
2910 /* Min IOCTL */\r
2911 EDMA3_DRV_IOCTL_MIN_IOCTL = 0,\r
2912 \r
2913 /**\r
2914 * PaRAM Sets will be cleared OR will not be cleared\r
2915 * during allocation, depending upon this option.\r
2916 *\r
2917 * For e.g.,\r
2918 * To clear the PaRAM Sets during allocation,\r
2919 * cmdArg = (void *)1;\r
2920 *\r
2921 * To NOT clear the PaRAM Sets during allocation,\r
2922 * cmdArg = (void *)0;\r
2923 *\r
2924 * For all other values, it will return error.\r
2925 *\r
2926 * By default, PaRAM Sets will be cleared during allocation.\r
2927 * Note: Since this enum can change the behavior how the resources are\r
2928 * initialized during their allocation, user is adviced to not use this\r
2929 * command while allocating the resources. User should first change the\r
2930 * behavior of resources' initialization and then should use start\r
2931 * allocating resources.\r
2932 */\r
2933 EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION,\r
2934 \r
2935 /**\r
2936 * To check whether PaRAM Sets will be cleared or not\r
2937 * during allocation.\r
2938 * If the value read is '1', it means that PaRAM Sets are getting cleared\r
2939 * during allocation.\r
2940 * If the value read is '0', it means that PaRAM Sets are NOT getting cleared\r
2941 * during allocation.\r
2942 *\r
2943 * For e.g.,\r
2944 * unsigned short isParamClearingDone;\r
2945 * cmdArg = ¶mClearingRequired;\r
2946 */\r
2947 EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION,\r
2948 \r
2949 /* Max IOCTLs */\r
2950 EDMA3_DRV_IOCTL_MAX_IOCTL\r
2951 } EDMA3_DRV_IoctlCmd;\r
2952 \r
2953 \r
2954 /**\r
2955 * \brief EDMA3 Driver IOCTL\r
2956 *\r
2957 * This function provides IOCTL functionality for EDMA3 Driver.\r
2958 *\r
2959 * \param hEdma [IN] Handle to the EDMA Driver Instance\r
2960 * \param cmd [IN] IOCTL command to be performed\r
2961 * \param cmdArg [IN/OUT] IOCTL command argument (if any)\r
2962 * \param param [IN/OUT] Device/Cmd specific argument\r
2963 *\r
2964 * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
2965 *\r
2966 * \note For 'EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION', this function is re-entrant.\r
2967 * For 'EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION', this function is re-entrant for\r
2968 * different EDMA3 Driver Instances (handles).\r
2969 */\r
2970 EDMA3_DRV_Result EDMA3_DRV_Ioctl(\r
2971 EDMA3_DRV_Handle hEdma,\r
2972 EDMA3_DRV_IoctlCmd cmd,\r
2973 void *cmdArg,\r
2974 void *param\r
2975 );\r
2976 \r
2977 \r
2978 /**\r
2979 * \brief Return the previously opened EDMA3 Driver Instance handle\r
2980 *\r
2981 * This API is used to return the previously opened EDMA3 Driver's\r
2982 * Instance Handle (region specific), which could be used to call other\r
2983 * EDMA3 Driver APIs. Since EDMA3 Driver does not allow multiple instances,\r
2984 * for a single shadow region, this API is provided. This API is meant\r
2985 * for users who DO NOT want to / could not open a new Driver Instance and\r
2986 * hence re-use the existing Driver Instance to allocate EDMA3 resources\r
2987 * and use various other EDMA3 Driver APIs.\r
2988 *\r
2989 * In case the Driver Instance is not yet opened, NULL is returned as the\r
2990 * function return value whereas EDMA3_DRV_E_INST_NOT_OPENED is returned\r
2991 * in the errorCode.\r
2992 *\r
2993 * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id (Hardware\r
2994 * instance id, starting from 0).\r
2995 * \param regionId [IN] Shadow Region id for which the previously\r
2996 * opened driver's instance handle is\r
2997 * required.\r
2998 * \param errorCode [OUT] Error code while returning Driver Instance\r
2999 * Handle.\r
3000 *\r
3001 * \return EDMA3_DRV_Handle : If successful, this API will return the\r
3002 * driver's instance handle.\r
3003 *\r
3004 * \note 1) This API returns the previously opened EDMA3 Driver's Instance\r
3005 * handle. The instance, if exists, could have been opened by some other\r
3006 * user (most probably) or may be by the same user calling this API. If\r
3007 * it was opened by some other user, then that user can very well close\r
3008 * this instance anytime, without even knowing that the same instance\r
3009 * handle is being used by other users as well. In that case, the\r
3010 * handle becomes INVALID and user has to open a valid driver\r
3011 * instance for his/her use.\r
3012 *\r
3013 * 2) This function is re-entrant.\r
3014 */\r
3015 EDMA3_DRV_Handle EDMA3_DRV_getInstHandle(unsigned int phyCtrllerInstId,\r
3016 EDMA3_RM_RegionId regionId,\r
3017 EDMA3_DRV_Result *errorCode);\r
3018 \r
3019 \r
3020 \r
3021 /* @} Edma3DrvTransferSetupOpt */\r
3022 \r
3023 \r
3024 /* @} Edma3DrvMain */\r
3025 \r
3026 #ifdef __cplusplus\r
3027 }\r
3028 #endif /* extern "C" */\r
3029 \r
3030 #endif /* _EDMA3_DRV_H_ */\r